1 /*- 2 * Copyright (c) 2015 Semihalf 3 * Copyright (c) 2015 Stormshield 4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/errno.h> 35 #include <sys/kernel.h> 36 #include <sys/kthread.h> 37 #include <sys/module.h> 38 #include <sys/socket.h> 39 #include <sys/sockio.h> 40 41 #include <net/if.h> 42 #include <net/if_media.h> 43 #include <net/if_types.h> 44 45 #include <dev/etherswitch/etherswitch.h> 46 #include <dev/mii/mii.h> 47 #include <dev/mii/miivar.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include "e6000swreg.h" 53 #include "etherswitch_if.h" 54 #include "miibus_if.h" 55 #include "mdio_if.h" 56 57 MALLOC_DECLARE(M_E6000SW); 58 MALLOC_DEFINE(M_E6000SW, "e6000sw", "e6000sw switch"); 59 60 #define E6000SW_LOCK(_sc) sx_xlock(&(_sc)->sx) 61 #define E6000SW_UNLOCK(_sc) sx_unlock(&(_sc)->sx) 62 #define E6000SW_LOCK_ASSERT(_sc, _what) sx_assert(&(_sc)->sx, (_what)) 63 #define E6000SW_TRYLOCK(_sc) sx_tryxlock(&(_sc)->sx) 64 #define E6000SW_WAITREADY(_sc, _reg, _bit) \ 65 e6000sw_waitready((_sc), REG_GLOBAL, (_reg), (_bit)) 66 #define E6000SW_WAITREADY2(_sc, _reg, _bit) \ 67 e6000sw_waitready((_sc), REG_GLOBAL2, (_reg), (_bit)) 68 #define MDIO_READ(dev, addr, reg) \ 69 MDIO_READREG(device_get_parent(dev), (addr), (reg)) 70 #define MDIO_WRITE(dev, addr, reg, val) \ 71 MDIO_WRITEREG(device_get_parent(dev), (addr), (reg), (val)) 72 73 74 typedef struct e6000sw_softc { 75 device_t dev; 76 phandle_t node; 77 78 struct sx sx; 79 struct ifnet *ifp[E6000SW_MAX_PORTS]; 80 char *ifname[E6000SW_MAX_PORTS]; 81 device_t miibus[E6000SW_MAX_PORTS]; 82 struct proc *kproc; 83 84 int vlans[E6000SW_NUM_VLANS]; 85 uint32_t swid; 86 uint32_t vlan_mode; 87 uint32_t cpuports_mask; 88 uint32_t fixed_mask; 89 uint32_t fixed25_mask; 90 uint32_t ports_mask; 91 int phy_base; 92 int sw_addr; 93 int num_ports; 94 } e6000sw_softc_t; 95 96 static etherswitch_info_t etherswitch_info = { 97 .es_nports = 0, 98 .es_nvlangroups = 0, 99 .es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q, 100 .es_name = "Marvell 6000 series switch" 101 }; 102 103 static void e6000sw_identify(driver_t *, device_t); 104 static int e6000sw_probe(device_t); 105 static int e6000sw_parse_fixed_link(e6000sw_softc_t *, phandle_t, uint32_t); 106 static int e6000sw_parse_ethernet(e6000sw_softc_t *, phandle_t, uint32_t); 107 static int e6000sw_attach(device_t); 108 static int e6000sw_detach(device_t); 109 static int e6000sw_read_xmdio(device_t, int, int, int); 110 static int e6000sw_write_xmdio(device_t, int, int, int, int); 111 static int e6000sw_readphy(device_t, int, int); 112 static int e6000sw_writephy(device_t, int, int, int); 113 static etherswitch_info_t* e6000sw_getinfo(device_t); 114 static int e6000sw_getconf(device_t, etherswitch_conf_t *); 115 static int e6000sw_setconf(device_t, etherswitch_conf_t *); 116 static void e6000sw_lock(device_t); 117 static void e6000sw_unlock(device_t); 118 static int e6000sw_getport(device_t, etherswitch_port_t *); 119 static int e6000sw_setport(device_t, etherswitch_port_t *); 120 static int e6000sw_set_vlan_mode(e6000sw_softc_t *, uint32_t); 121 static int e6000sw_readreg_wrapper(device_t, int); 122 static int e6000sw_writereg_wrapper(device_t, int, int); 123 static int e6000sw_readphy_wrapper(device_t, int, int); 124 static int e6000sw_writephy_wrapper(device_t, int, int, int); 125 static int e6000sw_getvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 126 static int e6000sw_setvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 127 static int e6000sw_setvgroup(device_t, etherswitch_vlangroup_t *); 128 static int e6000sw_getvgroup(device_t, etherswitch_vlangroup_t *); 129 static void e6000sw_setup(device_t, e6000sw_softc_t *); 130 static void e6000sw_tick(void *); 131 static void e6000sw_set_atustat(device_t, e6000sw_softc_t *, int, int); 132 static int e6000sw_atu_flush(device_t, e6000sw_softc_t *, int); 133 static int e6000sw_vtu_flush(e6000sw_softc_t *); 134 static int e6000sw_vtu_update(e6000sw_softc_t *, int, int, int, int, int); 135 static __inline void e6000sw_writereg(e6000sw_softc_t *, int, int, int); 136 static __inline uint32_t e6000sw_readreg(e6000sw_softc_t *, int, int); 137 static int e6000sw_ifmedia_upd(struct ifnet *); 138 static void e6000sw_ifmedia_sts(struct ifnet *, struct ifmediareq *); 139 static int e6000sw_atu_mac_table(device_t, e6000sw_softc_t *, struct atu_opt *, 140 int); 141 static int e6000sw_get_pvid(e6000sw_softc_t *, int, int *); 142 static void e6000sw_set_pvid(e6000sw_softc_t *, int, int); 143 static __inline bool e6000sw_is_cpuport(e6000sw_softc_t *, int); 144 static __inline bool e6000sw_is_fixedport(e6000sw_softc_t *, int); 145 static __inline bool e6000sw_is_fixed25port(e6000sw_softc_t *, int); 146 static __inline bool e6000sw_is_phyport(e6000sw_softc_t *, int); 147 static __inline bool e6000sw_is_portenabled(e6000sw_softc_t *, int); 148 static __inline struct mii_data *e6000sw_miiforphy(e6000sw_softc_t *, 149 unsigned int); 150 151 static device_method_t e6000sw_methods[] = { 152 /* device interface */ 153 DEVMETHOD(device_identify, e6000sw_identify), 154 DEVMETHOD(device_probe, e6000sw_probe), 155 DEVMETHOD(device_attach, e6000sw_attach), 156 DEVMETHOD(device_detach, e6000sw_detach), 157 158 /* bus interface */ 159 DEVMETHOD(bus_add_child, device_add_child_ordered), 160 161 /* mii interface */ 162 DEVMETHOD(miibus_readreg, e6000sw_readphy), 163 DEVMETHOD(miibus_writereg, e6000sw_writephy), 164 165 /* etherswitch interface */ 166 DEVMETHOD(etherswitch_getinfo, e6000sw_getinfo), 167 DEVMETHOD(etherswitch_getconf, e6000sw_getconf), 168 DEVMETHOD(etherswitch_setconf, e6000sw_setconf), 169 DEVMETHOD(etherswitch_lock, e6000sw_lock), 170 DEVMETHOD(etherswitch_unlock, e6000sw_unlock), 171 DEVMETHOD(etherswitch_getport, e6000sw_getport), 172 DEVMETHOD(etherswitch_setport, e6000sw_setport), 173 DEVMETHOD(etherswitch_readreg, e6000sw_readreg_wrapper), 174 DEVMETHOD(etherswitch_writereg, e6000sw_writereg_wrapper), 175 DEVMETHOD(etherswitch_readphyreg, e6000sw_readphy_wrapper), 176 DEVMETHOD(etherswitch_writephyreg, e6000sw_writephy_wrapper), 177 DEVMETHOD(etherswitch_setvgroup, e6000sw_setvgroup_wrapper), 178 DEVMETHOD(etherswitch_getvgroup, e6000sw_getvgroup_wrapper), 179 180 DEVMETHOD_END 181 }; 182 183 static devclass_t e6000sw_devclass; 184 185 DEFINE_CLASS_0(e6000sw, e6000sw_driver, e6000sw_methods, 186 sizeof(e6000sw_softc_t)); 187 188 DRIVER_MODULE(e6000sw, mdio, e6000sw_driver, e6000sw_devclass, 0, 0); 189 DRIVER_MODULE(etherswitch, e6000sw, etherswitch_driver, etherswitch_devclass, 0, 190 0); 191 DRIVER_MODULE(miibus, e6000sw, miibus_driver, miibus_devclass, 0, 0); 192 MODULE_DEPEND(e6000sw, mdio, 1, 1, 1); 193 194 195 static void 196 e6000sw_identify(driver_t *driver, device_t parent) 197 { 198 199 if (device_find_child(parent, "e6000sw", -1) == NULL) 200 BUS_ADD_CHILD(parent, 0, "e6000sw", -1); 201 } 202 203 static int 204 e6000sw_probe(device_t dev) 205 { 206 e6000sw_softc_t *sc; 207 const char *description; 208 phandle_t switch_node; 209 210 sc = device_get_softc(dev); 211 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 212 "marvell,mv88e6085"); 213 if (switch_node == 0) { 214 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 215 "marvell,mv88e6190"); 216 217 if (switch_node == 0) 218 return (ENXIO); 219 220 /* 221 * Trust DTS and fix the port register offset for the MV88E6190 222 * detection bellow. 223 */ 224 sc->swid = MV88E6190; 225 } 226 227 if (bootverbose) 228 device_printf(dev, "Found switch_node: 0x%x\n", switch_node); 229 230 sc->dev = dev; 231 sc->node = switch_node; 232 233 if (OF_getencprop(sc->node, "reg", &sc->sw_addr, 234 sizeof(sc->sw_addr)) < 0) 235 return (ENXIO); 236 if (sc->sw_addr < 0 || sc->sw_addr > 32) 237 return (ENXIO); 238 239 /* 240 * Create temporary lock, just to satisfy assertions, 241 * when obtaining the switch ID. Destroy immediately afterwards. 242 */ 243 sx_init(&sc->sx, "e6000sw_tmp"); 244 E6000SW_LOCK(sc); 245 sc->swid = e6000sw_readreg(sc, REG_PORT(sc, 0), SWITCH_ID) & 0xfff0; 246 E6000SW_UNLOCK(sc); 247 sx_destroy(&sc->sx); 248 249 switch (sc->swid) { 250 case MV88E6141: 251 description = "Marvell 88E6141"; 252 sc->phy_base = 0x10; 253 sc->num_ports = 6; 254 break; 255 case MV88E6341: 256 description = "Marvell 88E6341"; 257 sc->phy_base = 0x10; 258 sc->num_ports = 6; 259 break; 260 case MV88E6352: 261 description = "Marvell 88E6352"; 262 sc->num_ports = 7; 263 break; 264 case MV88E6172: 265 description = "Marvell 88E6172"; 266 sc->num_ports = 7; 267 break; 268 case MV88E6176: 269 description = "Marvell 88E6176"; 270 sc->num_ports = 7; 271 break; 272 case MV88E6190: 273 description = "Marvell 88E6190"; 274 sc->num_ports = 11; 275 break; 276 default: 277 device_printf(dev, "Unrecognized device, id 0x%x.\n", sc->swid); 278 return (ENXIO); 279 } 280 281 device_set_desc(dev, description); 282 283 return (BUS_PROBE_DEFAULT); 284 } 285 286 static int 287 e6000sw_parse_fixed_link(e6000sw_softc_t *sc, phandle_t node, uint32_t port) 288 { 289 int speed; 290 phandle_t fixed_link; 291 292 fixed_link = ofw_bus_find_child(node, "fixed-link"); 293 294 if (fixed_link != 0) { 295 sc->fixed_mask |= (1 << port); 296 297 if (OF_getencprop(fixed_link, 298 "speed", &speed, sizeof(speed)) < 0) { 299 device_printf(sc->dev, 300 "Port %d has a fixed-link node without a speed " 301 "property\n", port); 302 return (ENXIO); 303 } 304 if (speed == 2500 && (MVSWITCH(sc, MV88E6141) || 305 MVSWITCH(sc, MV88E6341) || MVSWITCH(sc, MV88E6190))) 306 sc->fixed25_mask |= (1 << port); 307 } 308 309 return (0); 310 } 311 312 static int 313 e6000sw_parse_ethernet(e6000sw_softc_t *sc, phandle_t port_handle, uint32_t port) { 314 phandle_t switch_eth, switch_eth_handle; 315 316 if (OF_getencprop(port_handle, "ethernet", (void*)&switch_eth_handle, 317 sizeof(switch_eth_handle)) > 0) { 318 if (switch_eth_handle > 0) { 319 switch_eth = OF_node_from_xref(switch_eth_handle); 320 321 device_printf(sc->dev, "CPU port at %d\n", port); 322 sc->cpuports_mask |= (1 << port); 323 324 return (e6000sw_parse_fixed_link(sc, switch_eth, port)); 325 } else 326 device_printf(sc->dev, 327 "Port %d has ethernet property but it points " 328 "to an invalid location\n", port); 329 } 330 331 return (0); 332 } 333 334 static int 335 e6000sw_parse_child_fdt(e6000sw_softc_t *sc, phandle_t child, int *pport) 336 { 337 uint32_t port; 338 339 if (pport == NULL) 340 return (ENXIO); 341 342 if (OF_getencprop(child, "reg", (void *)&port, sizeof(port)) < 0) 343 return (ENXIO); 344 if (port >= sc->num_ports) 345 return (ENXIO); 346 *pport = port; 347 348 if (e6000sw_parse_fixed_link(sc, child, port) != 0) 349 return (ENXIO); 350 351 if (e6000sw_parse_ethernet(sc, child, port) != 0) 352 return (ENXIO); 353 354 if ((sc->fixed_mask & (1 << port)) != 0) 355 device_printf(sc->dev, "fixed port at %d\n", port); 356 else 357 device_printf(sc->dev, "PHY at port %d\n", port); 358 359 return (0); 360 } 361 362 static int 363 e6000sw_init_interface(e6000sw_softc_t *sc, int port) 364 { 365 char name[IFNAMSIZ]; 366 367 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->dev)); 368 369 sc->ifp[port] = if_alloc(IFT_ETHER); 370 if (sc->ifp[port] == NULL) 371 return (ENOMEM); 372 sc->ifp[port]->if_softc = sc; 373 sc->ifp[port]->if_flags |= IFF_UP | IFF_BROADCAST | 374 IFF_DRV_RUNNING | IFF_SIMPLEX; 375 sc->ifname[port] = malloc(strlen(name) + 1, M_E6000SW, M_NOWAIT); 376 if (sc->ifname[port] == NULL) { 377 if_free(sc->ifp[port]); 378 return (ENOMEM); 379 } 380 memcpy(sc->ifname[port], name, strlen(name) + 1); 381 if_initname(sc->ifp[port], sc->ifname[port], port); 382 383 return (0); 384 } 385 386 static int 387 e6000sw_attach_miibus(e6000sw_softc_t *sc, int port) 388 { 389 int err; 390 391 err = mii_attach(sc->dev, &sc->miibus[port], sc->ifp[port], 392 e6000sw_ifmedia_upd, e6000sw_ifmedia_sts, BMSR_DEFCAPMASK, 393 port + sc->phy_base, MII_OFFSET_ANY, 0); 394 if (err != 0) 395 return (err); 396 397 return (0); 398 } 399 400 static void 401 e6000sw_serdes_power(device_t dev, int port, bool sgmii) 402 { 403 uint32_t reg; 404 405 /* SGMII */ 406 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 407 E6000SW_SERDES_SGMII_CTL); 408 if (sgmii) 409 reg &= ~E6000SW_SERDES_PDOWN; 410 else 411 reg |= E6000SW_SERDES_PDOWN; 412 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 413 E6000SW_SERDES_SGMII_CTL, reg); 414 415 /* 10GBASE-R/10GBASE-X4/X2 */ 416 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 417 E6000SW_SERDES_PCS_CTL1); 418 if (sgmii) 419 reg |= E6000SW_SERDES_PDOWN; 420 else 421 reg &= ~E6000SW_SERDES_PDOWN; 422 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 423 E6000SW_SERDES_PCS_CTL1, reg); 424 } 425 426 static int 427 e6000sw_attach(device_t dev) 428 { 429 bool sgmii; 430 e6000sw_softc_t *sc; 431 phandle_t child, ports; 432 int err, port; 433 uint32_t reg; 434 435 err = 0; 436 sc = device_get_softc(dev); 437 438 /* 439 * According to the Linux source code, all of the Switch IDs we support 440 * are multi_chip capable, and should go into multi-chip mode if the 441 * sw_addr != 0. 442 */ 443 if (MVSWITCH_MULTICHIP(sc)) 444 device_printf(dev, "multi-chip addressing mode (%#x)\n", 445 sc->sw_addr); 446 else 447 device_printf(dev, "single-chip addressing mode\n"); 448 449 sx_init(&sc->sx, "e6000sw"); 450 451 E6000SW_LOCK(sc); 452 e6000sw_setup(dev, sc); 453 454 ports = ofw_bus_find_child(sc->node, "ports"); 455 456 if (ports == 0) { 457 device_printf(dev, "failed to parse DTS: no ports found for " 458 "switch\n"); 459 return (ENXIO); 460 } 461 462 for (child = OF_child(ports); child != 0; child = OF_peer(child)) { 463 err = e6000sw_parse_child_fdt(sc, child, &port); 464 if (err != 0) { 465 device_printf(sc->dev, "failed to parse DTS\n"); 466 goto out_fail; 467 } 468 469 /* Port is in use. */ 470 sc->ports_mask |= (1 << port); 471 472 err = e6000sw_init_interface(sc, port); 473 if (err != 0) { 474 device_printf(sc->dev, "failed to init interface\n"); 475 goto out_fail; 476 } 477 478 if (e6000sw_is_fixedport(sc, port)) { 479 /* Link must be down to change speed force value. */ 480 reg = e6000sw_readreg(sc, REG_PORT(sc, port), 481 PSC_CONTROL); 482 reg &= ~PSC_CONTROL_LINK_UP; 483 reg |= PSC_CONTROL_FORCED_LINK; 484 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 485 reg); 486 487 /* 488 * Force speed, full-duplex, EEE off and flow-control 489 * on. 490 */ 491 reg &= ~(PSC_CONTROL_SPD2500 | PSC_CONTROL_ALT_SPD | 492 PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON | 493 PSC_CONTROL_FORCED_EEE); 494 if (e6000sw_is_fixed25port(sc, port)) 495 reg |= PSC_CONTROL_SPD2500; 496 else 497 reg |= PSC_CONTROL_SPD1000; 498 if (MVSWITCH(sc, MV88E6190) && 499 e6000sw_is_fixed25port(sc, port)) 500 reg |= PSC_CONTROL_ALT_SPD; 501 reg |= PSC_CONTROL_FORCED_DPX | PSC_CONTROL_FULLDPX | 502 PSC_CONTROL_FORCED_LINK | PSC_CONTROL_LINK_UP | 503 PSC_CONTROL_FORCED_SPD; 504 if (!MVSWITCH(sc, MV88E6190)) 505 reg |= PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON; 506 if (MVSWITCH(sc, MV88E6141) || 507 MVSWITCH(sc, MV88E6341) || 508 MVSWITCH(sc, MV88E6190)) 509 reg |= PSC_CONTROL_FORCED_EEE; 510 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 511 reg); 512 /* Power on the SERDES interfaces. */ 513 if (MVSWITCH(sc, MV88E6190) && 514 (port == 9 || port == 10)) { 515 if (e6000sw_is_fixed25port(sc, port)) 516 sgmii = false; 517 else 518 sgmii = true; 519 e6000sw_serdes_power(sc->dev, port, sgmii); 520 } 521 } 522 523 /* Don't attach miibus at CPU/fixed ports */ 524 if (!e6000sw_is_phyport(sc, port)) 525 continue; 526 527 err = e6000sw_attach_miibus(sc, port); 528 if (err != 0) { 529 device_printf(sc->dev, "failed to attach miibus\n"); 530 goto out_fail; 531 } 532 } 533 534 etherswitch_info.es_nports = sc->num_ports; 535 536 /* Default to port vlan. */ 537 e6000sw_set_vlan_mode(sc, ETHERSWITCH_VLAN_PORT); 538 539 reg = e6000sw_readreg(sc, REG_GLOBAL, SWITCH_GLOBAL_STATUS); 540 if (reg & SWITCH_GLOBAL_STATUS_IR) 541 device_printf(dev, "switch is ready.\n"); 542 E6000SW_UNLOCK(sc); 543 544 bus_generic_probe(dev); 545 bus_generic_attach(dev); 546 547 kproc_create(e6000sw_tick, sc, &sc->kproc, 0, 0, "e6000sw tick kproc"); 548 549 return (0); 550 551 out_fail: 552 E6000SW_UNLOCK(sc); 553 e6000sw_detach(dev); 554 555 return (err); 556 } 557 558 static int 559 e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg, 560 uint32_t busybit) 561 { 562 int i; 563 564 for (i = 0; i < E6000SW_RETRIES; i++) { 565 if ((e6000sw_readreg(sc, phy, reg) & busybit) == 0) 566 return (0); 567 DELAY(1); 568 } 569 570 return (1); 571 } 572 573 /* XMDIO/Clause 45 access. */ 574 static int 575 e6000sw_read_xmdio(device_t dev, int phy, int devaddr, int devreg) 576 { 577 e6000sw_softc_t *sc; 578 uint32_t reg; 579 580 sc = device_get_softc(dev); 581 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 582 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 583 device_printf(dev, "Timeout while waiting for switch\n"); 584 return (ETIMEDOUT); 585 } 586 587 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 588 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 589 590 /* Load C45 register address. */ 591 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 592 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 593 reg | SMI_CMD_OP_C45_ADDR); 594 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 595 device_printf(dev, "Timeout while waiting for switch\n"); 596 return (ETIMEDOUT); 597 } 598 599 /* Start C45 read operation. */ 600 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 601 reg | SMI_CMD_OP_C45_READ); 602 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 603 device_printf(dev, "Timeout while waiting for switch\n"); 604 return (ETIMEDOUT); 605 } 606 607 /* Read C45 data. */ 608 reg = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 609 610 return (reg & PHY_DATA_MASK); 611 } 612 613 static int 614 e6000sw_write_xmdio(device_t dev, int phy, int devaddr, int devreg, int val) 615 { 616 e6000sw_softc_t *sc; 617 uint32_t reg; 618 619 sc = device_get_softc(dev); 620 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 621 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 622 device_printf(dev, "Timeout while waiting for switch\n"); 623 return (ETIMEDOUT); 624 } 625 626 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 627 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 628 629 /* Load C45 register address. */ 630 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 631 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 632 reg | SMI_CMD_OP_C45_ADDR); 633 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 634 device_printf(dev, "Timeout while waiting for switch\n"); 635 return (ETIMEDOUT); 636 } 637 638 /* Load data and start the C45 write operation. */ 639 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 640 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 641 reg | SMI_CMD_OP_C45_WRITE); 642 643 return (0); 644 } 645 646 /* 647 * PHY registers are paged. Put page index in reg 22 (accessible from every 648 * page), then access specific register. 649 */ 650 static int 651 e6000sw_readphy(device_t dev, int phy, int reg) 652 { 653 e6000sw_softc_t *sc; 654 uint32_t val; 655 656 sc = device_get_softc(dev); 657 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 658 device_printf(dev, "Wrong register address.\n"); 659 return (EINVAL); 660 } 661 662 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 663 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 664 device_printf(dev, "Timeout while waiting for switch\n"); 665 return (ETIMEDOUT); 666 } 667 668 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 669 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 670 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 671 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 672 device_printf(dev, "Timeout while waiting for switch\n"); 673 return (ETIMEDOUT); 674 } 675 676 val = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 677 678 return (val & PHY_DATA_MASK); 679 } 680 681 static int 682 e6000sw_writephy(device_t dev, int phy, int reg, int data) 683 { 684 e6000sw_softc_t *sc; 685 686 sc = device_get_softc(dev); 687 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 688 device_printf(dev, "Wrong register address.\n"); 689 return (EINVAL); 690 } 691 692 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 693 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 694 device_printf(dev, "Timeout while waiting for switch\n"); 695 return (ETIMEDOUT); 696 } 697 698 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, 699 data & PHY_DATA_MASK); 700 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 701 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 702 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 703 704 return (0); 705 } 706 707 static int 708 e6000sw_detach(device_t dev) 709 { 710 int phy; 711 e6000sw_softc_t *sc; 712 713 sc = device_get_softc(dev); 714 bus_generic_detach(dev); 715 sx_destroy(&sc->sx); 716 for (phy = 0; phy < sc->num_ports; phy++) { 717 if (sc->miibus[phy] != NULL) 718 device_delete_child(dev, sc->miibus[phy]); 719 if (sc->ifp[phy] != NULL) 720 if_free(sc->ifp[phy]); 721 if (sc->ifname[phy] != NULL) 722 free(sc->ifname[phy], M_E6000SW); 723 } 724 725 return (0); 726 } 727 728 static etherswitch_info_t* 729 e6000sw_getinfo(device_t dev) 730 { 731 732 return (ðerswitch_info); 733 } 734 735 static int 736 e6000sw_getconf(device_t dev, etherswitch_conf_t *conf) 737 { 738 struct e6000sw_softc *sc; 739 740 /* Return the VLAN mode. */ 741 sc = device_get_softc(dev); 742 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 743 conf->vlan_mode = sc->vlan_mode; 744 745 return (0); 746 } 747 748 static int 749 e6000sw_setconf(device_t dev, etherswitch_conf_t *conf) 750 { 751 struct e6000sw_softc *sc; 752 753 /* Set the VLAN mode. */ 754 sc = device_get_softc(dev); 755 if (conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) { 756 E6000SW_LOCK(sc); 757 e6000sw_set_vlan_mode(sc, conf->vlan_mode); 758 E6000SW_UNLOCK(sc); 759 } 760 761 return (0); 762 } 763 764 static void 765 e6000sw_lock(device_t dev) 766 { 767 struct e6000sw_softc *sc; 768 769 sc = device_get_softc(dev); 770 771 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 772 E6000SW_LOCK(sc); 773 } 774 775 static void 776 e6000sw_unlock(device_t dev) 777 { 778 struct e6000sw_softc *sc; 779 780 sc = device_get_softc(dev); 781 782 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 783 E6000SW_UNLOCK(sc); 784 } 785 786 static int 787 e6000sw_getport(device_t dev, etherswitch_port_t *p) 788 { 789 struct mii_data *mii; 790 int err; 791 struct ifmediareq *ifmr; 792 uint32_t reg; 793 794 e6000sw_softc_t *sc = device_get_softc(dev); 795 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 796 797 if (p->es_port >= sc->num_ports || p->es_port < 0) 798 return (EINVAL); 799 if (!e6000sw_is_portenabled(sc, p->es_port)) 800 return (0); 801 802 E6000SW_LOCK(sc); 803 e6000sw_get_pvid(sc, p->es_port, &p->es_pvid); 804 805 /* Port flags. */ 806 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 807 if (reg & PORT_CONTROL2_DISC_TAGGED) 808 p->es_flags |= ETHERSWITCH_PORT_DROPTAGGED; 809 if (reg & PORT_CONTROL2_DISC_UNTAGGED) 810 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 811 812 err = 0; 813 if (e6000sw_is_fixedport(sc, p->es_port)) { 814 if (e6000sw_is_cpuport(sc, p->es_port)) 815 p->es_flags |= ETHERSWITCH_PORT_CPU; 816 ifmr = &p->es_ifmr; 817 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 818 ifmr->ifm_count = 0; 819 if (e6000sw_is_fixed25port(sc, p->es_port)) 820 ifmr->ifm_active = IFM_2500_T; 821 else 822 ifmr->ifm_active = IFM_1000_T; 823 ifmr->ifm_active |= IFM_ETHER | IFM_FDX; 824 ifmr->ifm_current = ifmr->ifm_active; 825 ifmr->ifm_mask = 0; 826 } else { 827 mii = e6000sw_miiforphy(sc, p->es_port); 828 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, 829 &mii->mii_media, SIOCGIFMEDIA); 830 } 831 E6000SW_UNLOCK(sc); 832 833 return (err); 834 } 835 836 static int 837 e6000sw_setport(device_t dev, etherswitch_port_t *p) 838 { 839 e6000sw_softc_t *sc; 840 int err; 841 struct mii_data *mii; 842 uint32_t reg; 843 844 sc = device_get_softc(dev); 845 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 846 847 if (p->es_port >= sc->num_ports || p->es_port < 0) 848 return (EINVAL); 849 if (!e6000sw_is_portenabled(sc, p->es_port)) 850 return (0); 851 852 /* Port flags. */ 853 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 854 if (p->es_flags & ETHERSWITCH_PORT_DROPTAGGED) 855 reg |= PORT_CONTROL2_DISC_TAGGED; 856 else 857 reg &= ~PORT_CONTROL2_DISC_TAGGED; 858 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 859 reg |= PORT_CONTROL2_DISC_UNTAGGED; 860 else 861 reg &= ~PORT_CONTROL2_DISC_UNTAGGED; 862 e6000sw_writereg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2, reg); 863 864 err = 0; 865 E6000SW_LOCK(sc); 866 if (p->es_pvid != 0) 867 e6000sw_set_pvid(sc, p->es_port, p->es_pvid); 868 if (e6000sw_is_phyport(sc, p->es_port)) { 869 mii = e6000sw_miiforphy(sc, p->es_port); 870 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, &mii->mii_media, 871 SIOCSIFMEDIA); 872 } 873 E6000SW_UNLOCK(sc); 874 875 return (err); 876 } 877 878 static __inline void 879 e6000sw_port_vlan_assign(e6000sw_softc_t *sc, int port, uint32_t fid, 880 uint32_t members) 881 { 882 uint32_t reg; 883 884 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 885 reg &= ~(PORT_MASK(sc) | PORT_VLAN_MAP_FID_MASK); 886 reg |= members & PORT_MASK(sc) & ~(1 << port); 887 reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK; 888 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VLAN_MAP, reg); 889 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 890 reg &= ~PORT_CONTROL1_FID_MASK; 891 reg |= (fid >> 4) & PORT_CONTROL1_FID_MASK; 892 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL1, reg); 893 } 894 895 static int 896 e6000sw_init_vlan(struct e6000sw_softc *sc) 897 { 898 int i, port, ret; 899 uint32_t members; 900 901 /* Disable all ports */ 902 for (port = 0; port < sc->num_ports; port++) { 903 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 904 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 905 (ret & ~PORT_CONTROL_ENABLE)); 906 } 907 908 /* Flush VTU. */ 909 e6000sw_vtu_flush(sc); 910 911 for (port = 0; port < sc->num_ports; port++) { 912 /* Reset the egress and frame mode. */ 913 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 914 ret &= ~(PORT_CONTROL_EGRESS | PORT_CONTROL_FRAME); 915 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, ret); 916 917 /* Set the the 802.1q mode. */ 918 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL2); 919 ret &= ~PORT_CONTROL2_DOT1Q; 920 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 921 ret |= PORT_CONTROL2_DOT1Q; 922 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL2, ret); 923 } 924 925 for (port = 0; port < sc->num_ports; port++) { 926 if (!e6000sw_is_portenabled(sc, port)) 927 continue; 928 929 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 930 931 /* Set port priority */ 932 ret &= ~PORT_VID_PRIORITY_MASK; 933 934 /* Set VID map */ 935 ret &= ~PORT_VID_DEF_VID_MASK; 936 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 937 ret |= 1; 938 else 939 ret |= (port + 1); 940 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, ret); 941 } 942 943 /* Assign the member ports to each origin port. */ 944 for (port = 0; port < sc->num_ports; port++) { 945 members = 0; 946 if (e6000sw_is_portenabled(sc, port)) { 947 for (i = 0; i < sc->num_ports; i++) { 948 if (i == port || !e6000sw_is_portenabled(sc, i)) 949 continue; 950 members |= (1 << i); 951 } 952 } 953 /* Default to FID 0. */ 954 e6000sw_port_vlan_assign(sc, port, 0, members); 955 } 956 957 /* Reset internal VLAN table. */ 958 for (i = 0; i < nitems(sc->vlans); i++) 959 sc->vlans[i] = 0; 960 961 /* Create default VLAN (1). */ 962 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 963 sc->vlans[0] = 1; 964 e6000sw_vtu_update(sc, 0, sc->vlans[0], 1, 0, sc->ports_mask); 965 } 966 967 /* Enable all ports */ 968 for (port = 0; port < sc->num_ports; port++) { 969 if (!e6000sw_is_portenabled(sc, port)) 970 continue; 971 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 972 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 973 (ret | PORT_CONTROL_ENABLE)); 974 } 975 976 return (0); 977 } 978 979 static int 980 e6000sw_set_vlan_mode(struct e6000sw_softc *sc, uint32_t mode) 981 { 982 983 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 984 switch (mode) { 985 case ETHERSWITCH_VLAN_PORT: 986 sc->vlan_mode = ETHERSWITCH_VLAN_PORT; 987 etherswitch_info.es_nvlangroups = sc->num_ports; 988 return (e6000sw_init_vlan(sc)); 989 break; 990 case ETHERSWITCH_VLAN_DOT1Q: 991 sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 992 etherswitch_info.es_nvlangroups = E6000SW_NUM_VLANS; 993 return (e6000sw_init_vlan(sc)); 994 break; 995 default: 996 return (EINVAL); 997 } 998 } 999 1000 /* 1001 * Registers in this switch are divided into sections, specified in 1002 * documentation. So as to access any of them, section index and reg index 1003 * is necessary. etherswitchcfg uses only one variable, so indexes were 1004 * compressed into addr_reg: 32 * section_index + reg_index. 1005 */ 1006 static int 1007 e6000sw_readreg_wrapper(device_t dev, int addr_reg) 1008 { 1009 e6000sw_softc_t *sc; 1010 1011 sc = device_get_softc(dev); 1012 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1013 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1014 device_printf(dev, "Wrong register address.\n"); 1015 return (EINVAL); 1016 } 1017 1018 return (e6000sw_readreg(device_get_softc(dev), addr_reg / 32, 1019 addr_reg % 32)); 1020 } 1021 1022 static int 1023 e6000sw_writereg_wrapper(device_t dev, int addr_reg, int val) 1024 { 1025 e6000sw_softc_t *sc; 1026 1027 sc = device_get_softc(dev); 1028 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1029 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1030 device_printf(dev, "Wrong register address.\n"); 1031 return (EINVAL); 1032 } 1033 e6000sw_writereg(device_get_softc(dev), addr_reg / 5, 1034 addr_reg % 32, val); 1035 1036 return (0); 1037 } 1038 1039 /* 1040 * These wrappers are necessary because PHY accesses from etherswitchcfg 1041 * need to be synchronized with locks, while miibus PHY accesses do not. 1042 */ 1043 static int 1044 e6000sw_readphy_wrapper(device_t dev, int phy, int reg) 1045 { 1046 e6000sw_softc_t *sc; 1047 int ret; 1048 1049 sc = device_get_softc(dev); 1050 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1051 1052 E6000SW_LOCK(sc); 1053 ret = e6000sw_readphy(dev, phy, reg); 1054 E6000SW_UNLOCK(sc); 1055 1056 return (ret); 1057 } 1058 1059 static int 1060 e6000sw_writephy_wrapper(device_t dev, int phy, int reg, int data) 1061 { 1062 e6000sw_softc_t *sc; 1063 int ret; 1064 1065 sc = device_get_softc(dev); 1066 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1067 1068 E6000SW_LOCK(sc); 1069 ret = e6000sw_writephy(dev, phy, reg, data); 1070 E6000SW_UNLOCK(sc); 1071 1072 return (ret); 1073 } 1074 1075 /* 1076 * setvgroup/getvgroup called from etherswitchfcg need to be locked, 1077 * while internal calls do not. 1078 */ 1079 static int 1080 e6000sw_setvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1081 { 1082 e6000sw_softc_t *sc; 1083 int ret; 1084 1085 sc = device_get_softc(dev); 1086 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1087 1088 E6000SW_LOCK(sc); 1089 ret = e6000sw_setvgroup(dev, vg); 1090 E6000SW_UNLOCK(sc); 1091 1092 return (ret); 1093 } 1094 1095 static int 1096 e6000sw_getvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1097 { 1098 e6000sw_softc_t *sc; 1099 int ret; 1100 1101 sc = device_get_softc(dev); 1102 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1103 1104 E6000SW_LOCK(sc); 1105 ret = e6000sw_getvgroup(dev, vg); 1106 E6000SW_UNLOCK(sc); 1107 1108 return (ret); 1109 } 1110 1111 static int 1112 e6000sw_set_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1113 { 1114 uint32_t port; 1115 1116 port = vg->es_vlangroup; 1117 if (port > sc->num_ports) 1118 return (EINVAL); 1119 1120 if (vg->es_member_ports != vg->es_untagged_ports) { 1121 device_printf(sc->dev, "Tagged ports not supported.\n"); 1122 return (EINVAL); 1123 } 1124 1125 e6000sw_port_vlan_assign(sc, port, 0, vg->es_untagged_ports); 1126 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1127 1128 return (0); 1129 } 1130 1131 static int 1132 e6000sw_set_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1133 { 1134 int i, vlan; 1135 1136 vlan = vg->es_vid & ETHERSWITCH_VID_MASK; 1137 1138 /* Set VLAN to '0' removes it from table. */ 1139 if (vlan == 0) { 1140 e6000sw_vtu_update(sc, VTU_PURGE, 1141 sc->vlans[vg->es_vlangroup], 0, 0, 0); 1142 sc->vlans[vg->es_vlangroup] = 0; 1143 return (0); 1144 } 1145 1146 /* Is this VLAN already in table ? */ 1147 for (i = 0; i < etherswitch_info.es_nvlangroups; i++) 1148 if (i != vg->es_vlangroup && vlan == sc->vlans[i]) 1149 return (EINVAL); 1150 1151 sc->vlans[vg->es_vlangroup] = vlan; 1152 e6000sw_vtu_update(sc, 0, vlan, vg->es_vlangroup + 1, 1153 vg->es_member_ports & sc->ports_mask, 1154 vg->es_untagged_ports & sc->ports_mask); 1155 1156 return (0); 1157 } 1158 1159 static int 1160 e6000sw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1161 { 1162 e6000sw_softc_t *sc; 1163 1164 sc = device_get_softc(dev); 1165 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1166 1167 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1168 return (e6000sw_set_port_vlan(sc, vg)); 1169 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1170 return (e6000sw_set_dot1q_vlan(sc, vg)); 1171 1172 return (EINVAL); 1173 } 1174 1175 static int 1176 e6000sw_get_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1177 { 1178 uint32_t port, reg; 1179 1180 port = vg->es_vlangroup; 1181 if (port > sc->num_ports) 1182 return (EINVAL); 1183 1184 if (!e6000sw_is_portenabled(sc, port)) { 1185 vg->es_vid = port; 1186 return (0); 1187 } 1188 1189 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 1190 vg->es_untagged_ports = vg->es_member_ports = reg & PORT_MASK(sc); 1191 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1192 vg->es_fid = (reg & PORT_VLAN_MAP_FID_MASK) >> PORT_VLAN_MAP_FID; 1193 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 1194 vg->es_fid |= (reg & PORT_CONTROL1_FID_MASK) << 4; 1195 1196 return (0); 1197 } 1198 1199 static int 1200 e6000sw_get_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1201 { 1202 int i, port; 1203 uint32_t reg; 1204 1205 vg->es_fid = 0; 1206 vg->es_vid = sc->vlans[vg->es_vlangroup]; 1207 vg->es_untagged_ports = vg->es_member_ports = 0; 1208 if (vg->es_vid == 0) 1209 return (0); 1210 1211 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1212 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1213 return (EBUSY); 1214 } 1215 1216 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, vg->es_vid - 1); 1217 1218 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_OPERATION); 1219 reg &= ~VTU_OP_MASK; 1220 reg |= VTU_GET_NEXT | VTU_BUSY; 1221 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, reg); 1222 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1223 device_printf(sc->dev, "Timeout while reading\n"); 1224 return (EBUSY); 1225 } 1226 1227 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_VID); 1228 if (reg == VTU_VID_MASK || (reg & VTU_VID_VALID) == 0) 1229 return (EINVAL); 1230 if ((reg & VTU_VID_MASK) != vg->es_vid) 1231 return (EINVAL); 1232 1233 vg->es_vid |= ETHERSWITCH_VID_VALID; 1234 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA); 1235 for (i = 0; i < sc->num_ports; i++) { 1236 if (i == VTU_PPREG(sc)) 1237 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA2); 1238 port = (reg >> VTU_PORT(sc, i)) & VTU_PORT_MASK; 1239 if (port == VTU_PORT_UNTAGGED) { 1240 vg->es_untagged_ports |= (1 << i); 1241 vg->es_member_ports |= (1 << i); 1242 } else if (port == VTU_PORT_TAGGED) 1243 vg->es_member_ports |= (1 << i); 1244 } 1245 1246 return (0); 1247 } 1248 1249 static int 1250 e6000sw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1251 { 1252 e6000sw_softc_t *sc; 1253 1254 sc = device_get_softc(dev); 1255 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1256 1257 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1258 return (e6000sw_get_port_vlan(sc, vg)); 1259 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1260 return (e6000sw_get_dot1q_vlan(sc, vg)); 1261 1262 return (EINVAL); 1263 } 1264 1265 static __inline struct mii_data* 1266 e6000sw_miiforphy(e6000sw_softc_t *sc, unsigned int phy) 1267 { 1268 1269 if (!e6000sw_is_phyport(sc, phy)) 1270 return (NULL); 1271 1272 return (device_get_softc(sc->miibus[phy])); 1273 } 1274 1275 static int 1276 e6000sw_ifmedia_upd(struct ifnet *ifp) 1277 { 1278 e6000sw_softc_t *sc; 1279 struct mii_data *mii; 1280 1281 sc = ifp->if_softc; 1282 mii = e6000sw_miiforphy(sc, ifp->if_dunit); 1283 if (mii == NULL) 1284 return (ENXIO); 1285 mii_mediachg(mii); 1286 1287 return (0); 1288 } 1289 1290 static void 1291 e6000sw_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1292 { 1293 e6000sw_softc_t *sc; 1294 struct mii_data *mii; 1295 1296 sc = ifp->if_softc; 1297 mii = e6000sw_miiforphy(sc, ifp->if_dunit); 1298 1299 if (mii == NULL) 1300 return; 1301 1302 mii_pollstat(mii); 1303 ifmr->ifm_active = mii->mii_media_active; 1304 ifmr->ifm_status = mii->mii_media_status; 1305 } 1306 1307 static int 1308 e6000sw_smi_waitready(e6000sw_softc_t *sc, int phy) 1309 { 1310 int i; 1311 1312 for (i = 0; i < E6000SW_SMI_TIMEOUT; i++) { 1313 if ((MDIO_READ(sc->dev, phy, SMI_CMD) & SMI_CMD_BUSY) == 0) 1314 return (0); 1315 DELAY(1); 1316 } 1317 1318 return (1); 1319 } 1320 1321 static __inline uint32_t 1322 e6000sw_readreg(e6000sw_softc_t *sc, int addr, int reg) 1323 { 1324 1325 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1326 1327 if (!MVSWITCH_MULTICHIP(sc)) 1328 return (MDIO_READ(sc->dev, addr, reg) & 0xffff); 1329 1330 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1331 printf("e6000sw: readreg timeout\n"); 1332 return (0xffff); 1333 } 1334 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1335 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 1336 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1337 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1338 printf("e6000sw: readreg timeout\n"); 1339 return (0xffff); 1340 } 1341 1342 return (MDIO_READ(sc->dev, sc->sw_addr, SMI_DATA) & 0xffff); 1343 } 1344 1345 static __inline void 1346 e6000sw_writereg(e6000sw_softc_t *sc, int addr, int reg, int val) 1347 { 1348 1349 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1350 1351 if (!MVSWITCH_MULTICHIP(sc)) { 1352 MDIO_WRITE(sc->dev, addr, reg, val); 1353 return; 1354 } 1355 1356 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1357 printf("e6000sw: readreg timeout\n"); 1358 return; 1359 } 1360 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_DATA, val); 1361 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1362 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 1363 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1364 } 1365 1366 static __inline bool 1367 e6000sw_is_cpuport(e6000sw_softc_t *sc, int port) 1368 { 1369 1370 return ((sc->cpuports_mask & (1 << port)) ? true : false); 1371 } 1372 1373 static __inline bool 1374 e6000sw_is_fixedport(e6000sw_softc_t *sc, int port) 1375 { 1376 1377 return ((sc->fixed_mask & (1 << port)) ? true : false); 1378 } 1379 1380 static __inline bool 1381 e6000sw_is_fixed25port(e6000sw_softc_t *sc, int port) 1382 { 1383 1384 return ((sc->fixed25_mask & (1 << port)) ? true : false); 1385 } 1386 1387 static __inline bool 1388 e6000sw_is_phyport(e6000sw_softc_t *sc, int port) 1389 { 1390 uint32_t phy_mask; 1391 phy_mask = ~(sc->fixed_mask | sc->cpuports_mask); 1392 1393 return ((phy_mask & (1 << port)) ? true : false); 1394 } 1395 1396 static __inline bool 1397 e6000sw_is_portenabled(e6000sw_softc_t *sc, int port) 1398 { 1399 1400 return ((sc->ports_mask & (1 << port)) ? true : false); 1401 } 1402 1403 static __inline void 1404 e6000sw_set_pvid(e6000sw_softc_t *sc, int port, int pvid) 1405 { 1406 uint32_t reg; 1407 1408 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 1409 reg &= ~PORT_VID_DEF_VID_MASK; 1410 reg |= (pvid & PORT_VID_DEF_VID_MASK); 1411 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, reg); 1412 } 1413 1414 static __inline int 1415 e6000sw_get_pvid(e6000sw_softc_t *sc, int port, int *pvid) 1416 { 1417 1418 if (pvid == NULL) 1419 return (ENXIO); 1420 1421 *pvid = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID) & 1422 PORT_VID_DEF_VID_MASK; 1423 1424 return (0); 1425 } 1426 1427 /* 1428 * Convert port status to ifmedia. 1429 */ 1430 static void 1431 e6000sw_update_ifmedia(uint16_t portstatus, u_int *media_status, u_int *media_active) 1432 { 1433 *media_active = IFM_ETHER; 1434 *media_status = IFM_AVALID; 1435 1436 if ((portstatus & PORT_STATUS_LINK_MASK) != 0) 1437 *media_status |= IFM_ACTIVE; 1438 else { 1439 *media_active |= IFM_NONE; 1440 return; 1441 } 1442 1443 switch (portstatus & PORT_STATUS_SPEED_MASK) { 1444 case PORT_STATUS_SPEED_10: 1445 *media_active |= IFM_10_T; 1446 break; 1447 case PORT_STATUS_SPEED_100: 1448 *media_active |= IFM_100_TX; 1449 break; 1450 case PORT_STATUS_SPEED_1000: 1451 *media_active |= IFM_1000_T; 1452 break; 1453 } 1454 1455 if ((portstatus & PORT_STATUS_DUPLEX_MASK) == 0) 1456 *media_active |= IFM_FDX; 1457 else 1458 *media_active |= IFM_HDX; 1459 } 1460 1461 static void 1462 e6000sw_tick(void *arg) 1463 { 1464 e6000sw_softc_t *sc; 1465 struct mii_data *mii; 1466 struct mii_softc *miisc; 1467 uint16_t portstatus; 1468 int port; 1469 1470 sc = arg; 1471 1472 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1473 1474 for (;;) { 1475 E6000SW_LOCK(sc); 1476 for (port = 0; port < sc->num_ports; port++) { 1477 /* Tick only on PHY ports */ 1478 if (!e6000sw_is_portenabled(sc, port) || 1479 !e6000sw_is_phyport(sc, port)) 1480 continue; 1481 1482 mii = e6000sw_miiforphy(sc, port); 1483 if (mii == NULL) 1484 continue; 1485 1486 portstatus = e6000sw_readreg(sc, REG_PORT(sc, port), 1487 PORT_STATUS); 1488 1489 e6000sw_update_ifmedia(portstatus, 1490 &mii->mii_media_status, &mii->mii_media_active); 1491 1492 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1493 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) 1494 != miisc->mii_inst) 1495 continue; 1496 mii_phy_update(miisc, MII_POLLSTAT); 1497 } 1498 } 1499 E6000SW_UNLOCK(sc); 1500 pause("e6000sw tick", 1000); 1501 } 1502 } 1503 1504 static void 1505 e6000sw_setup(device_t dev, e6000sw_softc_t *sc) 1506 { 1507 uint32_t atu_ctrl; 1508 1509 /* Set aging time. */ 1510 atu_ctrl = e6000sw_readreg(sc, REG_GLOBAL, ATU_CONTROL); 1511 atu_ctrl &= ~ATU_CONTROL_AGETIME_MASK; 1512 atu_ctrl |= E6000SW_DEFAULT_AGETIME << ATU_CONTROL_AGETIME; 1513 e6000sw_writereg(sc, REG_GLOBAL, ATU_CONTROL, atu_ctrl); 1514 1515 /* Send all with specific mac address to cpu port */ 1516 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_2x, MGMT_EN_ALL); 1517 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_0x, MGMT_EN_ALL); 1518 1519 /* Disable Remote Management */ 1520 e6000sw_writereg(sc, REG_GLOBAL, SWITCH_GLOBAL_CONTROL2, 0); 1521 1522 /* Disable loopback filter and flow control messages */ 1523 e6000sw_writereg(sc, REG_GLOBAL2, SWITCH_MGMT, 1524 SWITCH_MGMT_PRI_MASK | 1525 (1 << SWITCH_MGMT_RSVD2CPU) | 1526 SWITCH_MGMT_FC_PRI_MASK | 1527 (1 << SWITCH_MGMT_FORCEFLOW)); 1528 1529 e6000sw_atu_flush(dev, sc, NO_OPERATION); 1530 e6000sw_atu_mac_table(dev, sc, NULL, NO_OPERATION); 1531 e6000sw_set_atustat(dev, sc, 0, COUNT_ALL); 1532 } 1533 1534 static void 1535 e6000sw_set_atustat(device_t dev, e6000sw_softc_t *sc, int bin, int flag) 1536 { 1537 uint16_t ret; 1538 1539 ret = e6000sw_readreg(sc, REG_GLOBAL2, ATU_STATS); 1540 e6000sw_writereg(sc, REG_GLOBAL2, ATU_STATS, (bin << ATU_STATS_BIN ) | 1541 (flag << ATU_STATS_FLAG)); 1542 } 1543 1544 static int 1545 e6000sw_atu_mac_table(device_t dev, e6000sw_softc_t *sc, struct atu_opt *atu, 1546 int flag) 1547 { 1548 uint16_t ret_opt; 1549 uint16_t ret_data; 1550 1551 if (flag == NO_OPERATION) 1552 return (0); 1553 else if ((flag & (LOAD_FROM_FIB | PURGE_FROM_FIB | GET_NEXT_IN_FIB | 1554 GET_VIOLATION_DATA | CLEAR_VIOLATION_DATA)) == 0) { 1555 device_printf(dev, "Wrong Opcode for ATU operation\n"); 1556 return (EINVAL); 1557 } 1558 1559 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1560 device_printf(dev, "ATU unit is busy, cannot access\n"); 1561 return (EBUSY); 1562 } 1563 1564 ret_opt = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1565 if (flag & LOAD_FROM_FIB) { 1566 ret_data = e6000sw_readreg(sc, REG_GLOBAL, ATU_DATA); 1567 e6000sw_writereg(sc, REG_GLOBAL2, ATU_DATA, (ret_data & 1568 ~ENTRY_STATE)); 1569 } 1570 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR01, atu->mac_01); 1571 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR23, atu->mac_23); 1572 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR45, atu->mac_45); 1573 e6000sw_writereg(sc, REG_GLOBAL, ATU_FID, atu->fid); 1574 1575 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1576 (ret_opt | ATU_UNIT_BUSY | flag)); 1577 1578 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1579 device_printf(dev, "Timeout while waiting ATU\n"); 1580 else if (flag & GET_NEXT_IN_FIB) { 1581 atu->mac_01 = e6000sw_readreg(sc, REG_GLOBAL, 1582 ATU_MAC_ADDR01); 1583 atu->mac_23 = e6000sw_readreg(sc, REG_GLOBAL, 1584 ATU_MAC_ADDR23); 1585 atu->mac_45 = e6000sw_readreg(sc, REG_GLOBAL, 1586 ATU_MAC_ADDR45); 1587 } 1588 1589 return (0); 1590 } 1591 1592 static int 1593 e6000sw_atu_flush(device_t dev, e6000sw_softc_t *sc, int flag) 1594 { 1595 uint32_t reg; 1596 1597 if (flag == NO_OPERATION) 1598 return (0); 1599 1600 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1601 device_printf(dev, "ATU unit is busy, cannot access\n"); 1602 return (EBUSY); 1603 } 1604 reg = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1605 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1606 (reg | ATU_UNIT_BUSY | flag)); 1607 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1608 device_printf(dev, "Timeout while flushing ATU\n"); 1609 1610 return (0); 1611 } 1612 1613 static int 1614 e6000sw_vtu_flush(e6000sw_softc_t *sc) 1615 { 1616 1617 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1618 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1619 return (EBUSY); 1620 } 1621 1622 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, VTU_FLUSH | VTU_BUSY); 1623 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1624 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1625 return (ETIMEDOUT); 1626 } 1627 1628 return (0); 1629 } 1630 1631 static int 1632 e6000sw_vtu_update(e6000sw_softc_t *sc, int purge, int vid, int fid, 1633 int members, int untagged) 1634 { 1635 int i, op; 1636 uint32_t data[2]; 1637 1638 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1639 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1640 return (EBUSY); 1641 } 1642 1643 *data = (vid & VTU_VID_MASK); 1644 if (purge == 0) 1645 *data |= VTU_VID_VALID; 1646 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, *data); 1647 1648 if (purge == 0) { 1649 data[0] = 0; 1650 data[1] = 0; 1651 for (i = 0; i < sc->num_ports; i++) { 1652 if ((untagged & (1 << i)) != 0) 1653 data[i / VTU_PPREG(sc)] |= 1654 VTU_PORT_UNTAGGED << VTU_PORT(sc, i); 1655 else if ((members & (1 << i)) != 0) 1656 data[i / VTU_PPREG(sc)] |= 1657 VTU_PORT_TAGGED << VTU_PORT(sc, i); 1658 else 1659 data[i / VTU_PPREG(sc)] |= 1660 VTU_PORT_DISCARD << VTU_PORT(sc, i); 1661 } 1662 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA, data[0]); 1663 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA2, data[1]); 1664 e6000sw_writereg(sc, REG_GLOBAL, VTU_FID, 1665 fid & VTU_FID_MASK(sc)); 1666 op = VTU_LOAD; 1667 } else 1668 op = VTU_PURGE; 1669 1670 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, op | VTU_BUSY); 1671 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1672 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1673 return (ETIMEDOUT); 1674 } 1675 1676 return (0); 1677 } 1678