1 /*- 2 * Copyright (c) 2015 Semihalf 3 * Copyright (c) 2015 Stormshield 4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/errno.h> 35 #include <sys/kernel.h> 36 #include <sys/kthread.h> 37 #include <sys/module.h> 38 #include <sys/taskqueue.h> 39 #include <sys/socket.h> 40 #include <sys/sockio.h> 41 42 #include <net/if.h> 43 #include <net/if_media.h> 44 #include <net/if_types.h> 45 46 #include <dev/etherswitch/etherswitch.h> 47 #include <dev/mii/mii.h> 48 #include <dev/mii/miivar.h> 49 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 53 #include "e6000swreg.h" 54 #include "etherswitch_if.h" 55 #include "miibus_if.h" 56 #include "mdio_if.h" 57 58 MALLOC_DECLARE(M_E6000SW); 59 MALLOC_DEFINE(M_E6000SW, "e6000sw", "e6000sw switch"); 60 61 #define E6000SW_LOCK(_sc) sx_xlock(&(_sc)->sx) 62 #define E6000SW_UNLOCK(_sc) sx_unlock(&(_sc)->sx) 63 #define E6000SW_LOCK_ASSERT(_sc, _what) sx_assert(&(_sc)->sx, (_what)) 64 #define E6000SW_TRYLOCK(_sc) sx_tryxlock(&(_sc)->sx) 65 #define E6000SW_WAITREADY(_sc, _reg, _bit) \ 66 e6000sw_waitready((_sc), REG_GLOBAL, (_reg), (_bit)) 67 #define E6000SW_WAITREADY2(_sc, _reg, _bit) \ 68 e6000sw_waitready((_sc), REG_GLOBAL2, (_reg), (_bit)) 69 #define MDIO_READ(dev, addr, reg) \ 70 MDIO_READREG(device_get_parent(dev), (addr), (reg)) 71 #define MDIO_WRITE(dev, addr, reg, val) \ 72 MDIO_WRITEREG(device_get_parent(dev), (addr), (reg), (val)) 73 74 75 typedef struct e6000sw_softc { 76 device_t dev; 77 phandle_t node; 78 79 struct sx sx; 80 struct ifnet *ifp[E6000SW_MAX_PORTS]; 81 char *ifname[E6000SW_MAX_PORTS]; 82 device_t miibus[E6000SW_MAX_PORTS]; 83 struct taskqueue *sc_tq; 84 struct timeout_task sc_tt; 85 86 int vlans[E6000SW_NUM_VLANS]; 87 uint32_t swid; 88 uint32_t vlan_mode; 89 uint32_t cpuports_mask; 90 uint32_t fixed_mask; 91 uint32_t fixed25_mask; 92 uint32_t ports_mask; 93 int phy_base; 94 int sw_addr; 95 int num_ports; 96 } e6000sw_softc_t; 97 98 static etherswitch_info_t etherswitch_info = { 99 .es_nports = 0, 100 .es_nvlangroups = 0, 101 .es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q, 102 .es_name = "Marvell 6000 series switch" 103 }; 104 105 static void e6000sw_identify(driver_t *, device_t); 106 static int e6000sw_probe(device_t); 107 static int e6000sw_parse_fixed_link(e6000sw_softc_t *, phandle_t, uint32_t); 108 static int e6000sw_parse_ethernet(e6000sw_softc_t *, phandle_t, uint32_t); 109 static int e6000sw_attach(device_t); 110 static int e6000sw_detach(device_t); 111 static int e6000sw_read_xmdio(device_t, int, int, int); 112 static int e6000sw_write_xmdio(device_t, int, int, int, int); 113 static int e6000sw_readphy(device_t, int, int); 114 static int e6000sw_writephy(device_t, int, int, int); 115 static int e6000sw_readphy_locked(device_t, int, int); 116 static int e6000sw_writephy_locked(device_t, int, int, int); 117 static etherswitch_info_t* e6000sw_getinfo(device_t); 118 static int e6000sw_getconf(device_t, etherswitch_conf_t *); 119 static int e6000sw_setconf(device_t, etherswitch_conf_t *); 120 static void e6000sw_lock(device_t); 121 static void e6000sw_unlock(device_t); 122 static int e6000sw_getport(device_t, etherswitch_port_t *); 123 static int e6000sw_setport(device_t, etherswitch_port_t *); 124 static int e6000sw_set_vlan_mode(e6000sw_softc_t *, uint32_t); 125 static int e6000sw_readreg_wrapper(device_t, int); 126 static int e6000sw_writereg_wrapper(device_t, int, int); 127 static int e6000sw_getvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 128 static int e6000sw_setvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 129 static int e6000sw_setvgroup(device_t, etherswitch_vlangroup_t *); 130 static int e6000sw_getvgroup(device_t, etherswitch_vlangroup_t *); 131 static void e6000sw_setup(device_t, e6000sw_softc_t *); 132 static void e6000sw_tick(void *, int); 133 static void e6000sw_set_atustat(device_t, e6000sw_softc_t *, int, int); 134 static int e6000sw_atu_flush(device_t, e6000sw_softc_t *, int); 135 static int e6000sw_vtu_flush(e6000sw_softc_t *); 136 static int e6000sw_vtu_update(e6000sw_softc_t *, int, int, int, int, int); 137 static __inline void e6000sw_writereg(e6000sw_softc_t *, int, int, int); 138 static __inline uint32_t e6000sw_readreg(e6000sw_softc_t *, int, int); 139 static int e6000sw_ifmedia_upd(struct ifnet *); 140 static void e6000sw_ifmedia_sts(struct ifnet *, struct ifmediareq *); 141 static int e6000sw_atu_mac_table(device_t, e6000sw_softc_t *, struct atu_opt *, 142 int); 143 static int e6000sw_get_pvid(e6000sw_softc_t *, int, int *); 144 static void e6000sw_set_pvid(e6000sw_softc_t *, int, int); 145 static __inline bool e6000sw_is_cpuport(e6000sw_softc_t *, int); 146 static __inline bool e6000sw_is_fixedport(e6000sw_softc_t *, int); 147 static __inline bool e6000sw_is_fixed25port(e6000sw_softc_t *, int); 148 static __inline bool e6000sw_is_phyport(e6000sw_softc_t *, int); 149 static __inline bool e6000sw_is_portenabled(e6000sw_softc_t *, int); 150 static __inline struct mii_data *e6000sw_miiforphy(e6000sw_softc_t *, 151 unsigned int); 152 153 static device_method_t e6000sw_methods[] = { 154 /* device interface */ 155 DEVMETHOD(device_identify, e6000sw_identify), 156 DEVMETHOD(device_probe, e6000sw_probe), 157 DEVMETHOD(device_attach, e6000sw_attach), 158 DEVMETHOD(device_detach, e6000sw_detach), 159 160 /* bus interface */ 161 DEVMETHOD(bus_add_child, device_add_child_ordered), 162 163 /* mii interface */ 164 DEVMETHOD(miibus_readreg, e6000sw_readphy_locked), 165 DEVMETHOD(miibus_writereg, e6000sw_writephy_locked), 166 167 /* etherswitch interface */ 168 DEVMETHOD(etherswitch_getinfo, e6000sw_getinfo), 169 DEVMETHOD(etherswitch_getconf, e6000sw_getconf), 170 DEVMETHOD(etherswitch_setconf, e6000sw_setconf), 171 DEVMETHOD(etherswitch_lock, e6000sw_lock), 172 DEVMETHOD(etherswitch_unlock, e6000sw_unlock), 173 DEVMETHOD(etherswitch_getport, e6000sw_getport), 174 DEVMETHOD(etherswitch_setport, e6000sw_setport), 175 DEVMETHOD(etherswitch_readreg, e6000sw_readreg_wrapper), 176 DEVMETHOD(etherswitch_writereg, e6000sw_writereg_wrapper), 177 DEVMETHOD(etherswitch_readphyreg, e6000sw_readphy), 178 DEVMETHOD(etherswitch_writephyreg, e6000sw_writephy), 179 DEVMETHOD(etherswitch_setvgroup, e6000sw_setvgroup_wrapper), 180 DEVMETHOD(etherswitch_getvgroup, e6000sw_getvgroup_wrapper), 181 182 DEVMETHOD_END 183 }; 184 185 DEFINE_CLASS_0(e6000sw, e6000sw_driver, e6000sw_methods, 186 sizeof(e6000sw_softc_t)); 187 188 DRIVER_MODULE(e6000sw, mdio, e6000sw_driver, 0, 0); 189 DRIVER_MODULE(etherswitch, e6000sw, etherswitch_driver, 0, 0); 190 DRIVER_MODULE(miibus, e6000sw, miibus_driver, 0, 0); 191 MODULE_DEPEND(e6000sw, mdio, 1, 1, 1); 192 193 194 static void 195 e6000sw_identify(driver_t *driver, device_t parent) 196 { 197 198 if (device_find_child(parent, "e6000sw", -1) == NULL) 199 BUS_ADD_CHILD(parent, 0, "e6000sw", -1); 200 } 201 202 static int 203 e6000sw_probe(device_t dev) 204 { 205 e6000sw_softc_t *sc; 206 const char *description; 207 phandle_t switch_node; 208 209 sc = device_get_softc(dev); 210 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 211 "marvell,mv88e6085"); 212 if (switch_node == 0) { 213 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 214 "marvell,mv88e6190"); 215 216 if (switch_node == 0) 217 return (ENXIO); 218 219 /* 220 * Trust DTS and fix the port register offset for the MV88E6190 221 * detection bellow. 222 */ 223 sc->swid = MV88E6190; 224 } 225 226 if (bootverbose) 227 device_printf(dev, "Found switch_node: 0x%x\n", switch_node); 228 229 sc->dev = dev; 230 sc->node = switch_node; 231 232 if (OF_getencprop(sc->node, "reg", &sc->sw_addr, 233 sizeof(sc->sw_addr)) < 0) 234 return (ENXIO); 235 if (sc->sw_addr < 0 || sc->sw_addr > 32) 236 return (ENXIO); 237 238 /* 239 * Create temporary lock, just to satisfy assertions, 240 * when obtaining the switch ID. Destroy immediately afterwards. 241 */ 242 sx_init(&sc->sx, "e6000sw_tmp"); 243 E6000SW_LOCK(sc); 244 sc->swid = e6000sw_readreg(sc, REG_PORT(sc, 0), SWITCH_ID) & 0xfff0; 245 E6000SW_UNLOCK(sc); 246 sx_destroy(&sc->sx); 247 248 switch (sc->swid) { 249 case MV88E6141: 250 description = "Marvell 88E6141"; 251 sc->phy_base = 0x10; 252 sc->num_ports = 6; 253 break; 254 case MV88E6341: 255 description = "Marvell 88E6341"; 256 sc->phy_base = 0x10; 257 sc->num_ports = 6; 258 break; 259 case MV88E6352: 260 description = "Marvell 88E6352"; 261 sc->num_ports = 7; 262 break; 263 case MV88E6172: 264 description = "Marvell 88E6172"; 265 sc->num_ports = 7; 266 break; 267 case MV88E6176: 268 description = "Marvell 88E6176"; 269 sc->num_ports = 7; 270 break; 271 case MV88E6190: 272 description = "Marvell 88E6190"; 273 sc->num_ports = 11; 274 break; 275 default: 276 device_printf(dev, "Unrecognized device, id 0x%x.\n", sc->swid); 277 return (ENXIO); 278 } 279 280 device_set_desc(dev, description); 281 282 return (BUS_PROBE_DEFAULT); 283 } 284 285 static int 286 e6000sw_parse_fixed_link(e6000sw_softc_t *sc, phandle_t node, uint32_t port) 287 { 288 int speed; 289 phandle_t fixed_link; 290 291 fixed_link = ofw_bus_find_child(node, "fixed-link"); 292 293 if (fixed_link != 0) { 294 sc->fixed_mask |= (1 << port); 295 296 if (OF_getencprop(fixed_link, 297 "speed", &speed, sizeof(speed)) < 0) { 298 device_printf(sc->dev, 299 "Port %d has a fixed-link node without a speed " 300 "property\n", port); 301 return (ENXIO); 302 } 303 if (speed == 2500 && (MVSWITCH(sc, MV88E6141) || 304 MVSWITCH(sc, MV88E6341) || MVSWITCH(sc, MV88E6190))) 305 sc->fixed25_mask |= (1 << port); 306 } 307 308 return (0); 309 } 310 311 static int 312 e6000sw_parse_ethernet(e6000sw_softc_t *sc, phandle_t port_handle, uint32_t port) { 313 phandle_t switch_eth, switch_eth_handle; 314 315 if (OF_getencprop(port_handle, "ethernet", (void*)&switch_eth_handle, 316 sizeof(switch_eth_handle)) > 0) { 317 if (switch_eth_handle > 0) { 318 switch_eth = OF_node_from_xref(switch_eth_handle); 319 320 device_printf(sc->dev, "CPU port at %d\n", port); 321 sc->cpuports_mask |= (1 << port); 322 323 return (e6000sw_parse_fixed_link(sc, switch_eth, port)); 324 } else 325 device_printf(sc->dev, 326 "Port %d has ethernet property but it points " 327 "to an invalid location\n", port); 328 } 329 330 return (0); 331 } 332 333 static int 334 e6000sw_parse_child_fdt(e6000sw_softc_t *sc, phandle_t child, int *pport) 335 { 336 uint32_t port; 337 338 if (pport == NULL) 339 return (ENXIO); 340 341 if (OF_getencprop(child, "reg", (void *)&port, sizeof(port)) < 0) 342 return (ENXIO); 343 if (port >= sc->num_ports) 344 return (ENXIO); 345 *pport = port; 346 347 if (e6000sw_parse_fixed_link(sc, child, port) != 0) 348 return (ENXIO); 349 350 if (e6000sw_parse_ethernet(sc, child, port) != 0) 351 return (ENXIO); 352 353 if ((sc->fixed_mask & (1 << port)) != 0) 354 device_printf(sc->dev, "fixed port at %d\n", port); 355 else 356 device_printf(sc->dev, "PHY at port %d\n", port); 357 358 return (0); 359 } 360 361 static int 362 e6000sw_init_interface(e6000sw_softc_t *sc, int port) 363 { 364 char name[IFNAMSIZ]; 365 366 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->dev)); 367 368 sc->ifp[port] = if_alloc(IFT_ETHER); 369 if (sc->ifp[port] == NULL) 370 return (ENOMEM); 371 sc->ifp[port]->if_softc = sc; 372 sc->ifp[port]->if_flags |= IFF_UP | IFF_BROADCAST | 373 IFF_DRV_RUNNING | IFF_SIMPLEX; 374 sc->ifname[port] = malloc(strlen(name) + 1, M_E6000SW, M_NOWAIT); 375 if (sc->ifname[port] == NULL) { 376 if_free(sc->ifp[port]); 377 return (ENOMEM); 378 } 379 memcpy(sc->ifname[port], name, strlen(name) + 1); 380 if_initname(sc->ifp[port], sc->ifname[port], port); 381 382 return (0); 383 } 384 385 static int 386 e6000sw_attach_miibus(e6000sw_softc_t *sc, int port) 387 { 388 int err; 389 390 err = mii_attach(sc->dev, &sc->miibus[port], sc->ifp[port], 391 e6000sw_ifmedia_upd, e6000sw_ifmedia_sts, BMSR_DEFCAPMASK, 392 port + sc->phy_base, MII_OFFSET_ANY, 0); 393 if (err != 0) 394 return (err); 395 396 return (0); 397 } 398 399 static void 400 e6000sw_serdes_power(device_t dev, int port, bool sgmii) 401 { 402 uint32_t reg; 403 404 /* SGMII */ 405 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 406 E6000SW_SERDES_SGMII_CTL); 407 if (sgmii) 408 reg &= ~E6000SW_SERDES_PDOWN; 409 else 410 reg |= E6000SW_SERDES_PDOWN; 411 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 412 E6000SW_SERDES_SGMII_CTL, reg); 413 414 /* 10GBASE-R/10GBASE-X4/X2 */ 415 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 416 E6000SW_SERDES_PCS_CTL1); 417 if (sgmii) 418 reg |= E6000SW_SERDES_PDOWN; 419 else 420 reg &= ~E6000SW_SERDES_PDOWN; 421 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 422 E6000SW_SERDES_PCS_CTL1, reg); 423 } 424 425 static int 426 e6000sw_attach(device_t dev) 427 { 428 bool sgmii; 429 e6000sw_softc_t *sc; 430 phandle_t child, ports; 431 int err, port; 432 uint32_t reg; 433 434 err = 0; 435 sc = device_get_softc(dev); 436 437 /* 438 * According to the Linux source code, all of the Switch IDs we support 439 * are multi_chip capable, and should go into multi-chip mode if the 440 * sw_addr != 0. 441 */ 442 if (MVSWITCH_MULTICHIP(sc)) 443 device_printf(dev, "multi-chip addressing mode (%#x)\n", 444 sc->sw_addr); 445 else 446 device_printf(dev, "single-chip addressing mode\n"); 447 448 sx_init(&sc->sx, "e6000sw"); 449 450 E6000SW_LOCK(sc); 451 e6000sw_setup(dev, sc); 452 ports = ofw_bus_find_child(sc->node, "ports"); 453 sc->sc_tq = taskqueue_create("e6000sw_taskq", M_NOWAIT, 454 taskqueue_thread_enqueue, &sc->sc_tq); 455 456 TIMEOUT_TASK_INIT(sc->sc_tq, &sc->sc_tt, 0, e6000sw_tick, sc); 457 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 458 device_get_nameunit(dev)); 459 460 if (ports == 0) { 461 device_printf(dev, "failed to parse DTS: no ports found for " 462 "switch\n"); 463 E6000SW_UNLOCK(sc); 464 return (ENXIO); 465 } 466 467 for (child = OF_child(ports); child != 0; child = OF_peer(child)) { 468 err = e6000sw_parse_child_fdt(sc, child, &port); 469 if (err != 0) { 470 device_printf(sc->dev, "failed to parse DTS\n"); 471 goto out_fail; 472 } 473 474 /* Port is in use. */ 475 sc->ports_mask |= (1 << port); 476 477 err = e6000sw_init_interface(sc, port); 478 if (err != 0) { 479 device_printf(sc->dev, "failed to init interface\n"); 480 goto out_fail; 481 } 482 483 if (e6000sw_is_fixedport(sc, port)) { 484 /* Link must be down to change speed force value. */ 485 reg = e6000sw_readreg(sc, REG_PORT(sc, port), 486 PSC_CONTROL); 487 reg &= ~PSC_CONTROL_LINK_UP; 488 reg |= PSC_CONTROL_FORCED_LINK; 489 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 490 reg); 491 492 /* 493 * Force speed, full-duplex, EEE off and flow-control 494 * on. 495 */ 496 reg &= ~(PSC_CONTROL_SPD2500 | PSC_CONTROL_ALT_SPD | 497 PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON | 498 PSC_CONTROL_FORCED_EEE); 499 if (e6000sw_is_fixed25port(sc, port)) 500 reg |= PSC_CONTROL_SPD2500; 501 else 502 reg |= PSC_CONTROL_SPD1000; 503 if (MVSWITCH(sc, MV88E6190) && 504 e6000sw_is_fixed25port(sc, port)) 505 reg |= PSC_CONTROL_ALT_SPD; 506 reg |= PSC_CONTROL_FORCED_DPX | PSC_CONTROL_FULLDPX | 507 PSC_CONTROL_FORCED_LINK | PSC_CONTROL_LINK_UP | 508 PSC_CONTROL_FORCED_SPD; 509 if (!MVSWITCH(sc, MV88E6190)) 510 reg |= PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON; 511 if (MVSWITCH(sc, MV88E6141) || 512 MVSWITCH(sc, MV88E6341) || 513 MVSWITCH(sc, MV88E6190)) 514 reg |= PSC_CONTROL_FORCED_EEE; 515 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 516 reg); 517 /* Power on the SERDES interfaces. */ 518 if (MVSWITCH(sc, MV88E6190) && 519 (port == 9 || port == 10)) { 520 if (e6000sw_is_fixed25port(sc, port)) 521 sgmii = false; 522 else 523 sgmii = true; 524 e6000sw_serdes_power(sc->dev, port, sgmii); 525 } 526 } 527 528 /* Don't attach miibus at CPU/fixed ports */ 529 if (!e6000sw_is_phyport(sc, port)) 530 continue; 531 532 /* 533 * It's necessary to unlock mutex, because e6000sw_attach_miibus 534 * calls functions, which try to lock mutex.That leads 535 * to recursive lock on non recursive mutex. 536 */ 537 E6000SW_UNLOCK(sc); 538 539 err = e6000sw_attach_miibus(sc, port); 540 if (err != 0) { 541 device_printf(sc->dev, "failed to attach miibus\n"); 542 goto out_fail; 543 } 544 545 E6000SW_LOCK(sc); 546 } 547 548 etherswitch_info.es_nports = sc->num_ports; 549 550 /* Default to port vlan. */ 551 e6000sw_set_vlan_mode(sc, ETHERSWITCH_VLAN_PORT); 552 553 reg = e6000sw_readreg(sc, REG_GLOBAL, SWITCH_GLOBAL_STATUS); 554 if (reg & SWITCH_GLOBAL_STATUS_IR) 555 device_printf(dev, "switch is ready.\n"); 556 E6000SW_UNLOCK(sc); 557 558 bus_generic_probe(dev); 559 bus_generic_attach(dev); 560 561 taskqueue_enqueue_timeout(sc->sc_tq, &sc->sc_tt, hz); 562 563 return (0); 564 565 out_fail: 566 e6000sw_detach(dev); 567 568 return (err); 569 } 570 571 static int 572 e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg, 573 uint32_t busybit) 574 { 575 int i; 576 577 for (i = 0; i < E6000SW_RETRIES; i++) { 578 if ((e6000sw_readreg(sc, phy, reg) & busybit) == 0) 579 return (0); 580 DELAY(1); 581 } 582 583 return (1); 584 } 585 586 /* XMDIO/Clause 45 access. */ 587 static int 588 e6000sw_read_xmdio(device_t dev, int phy, int devaddr, int devreg) 589 { 590 e6000sw_softc_t *sc; 591 uint32_t reg; 592 593 sc = device_get_softc(dev); 594 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 595 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 596 device_printf(dev, "Timeout while waiting for switch\n"); 597 return (ETIMEDOUT); 598 } 599 600 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 601 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 602 603 /* Load C45 register address. */ 604 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 605 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 606 reg | SMI_CMD_OP_C45_ADDR); 607 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 608 device_printf(dev, "Timeout while waiting for switch\n"); 609 return (ETIMEDOUT); 610 } 611 612 /* Start C45 read operation. */ 613 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 614 reg | SMI_CMD_OP_C45_READ); 615 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 616 device_printf(dev, "Timeout while waiting for switch\n"); 617 return (ETIMEDOUT); 618 } 619 620 /* Read C45 data. */ 621 reg = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 622 623 return (reg & PHY_DATA_MASK); 624 } 625 626 static int 627 e6000sw_write_xmdio(device_t dev, int phy, int devaddr, int devreg, int val) 628 { 629 e6000sw_softc_t *sc; 630 uint32_t reg; 631 632 sc = device_get_softc(dev); 633 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 634 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 635 device_printf(dev, "Timeout while waiting for switch\n"); 636 return (ETIMEDOUT); 637 } 638 639 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 640 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 641 642 /* Load C45 register address. */ 643 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 644 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 645 reg | SMI_CMD_OP_C45_ADDR); 646 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 647 device_printf(dev, "Timeout while waiting for switch\n"); 648 return (ETIMEDOUT); 649 } 650 651 /* Load data and start the C45 write operation. */ 652 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 653 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 654 reg | SMI_CMD_OP_C45_WRITE); 655 656 return (0); 657 } 658 659 static int e6000sw_readphy(device_t dev, int phy, int reg) 660 { 661 e6000sw_softc_t *sc; 662 int ret; 663 664 sc = device_get_softc(dev); 665 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 666 667 E6000SW_LOCK(sc); 668 ret = e6000sw_readphy_locked(dev, phy, reg); 669 E6000SW_UNLOCK(sc); 670 671 return (ret); 672 } 673 674 /* 675 * PHY registers are paged. Put page index in reg 22 (accessible from every 676 * page), then access specific register. 677 */ 678 static int 679 e6000sw_readphy_locked(device_t dev, int phy, int reg) 680 { 681 e6000sw_softc_t *sc; 682 uint32_t val; 683 684 sc = device_get_softc(dev); 685 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 686 687 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 688 device_printf(dev, "Wrong register address.\n"); 689 return (EINVAL); 690 } 691 692 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 693 device_printf(dev, "Timeout while waiting for switch\n"); 694 return (ETIMEDOUT); 695 } 696 697 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 698 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 699 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 700 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 701 device_printf(dev, "Timeout while waiting for switch\n"); 702 return (ETIMEDOUT); 703 } 704 705 val = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 706 707 return (val & PHY_DATA_MASK); 708 } 709 710 static int e6000sw_writephy(device_t dev, int phy, int reg, int data) 711 { 712 e6000sw_softc_t *sc; 713 int ret; 714 715 sc = device_get_softc(dev); 716 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 717 718 E6000SW_LOCK(sc); 719 ret = e6000sw_writephy_locked(dev, phy, reg, data); 720 E6000SW_UNLOCK(sc); 721 722 return (ret); 723 } 724 725 static int 726 e6000sw_writephy_locked(device_t dev, int phy, int reg, int data) 727 { 728 e6000sw_softc_t *sc; 729 730 sc = device_get_softc(dev); 731 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 732 733 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 734 device_printf(dev, "Wrong register address.\n"); 735 return (EINVAL); 736 } 737 738 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 739 device_printf(dev, "Timeout while waiting for switch\n"); 740 return (ETIMEDOUT); 741 } 742 743 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, 744 data & PHY_DATA_MASK); 745 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 746 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 747 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 748 749 return (0); 750 } 751 752 static int 753 e6000sw_detach(device_t dev) 754 { 755 int phy; 756 e6000sw_softc_t *sc; 757 758 sc = device_get_softc(dev); 759 760 if (device_is_attached(dev)) 761 taskqueue_drain_timeout(sc->sc_tq, &sc->sc_tt); 762 763 if (sc->sc_tq != NULL) 764 taskqueue_free(sc->sc_tq); 765 766 device_delete_children(dev); 767 768 sx_destroy(&sc->sx); 769 for (phy = 0; phy < sc->num_ports; phy++) { 770 if (sc->ifp[phy] != NULL) 771 if_free(sc->ifp[phy]); 772 if (sc->ifname[phy] != NULL) 773 free(sc->ifname[phy], M_E6000SW); 774 } 775 776 return (0); 777 } 778 779 static etherswitch_info_t* 780 e6000sw_getinfo(device_t dev) 781 { 782 783 return (ðerswitch_info); 784 } 785 786 static int 787 e6000sw_getconf(device_t dev, etherswitch_conf_t *conf) 788 { 789 struct e6000sw_softc *sc; 790 791 /* Return the VLAN mode. */ 792 sc = device_get_softc(dev); 793 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 794 conf->vlan_mode = sc->vlan_mode; 795 796 return (0); 797 } 798 799 static int 800 e6000sw_setconf(device_t dev, etherswitch_conf_t *conf) 801 { 802 struct e6000sw_softc *sc; 803 804 /* Set the VLAN mode. */ 805 sc = device_get_softc(dev); 806 if (conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) { 807 E6000SW_LOCK(sc); 808 e6000sw_set_vlan_mode(sc, conf->vlan_mode); 809 E6000SW_UNLOCK(sc); 810 } 811 812 return (0); 813 } 814 815 static void 816 e6000sw_lock(device_t dev) 817 { 818 struct e6000sw_softc *sc; 819 820 sc = device_get_softc(dev); 821 822 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 823 E6000SW_LOCK(sc); 824 } 825 826 static void 827 e6000sw_unlock(device_t dev) 828 { 829 struct e6000sw_softc *sc; 830 831 sc = device_get_softc(dev); 832 833 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 834 E6000SW_UNLOCK(sc); 835 } 836 837 static int 838 e6000sw_getport(device_t dev, etherswitch_port_t *p) 839 { 840 struct mii_data *mii; 841 int err; 842 struct ifmediareq *ifmr; 843 uint32_t reg; 844 845 e6000sw_softc_t *sc = device_get_softc(dev); 846 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 847 848 if (p->es_port >= sc->num_ports || p->es_port < 0) 849 return (EINVAL); 850 if (!e6000sw_is_portenabled(sc, p->es_port)) 851 return (0); 852 853 E6000SW_LOCK(sc); 854 e6000sw_get_pvid(sc, p->es_port, &p->es_pvid); 855 856 /* Port flags. */ 857 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 858 if (reg & PORT_CONTROL2_DISC_TAGGED) 859 p->es_flags |= ETHERSWITCH_PORT_DROPTAGGED; 860 if (reg & PORT_CONTROL2_DISC_UNTAGGED) 861 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 862 863 err = 0; 864 if (e6000sw_is_fixedport(sc, p->es_port)) { 865 if (e6000sw_is_cpuport(sc, p->es_port)) 866 p->es_flags |= ETHERSWITCH_PORT_CPU; 867 ifmr = &p->es_ifmr; 868 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 869 ifmr->ifm_count = 0; 870 if (e6000sw_is_fixed25port(sc, p->es_port)) 871 ifmr->ifm_active = IFM_2500_T; 872 else 873 ifmr->ifm_active = IFM_1000_T; 874 ifmr->ifm_active |= IFM_ETHER | IFM_FDX; 875 ifmr->ifm_current = ifmr->ifm_active; 876 ifmr->ifm_mask = 0; 877 } else { 878 mii = e6000sw_miiforphy(sc, p->es_port); 879 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, 880 &mii->mii_media, SIOCGIFMEDIA); 881 } 882 E6000SW_UNLOCK(sc); 883 884 return (err); 885 } 886 887 static int 888 e6000sw_setport(device_t dev, etherswitch_port_t *p) 889 { 890 e6000sw_softc_t *sc; 891 int err; 892 struct mii_data *mii; 893 uint32_t reg; 894 895 sc = device_get_softc(dev); 896 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 897 898 if (p->es_port >= sc->num_ports || p->es_port < 0) 899 return (EINVAL); 900 if (!e6000sw_is_portenabled(sc, p->es_port)) 901 return (0); 902 903 E6000SW_LOCK(sc); 904 905 /* Port flags. */ 906 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 907 if (p->es_flags & ETHERSWITCH_PORT_DROPTAGGED) 908 reg |= PORT_CONTROL2_DISC_TAGGED; 909 else 910 reg &= ~PORT_CONTROL2_DISC_TAGGED; 911 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 912 reg |= PORT_CONTROL2_DISC_UNTAGGED; 913 else 914 reg &= ~PORT_CONTROL2_DISC_UNTAGGED; 915 e6000sw_writereg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2, reg); 916 917 err = 0; 918 if (p->es_pvid != 0) 919 e6000sw_set_pvid(sc, p->es_port, p->es_pvid); 920 if (e6000sw_is_phyport(sc, p->es_port)) { 921 mii = e6000sw_miiforphy(sc, p->es_port); 922 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, &mii->mii_media, 923 SIOCSIFMEDIA); 924 } 925 E6000SW_UNLOCK(sc); 926 927 return (err); 928 } 929 930 static __inline void 931 e6000sw_port_vlan_assign(e6000sw_softc_t *sc, int port, uint32_t fid, 932 uint32_t members) 933 { 934 uint32_t reg; 935 936 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 937 reg &= ~(PORT_MASK(sc) | PORT_VLAN_MAP_FID_MASK); 938 reg |= members & PORT_MASK(sc) & ~(1 << port); 939 reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK; 940 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VLAN_MAP, reg); 941 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 942 reg &= ~PORT_CONTROL1_FID_MASK; 943 reg |= (fid >> 4) & PORT_CONTROL1_FID_MASK; 944 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL1, reg); 945 } 946 947 static int 948 e6000sw_init_vlan(struct e6000sw_softc *sc) 949 { 950 int i, port, ret; 951 uint32_t members; 952 953 /* Disable all ports */ 954 for (port = 0; port < sc->num_ports; port++) { 955 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 956 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 957 (ret & ~PORT_CONTROL_ENABLE)); 958 } 959 960 /* Flush VTU. */ 961 e6000sw_vtu_flush(sc); 962 963 for (port = 0; port < sc->num_ports; port++) { 964 /* Reset the egress and frame mode. */ 965 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 966 ret &= ~(PORT_CONTROL_EGRESS | PORT_CONTROL_FRAME); 967 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, ret); 968 969 /* Set the the 802.1q mode. */ 970 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL2); 971 ret &= ~PORT_CONTROL2_DOT1Q; 972 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 973 ret |= PORT_CONTROL2_DOT1Q; 974 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL2, ret); 975 } 976 977 for (port = 0; port < sc->num_ports; port++) { 978 if (!e6000sw_is_portenabled(sc, port)) 979 continue; 980 981 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 982 983 /* Set port priority */ 984 ret &= ~PORT_VID_PRIORITY_MASK; 985 986 /* Set VID map */ 987 ret &= ~PORT_VID_DEF_VID_MASK; 988 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 989 ret |= 1; 990 else 991 ret |= (port + 1); 992 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, ret); 993 } 994 995 /* Assign the member ports to each origin port. */ 996 for (port = 0; port < sc->num_ports; port++) { 997 members = 0; 998 if (e6000sw_is_portenabled(sc, port)) { 999 for (i = 0; i < sc->num_ports; i++) { 1000 if (i == port || !e6000sw_is_portenabled(sc, i)) 1001 continue; 1002 members |= (1 << i); 1003 } 1004 } 1005 /* Default to FID 0. */ 1006 e6000sw_port_vlan_assign(sc, port, 0, members); 1007 } 1008 1009 /* Reset internal VLAN table. */ 1010 for (i = 0; i < nitems(sc->vlans); i++) 1011 sc->vlans[i] = 0; 1012 1013 /* Create default VLAN (1). */ 1014 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 1015 sc->vlans[0] = 1; 1016 e6000sw_vtu_update(sc, 0, sc->vlans[0], 1, 0, sc->ports_mask); 1017 } 1018 1019 /* Enable all ports */ 1020 for (port = 0; port < sc->num_ports; port++) { 1021 if (!e6000sw_is_portenabled(sc, port)) 1022 continue; 1023 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 1024 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 1025 (ret | PORT_CONTROL_ENABLE)); 1026 } 1027 1028 return (0); 1029 } 1030 1031 static int 1032 e6000sw_set_vlan_mode(struct e6000sw_softc *sc, uint32_t mode) 1033 { 1034 1035 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1036 switch (mode) { 1037 case ETHERSWITCH_VLAN_PORT: 1038 sc->vlan_mode = ETHERSWITCH_VLAN_PORT; 1039 etherswitch_info.es_nvlangroups = sc->num_ports; 1040 return (e6000sw_init_vlan(sc)); 1041 break; 1042 case ETHERSWITCH_VLAN_DOT1Q: 1043 sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 1044 etherswitch_info.es_nvlangroups = E6000SW_NUM_VLANS; 1045 return (e6000sw_init_vlan(sc)); 1046 break; 1047 default: 1048 return (EINVAL); 1049 } 1050 } 1051 1052 /* 1053 * Registers in this switch are divided into sections, specified in 1054 * documentation. So as to access any of them, section index and reg index 1055 * is necessary. etherswitchcfg uses only one variable, so indexes were 1056 * compressed into addr_reg: 32 * section_index + reg_index. 1057 */ 1058 static int 1059 e6000sw_readreg_wrapper(device_t dev, int addr_reg) 1060 { 1061 e6000sw_softc_t *sc; 1062 1063 sc = device_get_softc(dev); 1064 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1065 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1066 device_printf(dev, "Wrong register address.\n"); 1067 return (EINVAL); 1068 } 1069 1070 return (e6000sw_readreg(device_get_softc(dev), addr_reg / 32, 1071 addr_reg % 32)); 1072 } 1073 1074 static int 1075 e6000sw_writereg_wrapper(device_t dev, int addr_reg, int val) 1076 { 1077 e6000sw_softc_t *sc; 1078 1079 sc = device_get_softc(dev); 1080 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1081 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1082 device_printf(dev, "Wrong register address.\n"); 1083 return (EINVAL); 1084 } 1085 e6000sw_writereg(device_get_softc(dev), addr_reg / 32, 1086 addr_reg % 32, val); 1087 1088 return (0); 1089 } 1090 1091 /* 1092 * setvgroup/getvgroup called from etherswitchfcg need to be locked, 1093 * while internal calls do not. 1094 */ 1095 static int 1096 e6000sw_setvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1097 { 1098 e6000sw_softc_t *sc; 1099 int ret; 1100 1101 sc = device_get_softc(dev); 1102 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1103 1104 E6000SW_LOCK(sc); 1105 ret = e6000sw_setvgroup(dev, vg); 1106 E6000SW_UNLOCK(sc); 1107 1108 return (ret); 1109 } 1110 1111 static int 1112 e6000sw_getvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1113 { 1114 e6000sw_softc_t *sc; 1115 int ret; 1116 1117 sc = device_get_softc(dev); 1118 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1119 1120 E6000SW_LOCK(sc); 1121 ret = e6000sw_getvgroup(dev, vg); 1122 E6000SW_UNLOCK(sc); 1123 1124 return (ret); 1125 } 1126 1127 static int 1128 e6000sw_set_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1129 { 1130 uint32_t port; 1131 1132 port = vg->es_vlangroup; 1133 if (port > sc->num_ports) 1134 return (EINVAL); 1135 1136 if (vg->es_member_ports != vg->es_untagged_ports) { 1137 device_printf(sc->dev, "Tagged ports not supported.\n"); 1138 return (EINVAL); 1139 } 1140 1141 e6000sw_port_vlan_assign(sc, port, 0, vg->es_untagged_ports); 1142 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1143 1144 return (0); 1145 } 1146 1147 static int 1148 e6000sw_set_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1149 { 1150 int i, vlan; 1151 1152 vlan = vg->es_vid & ETHERSWITCH_VID_MASK; 1153 1154 /* Set VLAN to '0' removes it from table. */ 1155 if (vlan == 0) { 1156 e6000sw_vtu_update(sc, VTU_PURGE, 1157 sc->vlans[vg->es_vlangroup], 0, 0, 0); 1158 sc->vlans[vg->es_vlangroup] = 0; 1159 return (0); 1160 } 1161 1162 /* Is this VLAN already in table ? */ 1163 for (i = 0; i < etherswitch_info.es_nvlangroups; i++) 1164 if (i != vg->es_vlangroup && vlan == sc->vlans[i]) 1165 return (EINVAL); 1166 1167 sc->vlans[vg->es_vlangroup] = vlan; 1168 e6000sw_vtu_update(sc, 0, vlan, vg->es_vlangroup + 1, 1169 vg->es_member_ports & sc->ports_mask, 1170 vg->es_untagged_ports & sc->ports_mask); 1171 1172 return (0); 1173 } 1174 1175 static int 1176 e6000sw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1177 { 1178 e6000sw_softc_t *sc; 1179 1180 sc = device_get_softc(dev); 1181 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1182 1183 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1184 return (e6000sw_set_port_vlan(sc, vg)); 1185 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1186 return (e6000sw_set_dot1q_vlan(sc, vg)); 1187 1188 return (EINVAL); 1189 } 1190 1191 static int 1192 e6000sw_get_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1193 { 1194 uint32_t port, reg; 1195 1196 port = vg->es_vlangroup; 1197 if (port > sc->num_ports) 1198 return (EINVAL); 1199 1200 if (!e6000sw_is_portenabled(sc, port)) { 1201 vg->es_vid = port; 1202 return (0); 1203 } 1204 1205 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 1206 vg->es_untagged_ports = vg->es_member_ports = reg & PORT_MASK(sc); 1207 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1208 vg->es_fid = (reg & PORT_VLAN_MAP_FID_MASK) >> PORT_VLAN_MAP_FID; 1209 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 1210 vg->es_fid |= (reg & PORT_CONTROL1_FID_MASK) << 4; 1211 1212 return (0); 1213 } 1214 1215 static int 1216 e6000sw_get_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1217 { 1218 int i, port; 1219 uint32_t reg; 1220 1221 vg->es_fid = 0; 1222 vg->es_vid = sc->vlans[vg->es_vlangroup]; 1223 vg->es_untagged_ports = vg->es_member_ports = 0; 1224 if (vg->es_vid == 0) 1225 return (0); 1226 1227 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1228 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1229 return (EBUSY); 1230 } 1231 1232 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, vg->es_vid - 1); 1233 1234 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_OPERATION); 1235 reg &= ~VTU_OP_MASK; 1236 reg |= VTU_GET_NEXT | VTU_BUSY; 1237 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, reg); 1238 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1239 device_printf(sc->dev, "Timeout while reading\n"); 1240 return (EBUSY); 1241 } 1242 1243 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_VID); 1244 if (reg == VTU_VID_MASK || (reg & VTU_VID_VALID) == 0) 1245 return (EINVAL); 1246 if ((reg & VTU_VID_MASK) != vg->es_vid) 1247 return (EINVAL); 1248 1249 vg->es_vid |= ETHERSWITCH_VID_VALID; 1250 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA); 1251 for (i = 0; i < sc->num_ports; i++) { 1252 if (i == VTU_PPREG(sc)) 1253 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA2); 1254 port = (reg >> VTU_PORT(sc, i)) & VTU_PORT_MASK; 1255 if (port == VTU_PORT_UNTAGGED) { 1256 vg->es_untagged_ports |= (1 << i); 1257 vg->es_member_ports |= (1 << i); 1258 } else if (port == VTU_PORT_TAGGED) 1259 vg->es_member_ports |= (1 << i); 1260 } 1261 1262 return (0); 1263 } 1264 1265 static int 1266 e6000sw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1267 { 1268 e6000sw_softc_t *sc; 1269 1270 sc = device_get_softc(dev); 1271 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1272 1273 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1274 return (e6000sw_get_port_vlan(sc, vg)); 1275 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1276 return (e6000sw_get_dot1q_vlan(sc, vg)); 1277 1278 return (EINVAL); 1279 } 1280 1281 static __inline struct mii_data* 1282 e6000sw_miiforphy(e6000sw_softc_t *sc, unsigned int phy) 1283 { 1284 1285 if (!e6000sw_is_phyport(sc, phy)) 1286 return (NULL); 1287 1288 return (device_get_softc(sc->miibus[phy])); 1289 } 1290 1291 static int 1292 e6000sw_ifmedia_upd(struct ifnet *ifp) 1293 { 1294 e6000sw_softc_t *sc; 1295 struct mii_data *mii; 1296 1297 sc = ifp->if_softc; 1298 mii = e6000sw_miiforphy(sc, ifp->if_dunit); 1299 if (mii == NULL) 1300 return (ENXIO); 1301 mii_mediachg(mii); 1302 1303 return (0); 1304 } 1305 1306 static void 1307 e6000sw_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1308 { 1309 e6000sw_softc_t *sc; 1310 struct mii_data *mii; 1311 1312 sc = ifp->if_softc; 1313 mii = e6000sw_miiforphy(sc, ifp->if_dunit); 1314 1315 if (mii == NULL) 1316 return; 1317 1318 mii_pollstat(mii); 1319 ifmr->ifm_active = mii->mii_media_active; 1320 ifmr->ifm_status = mii->mii_media_status; 1321 } 1322 1323 static int 1324 e6000sw_smi_waitready(e6000sw_softc_t *sc, int phy) 1325 { 1326 int i; 1327 1328 for (i = 0; i < E6000SW_SMI_TIMEOUT; i++) { 1329 if ((MDIO_READ(sc->dev, phy, SMI_CMD) & SMI_CMD_BUSY) == 0) 1330 return (0); 1331 DELAY(1); 1332 } 1333 1334 return (1); 1335 } 1336 1337 static __inline uint32_t 1338 e6000sw_readreg(e6000sw_softc_t *sc, int addr, int reg) 1339 { 1340 1341 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1342 1343 if (!MVSWITCH_MULTICHIP(sc)) 1344 return (MDIO_READ(sc->dev, addr, reg) & 0xffff); 1345 1346 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1347 printf("e6000sw: readreg timeout\n"); 1348 return (0xffff); 1349 } 1350 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1351 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 1352 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1353 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1354 printf("e6000sw: readreg timeout\n"); 1355 return (0xffff); 1356 } 1357 1358 return (MDIO_READ(sc->dev, sc->sw_addr, SMI_DATA) & 0xffff); 1359 } 1360 1361 static __inline void 1362 e6000sw_writereg(e6000sw_softc_t *sc, int addr, int reg, int val) 1363 { 1364 1365 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1366 1367 if (!MVSWITCH_MULTICHIP(sc)) { 1368 MDIO_WRITE(sc->dev, addr, reg, val); 1369 return; 1370 } 1371 1372 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1373 printf("e6000sw: readreg timeout\n"); 1374 return; 1375 } 1376 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_DATA, val); 1377 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1378 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 1379 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1380 } 1381 1382 static __inline bool 1383 e6000sw_is_cpuport(e6000sw_softc_t *sc, int port) 1384 { 1385 1386 return ((sc->cpuports_mask & (1 << port)) ? true : false); 1387 } 1388 1389 static __inline bool 1390 e6000sw_is_fixedport(e6000sw_softc_t *sc, int port) 1391 { 1392 1393 return ((sc->fixed_mask & (1 << port)) ? true : false); 1394 } 1395 1396 static __inline bool 1397 e6000sw_is_fixed25port(e6000sw_softc_t *sc, int port) 1398 { 1399 1400 return ((sc->fixed25_mask & (1 << port)) ? true : false); 1401 } 1402 1403 static __inline bool 1404 e6000sw_is_phyport(e6000sw_softc_t *sc, int port) 1405 { 1406 uint32_t phy_mask; 1407 phy_mask = ~(sc->fixed_mask | sc->cpuports_mask); 1408 1409 return ((phy_mask & (1 << port)) ? true : false); 1410 } 1411 1412 static __inline bool 1413 e6000sw_is_portenabled(e6000sw_softc_t *sc, int port) 1414 { 1415 1416 return ((sc->ports_mask & (1 << port)) ? true : false); 1417 } 1418 1419 static __inline void 1420 e6000sw_set_pvid(e6000sw_softc_t *sc, int port, int pvid) 1421 { 1422 uint32_t reg; 1423 1424 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 1425 reg &= ~PORT_VID_DEF_VID_MASK; 1426 reg |= (pvid & PORT_VID_DEF_VID_MASK); 1427 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, reg); 1428 } 1429 1430 static __inline int 1431 e6000sw_get_pvid(e6000sw_softc_t *sc, int port, int *pvid) 1432 { 1433 1434 if (pvid == NULL) 1435 return (ENXIO); 1436 1437 *pvid = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID) & 1438 PORT_VID_DEF_VID_MASK; 1439 1440 return (0); 1441 } 1442 1443 /* 1444 * Convert port status to ifmedia. 1445 */ 1446 static void 1447 e6000sw_update_ifmedia(uint16_t portstatus, u_int *media_status, u_int *media_active) 1448 { 1449 *media_active = IFM_ETHER; 1450 *media_status = IFM_AVALID; 1451 1452 if ((portstatus & PORT_STATUS_LINK_MASK) != 0) 1453 *media_status |= IFM_ACTIVE; 1454 else { 1455 *media_active |= IFM_NONE; 1456 return; 1457 } 1458 1459 switch (portstatus & PORT_STATUS_SPEED_MASK) { 1460 case PORT_STATUS_SPEED_10: 1461 *media_active |= IFM_10_T; 1462 break; 1463 case PORT_STATUS_SPEED_100: 1464 *media_active |= IFM_100_TX; 1465 break; 1466 case PORT_STATUS_SPEED_1000: 1467 *media_active |= IFM_1000_T; 1468 break; 1469 } 1470 1471 if ((portstatus & PORT_STATUS_DUPLEX_MASK) == 0) 1472 *media_active |= IFM_FDX; 1473 else 1474 *media_active |= IFM_HDX; 1475 } 1476 1477 static void 1478 e6000sw_tick(void *arg, int p __unused) 1479 { 1480 e6000sw_softc_t *sc; 1481 struct mii_data *mii; 1482 struct mii_softc *miisc; 1483 uint16_t portstatus; 1484 int port; 1485 1486 sc = arg; 1487 1488 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1489 1490 E6000SW_LOCK(sc); 1491 for (port = 0; port < sc->num_ports; port++) { 1492 /* Tick only on PHY ports */ 1493 if (!e6000sw_is_portenabled(sc, port) || 1494 !e6000sw_is_phyport(sc, port)) 1495 continue; 1496 1497 mii = e6000sw_miiforphy(sc, port); 1498 if (mii == NULL) 1499 continue; 1500 1501 portstatus = e6000sw_readreg(sc, REG_PORT(sc, port), 1502 PORT_STATUS); 1503 1504 e6000sw_update_ifmedia(portstatus, 1505 &mii->mii_media_status, &mii->mii_media_active); 1506 1507 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1508 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) 1509 != miisc->mii_inst) 1510 continue; 1511 mii_phy_update(miisc, MII_POLLSTAT); 1512 } 1513 } 1514 E6000SW_UNLOCK(sc); 1515 } 1516 1517 static void 1518 e6000sw_setup(device_t dev, e6000sw_softc_t *sc) 1519 { 1520 uint32_t atu_ctrl; 1521 1522 /* Set aging time. */ 1523 atu_ctrl = e6000sw_readreg(sc, REG_GLOBAL, ATU_CONTROL); 1524 atu_ctrl &= ~ATU_CONTROL_AGETIME_MASK; 1525 atu_ctrl |= E6000SW_DEFAULT_AGETIME << ATU_CONTROL_AGETIME; 1526 e6000sw_writereg(sc, REG_GLOBAL, ATU_CONTROL, atu_ctrl); 1527 1528 /* Send all with specific mac address to cpu port */ 1529 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_2x, MGMT_EN_ALL); 1530 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_0x, MGMT_EN_ALL); 1531 1532 /* Disable Remote Management */ 1533 e6000sw_writereg(sc, REG_GLOBAL, SWITCH_GLOBAL_CONTROL2, 0); 1534 1535 /* Disable loopback filter and flow control messages */ 1536 e6000sw_writereg(sc, REG_GLOBAL2, SWITCH_MGMT, 1537 SWITCH_MGMT_PRI_MASK | 1538 (1 << SWITCH_MGMT_RSVD2CPU) | 1539 SWITCH_MGMT_FC_PRI_MASK | 1540 (1 << SWITCH_MGMT_FORCEFLOW)); 1541 1542 e6000sw_atu_flush(dev, sc, NO_OPERATION); 1543 e6000sw_atu_mac_table(dev, sc, NULL, NO_OPERATION); 1544 e6000sw_set_atustat(dev, sc, 0, COUNT_ALL); 1545 } 1546 1547 static void 1548 e6000sw_set_atustat(device_t dev, e6000sw_softc_t *sc, int bin, int flag) 1549 { 1550 1551 e6000sw_readreg(sc, REG_GLOBAL2, ATU_STATS); 1552 e6000sw_writereg(sc, REG_GLOBAL2, ATU_STATS, (bin << ATU_STATS_BIN ) | 1553 (flag << ATU_STATS_FLAG)); 1554 } 1555 1556 static int 1557 e6000sw_atu_mac_table(device_t dev, e6000sw_softc_t *sc, struct atu_opt *atu, 1558 int flag) 1559 { 1560 uint16_t ret_opt; 1561 uint16_t ret_data; 1562 1563 if (flag == NO_OPERATION) 1564 return (0); 1565 else if ((flag & (LOAD_FROM_FIB | PURGE_FROM_FIB | GET_NEXT_IN_FIB | 1566 GET_VIOLATION_DATA | CLEAR_VIOLATION_DATA)) == 0) { 1567 device_printf(dev, "Wrong Opcode for ATU operation\n"); 1568 return (EINVAL); 1569 } 1570 1571 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1572 device_printf(dev, "ATU unit is busy, cannot access\n"); 1573 return (EBUSY); 1574 } 1575 1576 ret_opt = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1577 if (flag & LOAD_FROM_FIB) { 1578 ret_data = e6000sw_readreg(sc, REG_GLOBAL, ATU_DATA); 1579 e6000sw_writereg(sc, REG_GLOBAL2, ATU_DATA, (ret_data & 1580 ~ENTRY_STATE)); 1581 } 1582 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR01, atu->mac_01); 1583 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR23, atu->mac_23); 1584 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR45, atu->mac_45); 1585 e6000sw_writereg(sc, REG_GLOBAL, ATU_FID, atu->fid); 1586 1587 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1588 (ret_opt | ATU_UNIT_BUSY | flag)); 1589 1590 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1591 device_printf(dev, "Timeout while waiting ATU\n"); 1592 else if (flag & GET_NEXT_IN_FIB) { 1593 atu->mac_01 = e6000sw_readreg(sc, REG_GLOBAL, 1594 ATU_MAC_ADDR01); 1595 atu->mac_23 = e6000sw_readreg(sc, REG_GLOBAL, 1596 ATU_MAC_ADDR23); 1597 atu->mac_45 = e6000sw_readreg(sc, REG_GLOBAL, 1598 ATU_MAC_ADDR45); 1599 } 1600 1601 return (0); 1602 } 1603 1604 static int 1605 e6000sw_atu_flush(device_t dev, e6000sw_softc_t *sc, int flag) 1606 { 1607 uint32_t reg; 1608 1609 if (flag == NO_OPERATION) 1610 return (0); 1611 1612 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1613 device_printf(dev, "ATU unit is busy, cannot access\n"); 1614 return (EBUSY); 1615 } 1616 reg = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1617 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1618 (reg | ATU_UNIT_BUSY | flag)); 1619 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1620 device_printf(dev, "Timeout while flushing ATU\n"); 1621 1622 return (0); 1623 } 1624 1625 static int 1626 e6000sw_vtu_flush(e6000sw_softc_t *sc) 1627 { 1628 1629 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1630 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1631 return (EBUSY); 1632 } 1633 1634 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, VTU_FLUSH | VTU_BUSY); 1635 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1636 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1637 return (ETIMEDOUT); 1638 } 1639 1640 return (0); 1641 } 1642 1643 static int 1644 e6000sw_vtu_update(e6000sw_softc_t *sc, int purge, int vid, int fid, 1645 int members, int untagged) 1646 { 1647 int i, op; 1648 uint32_t data[2]; 1649 1650 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1651 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1652 return (EBUSY); 1653 } 1654 1655 *data = (vid & VTU_VID_MASK); 1656 if (purge == 0) 1657 *data |= VTU_VID_VALID; 1658 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, *data); 1659 1660 if (purge == 0) { 1661 data[0] = 0; 1662 data[1] = 0; 1663 for (i = 0; i < sc->num_ports; i++) { 1664 if ((untagged & (1 << i)) != 0) 1665 data[i / VTU_PPREG(sc)] |= 1666 VTU_PORT_UNTAGGED << VTU_PORT(sc, i); 1667 else if ((members & (1 << i)) != 0) 1668 data[i / VTU_PPREG(sc)] |= 1669 VTU_PORT_TAGGED << VTU_PORT(sc, i); 1670 else 1671 data[i / VTU_PPREG(sc)] |= 1672 VTU_PORT_DISCARD << VTU_PORT(sc, i); 1673 } 1674 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA, data[0]); 1675 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA2, data[1]); 1676 e6000sw_writereg(sc, REG_GLOBAL, VTU_FID, 1677 fid & VTU_FID_MASK(sc)); 1678 op = VTU_LOAD; 1679 } else 1680 op = VTU_PURGE; 1681 1682 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, op | VTU_BUSY); 1683 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1684 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1685 return (ETIMEDOUT); 1686 } 1687 1688 return (0); 1689 } 1690