1 /*- 2 * Copyright (c) 2015 Semihalf 3 * Copyright (c) 2015 Stormshield 4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/errno.h> 33 #include <sys/kernel.h> 34 #include <sys/kthread.h> 35 #include <sys/module.h> 36 #include <sys/taskqueue.h> 37 #include <sys/socket.h> 38 #include <sys/sockio.h> 39 40 #include <net/if.h> 41 #include <net/if_media.h> 42 #include <net/if_types.h> 43 44 #include <dev/etherswitch/etherswitch.h> 45 #include <dev/mii/mii.h> 46 #include <dev/mii/miivar.h> 47 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include "e6000swreg.h" 52 #include "etherswitch_if.h" 53 #include "miibus_if.h" 54 #include "mdio_if.h" 55 56 MALLOC_DECLARE(M_E6000SW); 57 MALLOC_DEFINE(M_E6000SW, "e6000sw", "e6000sw switch"); 58 59 #define E6000SW_LOCK(_sc) sx_xlock(&(_sc)->sx) 60 #define E6000SW_UNLOCK(_sc) sx_unlock(&(_sc)->sx) 61 #define E6000SW_LOCK_ASSERT(_sc, _what) sx_assert(&(_sc)->sx, (_what)) 62 #define E6000SW_TRYLOCK(_sc) sx_tryxlock(&(_sc)->sx) 63 #define E6000SW_WAITREADY(_sc, _reg, _bit) \ 64 e6000sw_waitready((_sc), REG_GLOBAL, (_reg), (_bit)) 65 #define E6000SW_WAITREADY2(_sc, _reg, _bit) \ 66 e6000sw_waitready((_sc), REG_GLOBAL2, (_reg), (_bit)) 67 #define MDIO_READ(dev, addr, reg) \ 68 MDIO_READREG(device_get_parent(dev), (addr), (reg)) 69 #define MDIO_WRITE(dev, addr, reg, val) \ 70 MDIO_WRITEREG(device_get_parent(dev), (addr), (reg), (val)) 71 72 73 typedef struct e6000sw_softc { 74 device_t dev; 75 phandle_t node; 76 77 struct sx sx; 78 if_t ifp[E6000SW_MAX_PORTS]; 79 char *ifname[E6000SW_MAX_PORTS]; 80 device_t miibus[E6000SW_MAX_PORTS]; 81 struct taskqueue *sc_tq; 82 struct timeout_task sc_tt; 83 84 int vlans[E6000SW_NUM_VLANS]; 85 uint32_t swid; 86 uint32_t vlan_mode; 87 uint32_t cpuports_mask; 88 uint32_t fixed_mask; 89 uint32_t fixed25_mask; 90 uint32_t ports_mask; 91 int phy_base; 92 int sw_addr; 93 int num_ports; 94 } e6000sw_softc_t; 95 96 static etherswitch_info_t etherswitch_info = { 97 .es_nports = 0, 98 .es_nvlangroups = 0, 99 .es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q, 100 .es_name = "Marvell 6000 series switch" 101 }; 102 103 static void e6000sw_identify(driver_t *, device_t); 104 static int e6000sw_probe(device_t); 105 static int e6000sw_parse_fixed_link(e6000sw_softc_t *, phandle_t, uint32_t); 106 static int e6000sw_parse_ethernet(e6000sw_softc_t *, phandle_t, uint32_t); 107 static int e6000sw_attach(device_t); 108 static int e6000sw_detach(device_t); 109 static int e6000sw_read_xmdio(device_t, int, int, int); 110 static int e6000sw_write_xmdio(device_t, int, int, int, int); 111 static int e6000sw_readphy(device_t, int, int); 112 static int e6000sw_writephy(device_t, int, int, int); 113 static int e6000sw_readphy_locked(device_t, int, int); 114 static int e6000sw_writephy_locked(device_t, int, int, int); 115 static etherswitch_info_t* e6000sw_getinfo(device_t); 116 static int e6000sw_getconf(device_t, etherswitch_conf_t *); 117 static int e6000sw_setconf(device_t, etherswitch_conf_t *); 118 static void e6000sw_lock(device_t); 119 static void e6000sw_unlock(device_t); 120 static int e6000sw_getport(device_t, etherswitch_port_t *); 121 static int e6000sw_setport(device_t, etherswitch_port_t *); 122 static int e6000sw_set_vlan_mode(e6000sw_softc_t *, uint32_t); 123 static int e6000sw_readreg_wrapper(device_t, int); 124 static int e6000sw_writereg_wrapper(device_t, int, int); 125 static int e6000sw_getvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 126 static int e6000sw_setvgroup_wrapper(device_t, etherswitch_vlangroup_t *); 127 static int e6000sw_setvgroup(device_t, etherswitch_vlangroup_t *); 128 static int e6000sw_getvgroup(device_t, etherswitch_vlangroup_t *); 129 static void e6000sw_setup(device_t, e6000sw_softc_t *); 130 static void e6000sw_tick(void *, int); 131 static void e6000sw_set_atustat(device_t, e6000sw_softc_t *, int, int); 132 static int e6000sw_atu_flush(device_t, e6000sw_softc_t *, int); 133 static int e6000sw_vtu_flush(e6000sw_softc_t *); 134 static int e6000sw_vtu_update(e6000sw_softc_t *, int, int, int, int, int); 135 static __inline void e6000sw_writereg(e6000sw_softc_t *, int, int, int); 136 static __inline uint32_t e6000sw_readreg(e6000sw_softc_t *, int, int); 137 static int e6000sw_ifmedia_upd(if_t); 138 static void e6000sw_ifmedia_sts(if_t, struct ifmediareq *); 139 static int e6000sw_atu_mac_table(device_t, e6000sw_softc_t *, struct atu_opt *, 140 int); 141 static int e6000sw_get_pvid(e6000sw_softc_t *, int, int *); 142 static void e6000sw_set_pvid(e6000sw_softc_t *, int, int); 143 static __inline bool e6000sw_is_cpuport(e6000sw_softc_t *, int); 144 static __inline bool e6000sw_is_fixedport(e6000sw_softc_t *, int); 145 static __inline bool e6000sw_is_fixed25port(e6000sw_softc_t *, int); 146 static __inline bool e6000sw_is_phyport(e6000sw_softc_t *, int); 147 static __inline bool e6000sw_is_portenabled(e6000sw_softc_t *, int); 148 static __inline struct mii_data *e6000sw_miiforphy(e6000sw_softc_t *, 149 unsigned int); 150 151 static device_method_t e6000sw_methods[] = { 152 /* device interface */ 153 DEVMETHOD(device_identify, e6000sw_identify), 154 DEVMETHOD(device_probe, e6000sw_probe), 155 DEVMETHOD(device_attach, e6000sw_attach), 156 DEVMETHOD(device_detach, e6000sw_detach), 157 158 /* bus interface */ 159 DEVMETHOD(bus_add_child, device_add_child_ordered), 160 161 /* mii interface */ 162 DEVMETHOD(miibus_readreg, e6000sw_readphy_locked), 163 DEVMETHOD(miibus_writereg, e6000sw_writephy_locked), 164 165 /* etherswitch interface */ 166 DEVMETHOD(etherswitch_getinfo, e6000sw_getinfo), 167 DEVMETHOD(etherswitch_getconf, e6000sw_getconf), 168 DEVMETHOD(etherswitch_setconf, e6000sw_setconf), 169 DEVMETHOD(etherswitch_lock, e6000sw_lock), 170 DEVMETHOD(etherswitch_unlock, e6000sw_unlock), 171 DEVMETHOD(etherswitch_getport, e6000sw_getport), 172 DEVMETHOD(etherswitch_setport, e6000sw_setport), 173 DEVMETHOD(etherswitch_readreg, e6000sw_readreg_wrapper), 174 DEVMETHOD(etherswitch_writereg, e6000sw_writereg_wrapper), 175 DEVMETHOD(etherswitch_readphyreg, e6000sw_readphy), 176 DEVMETHOD(etherswitch_writephyreg, e6000sw_writephy), 177 DEVMETHOD(etherswitch_setvgroup, e6000sw_setvgroup_wrapper), 178 DEVMETHOD(etherswitch_getvgroup, e6000sw_getvgroup_wrapper), 179 180 DEVMETHOD_END 181 }; 182 183 DEFINE_CLASS_0(e6000sw, e6000sw_driver, e6000sw_methods, 184 sizeof(e6000sw_softc_t)); 185 186 DRIVER_MODULE(e6000sw, mdio, e6000sw_driver, 0, 0); 187 DRIVER_MODULE(etherswitch, e6000sw, etherswitch_driver, 0, 0); 188 DRIVER_MODULE(miibus, e6000sw, miibus_driver, 0, 0); 189 MODULE_DEPEND(e6000sw, mdio, 1, 1, 1); 190 191 192 static void 193 e6000sw_identify(driver_t *driver, device_t parent) 194 { 195 196 if (device_find_child(parent, "e6000sw", -1) == NULL) 197 BUS_ADD_CHILD(parent, 0, "e6000sw", -1); 198 } 199 200 static int 201 e6000sw_probe(device_t dev) 202 { 203 e6000sw_softc_t *sc; 204 const char *description; 205 phandle_t switch_node; 206 207 sc = device_get_softc(dev); 208 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 209 "marvell,mv88e6085"); 210 if (switch_node == 0) { 211 switch_node = ofw_bus_find_compatible(OF_finddevice("/"), 212 "marvell,mv88e6190"); 213 214 if (switch_node == 0) 215 return (ENXIO); 216 217 /* 218 * Trust DTS and fix the port register offset for the MV88E6190 219 * detection bellow. 220 */ 221 sc->swid = MV88E6190; 222 } 223 224 if (bootverbose) 225 device_printf(dev, "Found switch_node: 0x%x\n", switch_node); 226 227 sc->dev = dev; 228 sc->node = switch_node; 229 230 if (OF_getencprop(sc->node, "reg", &sc->sw_addr, 231 sizeof(sc->sw_addr)) < 0) 232 return (ENXIO); 233 if (sc->sw_addr < 0 || sc->sw_addr > 32) 234 return (ENXIO); 235 236 /* 237 * Create temporary lock, just to satisfy assertions, 238 * when obtaining the switch ID. Destroy immediately afterwards. 239 */ 240 sx_init(&sc->sx, "e6000sw_tmp"); 241 E6000SW_LOCK(sc); 242 sc->swid = e6000sw_readreg(sc, REG_PORT(sc, 0), SWITCH_ID) & 0xfff0; 243 E6000SW_UNLOCK(sc); 244 sx_destroy(&sc->sx); 245 246 switch (sc->swid) { 247 case MV88E6141: 248 description = "Marvell 88E6141"; 249 sc->phy_base = 0x10; 250 sc->num_ports = 6; 251 break; 252 case MV88E6341: 253 description = "Marvell 88E6341"; 254 sc->phy_base = 0x10; 255 sc->num_ports = 6; 256 break; 257 case MV88E6352: 258 description = "Marvell 88E6352"; 259 sc->num_ports = 7; 260 break; 261 case MV88E6172: 262 description = "Marvell 88E6172"; 263 sc->num_ports = 7; 264 break; 265 case MV88E6176: 266 description = "Marvell 88E6176"; 267 sc->num_ports = 7; 268 break; 269 case MV88E6190: 270 description = "Marvell 88E6190"; 271 sc->num_ports = 11; 272 break; 273 default: 274 device_printf(dev, "Unrecognized device, id 0x%x.\n", sc->swid); 275 return (ENXIO); 276 } 277 278 device_set_desc(dev, description); 279 280 return (BUS_PROBE_DEFAULT); 281 } 282 283 static int 284 e6000sw_parse_fixed_link(e6000sw_softc_t *sc, phandle_t node, uint32_t port) 285 { 286 int speed; 287 phandle_t fixed_link; 288 289 fixed_link = ofw_bus_find_child(node, "fixed-link"); 290 291 if (fixed_link != 0) { 292 sc->fixed_mask |= (1 << port); 293 294 if (OF_getencprop(fixed_link, 295 "speed", &speed, sizeof(speed)) < 0) { 296 device_printf(sc->dev, 297 "Port %d has a fixed-link node without a speed " 298 "property\n", port); 299 return (ENXIO); 300 } 301 if (speed == 2500 && (MVSWITCH(sc, MV88E6141) || 302 MVSWITCH(sc, MV88E6341) || MVSWITCH(sc, MV88E6190))) 303 sc->fixed25_mask |= (1 << port); 304 } 305 306 return (0); 307 } 308 309 static int 310 e6000sw_parse_ethernet(e6000sw_softc_t *sc, phandle_t port_handle, uint32_t port) { 311 phandle_t switch_eth, switch_eth_handle; 312 313 if (OF_getencprop(port_handle, "ethernet", (void*)&switch_eth_handle, 314 sizeof(switch_eth_handle)) > 0) { 315 if (switch_eth_handle > 0) { 316 switch_eth = OF_node_from_xref(switch_eth_handle); 317 318 device_printf(sc->dev, "CPU port at %d\n", port); 319 sc->cpuports_mask |= (1 << port); 320 321 return (e6000sw_parse_fixed_link(sc, switch_eth, port)); 322 } else 323 device_printf(sc->dev, 324 "Port %d has ethernet property but it points " 325 "to an invalid location\n", port); 326 } 327 328 return (0); 329 } 330 331 static int 332 e6000sw_parse_child_fdt(e6000sw_softc_t *sc, phandle_t child, int *pport) 333 { 334 uint32_t port; 335 336 if (pport == NULL) 337 return (ENXIO); 338 339 if (OF_getencprop(child, "reg", (void *)&port, sizeof(port)) < 0) 340 return (ENXIO); 341 if (port >= sc->num_ports) 342 return (ENXIO); 343 *pport = port; 344 345 if (e6000sw_parse_fixed_link(sc, child, port) != 0) 346 return (ENXIO); 347 348 if (e6000sw_parse_ethernet(sc, child, port) != 0) 349 return (ENXIO); 350 351 if ((sc->fixed_mask & (1 << port)) != 0) 352 device_printf(sc->dev, "fixed port at %d\n", port); 353 else 354 device_printf(sc->dev, "PHY at port %d\n", port); 355 356 return (0); 357 } 358 359 static int 360 e6000sw_init_interface(e6000sw_softc_t *sc, int port) 361 { 362 char name[IFNAMSIZ]; 363 364 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->dev)); 365 366 sc->ifp[port] = if_alloc(IFT_ETHER); 367 if (sc->ifp[port] == NULL) 368 return (ENOMEM); 369 if_setsoftc(sc->ifp[port], sc); 370 if_setflagbits(sc->ifp[port], IFF_UP | IFF_BROADCAST | 371 IFF_DRV_RUNNING | IFF_SIMPLEX, 0); 372 sc->ifname[port] = malloc(strlen(name) + 1, M_E6000SW, M_NOWAIT); 373 if (sc->ifname[port] == NULL) { 374 if_free(sc->ifp[port]); 375 return (ENOMEM); 376 } 377 memcpy(sc->ifname[port], name, strlen(name) + 1); 378 if_initname(sc->ifp[port], sc->ifname[port], port); 379 380 return (0); 381 } 382 383 static int 384 e6000sw_attach_miibus(e6000sw_softc_t *sc, int port) 385 { 386 int err; 387 388 err = mii_attach(sc->dev, &sc->miibus[port], sc->ifp[port], 389 e6000sw_ifmedia_upd, e6000sw_ifmedia_sts, BMSR_DEFCAPMASK, 390 port + sc->phy_base, MII_OFFSET_ANY, 0); 391 if (err != 0) 392 return (err); 393 394 return (0); 395 } 396 397 static void 398 e6000sw_serdes_power(device_t dev, int port, bool sgmii) 399 { 400 uint32_t reg; 401 402 /* SGMII */ 403 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 404 E6000SW_SERDES_SGMII_CTL); 405 if (sgmii) 406 reg &= ~E6000SW_SERDES_PDOWN; 407 else 408 reg |= E6000SW_SERDES_PDOWN; 409 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 410 E6000SW_SERDES_SGMII_CTL, reg); 411 412 /* 10GBASE-R/10GBASE-X4/X2 */ 413 reg = e6000sw_read_xmdio(dev, port, E6000SW_SERDES_DEV, 414 E6000SW_SERDES_PCS_CTL1); 415 if (sgmii) 416 reg |= E6000SW_SERDES_PDOWN; 417 else 418 reg &= ~E6000SW_SERDES_PDOWN; 419 e6000sw_write_xmdio(dev, port, E6000SW_SERDES_DEV, 420 E6000SW_SERDES_PCS_CTL1, reg); 421 } 422 423 static int 424 e6000sw_attach(device_t dev) 425 { 426 bool sgmii; 427 e6000sw_softc_t *sc; 428 phandle_t child, ports; 429 int err, port; 430 uint32_t reg; 431 432 err = 0; 433 sc = device_get_softc(dev); 434 435 /* 436 * According to the Linux source code, all of the Switch IDs we support 437 * are multi_chip capable, and should go into multi-chip mode if the 438 * sw_addr != 0. 439 */ 440 if (MVSWITCH_MULTICHIP(sc)) 441 device_printf(dev, "multi-chip addressing mode (%#x)\n", 442 sc->sw_addr); 443 else 444 device_printf(dev, "single-chip addressing mode\n"); 445 446 sx_init(&sc->sx, "e6000sw"); 447 448 E6000SW_LOCK(sc); 449 e6000sw_setup(dev, sc); 450 ports = ofw_bus_find_child(sc->node, "ports"); 451 sc->sc_tq = taskqueue_create("e6000sw_taskq", M_NOWAIT, 452 taskqueue_thread_enqueue, &sc->sc_tq); 453 454 TIMEOUT_TASK_INIT(sc->sc_tq, &sc->sc_tt, 0, e6000sw_tick, sc); 455 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 456 device_get_nameunit(dev)); 457 458 if (ports == 0) { 459 device_printf(dev, "failed to parse DTS: no ports found for " 460 "switch\n"); 461 E6000SW_UNLOCK(sc); 462 return (ENXIO); 463 } 464 465 for (child = OF_child(ports); child != 0; child = OF_peer(child)) { 466 err = e6000sw_parse_child_fdt(sc, child, &port); 467 if (err != 0) { 468 device_printf(sc->dev, "failed to parse DTS\n"); 469 goto out_fail; 470 } 471 472 /* Port is in use. */ 473 sc->ports_mask |= (1 << port); 474 475 err = e6000sw_init_interface(sc, port); 476 if (err != 0) { 477 device_printf(sc->dev, "failed to init interface\n"); 478 goto out_fail; 479 } 480 481 if (e6000sw_is_fixedport(sc, port)) { 482 /* Link must be down to change speed force value. */ 483 reg = e6000sw_readreg(sc, REG_PORT(sc, port), 484 PSC_CONTROL); 485 reg &= ~PSC_CONTROL_LINK_UP; 486 reg |= PSC_CONTROL_FORCED_LINK; 487 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 488 reg); 489 490 /* 491 * Force speed, full-duplex, EEE off and flow-control 492 * on. 493 */ 494 reg &= ~(PSC_CONTROL_SPD2500 | PSC_CONTROL_ALT_SPD | 495 PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON | 496 PSC_CONTROL_FORCED_EEE); 497 if (e6000sw_is_fixed25port(sc, port)) 498 reg |= PSC_CONTROL_SPD2500; 499 else 500 reg |= PSC_CONTROL_SPD1000; 501 if (MVSWITCH(sc, MV88E6190) && 502 e6000sw_is_fixed25port(sc, port)) 503 reg |= PSC_CONTROL_ALT_SPD; 504 reg |= PSC_CONTROL_FORCED_DPX | PSC_CONTROL_FULLDPX | 505 PSC_CONTROL_FORCED_LINK | PSC_CONTROL_LINK_UP | 506 PSC_CONTROL_FORCED_SPD; 507 if (!MVSWITCH(sc, MV88E6190)) 508 reg |= PSC_CONTROL_FORCED_FC | PSC_CONTROL_FC_ON; 509 if (MVSWITCH(sc, MV88E6141) || 510 MVSWITCH(sc, MV88E6341) || 511 MVSWITCH(sc, MV88E6190)) 512 reg |= PSC_CONTROL_FORCED_EEE; 513 e6000sw_writereg(sc, REG_PORT(sc, port), PSC_CONTROL, 514 reg); 515 /* Power on the SERDES interfaces. */ 516 if (MVSWITCH(sc, MV88E6190) && 517 (port == 9 || port == 10)) { 518 if (e6000sw_is_fixed25port(sc, port)) 519 sgmii = false; 520 else 521 sgmii = true; 522 e6000sw_serdes_power(sc->dev, port, sgmii); 523 } 524 } 525 526 /* Don't attach miibus at CPU/fixed ports */ 527 if (!e6000sw_is_phyport(sc, port)) 528 continue; 529 530 err = e6000sw_attach_miibus(sc, port); 531 if (err != 0) { 532 device_printf(sc->dev, "failed to attach miibus\n"); 533 goto out_fail; 534 } 535 } 536 537 etherswitch_info.es_nports = sc->num_ports; 538 539 /* Default to port vlan. */ 540 e6000sw_set_vlan_mode(sc, ETHERSWITCH_VLAN_PORT); 541 542 reg = e6000sw_readreg(sc, REG_GLOBAL, SWITCH_GLOBAL_STATUS); 543 if (reg & SWITCH_GLOBAL_STATUS_IR) 544 device_printf(dev, "switch is ready.\n"); 545 E6000SW_UNLOCK(sc); 546 547 bus_generic_probe(dev); 548 bus_generic_attach(dev); 549 550 taskqueue_enqueue_timeout(sc->sc_tq, &sc->sc_tt, hz); 551 552 return (0); 553 554 out_fail: 555 e6000sw_detach(dev); 556 557 return (err); 558 } 559 560 static int 561 e6000sw_waitready(e6000sw_softc_t *sc, uint32_t phy, uint32_t reg, 562 uint32_t busybit) 563 { 564 int i; 565 566 for (i = 0; i < E6000SW_RETRIES; i++) { 567 if ((e6000sw_readreg(sc, phy, reg) & busybit) == 0) 568 return (0); 569 DELAY(1); 570 } 571 572 return (1); 573 } 574 575 /* XMDIO/Clause 45 access. */ 576 static int 577 e6000sw_read_xmdio(device_t dev, int phy, int devaddr, int devreg) 578 { 579 e6000sw_softc_t *sc; 580 uint32_t reg; 581 582 sc = device_get_softc(dev); 583 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 584 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 585 device_printf(dev, "Timeout while waiting for switch\n"); 586 return (ETIMEDOUT); 587 } 588 589 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 590 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 591 592 /* Load C45 register address. */ 593 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 594 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 595 reg | SMI_CMD_OP_C45_ADDR); 596 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 597 device_printf(dev, "Timeout while waiting for switch\n"); 598 return (ETIMEDOUT); 599 } 600 601 /* Start C45 read operation. */ 602 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 603 reg | SMI_CMD_OP_C45_READ); 604 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 605 device_printf(dev, "Timeout while waiting for switch\n"); 606 return (ETIMEDOUT); 607 } 608 609 /* Read C45 data. */ 610 reg = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 611 612 return (reg & PHY_DATA_MASK); 613 } 614 615 static int 616 e6000sw_write_xmdio(device_t dev, int phy, int devaddr, int devreg, int val) 617 { 618 e6000sw_softc_t *sc; 619 uint32_t reg; 620 621 sc = device_get_softc(dev); 622 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 623 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 624 device_printf(dev, "Timeout while waiting for switch\n"); 625 return (ETIMEDOUT); 626 } 627 628 reg = devaddr & SMI_CMD_REG_ADDR_MASK; 629 reg |= (phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK; 630 631 /* Load C45 register address. */ 632 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 633 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 634 reg | SMI_CMD_OP_C45_ADDR); 635 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 636 device_printf(dev, "Timeout while waiting for switch\n"); 637 return (ETIMEDOUT); 638 } 639 640 /* Load data and start the C45 write operation. */ 641 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, devreg); 642 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 643 reg | SMI_CMD_OP_C45_WRITE); 644 645 return (0); 646 } 647 648 static int e6000sw_readphy(device_t dev, int phy, int reg) 649 { 650 e6000sw_softc_t *sc; 651 int ret; 652 653 sc = device_get_softc(dev); 654 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 655 656 E6000SW_LOCK(sc); 657 ret = e6000sw_readphy_locked(dev, phy, reg); 658 E6000SW_UNLOCK(sc); 659 660 return (ret); 661 } 662 663 /* 664 * PHY registers are paged. Put page index in reg 22 (accessible from every 665 * page), then access specific register. 666 */ 667 static int 668 e6000sw_readphy_locked(device_t dev, int phy, int reg) 669 { 670 e6000sw_softc_t *sc; 671 uint32_t val; 672 673 sc = device_get_softc(dev); 674 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 675 676 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 677 device_printf(dev, "Wrong register address.\n"); 678 return (EINVAL); 679 } 680 681 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 682 device_printf(dev, "Timeout while waiting for switch\n"); 683 return (ETIMEDOUT); 684 } 685 686 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 687 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 688 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 689 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 690 device_printf(dev, "Timeout while waiting for switch\n"); 691 return (ETIMEDOUT); 692 } 693 694 val = e6000sw_readreg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG); 695 696 return (val & PHY_DATA_MASK); 697 } 698 699 static int e6000sw_writephy(device_t dev, int phy, int reg, int data) 700 { 701 e6000sw_softc_t *sc; 702 int ret; 703 704 sc = device_get_softc(dev); 705 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 706 707 E6000SW_LOCK(sc); 708 ret = e6000sw_writephy_locked(dev, phy, reg, data); 709 E6000SW_UNLOCK(sc); 710 711 return (ret); 712 } 713 714 static int 715 e6000sw_writephy_locked(device_t dev, int phy, int reg, int data) 716 { 717 e6000sw_softc_t *sc; 718 719 sc = device_get_softc(dev); 720 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 721 722 if (!e6000sw_is_phyport(sc, phy) || reg >= E6000SW_NUM_PHY_REGS) { 723 device_printf(dev, "Wrong register address.\n"); 724 return (EINVAL); 725 } 726 727 if (E6000SW_WAITREADY2(sc, SMI_PHY_CMD_REG, SMI_CMD_BUSY)) { 728 device_printf(dev, "Timeout while waiting for switch\n"); 729 return (ETIMEDOUT); 730 } 731 732 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_DATA_REG, 733 data & PHY_DATA_MASK); 734 e6000sw_writereg(sc, REG_GLOBAL2, SMI_PHY_CMD_REG, 735 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 736 ((phy << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 737 738 return (0); 739 } 740 741 static int 742 e6000sw_detach(device_t dev) 743 { 744 int phy; 745 e6000sw_softc_t *sc; 746 747 sc = device_get_softc(dev); 748 749 if (device_is_attached(dev)) 750 taskqueue_drain_timeout(sc->sc_tq, &sc->sc_tt); 751 752 if (sc->sc_tq != NULL) 753 taskqueue_free(sc->sc_tq); 754 755 device_delete_children(dev); 756 757 sx_destroy(&sc->sx); 758 for (phy = 0; phy < sc->num_ports; phy++) { 759 if (sc->ifp[phy] != NULL) 760 if_free(sc->ifp[phy]); 761 if (sc->ifname[phy] != NULL) 762 free(sc->ifname[phy], M_E6000SW); 763 } 764 765 return (0); 766 } 767 768 static etherswitch_info_t* 769 e6000sw_getinfo(device_t dev) 770 { 771 772 return (ðerswitch_info); 773 } 774 775 static int 776 e6000sw_getconf(device_t dev, etherswitch_conf_t *conf) 777 { 778 struct e6000sw_softc *sc; 779 780 /* Return the VLAN mode. */ 781 sc = device_get_softc(dev); 782 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 783 conf->vlan_mode = sc->vlan_mode; 784 785 return (0); 786 } 787 788 static int 789 e6000sw_setconf(device_t dev, etherswitch_conf_t *conf) 790 { 791 struct e6000sw_softc *sc; 792 793 /* Set the VLAN mode. */ 794 sc = device_get_softc(dev); 795 if (conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) { 796 E6000SW_LOCK(sc); 797 e6000sw_set_vlan_mode(sc, conf->vlan_mode); 798 E6000SW_UNLOCK(sc); 799 } 800 801 return (0); 802 } 803 804 static void 805 e6000sw_lock(device_t dev) 806 { 807 struct e6000sw_softc *sc; 808 809 sc = device_get_softc(dev); 810 811 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 812 E6000SW_LOCK(sc); 813 } 814 815 static void 816 e6000sw_unlock(device_t dev) 817 { 818 struct e6000sw_softc *sc; 819 820 sc = device_get_softc(dev); 821 822 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 823 E6000SW_UNLOCK(sc); 824 } 825 826 static int 827 e6000sw_getport(device_t dev, etherswitch_port_t *p) 828 { 829 struct mii_data *mii; 830 int err; 831 struct ifmediareq *ifmr; 832 uint32_t reg; 833 834 e6000sw_softc_t *sc = device_get_softc(dev); 835 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 836 837 if (p->es_port >= sc->num_ports || p->es_port < 0) 838 return (EINVAL); 839 if (!e6000sw_is_portenabled(sc, p->es_port)) 840 return (0); 841 842 E6000SW_LOCK(sc); 843 e6000sw_get_pvid(sc, p->es_port, &p->es_pvid); 844 845 /* Port flags. */ 846 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 847 if (reg & PORT_CONTROL2_DISC_TAGGED) 848 p->es_flags |= ETHERSWITCH_PORT_DROPTAGGED; 849 if (reg & PORT_CONTROL2_DISC_UNTAGGED) 850 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 851 852 err = 0; 853 if (e6000sw_is_fixedport(sc, p->es_port)) { 854 if (e6000sw_is_cpuport(sc, p->es_port)) 855 p->es_flags |= ETHERSWITCH_PORT_CPU; 856 ifmr = &p->es_ifmr; 857 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 858 ifmr->ifm_count = 0; 859 if (e6000sw_is_fixed25port(sc, p->es_port)) 860 ifmr->ifm_active = IFM_2500_T; 861 else 862 ifmr->ifm_active = IFM_1000_T; 863 ifmr->ifm_active |= IFM_ETHER | IFM_FDX; 864 ifmr->ifm_current = ifmr->ifm_active; 865 ifmr->ifm_mask = 0; 866 } else { 867 mii = e6000sw_miiforphy(sc, p->es_port); 868 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, 869 &mii->mii_media, SIOCGIFMEDIA); 870 } 871 E6000SW_UNLOCK(sc); 872 873 return (err); 874 } 875 876 static int 877 e6000sw_setport(device_t dev, etherswitch_port_t *p) 878 { 879 e6000sw_softc_t *sc; 880 int err; 881 struct mii_data *mii; 882 uint32_t reg; 883 884 sc = device_get_softc(dev); 885 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 886 887 if (p->es_port >= sc->num_ports || p->es_port < 0) 888 return (EINVAL); 889 if (!e6000sw_is_portenabled(sc, p->es_port)) 890 return (0); 891 892 E6000SW_LOCK(sc); 893 894 /* Port flags. */ 895 reg = e6000sw_readreg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2); 896 if (p->es_flags & ETHERSWITCH_PORT_DROPTAGGED) 897 reg |= PORT_CONTROL2_DISC_TAGGED; 898 else 899 reg &= ~PORT_CONTROL2_DISC_TAGGED; 900 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 901 reg |= PORT_CONTROL2_DISC_UNTAGGED; 902 else 903 reg &= ~PORT_CONTROL2_DISC_UNTAGGED; 904 e6000sw_writereg(sc, REG_PORT(sc, p->es_port), PORT_CONTROL2, reg); 905 906 err = 0; 907 if (p->es_pvid != 0) 908 e6000sw_set_pvid(sc, p->es_port, p->es_pvid); 909 if (e6000sw_is_phyport(sc, p->es_port)) { 910 mii = e6000sw_miiforphy(sc, p->es_port); 911 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr, &mii->mii_media, 912 SIOCSIFMEDIA); 913 } 914 E6000SW_UNLOCK(sc); 915 916 return (err); 917 } 918 919 static __inline void 920 e6000sw_port_vlan_assign(e6000sw_softc_t *sc, int port, uint32_t fid, 921 uint32_t members) 922 { 923 uint32_t reg; 924 925 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 926 reg &= ~(PORT_MASK(sc) | PORT_VLAN_MAP_FID_MASK); 927 reg |= members & PORT_MASK(sc) & ~(1 << port); 928 reg |= (fid << PORT_VLAN_MAP_FID) & PORT_VLAN_MAP_FID_MASK; 929 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VLAN_MAP, reg); 930 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 931 reg &= ~PORT_CONTROL1_FID_MASK; 932 reg |= (fid >> 4) & PORT_CONTROL1_FID_MASK; 933 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL1, reg); 934 } 935 936 static int 937 e6000sw_init_vlan(struct e6000sw_softc *sc) 938 { 939 int i, port, ret; 940 uint32_t members; 941 942 /* Disable all ports */ 943 for (port = 0; port < sc->num_ports; port++) { 944 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 945 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 946 (ret & ~PORT_CONTROL_ENABLE)); 947 } 948 949 /* Flush VTU. */ 950 e6000sw_vtu_flush(sc); 951 952 for (port = 0; port < sc->num_ports; port++) { 953 /* Reset the egress and frame mode. */ 954 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 955 ret &= ~(PORT_CONTROL_EGRESS | PORT_CONTROL_FRAME); 956 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, ret); 957 958 /* Set the 802.1q mode. */ 959 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL2); 960 ret &= ~PORT_CONTROL2_DOT1Q; 961 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 962 ret |= PORT_CONTROL2_DOT1Q; 963 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL2, ret); 964 } 965 966 for (port = 0; port < sc->num_ports; port++) { 967 if (!e6000sw_is_portenabled(sc, port)) 968 continue; 969 970 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 971 972 /* Set port priority */ 973 ret &= ~PORT_VID_PRIORITY_MASK; 974 975 /* Set VID map */ 976 ret &= ~PORT_VID_DEF_VID_MASK; 977 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 978 ret |= 1; 979 else 980 ret |= (port + 1); 981 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, ret); 982 } 983 984 /* Assign the member ports to each origin port. */ 985 for (port = 0; port < sc->num_ports; port++) { 986 members = 0; 987 if (e6000sw_is_portenabled(sc, port)) { 988 for (i = 0; i < sc->num_ports; i++) { 989 if (i == port || !e6000sw_is_portenabled(sc, i)) 990 continue; 991 members |= (1 << i); 992 } 993 } 994 /* Default to FID 0. */ 995 e6000sw_port_vlan_assign(sc, port, 0, members); 996 } 997 998 /* Reset internal VLAN table. */ 999 for (i = 0; i < nitems(sc->vlans); i++) 1000 sc->vlans[i] = 0; 1001 1002 /* Create default VLAN (1). */ 1003 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 1004 sc->vlans[0] = 1; 1005 e6000sw_vtu_update(sc, 0, sc->vlans[0], 1, 0, sc->ports_mask); 1006 } 1007 1008 /* Enable all ports */ 1009 for (port = 0; port < sc->num_ports; port++) { 1010 if (!e6000sw_is_portenabled(sc, port)) 1011 continue; 1012 ret = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL); 1013 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_CONTROL, 1014 (ret | PORT_CONTROL_ENABLE)); 1015 } 1016 1017 return (0); 1018 } 1019 1020 static int 1021 e6000sw_set_vlan_mode(struct e6000sw_softc *sc, uint32_t mode) 1022 { 1023 1024 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1025 switch (mode) { 1026 case ETHERSWITCH_VLAN_PORT: 1027 sc->vlan_mode = ETHERSWITCH_VLAN_PORT; 1028 etherswitch_info.es_nvlangroups = sc->num_ports; 1029 return (e6000sw_init_vlan(sc)); 1030 break; 1031 case ETHERSWITCH_VLAN_DOT1Q: 1032 sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 1033 etherswitch_info.es_nvlangroups = E6000SW_NUM_VLANS; 1034 return (e6000sw_init_vlan(sc)); 1035 break; 1036 default: 1037 return (EINVAL); 1038 } 1039 } 1040 1041 /* 1042 * Registers in this switch are divided into sections, specified in 1043 * documentation. So as to access any of them, section index and reg index 1044 * is necessary. etherswitchcfg uses only one variable, so indexes were 1045 * compressed into addr_reg: 32 * section_index + reg_index. 1046 */ 1047 static int 1048 e6000sw_readreg_wrapper(device_t dev, int addr_reg) 1049 { 1050 e6000sw_softc_t *sc; 1051 1052 sc = device_get_softc(dev); 1053 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1054 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1055 device_printf(dev, "Wrong register address.\n"); 1056 return (EINVAL); 1057 } 1058 1059 return (e6000sw_readreg(device_get_softc(dev), addr_reg / 32, 1060 addr_reg % 32)); 1061 } 1062 1063 static int 1064 e6000sw_writereg_wrapper(device_t dev, int addr_reg, int val) 1065 { 1066 e6000sw_softc_t *sc; 1067 1068 sc = device_get_softc(dev); 1069 if ((addr_reg > (REG_GLOBAL2 * 32 + REG_NUM_MAX)) || 1070 (addr_reg < (REG_PORT(sc, 0) * 32))) { 1071 device_printf(dev, "Wrong register address.\n"); 1072 return (EINVAL); 1073 } 1074 e6000sw_writereg(device_get_softc(dev), addr_reg / 32, 1075 addr_reg % 32, val); 1076 1077 return (0); 1078 } 1079 1080 /* 1081 * setvgroup/getvgroup called from etherswitchfcg need to be locked, 1082 * while internal calls do not. 1083 */ 1084 static int 1085 e6000sw_setvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1086 { 1087 e6000sw_softc_t *sc; 1088 int ret; 1089 1090 sc = device_get_softc(dev); 1091 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1092 1093 E6000SW_LOCK(sc); 1094 ret = e6000sw_setvgroup(dev, vg); 1095 E6000SW_UNLOCK(sc); 1096 1097 return (ret); 1098 } 1099 1100 static int 1101 e6000sw_getvgroup_wrapper(device_t dev, etherswitch_vlangroup_t *vg) 1102 { 1103 e6000sw_softc_t *sc; 1104 int ret; 1105 1106 sc = device_get_softc(dev); 1107 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1108 1109 E6000SW_LOCK(sc); 1110 ret = e6000sw_getvgroup(dev, vg); 1111 E6000SW_UNLOCK(sc); 1112 1113 return (ret); 1114 } 1115 1116 static int 1117 e6000sw_set_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1118 { 1119 uint32_t port; 1120 1121 port = vg->es_vlangroup; 1122 if (port > sc->num_ports) 1123 return (EINVAL); 1124 1125 if (vg->es_member_ports != vg->es_untagged_ports) { 1126 device_printf(sc->dev, "Tagged ports not supported.\n"); 1127 return (EINVAL); 1128 } 1129 1130 e6000sw_port_vlan_assign(sc, port, 0, vg->es_untagged_ports); 1131 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1132 1133 return (0); 1134 } 1135 1136 static int 1137 e6000sw_set_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1138 { 1139 int i, vlan; 1140 1141 vlan = vg->es_vid & ETHERSWITCH_VID_MASK; 1142 1143 /* Set VLAN to '0' removes it from table. */ 1144 if (vlan == 0) { 1145 e6000sw_vtu_update(sc, VTU_PURGE, 1146 sc->vlans[vg->es_vlangroup], 0, 0, 0); 1147 sc->vlans[vg->es_vlangroup] = 0; 1148 return (0); 1149 } 1150 1151 /* Is this VLAN already in table ? */ 1152 for (i = 0; i < etherswitch_info.es_nvlangroups; i++) 1153 if (i != vg->es_vlangroup && vlan == sc->vlans[i]) 1154 return (EINVAL); 1155 1156 sc->vlans[vg->es_vlangroup] = vlan; 1157 e6000sw_vtu_update(sc, 0, vlan, vg->es_vlangroup + 1, 1158 vg->es_member_ports & sc->ports_mask, 1159 vg->es_untagged_ports & sc->ports_mask); 1160 1161 return (0); 1162 } 1163 1164 static int 1165 e6000sw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1166 { 1167 e6000sw_softc_t *sc; 1168 1169 sc = device_get_softc(dev); 1170 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1171 1172 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1173 return (e6000sw_set_port_vlan(sc, vg)); 1174 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1175 return (e6000sw_set_dot1q_vlan(sc, vg)); 1176 1177 return (EINVAL); 1178 } 1179 1180 static int 1181 e6000sw_get_port_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1182 { 1183 uint32_t port, reg; 1184 1185 port = vg->es_vlangroup; 1186 if (port > sc->num_ports) 1187 return (EINVAL); 1188 1189 if (!e6000sw_is_portenabled(sc, port)) { 1190 vg->es_vid = port; 1191 return (0); 1192 } 1193 1194 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VLAN_MAP); 1195 vg->es_untagged_ports = vg->es_member_ports = reg & PORT_MASK(sc); 1196 vg->es_vid = port | ETHERSWITCH_VID_VALID; 1197 vg->es_fid = (reg & PORT_VLAN_MAP_FID_MASK) >> PORT_VLAN_MAP_FID; 1198 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_CONTROL1); 1199 vg->es_fid |= (reg & PORT_CONTROL1_FID_MASK) << 4; 1200 1201 return (0); 1202 } 1203 1204 static int 1205 e6000sw_get_dot1q_vlan(e6000sw_softc_t *sc, etherswitch_vlangroup_t *vg) 1206 { 1207 int i, port; 1208 uint32_t reg; 1209 1210 vg->es_fid = 0; 1211 vg->es_vid = sc->vlans[vg->es_vlangroup]; 1212 vg->es_untagged_ports = vg->es_member_ports = 0; 1213 if (vg->es_vid == 0) 1214 return (0); 1215 1216 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1217 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1218 return (EBUSY); 1219 } 1220 1221 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, vg->es_vid - 1); 1222 1223 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_OPERATION); 1224 reg &= ~VTU_OP_MASK; 1225 reg |= VTU_GET_NEXT | VTU_BUSY; 1226 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, reg); 1227 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1228 device_printf(sc->dev, "Timeout while reading\n"); 1229 return (EBUSY); 1230 } 1231 1232 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_VID); 1233 if (reg == VTU_VID_MASK || (reg & VTU_VID_VALID) == 0) 1234 return (EINVAL); 1235 if ((reg & VTU_VID_MASK) != vg->es_vid) 1236 return (EINVAL); 1237 1238 vg->es_vid |= ETHERSWITCH_VID_VALID; 1239 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA); 1240 for (i = 0; i < sc->num_ports; i++) { 1241 if (i == VTU_PPREG(sc)) 1242 reg = e6000sw_readreg(sc, REG_GLOBAL, VTU_DATA2); 1243 port = (reg >> VTU_PORT(sc, i)) & VTU_PORT_MASK; 1244 if (port == VTU_PORT_UNTAGGED) { 1245 vg->es_untagged_ports |= (1 << i); 1246 vg->es_member_ports |= (1 << i); 1247 } else if (port == VTU_PORT_TAGGED) 1248 vg->es_member_ports |= (1 << i); 1249 } 1250 1251 return (0); 1252 } 1253 1254 static int 1255 e6000sw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 1256 { 1257 e6000sw_softc_t *sc; 1258 1259 sc = device_get_softc(dev); 1260 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1261 1262 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) 1263 return (e6000sw_get_port_vlan(sc, vg)); 1264 else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) 1265 return (e6000sw_get_dot1q_vlan(sc, vg)); 1266 1267 return (EINVAL); 1268 } 1269 1270 static __inline struct mii_data* 1271 e6000sw_miiforphy(e6000sw_softc_t *sc, unsigned int phy) 1272 { 1273 1274 if (!e6000sw_is_phyport(sc, phy)) 1275 return (NULL); 1276 1277 return (device_get_softc(sc->miibus[phy])); 1278 } 1279 1280 static int 1281 e6000sw_ifmedia_upd(if_t ifp) 1282 { 1283 e6000sw_softc_t *sc; 1284 struct mii_data *mii; 1285 1286 sc = if_getsoftc(ifp); 1287 mii = e6000sw_miiforphy(sc, if_getdunit(ifp)); 1288 if (mii == NULL) 1289 return (ENXIO); 1290 mii_mediachg(mii); 1291 1292 return (0); 1293 } 1294 1295 static void 1296 e6000sw_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1297 { 1298 e6000sw_softc_t *sc; 1299 struct mii_data *mii; 1300 1301 sc = if_getsoftc(ifp); 1302 mii = e6000sw_miiforphy(sc, if_getdunit(ifp)); 1303 1304 if (mii == NULL) 1305 return; 1306 1307 mii_pollstat(mii); 1308 ifmr->ifm_active = mii->mii_media_active; 1309 ifmr->ifm_status = mii->mii_media_status; 1310 } 1311 1312 static int 1313 e6000sw_smi_waitready(e6000sw_softc_t *sc, int phy) 1314 { 1315 int i; 1316 1317 for (i = 0; i < E6000SW_SMI_TIMEOUT; i++) { 1318 if ((MDIO_READ(sc->dev, phy, SMI_CMD) & SMI_CMD_BUSY) == 0) 1319 return (0); 1320 DELAY(1); 1321 } 1322 1323 return (1); 1324 } 1325 1326 static __inline uint32_t 1327 e6000sw_readreg(e6000sw_softc_t *sc, int addr, int reg) 1328 { 1329 1330 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1331 1332 if (!MVSWITCH_MULTICHIP(sc)) 1333 return (MDIO_READ(sc->dev, addr, reg) & 0xffff); 1334 1335 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1336 printf("e6000sw: readreg timeout\n"); 1337 return (0xffff); 1338 } 1339 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1340 SMI_CMD_OP_C22_READ | (reg & SMI_CMD_REG_ADDR_MASK) | 1341 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1342 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1343 printf("e6000sw: readreg timeout\n"); 1344 return (0xffff); 1345 } 1346 1347 return (MDIO_READ(sc->dev, sc->sw_addr, SMI_DATA) & 0xffff); 1348 } 1349 1350 static __inline void 1351 e6000sw_writereg(e6000sw_softc_t *sc, int addr, int reg, int val) 1352 { 1353 1354 E6000SW_LOCK_ASSERT(sc, SA_XLOCKED); 1355 1356 if (!MVSWITCH_MULTICHIP(sc)) { 1357 MDIO_WRITE(sc->dev, addr, reg, val); 1358 return; 1359 } 1360 1361 if (e6000sw_smi_waitready(sc, sc->sw_addr)) { 1362 printf("e6000sw: readreg timeout\n"); 1363 return; 1364 } 1365 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_DATA, val); 1366 MDIO_WRITE(sc->dev, sc->sw_addr, SMI_CMD, 1367 SMI_CMD_OP_C22_WRITE | (reg & SMI_CMD_REG_ADDR_MASK) | 1368 ((addr << SMI_CMD_DEV_ADDR) & SMI_CMD_DEV_ADDR_MASK)); 1369 } 1370 1371 static __inline bool 1372 e6000sw_is_cpuport(e6000sw_softc_t *sc, int port) 1373 { 1374 1375 return ((sc->cpuports_mask & (1 << port)) ? true : false); 1376 } 1377 1378 static __inline bool 1379 e6000sw_is_fixedport(e6000sw_softc_t *sc, int port) 1380 { 1381 1382 return ((sc->fixed_mask & (1 << port)) ? true : false); 1383 } 1384 1385 static __inline bool 1386 e6000sw_is_fixed25port(e6000sw_softc_t *sc, int port) 1387 { 1388 1389 return ((sc->fixed25_mask & (1 << port)) ? true : false); 1390 } 1391 1392 static __inline bool 1393 e6000sw_is_phyport(e6000sw_softc_t *sc, int port) 1394 { 1395 uint32_t phy_mask; 1396 phy_mask = ~(sc->fixed_mask | sc->cpuports_mask); 1397 1398 return ((phy_mask & (1 << port)) ? true : false); 1399 } 1400 1401 static __inline bool 1402 e6000sw_is_portenabled(e6000sw_softc_t *sc, int port) 1403 { 1404 1405 return ((sc->ports_mask & (1 << port)) ? true : false); 1406 } 1407 1408 static __inline void 1409 e6000sw_set_pvid(e6000sw_softc_t *sc, int port, int pvid) 1410 { 1411 uint32_t reg; 1412 1413 reg = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID); 1414 reg &= ~PORT_VID_DEF_VID_MASK; 1415 reg |= (pvid & PORT_VID_DEF_VID_MASK); 1416 e6000sw_writereg(sc, REG_PORT(sc, port), PORT_VID, reg); 1417 } 1418 1419 static __inline int 1420 e6000sw_get_pvid(e6000sw_softc_t *sc, int port, int *pvid) 1421 { 1422 1423 if (pvid == NULL) 1424 return (ENXIO); 1425 1426 *pvid = e6000sw_readreg(sc, REG_PORT(sc, port), PORT_VID) & 1427 PORT_VID_DEF_VID_MASK; 1428 1429 return (0); 1430 } 1431 1432 /* 1433 * Convert port status to ifmedia. 1434 */ 1435 static void 1436 e6000sw_update_ifmedia(uint16_t portstatus, u_int *media_status, u_int *media_active) 1437 { 1438 *media_active = IFM_ETHER; 1439 *media_status = IFM_AVALID; 1440 1441 if ((portstatus & PORT_STATUS_LINK_MASK) != 0) 1442 *media_status |= IFM_ACTIVE; 1443 else { 1444 *media_active |= IFM_NONE; 1445 return; 1446 } 1447 1448 switch (portstatus & PORT_STATUS_SPEED_MASK) { 1449 case PORT_STATUS_SPEED_10: 1450 *media_active |= IFM_10_T; 1451 break; 1452 case PORT_STATUS_SPEED_100: 1453 *media_active |= IFM_100_TX; 1454 break; 1455 case PORT_STATUS_SPEED_1000: 1456 *media_active |= IFM_1000_T; 1457 break; 1458 } 1459 1460 if ((portstatus & PORT_STATUS_DUPLEX_MASK) == 0) 1461 *media_active |= IFM_FDX; 1462 else 1463 *media_active |= IFM_HDX; 1464 } 1465 1466 static void 1467 e6000sw_tick(void *arg, int p __unused) 1468 { 1469 e6000sw_softc_t *sc; 1470 struct mii_data *mii; 1471 struct mii_softc *miisc; 1472 uint16_t portstatus; 1473 int port; 1474 1475 sc = arg; 1476 1477 E6000SW_LOCK_ASSERT(sc, SA_UNLOCKED); 1478 1479 E6000SW_LOCK(sc); 1480 for (port = 0; port < sc->num_ports; port++) { 1481 /* Tick only on PHY ports */ 1482 if (!e6000sw_is_portenabled(sc, port) || 1483 !e6000sw_is_phyport(sc, port)) 1484 continue; 1485 1486 mii = e6000sw_miiforphy(sc, port); 1487 if (mii == NULL) 1488 continue; 1489 1490 portstatus = e6000sw_readreg(sc, REG_PORT(sc, port), 1491 PORT_STATUS); 1492 1493 e6000sw_update_ifmedia(portstatus, 1494 &mii->mii_media_status, &mii->mii_media_active); 1495 1496 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1497 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) 1498 != miisc->mii_inst) 1499 continue; 1500 mii_phy_update(miisc, MII_POLLSTAT); 1501 } 1502 } 1503 E6000SW_UNLOCK(sc); 1504 } 1505 1506 static void 1507 e6000sw_setup(device_t dev, e6000sw_softc_t *sc) 1508 { 1509 uint32_t atu_ctrl; 1510 1511 /* Set aging time. */ 1512 atu_ctrl = e6000sw_readreg(sc, REG_GLOBAL, ATU_CONTROL); 1513 atu_ctrl &= ~ATU_CONTROL_AGETIME_MASK; 1514 atu_ctrl |= E6000SW_DEFAULT_AGETIME << ATU_CONTROL_AGETIME; 1515 e6000sw_writereg(sc, REG_GLOBAL, ATU_CONTROL, atu_ctrl); 1516 1517 /* Send all with specific mac address to cpu port */ 1518 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_2x, MGMT_EN_ALL); 1519 e6000sw_writereg(sc, REG_GLOBAL2, MGMT_EN_0x, MGMT_EN_ALL); 1520 1521 /* Disable Remote Management */ 1522 e6000sw_writereg(sc, REG_GLOBAL, SWITCH_GLOBAL_CONTROL2, 0); 1523 1524 /* Disable loopback filter and flow control messages */ 1525 e6000sw_writereg(sc, REG_GLOBAL2, SWITCH_MGMT, 1526 SWITCH_MGMT_PRI_MASK | 1527 (1 << SWITCH_MGMT_RSVD2CPU) | 1528 SWITCH_MGMT_FC_PRI_MASK | 1529 (1 << SWITCH_MGMT_FORCEFLOW)); 1530 1531 e6000sw_atu_flush(dev, sc, NO_OPERATION); 1532 e6000sw_atu_mac_table(dev, sc, NULL, NO_OPERATION); 1533 e6000sw_set_atustat(dev, sc, 0, COUNT_ALL); 1534 } 1535 1536 static void 1537 e6000sw_set_atustat(device_t dev, e6000sw_softc_t *sc, int bin, int flag) 1538 { 1539 1540 e6000sw_readreg(sc, REG_GLOBAL2, ATU_STATS); 1541 e6000sw_writereg(sc, REG_GLOBAL2, ATU_STATS, (bin << ATU_STATS_BIN ) | 1542 (flag << ATU_STATS_FLAG)); 1543 } 1544 1545 static int 1546 e6000sw_atu_mac_table(device_t dev, e6000sw_softc_t *sc, struct atu_opt *atu, 1547 int flag) 1548 { 1549 uint16_t ret_opt; 1550 uint16_t ret_data; 1551 1552 if (flag == NO_OPERATION) 1553 return (0); 1554 else if ((flag & (LOAD_FROM_FIB | PURGE_FROM_FIB | GET_NEXT_IN_FIB | 1555 GET_VIOLATION_DATA | CLEAR_VIOLATION_DATA)) == 0) { 1556 device_printf(dev, "Wrong Opcode for ATU operation\n"); 1557 return (EINVAL); 1558 } 1559 1560 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1561 device_printf(dev, "ATU unit is busy, cannot access\n"); 1562 return (EBUSY); 1563 } 1564 1565 ret_opt = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1566 if (flag & LOAD_FROM_FIB) { 1567 ret_data = e6000sw_readreg(sc, REG_GLOBAL, ATU_DATA); 1568 e6000sw_writereg(sc, REG_GLOBAL2, ATU_DATA, (ret_data & 1569 ~ENTRY_STATE)); 1570 } 1571 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR01, atu->mac_01); 1572 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR23, atu->mac_23); 1573 e6000sw_writereg(sc, REG_GLOBAL, ATU_MAC_ADDR45, atu->mac_45); 1574 e6000sw_writereg(sc, REG_GLOBAL, ATU_FID, atu->fid); 1575 1576 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1577 (ret_opt | ATU_UNIT_BUSY | flag)); 1578 1579 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1580 device_printf(dev, "Timeout while waiting ATU\n"); 1581 else if (flag & GET_NEXT_IN_FIB) { 1582 atu->mac_01 = e6000sw_readreg(sc, REG_GLOBAL, 1583 ATU_MAC_ADDR01); 1584 atu->mac_23 = e6000sw_readreg(sc, REG_GLOBAL, 1585 ATU_MAC_ADDR23); 1586 atu->mac_45 = e6000sw_readreg(sc, REG_GLOBAL, 1587 ATU_MAC_ADDR45); 1588 } 1589 1590 return (0); 1591 } 1592 1593 static int 1594 e6000sw_atu_flush(device_t dev, e6000sw_softc_t *sc, int flag) 1595 { 1596 uint32_t reg; 1597 1598 if (flag == NO_OPERATION) 1599 return (0); 1600 1601 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) { 1602 device_printf(dev, "ATU unit is busy, cannot access\n"); 1603 return (EBUSY); 1604 } 1605 reg = e6000sw_readreg(sc, REG_GLOBAL, ATU_OPERATION); 1606 e6000sw_writereg(sc, REG_GLOBAL, ATU_OPERATION, 1607 (reg | ATU_UNIT_BUSY | flag)); 1608 if (E6000SW_WAITREADY(sc, ATU_OPERATION, ATU_UNIT_BUSY)) 1609 device_printf(dev, "Timeout while flushing ATU\n"); 1610 1611 return (0); 1612 } 1613 1614 static int 1615 e6000sw_vtu_flush(e6000sw_softc_t *sc) 1616 { 1617 1618 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1619 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1620 return (EBUSY); 1621 } 1622 1623 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, VTU_FLUSH | VTU_BUSY); 1624 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1625 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1626 return (ETIMEDOUT); 1627 } 1628 1629 return (0); 1630 } 1631 1632 static int 1633 e6000sw_vtu_update(e6000sw_softc_t *sc, int purge, int vid, int fid, 1634 int members, int untagged) 1635 { 1636 int i, op; 1637 uint32_t data[2]; 1638 1639 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1640 device_printf(sc->dev, "VTU unit is busy, cannot access\n"); 1641 return (EBUSY); 1642 } 1643 1644 *data = (vid & VTU_VID_MASK); 1645 if (purge == 0) 1646 *data |= VTU_VID_VALID; 1647 e6000sw_writereg(sc, REG_GLOBAL, VTU_VID, *data); 1648 1649 if (purge == 0) { 1650 data[0] = 0; 1651 data[1] = 0; 1652 for (i = 0; i < sc->num_ports; i++) { 1653 if ((untagged & (1 << i)) != 0) 1654 data[i / VTU_PPREG(sc)] |= 1655 VTU_PORT_UNTAGGED << VTU_PORT(sc, i); 1656 else if ((members & (1 << i)) != 0) 1657 data[i / VTU_PPREG(sc)] |= 1658 VTU_PORT_TAGGED << VTU_PORT(sc, i); 1659 else 1660 data[i / VTU_PPREG(sc)] |= 1661 VTU_PORT_DISCARD << VTU_PORT(sc, i); 1662 } 1663 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA, data[0]); 1664 e6000sw_writereg(sc, REG_GLOBAL, VTU_DATA2, data[1]); 1665 e6000sw_writereg(sc, REG_GLOBAL, VTU_FID, 1666 fid & VTU_FID_MASK(sc)); 1667 op = VTU_LOAD; 1668 } else 1669 op = VTU_PURGE; 1670 1671 e6000sw_writereg(sc, REG_GLOBAL, VTU_OPERATION, op | VTU_BUSY); 1672 if (E6000SW_WAITREADY(sc, VTU_OPERATION, VTU_BUSY)) { 1673 device_printf(sc->dev, "Timeout while flushing VTU\n"); 1674 return (ETIMEDOUT); 1675 } 1676 1677 return (0); 1678 } 1679