1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Aleksandr Rybalko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __AR8X16_SWITCHREG_H__ 32 #define __AR8X16_SWITCHREG_H__ 33 34 /* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */ 35 /* 36 * Register manipulation macros that expect bit field defines 37 * to follow the convention that an _S suffix is appended for 38 * a shift count, while the field mask has no suffix. 39 */ 40 #define SM(_v, _f) (((_v) << _f##_S) & (_f)) 41 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 42 43 /* XXX Linux define compatibility stuff */ 44 #define BIT(_m) (1UL << (_m)) 45 #define BITM(_count) ((1UL << (_count)) - 1) 46 #define BITS(_shift, _count) (BITM(_count) << (_shift)) 47 48 /* Atheros specific MII registers */ 49 #define MII_ATH_MMD_ADDR 0x0d 50 #define MII_ATH_MMD_DATA 0x0e 51 #define MII_ATH_DBG_ADDR 0x1d 52 #define MII_ATH_DBG_DATA 0x1e 53 54 #define AR8X16_REG_MASK_CTRL 0x0000 55 #define AR8X16_MASK_CTRL_REV_MASK 0x000000ff 56 #define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00 57 #define AR8X16_MASK_CTRL_VER_SHIFT 8 58 #define AR8X16_MASK_CTRL_SOFT_RESET (1U << 31) 59 60 #define AR8X16_REG_MODE 0x0008 61 /* DIR-615 E4 U-Boot */ 62 #define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0 63 /* From Ubiquiti RSPRO */ 64 #define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea 65 #define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2 66 /* AVM Fritz!Box 7390 */ 67 #define AR8X16_MODE_GMII 0x010e5b71 68 /* from avm_cpmac/linux_ar_reg.h */ 69 #define AR8X16_MODE_RESERVED 0x000e1b20 70 #define AR8X16_MODE_MAC0_GMII_EN (1u << 0) 71 #define AR8X16_MODE_MAC0_RGMII_EN (1u << 1) 72 #define AR8X16_MODE_PHY4_GMII_EN (1u << 2) 73 #define AR8X16_MODE_PHY4_RGMII_EN (1u << 3) 74 #define AR8X16_MODE_MAC0_MAC_MODE (1u << 4) 75 #define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6) 76 #define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7) 77 #define AR8X16_MODE_MAC5_MAC_MODE (1u << 14) 78 #define AR8X16_MODE_MAC5_PHY_MODE (1u << 15) 79 #define AR8X16_MODE_TXDELAY_S0 (1u << 21) 80 #define AR8X16_MODE_TXDELAY_S1 (1u << 22) 81 #define AR8X16_MODE_RXDELAY_S0 (1u << 23) 82 #define AR8X16_MODE_LED_OPEN_EN (1u << 24) 83 #define AR8X16_MODE_SPI_EN (1u << 25) 84 #define AR8X16_MODE_RXDELAY_S1 (1u << 26) 85 #define AR8X16_MODE_POWER_ON_SEL (1u << 31) 86 87 #define AR8X16_REG_ISR 0x0010 88 #define AR8X16_REG_IMR 0x0014 89 90 #define AR8X16_REG_SW_MAC_ADDR0 0x0020 91 #define AR8X16_REG_SW_MAC_ADDR1 0x0024 92 93 #define AR8X16_REG_FLOOD_MASK 0x002c 94 #define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26) 95 96 #define AR8X16_REG_GLOBAL_CTRL 0x0030 97 #define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff 98 #define AR8216_GLOBAL_CTRL_MTU_MASK_S 0 99 #define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff 100 #define AR8316_GLOBAL_CTRL_MTU_MASK_S 0 101 #define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff 102 #define AR8236_GLOBAL_CTRL_MTU_MASK_S 0 103 #define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff 104 #define AR7240_GLOBAL_CTRL_MTU_MASK_S 0 105 106 #define AR8X16_REG_VLAN_CTRL 0x0040 107 #define AR8X16_VLAN_OP 0x00000007 108 #define AR8X16_VLAN_OP_NOOP 0x0 109 #define AR8X16_VLAN_OP_FLUSH 0x1 110 #define AR8X16_VLAN_OP_LOAD 0x2 111 #define AR8X16_VLAN_OP_PURGE 0x3 112 #define AR8X16_VLAN_OP_REMOVE_PORT 0x4 113 #define AR8X16_VLAN_OP_GET_NEXT 0x5 114 #define AR8X16_VLAN_OP_GET 0x6 115 #define AR8X16_VLAN_ACTIVE (1 << 3) 116 #define AR8X16_VLAN_FULL (1 << 4) 117 #define AR8X16_VLAN_PORT 0x00000f00 118 #define AR8X16_VLAN_PORT_SHIFT 8 119 #define AR8X16_VLAN_VID 0x0fff0000 120 #define AR8X16_VLAN_VID_SHIFT 16 121 #define AR8X16_VLAN_PRIO 0x70000000 122 #define AR8X16_VLAN_PRIO_SHIFT 28 123 #define AR8X16_VLAN_PRIO_EN (1U << 31) 124 125 #define AR8X16_REG_VLAN_DATA 0x0044 126 #define AR8X16_VLAN_MEMBER 0x0000003f 127 #define AR8X16_VLAN_VALID (1 << 11) 128 129 #define AR8216_REG_ATU 0x0050 130 #define AR8216_ATU_OP BITS(0, 3) 131 #define AR8216_ATU_OP_NOOP 0x0 132 #define AR8216_ATU_OP_FLUSH 0x1 133 #define AR8216_ATU_OP_LOAD 0x2 134 #define AR8216_ATU_OP_PURGE 0x3 135 #define AR8216_ATU_OP_FLUSH_LOCKED 0x4 136 #define AR8216_ATU_OP_FLUSH_UNICAST 0x5 137 #define AR8216_ATU_OP_GET_NEXT 0x6 138 #define AR8216_ATU_ACTIVE BIT(3) 139 #define AR8216_ATU_PORT_NUM BITS(8, 4) 140 #define AR8216_ATU_FULL_VIO BIT(12) 141 #define AR8216_ATU_ADDR4 BITS(16, 8) 142 #define AR8216_ATU_ADDR5 BITS(24, 8) 143 144 #define AR8216_REG_ATU_DATA 0x0054 145 #define AR8216_ATU_ADDR3 BITS(0, 8) 146 #define AR8216_ATU_ADDR2 BITS(8, 8) 147 #define AR8216_ATU_ADDR1 BITS(16, 8) 148 #define AR8216_ATU_ADDR0 BITS(24, 8) 149 150 #define AR8X16_REG_ARL_CTRL2 0x0058 151 152 #define AR8216_REG_ATU_CTRL 0x005C 153 #define AR8216_ATU_CTRL_AGE_EN BIT(17) 154 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) 155 #define AR8216_ATU_CTRL_AGE_TIME_S 0 156 157 #define AR8X16_REG_AT_CTRL 0x005c 158 #define AR8X16_AT_CTRL_ARP_EN (1 << 20) 159 160 #define AR8X16_REG_IP_PRIORITY_1 0x0060 161 #define AR8X16_REG_IP_PRIORITY_2 0x0064 162 #define AR8X16_REG_IP_PRIORITY_3 0x0068 163 #define AR8X16_REG_IP_PRIORITY_4 0x006C 164 165 #define AR8X16_REG_TAG_PRIO 0x0070 166 167 #define AR8X16_REG_SERVICE_TAG 0x0074 168 #define AR8X16_SERVICE_TAG_MASK 0x0000ffff 169 170 #define AR8X16_REG_CPU_PORT 0x0078 171 #define AR8X16_MIRROR_PORT_SHIFT 4 172 #define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT) 173 #define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT) 174 #define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf) 175 #define AR8X16_CPU_PORT_EN (1 << 8) 176 177 #define AR8X16_REG_MIB_FUNC0 0x0080 178 #define AR8X16_MIB_TIMER_MASK 0x0000ffff 179 #define AR8X16_MIB_AT_HALF_EN (1 << 16) 180 #define AR8X16_MIB_BUSY (1 << 17) 181 #define AR8X16_MIB_FUNC_SHIFT 24 182 #define AR8X16_MIB_FUNC_NO_OP 0x0 183 #define AR8X16_MIB_FUNC_FLUSH 0x1 184 #define AR8X16_MIB_FUNC_CAPTURE 0x3 185 #define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */ 186 187 #define AR934X_MIB_ENABLE (1 << 30) 188 189 #define AR8X16_REG_MDIO_HIGH_ADDR 0x0094 190 191 #define AR8X16_REG_MDIO_CTRL 0x0098 192 #define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff 193 #define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16 194 #define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21 195 #define AR8X16_MDIO_CTRL_CMD_WRITE 0 196 #define AR8X16_MDIO_CTRL_CMD_READ (1 << 27) 197 #define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30) 198 #define AR8X16_MDIO_CTRL_BUSY (1U << 31) 199 200 #define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100) 201 202 #define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000) 203 #define AR8X16_PORT_STS_SPEED_MASK 0x00000003 204 #define AR8X16_PORT_STS_SPEED_10 0 205 #define AR8X16_PORT_STS_SPEED_100 1 206 #define AR8X16_PORT_STS_SPEED_1000 2 207 #define AR8X16_PORT_STS_TXMAC (1 << 2) 208 #define AR8X16_PORT_STS_RXMAC (1 << 3) 209 #define AR8X16_PORT_STS_TXFLOW (1 << 4) 210 #define AR8X16_PORT_STS_RXFLOW (1 << 5) 211 #define AR8X16_PORT_STS_DUPLEX (1 << 6) 212 #define AR8X16_PORT_STS_LINK_UP (1 << 8) 213 #define AR8X16_PORT_STS_LINK_AUTO (1 << 9) 214 #define AR8X16_PORT_STS_LINK_PAUSE (1 << 10) 215 216 #define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004) 217 #define AR8X16_PORT_CTRL_STATE_MASK 0x00000007 218 #define AR8X16_PORT_CTRL_STATE_DISABLED 0 219 #define AR8X16_PORT_CTRL_STATE_BLOCK 1 220 #define AR8X16_PORT_CTRL_STATE_LISTEN 2 221 #define AR8X16_PORT_CTRL_STATE_LEARN 3 222 #define AR8X16_PORT_CTRL_STATE_FORWARD 4 223 #define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7) 224 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8 225 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0 226 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1 227 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2 228 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3 229 #define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10) 230 #define AR8X16_PORT_CTRL_HEADER (1 << 11) 231 #define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12) 232 #define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13) 233 #define AR8X16_PORT_CTRL_LEARN (1 << 14) 234 #define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15) 235 #define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16) 236 #define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17) 237 238 #define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008) 239 240 #define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0 241 #define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16 242 #define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000 243 #define AR8X16_PORT_VLAN_MODE_SHIFT 30 244 #define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0 245 #define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1 246 #define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2 247 #define AR8X16_PORT_VLAN_MODE_SECURE 3 248 249 #define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c) 250 #define AR8X16_PORT_RATE_LIM_128KB 0 251 #define AR8X16_PORT_RATE_LIM_256KB 1 252 #define AR8X16_PORT_RATE_LIM_512KB 2 253 #define AR8X16_PORT_RATE_LIM_1MB 3 254 #define AR8X16_PORT_RATE_LIM_2MB 4 255 #define AR8X16_PORT_RATE_LIM_4MB 5 256 #define AR8X16_PORT_RATE_LIM_8MB 6 257 #define AR8X16_PORT_RATE_LIM_16MB 7 258 #define AR8X16_PORT_RATE_LIM_32MB 8 259 #define AR8X16_PORT_RATE_LIM_64MB 9 260 #define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24) 261 #define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23) 262 #define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000 263 #define AR8X16_PORT_RATE_LIM_IN_SHIFT 16 264 #define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f 265 #define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0 266 267 #define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010) 268 269 #define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100) 270 271 #define AR8X16_STATS_RXBROAD 0x0000 272 #define AR8X16_STATS_RXPAUSE 0x0004 273 #define AR8X16_STATS_RXMULTI 0x0008 274 #define AR8X16_STATS_RXFCSERR 0x000c 275 #define AR8X16_STATS_RXALIGNERR 0x0010 276 #define AR8X16_STATS_RXRUNT 0x0014 277 #define AR8X16_STATS_RXFRAGMENT 0x0018 278 #define AR8X16_STATS_RX64BYTE 0x001c 279 #define AR8X16_STATS_RX128BYTE 0x0020 280 #define AR8X16_STATS_RX256BYTE 0x0024 281 #define AR8X16_STATS_RX512BYTE 0x0028 282 #define AR8X16_STATS_RX1024BYTE 0x002c 283 #define AR8X16_STATS_RX1518BYTE 0x0030 284 #define AR8X16_STATS_RXMAXBYTE 0x0034 285 #define AR8X16_STATS_RXTOOLONG 0x0038 286 #define AR8X16_STATS_RXGOODBYTE 0x003c 287 #define AR8X16_STATS_RXBADBYTE 0x0044 288 #define AR8X16_STATS_RXOVERFLOW 0x004c 289 #define AR8X16_STATS_FILTERED 0x0050 290 #define AR8X16_STATS_TXBROAD 0x0054 291 #define AR8X16_STATS_TXPAUSE 0x0058 292 #define AR8X16_STATS_TXMULTI 0x005c 293 #define AR8X16_STATS_TXUNDERRUN 0x0060 294 #define AR8X16_STATS_TX64BYTE 0x0064 295 #define AR8X16_STATS_TX128BYTE 0x0068 296 #define AR8X16_STATS_TX256BYTE 0x006c 297 #define AR8X16_STATS_TX512BYTE 0x0070 298 #define AR8X16_STATS_TX1024BYTE 0x0074 299 #define AR8X16_STATS_TX1518BYTE 0x0078 300 #define AR8X16_STATS_TXMAXBYTE 0x007c 301 #define AR8X16_STATS_TXOVERSIZE 0x0080 302 #define AR8X16_STATS_TXBYTE 0x0084 303 #define AR8X16_STATS_TXCOLLISION 0x008c 304 #define AR8X16_STATS_TXABORTCOL 0x0090 305 #define AR8X16_STATS_TXMULTICOL 0x0094 306 #define AR8X16_STATS_TXSINGLECOL 0x0098 307 #define AR8X16_STATS_TXEXCDEFER 0x009c 308 #define AR8X16_STATS_TXDEFER 0x00a0 309 #define AR8X16_STATS_TXLATECOL 0x00a4 310 311 #define AR8X16_PORT_CPU 0 312 #define AR8X16_NUM_PORTS 6 313 #define AR8X16_NUM_PHYS 5 314 #define AR8X16_MAGIC 0xc000050e 315 316 #define AR8X16_PHY_ID1 0x004d 317 #define AR8X16_PHY_ID2 0xd041 318 319 #define AR8X16_PORT_MASK(_port) (1 << (_port)) 320 #define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1) 321 #define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port))) 322 323 #define AR8X16_MAX_VLANS 16 324 325 /* 326 * AR9340 switch specific definitions. 327 */ 328 329 #define AR934X_REG_OPER_MODE0 0x04 330 #define AR934X_OPER_MODE0_MAC_GMII_EN (1 << 6) 331 #define AR934X_OPER_MODE0_PHY_MII_EN (1 << 10) 332 333 #define AR934X_REG_OPER_MODE1 0x08 334 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN (1 << 28) 335 336 #define AR934X_REG_FLOOD_MASK 0x2c 337 #define AR934X_FLOOD_MASK_MC_DP(_p) (1 << (16 + (_p))) 338 #define AR934X_FLOOD_MASK_BC_DP(_p) (1 << (25 + (_p))) 339 340 #define AR934X_REG_QM_CTRL 0x3c 341 #define AR934X_QM_CTRL_ARP_EN (1 << 15) 342 343 #define AR934X_REG_AT_CTRL 0x5c 344 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15) 345 #define AR934X_AT_CTRL_AGE_EN (1 << 17) 346 #define AR934X_AT_CTRL_LEARN_CHANGE (1 << 18) 347 348 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) 349 350 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) 351 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0 352 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN (1 << 12) 353 #define AR934X_PORT_VLAN1_PORT_TLS_MODE (1 << 13) 354 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN (1 << 14) 355 #define AR934X_PORT_VLAN1_PORT_CLONE_EN (1 << 15) 356 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16 357 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN (1 << 28) 358 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29 359 360 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c) 361 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16 362 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30 363 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0 364 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1 365 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2 366 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3 367 368 /* 369 * AR8327 specific registers 370 */ 371 #define AR8327_NUM_PORTS 7 372 #define AR8327_NUM_PHYS 5 373 #define AR8327_PORTS_ALL 0x7f 374 375 #define AR8327_PORT_GMAC0 0 376 #define AR8327_PORT_GMAC6 6 377 378 #define AR8327_REG_MASK 0x000 379 380 #define AR8327_REG_PAD0_MODE 0x004 381 #define AR8327_REG_PAD5_MODE 0x008 382 #define AR8327_REG_PAD6_MODE 0x00c 383 384 #define AR8327_PAD_MAC_MII_RXCLK_SEL (1 << 0) 385 #define AR8327_PAD_MAC_MII_TXCLK_SEL (1 << 1) 386 #define AR8327_PAD_MAC_MII_EN (1 << 2) 387 #define AR8327_PAD_MAC_GMII_RXCLK_SEL (1 << 4) 388 #define AR8327_PAD_MAC_GMII_TXCLK_SEL (1 << 5) 389 #define AR8327_PAD_MAC_GMII_EN (1 << 6) 390 #define AR8327_PAD_SGMII_EN (1 << 7) 391 #define AR8327_PAD_PHY_MII_RXCLK_SEL (1 << 8) 392 #define AR8327_PAD_PHY_MII_TXCLK_SEL (1 << 9) 393 #define AR8327_PAD_PHY_MII_EN (1 << 10) 394 #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL (1 << 11) 395 #define AR8327_PAD_PHY_GMII_RXCLK_SEL (1 << 12) 396 #define AR8327_PAD_PHY_GMII_TXCLK_SEL (1 << 13) 397 #define AR8327_PAD_PHY_GMII_EN (1 << 14) 398 #define AR8327_PAD_PHYX_GMII_EN (1 << 16) 399 #define AR8327_PAD_PHYX_RGMII_EN (1 << 17) 400 #define AR8327_PAD_PHYX_MII_EN (1 << 18) 401 #define AR8327_PAD_SGMII_DELAY_EN (1 << 19) 402 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) 403 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 404 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) 405 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 406 #define AR8327_PAD_RGMII_RXCLK_DELAY_EN (1 << 24) 407 #define AR8327_PAD_RGMII_TXCLK_DELAY_EN (1 << 25) 408 #define AR8327_PAD_RGMII_EN (1 << 26) 409 410 #define AR8327_REG_POWER_ON_STRIP 0x010 411 #define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1U << 31) 412 #define AR8327_POWER_ON_STRIP_LED_OPEN_EN (1 << 24) 413 #define AR8327_POWER_ON_STRIP_SERDES_AEN (1 << 7) 414 415 #define AR8327_REG_INT_STATUS0 0x020 416 #define AR8327_INT0_VT_DONE (1 << 20) 417 418 #define AR8327_REG_INT_STATUS1 0x024 419 #define AR8327_REG_INT_MASK0 0x028 420 #define AR8327_REG_INT_MASK1 0x02c 421 422 #define AR8327_REG_MODULE_EN 0x030 423 #define AR8327_MODULE_EN_MIB (1 << 0) 424 425 #define AR8327_REG_MIB_FUNC 0x034 426 #define AR8327_MIB_CPU_KEEP (1 << 20) 427 428 #define AR8327_REG_MDIO_CTRL 0x03c 429 430 #define AR8327_REG_SERVICE_TAG 0x048 431 #define AR8327_REG_LED_CTRL0 0x050 432 #define AR8327_REG_LED_CTRL1 0x054 433 #define AR8327_REG_LED_CTRL2 0x058 434 #define AR8327_REG_LED_CTRL3 0x05c 435 #define AR8327_REG_MAC_ADDR0 0x060 436 #define AR8327_REG_MAC_ADDR1 0x064 437 438 #define AR8327_REG_MAX_FRAME_SIZE 0x078 439 #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) 440 441 #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) 442 443 #define AR8327_REG_HEADER_CTRL 0x098 444 #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) 445 446 #define AR8327_REG_SGMII_CTRL 0x0e0 447 #define AR8327_SGMII_CTRL_EN_PLL (1 << 1) 448 #define AR8327_SGMII_CTRL_EN_RX (1 << 2) 449 #define AR8327_SGMII_CTRL_EN_TX (1 << 3) 450 451 #define AR8327_REG_EEE_CTRL 0x100 452 #define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) 453 454 #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) 455 #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) 456 #define AR8327_PORT_VLAN0_DEF_SVID_S 0 457 #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) 458 #define AR8327_PORT_VLAN0_DEF_CVID_S 16 459 460 #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) 461 #define AR8327_PORT_VLAN1_PORT_VLAN_PROP (1 << 6) 462 #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) 463 #define AR8327_PORT_VLAN1_OUT_MODE_S 12 464 #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 465 #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 466 #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 467 #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 468 469 #define AR8327_REG_ATU_DATA0 0x600 470 #define AR8327_REG_ATU_DATA1 0x604 471 #define AR8327_REG_ATU_DATA2 0x608 472 473 #define AR8327_REG_ATU_FUNC 0x60c 474 #define AR8327_ATU_FUNC_OP BITS(0, 4) 475 #define AR8327_ATU_FUNC_OP_NOOP 0x0 476 #define AR8327_ATU_FUNC_OP_FLUSH 0x1 477 #define AR8327_ATU_FUNC_OP_LOAD 0x2 478 #define AR8327_ATU_FUNC_OP_PURGE 0x3 479 #define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4 480 #define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5 481 #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 482 #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 483 #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 484 #define AR8327_ATU_FUNC_BUSY (1U << 31) 485 486 #define AR8327_REG_VTU_FUNC0 0x0610 487 #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) 488 #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) 489 #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 490 #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 491 #define AR8327_VTU_FUNC0_EG_MODE_TAG 2 492 #define AR8327_VTU_FUNC0_EG_MODE_NOT 3 493 #define AR8327_VTU_FUNC0_IVL (1 << 19) 494 #define AR8327_VTU_FUNC0_VALID (1 << 20) 495 496 #define AR8327_REG_VTU_FUNC1 0x0614 497 #define AR8327_VTU_FUNC1_OP BITS(0, 3) 498 #define AR8327_VTU_FUNC1_OP_NOOP 0 499 #define AR8327_VTU_FUNC1_OP_FLUSH 1 500 #define AR8327_VTU_FUNC1_OP_LOAD 2 501 #define AR8327_VTU_FUNC1_OP_PURGE 3 502 #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 503 #define AR8327_VTU_FUNC1_OP_GET_NEXT 5 504 #define AR8327_VTU_FUNC1_OP_GET_ONE 6 505 #define AR8327_VTU_FUNC1_FULL (1 << 4) 506 #define AR8327_VTU_FUNC1_PORT (1 << 8, 4) 507 #define AR8327_VTU_FUNC1_PORT_S 8 508 #define AR8327_VTU_FUNC1_VID (1 << 16, 12) 509 #define AR8327_VTU_FUNC1_VID_S 16 510 #define AR8327_VTU_FUNC1_BUSY (1U << 31) 511 512 #define AR8327_REG_FWD_CTRL0 0x620 513 #define AR8327_FWD_CTRL0_CPU_PORT_EN (1 << 10) 514 #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) 515 #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 516 517 #define AR8327_REG_FWD_CTRL1 0x624 518 #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) 519 #define AR8327_FWD_CTRL1_UC_FLOOD_S 0 520 #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) 521 #define AR8327_FWD_CTRL1_MC_FLOOD_S 8 522 #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) 523 #define AR8327_FWD_CTRL1_BC_FLOOD_S 16 524 #define AR8327_FWD_CTRL1_IGMP BITS(24, 7) 525 #define AR8327_FWD_CTRL1_IGMP_S 24 526 527 #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) 528 #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) 529 #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) 530 #define AR8327_PORT_LOOKUP_IN_MODE_S 8 531 #define AR8327_PORT_LOOKUP_STATE BITS(16, 3) 532 #define AR8327_PORT_LOOKUP_STATE_S 16 533 #define AR8327_PORT_LOOKUP_LEARN (1 << 20) 534 #define AR8327_PORT_LOOKUP_ING_MIRROR_EN (1 << 25) 535 536 #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) 537 538 #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) 539 #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN (1 << 16) 540 541 #define AR8327_REG_PORT_STATS_BASE(_i) (0x1000 + (_i) * 0x100) 542 543 #endif /* __AR8X16_SWITCHREG_H__ */ 544