1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Aleksandr Rybalko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __AR8X16_SWITCHREG_H__ 32 #define __AR8X16_SWITCHREG_H__ 33 34 /* XXX doesn't belong here; stolen shamelessly from ath_hal/ah_internal.h */ 35 /* 36 * Register manipulation macros that expect bit field defines 37 * to follow the convention that an _S suffix is appended for 38 * a shift count, while the field mask has no suffix. 39 */ 40 #define SM(_v, _f) (((_v) << _f##_S) & (_f)) 41 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 42 43 /* XXX Linux define compatibility stuff */ 44 #define BIT(_m) (1UL << (_m)) 45 #define BITM(_count) ((1UL << (_count)) - 1) 46 #define BITS(_shift, _count) (BITM(_count) << (_shift)) 47 48 /* Atheros specific MII registers */ 49 #define MII_ATH_MMD_ADDR 0x0d 50 #define MII_ATH_MMD_DATA 0x0e 51 #define MII_ATH_DBG_ADDR 0x1d 52 #define MII_ATH_DBG_DATA 0x1e 53 54 #define AR8X16_REG_MASK_CTRL 0x0000 55 #define AR8X16_MASK_CTRL_REV_MASK 0x000000ff 56 #define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00 57 #define AR8X16_MASK_CTRL_VER_SHIFT 8 58 #define AR8X16_MASK_CTRL_SOFT_RESET (1U << 31) 59 60 #define AR8X16_REG_MODE 0x0008 61 /* DIR-615 E4 U-Boot */ 62 #define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0 63 /* From Ubiquiti RSPRO */ 64 #define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea 65 #define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2 66 /* AVM Fritz!Box 7390 */ 67 #define AR8X16_MODE_GMII 0x010e5b71 68 /* from avm_cpmac/linux_ar_reg.h */ 69 #define AR8X16_MODE_RESERVED 0x000e1b20 70 #define AR8X16_MODE_MAC0_GMII_EN (1u << 0) 71 #define AR8X16_MODE_MAC0_RGMII_EN (1u << 1) 72 #define AR8X16_MODE_PHY4_GMII_EN (1u << 2) 73 #define AR8X16_MODE_PHY4_RGMII_EN (1u << 3) 74 #define AR8X16_MODE_MAC0_MAC_MODE (1u << 4) 75 #define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6) 76 #define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7) 77 #define AR8X16_MODE_MAC5_MAC_MODE (1u << 14) 78 #define AR8X16_MODE_MAC5_PHY_MODE (1u << 15) 79 #define AR8X16_MODE_TXDELAY_S0 (1u << 21) 80 #define AR8X16_MODE_TXDELAY_S1 (1u << 22) 81 #define AR8X16_MODE_RXDELAY_S0 (1u << 23) 82 #define AR8X16_MODE_LED_OPEN_EN (1u << 24) 83 #define AR8X16_MODE_SPI_EN (1u << 25) 84 #define AR8X16_MODE_RXDELAY_S1 (1u << 26) 85 #define AR8X16_MODE_POWER_ON_SEL (1u << 31) 86 87 #define AR8X16_REG_ISR 0x0010 88 #define AR8X16_REG_IMR 0x0014 89 90 #define AR8X16_REG_SW_MAC_ADDR0 0x0020 91 #define AR8X16_REG_SW_MAC_ADDR1 0x0024 92 93 #define AR8X16_REG_FLOOD_MASK 0x002c 94 #define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26) 95 96 #define AR8X16_REG_GLOBAL_CTRL 0x0030 97 #define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff 98 #define AR8216_GLOBAL_CTRL_MTU_MASK_S 0 99 #define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff 100 #define AR8316_GLOBAL_CTRL_MTU_MASK_S 0 101 #define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff 102 #define AR8236_GLOBAL_CTRL_MTU_MASK_S 0 103 #define AR7240_GLOBAL_CTRL_MTU_MASK 0x00003fff 104 #define AR7240_GLOBAL_CTRL_MTU_MASK_S 0 105 106 #define AR8X16_REG_VLAN_CTRL 0x0040 107 #define AR8X16_VLAN_OP 0x00000007 108 #define AR8X16_VLAN_OP_NOOP 0x0 109 #define AR8X16_VLAN_OP_FLUSH 0x1 110 #define AR8X16_VLAN_OP_LOAD 0x2 111 #define AR8X16_VLAN_OP_PURGE 0x3 112 #define AR8X16_VLAN_OP_REMOVE_PORT 0x4 113 #define AR8X16_VLAN_OP_GET_NEXT 0x5 114 #define AR8X16_VLAN_OP_GET 0x6 115 #define AR8X16_VLAN_ACTIVE (1 << 3) 116 #define AR8X16_VLAN_FULL (1 << 4) 117 #define AR8X16_VLAN_PORT 0x00000f00 118 #define AR8X16_VLAN_PORT_SHIFT 8 119 #define AR8X16_VLAN_VID 0x0fff0000 120 #define AR8X16_VLAN_VID_SHIFT 16 121 #define AR8X16_VLAN_PRIO 0x70000000 122 #define AR8X16_VLAN_PRIO_SHIFT 28 123 #define AR8X16_VLAN_PRIO_EN (1U << 31) 124 125 #define AR8X16_REG_VLAN_DATA 0x0044 126 #define AR8X16_VLAN_MEMBER 0x0000003f 127 #define AR8X16_VLAN_VALID (1 << 11) 128 129 #define AR8216_REG_ATU 0x0050 130 #define AR8216_ATU_OP BITS(0, 3) 131 #define AR8216_ATU_OP_NOOP 0x0 132 #define AR8216_ATU_OP_FLUSH 0x1 133 #define AR8216_ATU_OP_LOAD 0x2 134 #define AR8216_ATU_OP_PURGE 0x3 135 #define AR8216_ATU_OP_FLUSH_LOCKED 0x4 136 #define AR8216_ATU_OP_FLUSH_UNICAST 0x5 137 #define AR8216_ATU_OP_GET_NEXT 0x6 138 #define AR8216_ATU_ACTIVE BIT(3) 139 #define AR8216_ATU_PORT_NUM BITS(8, 4) 140 #define AR8216_ATU_PORT_NUM_S 8 141 #define AR8216_ATU_FULL_VIO BIT(12) 142 #define AR8216_ATU_ADDR4 BITS(16, 8) 143 #define AR8216_ATU_ADDR4_S 16 144 #define AR8216_ATU_ADDR5 BITS(24, 8) 145 #define AR8216_ATU_ADDR5_S 24 146 147 #define AR8216_REG_ATU_DATA 0x0054 148 #define AR8216_ATU_ADDR3 BITS(0, 8) 149 #define AR8216_ATU_ADDR3_S 0 150 #define AR8216_ATU_ADDR2 BITS(8, 8) 151 #define AR8216_ATU_ADDR2_S 8 152 #define AR8216_ATU_ADDR1 BITS(16, 8) 153 #define AR8216_ATU_ADDR1_S 16 154 #define AR8216_ATU_ADDR0 BITS(24, 8) 155 #define AR8216_ATU_ADDR0_S 24 156 157 #define AR8216_REG_ATU_CTRL2 0x0058 158 #define AR8216_ATU_CTRL2_DESPORT BITS(0, 5) 159 #define AR8216_ATU_CTRL2_DESPORT_S 0 160 #define AR8216_ATU_CTRL2_AT_PRIORITY BITS(10, 2) 161 #define AR8216_ATU_CTRL2_AT_PRIORITY_EN BIT(12) 162 #define AR8216_ATU_CTRL2_MIRROR_EN BIT(13) 163 #define AR8216_ATU_CTRL2_SA_DROP_EN BIT(14) 164 #define AR8216_ATU_CTRL2_AT_STATUS BITS(16, 4) 165 #define AR8216_ATU_CTRL2_AT_STATUS_S 16 166 #define AR8216_ATU_CTRL2_VLAN_LEAKY_EN BIT(24) 167 #define AR8216_ATU_CTRL2_REDIRECT2CPU BIT(25) 168 #define AR8216_ATU_CTRL2_COPY2CPU BIT(26) 169 170 #define AR8216_REG_ATU_CTRL 0x005C 171 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16) 172 #define AR8216_ATU_CTRL_AGE_TIME_S 0 173 #define AR8216_ATU_CTRL_AGE_EN BIT(17) 174 #define AR8216_ATU_CTRL_LEARN_CHANGE BIT(18) 175 #define AR8216_ATU_CTRL_ARP_EN BIT(20) 176 177 #define AR8X16_REG_IP_PRIORITY_1 0x0060 178 #define AR8X16_REG_IP_PRIORITY_2 0x0064 179 #define AR8X16_REG_IP_PRIORITY_3 0x0068 180 #define AR8X16_REG_IP_PRIORITY_4 0x006C 181 182 #define AR8X16_REG_TAG_PRIO 0x0070 183 184 #define AR8X16_REG_SERVICE_TAG 0x0074 185 #define AR8X16_SERVICE_TAG_MASK 0x0000ffff 186 187 #define AR8X16_REG_CPU_PORT 0x0078 188 #define AR8X16_MIRROR_PORT_SHIFT 4 189 #define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT) 190 #define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT) 191 #define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf) 192 #define AR8X16_CPU_PORT_EN (1 << 8) 193 194 #define AR8X16_REG_MIB_FUNC0 0x0080 195 #define AR8X16_MIB_TIMER_MASK 0x0000ffff 196 #define AR8X16_MIB_AT_HALF_EN (1 << 16) 197 #define AR8X16_MIB_BUSY (1 << 17) 198 #define AR8X16_MIB_FUNC_SHIFT 24 199 #define AR8X16_MIB_FUNC_NO_OP 0x0 200 #define AR8X16_MIB_FUNC_FLUSH 0x1 201 #define AR8X16_MIB_FUNC_CAPTURE 0x3 202 #define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */ 203 204 #define AR934X_MIB_ENABLE (1 << 30) 205 206 #define AR8X16_REG_MDIO_HIGH_ADDR 0x0094 207 208 #define AR8X16_REG_MDIO_CTRL 0x0098 209 #define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff 210 #define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16 211 #define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21 212 #define AR8X16_MDIO_CTRL_CMD_WRITE 0 213 #define AR8X16_MDIO_CTRL_CMD_READ (1 << 27) 214 #define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30) 215 #define AR8X16_MDIO_CTRL_BUSY (1U << 31) 216 217 #define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100) 218 219 #define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000) 220 #define AR8X16_PORT_STS_SPEED_MASK 0x00000003 221 #define AR8X16_PORT_STS_SPEED_10 0 222 #define AR8X16_PORT_STS_SPEED_100 1 223 #define AR8X16_PORT_STS_SPEED_1000 2 224 #define AR8X16_PORT_STS_TXMAC (1 << 2) 225 #define AR8X16_PORT_STS_RXMAC (1 << 3) 226 #define AR8X16_PORT_STS_TXFLOW (1 << 4) 227 #define AR8X16_PORT_STS_RXFLOW (1 << 5) 228 #define AR8X16_PORT_STS_DUPLEX (1 << 6) 229 #define AR8X16_PORT_STS_LINK_UP (1 << 8) 230 #define AR8X16_PORT_STS_LINK_AUTO (1 << 9) 231 #define AR8X16_PORT_STS_LINK_PAUSE (1 << 10) 232 233 #define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004) 234 #define AR8X16_PORT_CTRL_STATE_MASK 0x00000007 235 #define AR8X16_PORT_CTRL_STATE_DISABLED 0 236 #define AR8X16_PORT_CTRL_STATE_BLOCK 1 237 #define AR8X16_PORT_CTRL_STATE_LISTEN 2 238 #define AR8X16_PORT_CTRL_STATE_LEARN 3 239 #define AR8X16_PORT_CTRL_STATE_FORWARD 4 240 #define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7) 241 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8 242 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0 243 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1 244 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2 245 #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3 246 #define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10) 247 #define AR8X16_PORT_CTRL_HEADER (1 << 11) 248 #define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12) 249 #define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13) 250 #define AR8X16_PORT_CTRL_LEARN (1 << 14) 251 #define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15) 252 #define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16) 253 #define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17) 254 255 #define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008) 256 257 #define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0 258 #define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16 259 #define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000 260 #define AR8X16_PORT_VLAN_MODE_SHIFT 30 261 #define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0 262 #define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1 263 #define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2 264 #define AR8X16_PORT_VLAN_MODE_SECURE 3 265 266 #define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c) 267 #define AR8X16_PORT_RATE_LIM_128KB 0 268 #define AR8X16_PORT_RATE_LIM_256KB 1 269 #define AR8X16_PORT_RATE_LIM_512KB 2 270 #define AR8X16_PORT_RATE_LIM_1MB 3 271 #define AR8X16_PORT_RATE_LIM_2MB 4 272 #define AR8X16_PORT_RATE_LIM_4MB 5 273 #define AR8X16_PORT_RATE_LIM_8MB 6 274 #define AR8X16_PORT_RATE_LIM_16MB 7 275 #define AR8X16_PORT_RATE_LIM_32MB 8 276 #define AR8X16_PORT_RATE_LIM_64MB 9 277 #define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24) 278 #define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23) 279 #define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000 280 #define AR8X16_PORT_RATE_LIM_IN_SHIFT 16 281 #define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f 282 #define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0 283 284 #define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010) 285 286 #define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100) 287 288 #define AR8X16_STATS_RXBROAD 0x0000 289 #define AR8X16_STATS_RXPAUSE 0x0004 290 #define AR8X16_STATS_RXMULTI 0x0008 291 #define AR8X16_STATS_RXFCSERR 0x000c 292 #define AR8X16_STATS_RXALIGNERR 0x0010 293 #define AR8X16_STATS_RXRUNT 0x0014 294 #define AR8X16_STATS_RXFRAGMENT 0x0018 295 #define AR8X16_STATS_RX64BYTE 0x001c 296 #define AR8X16_STATS_RX128BYTE 0x0020 297 #define AR8X16_STATS_RX256BYTE 0x0024 298 #define AR8X16_STATS_RX512BYTE 0x0028 299 #define AR8X16_STATS_RX1024BYTE 0x002c 300 #define AR8X16_STATS_RX1518BYTE 0x0030 301 #define AR8X16_STATS_RXMAXBYTE 0x0034 302 #define AR8X16_STATS_RXTOOLONG 0x0038 303 #define AR8X16_STATS_RXGOODBYTE 0x003c 304 #define AR8X16_STATS_RXBADBYTE 0x0044 305 #define AR8X16_STATS_RXOVERFLOW 0x004c 306 #define AR8X16_STATS_FILTERED 0x0050 307 #define AR8X16_STATS_TXBROAD 0x0054 308 #define AR8X16_STATS_TXPAUSE 0x0058 309 #define AR8X16_STATS_TXMULTI 0x005c 310 #define AR8X16_STATS_TXUNDERRUN 0x0060 311 #define AR8X16_STATS_TX64BYTE 0x0064 312 #define AR8X16_STATS_TX128BYTE 0x0068 313 #define AR8X16_STATS_TX256BYTE 0x006c 314 #define AR8X16_STATS_TX512BYTE 0x0070 315 #define AR8X16_STATS_TX1024BYTE 0x0074 316 #define AR8X16_STATS_TX1518BYTE 0x0078 317 #define AR8X16_STATS_TXMAXBYTE 0x007c 318 #define AR8X16_STATS_TXOVERSIZE 0x0080 319 #define AR8X16_STATS_TXBYTE 0x0084 320 #define AR8X16_STATS_TXCOLLISION 0x008c 321 #define AR8X16_STATS_TXABORTCOL 0x0090 322 #define AR8X16_STATS_TXMULTICOL 0x0094 323 #define AR8X16_STATS_TXSINGLECOL 0x0098 324 #define AR8X16_STATS_TXEXCDEFER 0x009c 325 #define AR8X16_STATS_TXDEFER 0x00a0 326 #define AR8X16_STATS_TXLATECOL 0x00a4 327 328 #define AR8X16_PORT_CPU 0 329 #define AR8X16_NUM_PORTS 6 330 #define AR8X16_NUM_PHYS 5 331 #define AR8X16_MAGIC 0xc000050e 332 333 #define AR8X16_PHY_ID1 0x004d 334 #define AR8X16_PHY_ID2 0xd041 335 336 #define AR8X16_PORT_MASK(_port) (1 << (_port)) 337 #define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1) 338 #define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port))) 339 340 #define AR8X16_MAX_VLANS 16 341 342 /* 343 * AR9340 switch specific definitions. 344 */ 345 346 #define AR934X_REG_OPER_MODE0 0x04 347 #define AR934X_OPER_MODE0_MAC_GMII_EN (1 << 6) 348 #define AR934X_OPER_MODE0_PHY_MII_EN (1 << 10) 349 350 #define AR934X_REG_OPER_MODE1 0x08 351 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN (1 << 28) 352 353 #define AR934X_REG_FLOOD_MASK 0x2c 354 #define AR934X_FLOOD_MASK_MC_DP(_p) (1 << (16 + (_p))) 355 #define AR934X_FLOOD_MASK_BC_DP(_p) (1 << (25 + (_p))) 356 357 #define AR934X_REG_QM_CTRL 0x3c 358 #define AR934X_QM_CTRL_ARP_EN (1 << 15) 359 #define AR934X_QM_CTRL_ARP_COPY_EN (1 << 14) 360 361 #define AR934X_REG_AT_CTRL 0x5c 362 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15) 363 #define AR934X_AT_CTRL_AGE_EN (1 << 17) 364 #define AR934X_AT_CTRL_LEARN_CHANGE (1 << 18) 365 366 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) 367 368 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08) 369 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0 370 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN (1 << 12) 371 #define AR934X_PORT_VLAN1_PORT_TLS_MODE (1 << 13) 372 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN (1 << 14) 373 #define AR934X_PORT_VLAN1_PORT_CLONE_EN (1 << 15) 374 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16 375 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN (1 << 28) 376 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29 377 378 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c) 379 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16 380 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30 381 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0 382 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1 383 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2 384 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3 385 386 /* 387 * AR8327 specific registers 388 */ 389 #define AR8327_NUM_PORTS 7 390 #define AR8327_NUM_PHYS 5 391 #define AR8327_PORTS_ALL 0x7f 392 393 #define AR8327_PORT_GMAC0 0 394 #define AR8327_PORT_GMAC6 6 395 396 #define AR8327_REG_MASK 0x000 397 398 #define AR8327_REG_PAD0_MODE 0x004 399 #define AR8327_REG_PAD5_MODE 0x008 400 #define AR8327_REG_PAD6_MODE 0x00c 401 402 #define AR8327_PAD_MAC_MII_RXCLK_SEL (1 << 0) 403 #define AR8327_PAD_MAC_MII_TXCLK_SEL (1 << 1) 404 #define AR8327_PAD_MAC_MII_EN (1 << 2) 405 #define AR8327_PAD_MAC_GMII_RXCLK_SEL (1 << 4) 406 #define AR8327_PAD_MAC_GMII_TXCLK_SEL (1 << 5) 407 #define AR8327_PAD_MAC_GMII_EN (1 << 6) 408 #define AR8327_PAD_SGMII_EN (1 << 7) 409 #define AR8327_PAD_PHY_MII_RXCLK_SEL (1 << 8) 410 #define AR8327_PAD_PHY_MII_TXCLK_SEL (1 << 9) 411 #define AR8327_PAD_PHY_MII_EN (1 << 10) 412 #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL (1 << 11) 413 #define AR8327_PAD_PHY_GMII_RXCLK_SEL (1 << 12) 414 #define AR8327_PAD_PHY_GMII_TXCLK_SEL (1 << 13) 415 #define AR8327_PAD_PHY_GMII_EN (1 << 14) 416 #define AR8327_PAD_PHYX_GMII_EN (1 << 16) 417 #define AR8327_PAD_PHYX_RGMII_EN (1 << 17) 418 #define AR8327_PAD_PHYX_MII_EN (1 << 18) 419 #define AR8327_PAD_SGMII_DELAY_EN (1 << 19) 420 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) 421 #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 422 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) 423 #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 424 #define AR8327_PAD_RGMII_RXCLK_DELAY_EN (1 << 24) 425 #define AR8327_PAD_RGMII_TXCLK_DELAY_EN (1 << 25) 426 #define AR8327_PAD_RGMII_EN (1 << 26) 427 428 #define AR8327_REG_POWER_ON_STRIP 0x010 429 #define AR8327_POWER_ON_STRIP_POWER_ON_SEL (1U << 31) 430 #define AR8327_POWER_ON_STRIP_LED_OPEN_EN (1 << 24) 431 #define AR8327_POWER_ON_STRIP_SERDES_AEN (1 << 7) 432 433 #define AR8327_REG_INT_STATUS0 0x020 434 #define AR8327_INT0_VT_DONE (1 << 20) 435 436 #define AR8327_REG_INT_STATUS1 0x024 437 #define AR8327_REG_INT_MASK0 0x028 438 #define AR8327_REG_INT_MASK1 0x02c 439 440 #define AR8327_REG_MODULE_EN 0x030 441 #define AR8327_MODULE_EN_MIB (1 << 0) 442 443 #define AR8327_REG_MIB_FUNC 0x034 444 #define AR8327_MIB_CPU_KEEP (1 << 20) 445 446 #define AR8327_REG_MDIO_CTRL 0x03c 447 448 #define AR8327_REG_SERVICE_TAG 0x048 449 #define AR8327_REG_LED_CTRL0 0x050 450 #define AR8327_REG_LED_CTRL1 0x054 451 #define AR8327_REG_LED_CTRL2 0x058 452 #define AR8327_REG_LED_CTRL3 0x05c 453 #define AR8327_REG_MAC_ADDR0 0x060 454 #define AR8327_REG_MAC_ADDR1 0x064 455 456 #define AR8327_REG_MAX_FRAME_SIZE 0x078 457 #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) 458 459 #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) 460 461 #define AR8327_REG_HEADER_CTRL 0x098 462 #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) 463 464 #define AR8327_REG_SGMII_CTRL 0x0e0 465 #define AR8327_SGMII_CTRL_EN_PLL (1 << 1) 466 #define AR8327_SGMII_CTRL_EN_RX (1 << 2) 467 #define AR8327_SGMII_CTRL_EN_TX (1 << 3) 468 469 #define AR8327_REG_EEE_CTRL 0x100 470 #define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) 471 472 #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) 473 #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) 474 #define AR8327_PORT_VLAN0_DEF_SVID_S 0 475 #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) 476 #define AR8327_PORT_VLAN0_DEF_CVID_S 16 477 478 #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) 479 #define AR8327_PORT_VLAN1_PORT_VLAN_PROP (1 << 6) 480 #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) 481 #define AR8327_PORT_VLAN1_OUT_MODE_S 12 482 #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 483 #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 484 #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 485 #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 486 487 #define AR8327_REG_ATU_DATA0 0x600 488 #define AR8327_ATU_DATA0_MAC_ADDR3 BITS(0, 8) 489 #define AR8327_ATU_DATA0_MAC_ADDR3_S 0 490 #define AR8327_ATU_DATA0_MAC_ADDR2 BITS(8, 8) 491 #define AR8327_ATU_DATA0_MAC_ADDR2_S 8 492 #define AR8327_ATU_DATA0_MAC_ADDR1 BITS(16, 8) 493 #define AR8327_ATU_DATA0_MAC_ADDR1_S 16 494 #define AR8327_ATU_DATA0_MAC_ADDR0 BITS(24, 8) 495 #define AR8327_ATU_DATA0_MAC_ADDR0_S 24 496 497 #define AR8327_REG_ATU_DATA1 0x604 498 #define AR8327_ATU_DATA1_MAC_ADDR4 BITS(0, 8) 499 #define AR8327_ATU_DATA1_MAC_ADDR4_S 0 500 #define AR8327_ATU_DATA1_MAC_ADDR5 BITS(8, 8) 501 #define AR8327_ATU_DATA1_MAC_ADDR5_S 8 502 #define AR8327_ATU_DATA1_DEST_PORT BITS(16, 7) 503 #define AR8327_ATU_DATA1_DEST_PORT_S 16 504 #define AR8327_ATU_DATA1_CROSS_PORT_STATE_EN BIT(23) 505 #define AR8327_ATU_DATA1_PRI BITS(24, 3) 506 #define AR8327_ATU_DATA1_SVL_ENTRY BIT(27) 507 #define AR8327_ATU_DATA1_PRI_OVER_EN BIT(28) 508 #define AR8327_ATU_DATA1_MIRROR_EN BIT(29) 509 #define AR8327_ATU_DATA1_SA_DROP_EN BIT(30) 510 #define AR8327_ATU_DATA1_HASH_HIGH_ADDR BIT(31) 511 512 #define AR8327_REG_ATU_DATA2 0x608 513 #define AR8327_ATU_FUNC_DATA2_STATUS BITS(0, 4) 514 #define AR8327_ATU_FUNC_DATA2_STATUS_S 0 515 #define AR8327_ATU_FUNC_DATA2_VLAN_LEAKY_EN BIT(4) 516 #define AR8327_ATU_FUNC_DATA2_REDIRECT_TO_CPU BIT(5) 517 #define AR8327_ATU_FUNC_DATA2_COPY_TO_CPU BIT(6) 518 #define AR8327_ATU_FUNC_DATA2_SHORT_LOOP BIT(7) 519 #define AR8327_ATU_FUNC_DATA2_ATU_VID BITS(8, 12) 520 #define AR8327_ATU_FUNC_DATA2_ATU_VID_S 8 521 522 #define AR8327_REG_ATU_FUNC 0x60c 523 #define AR8327_ATU_FUNC_OP BITS(0, 4) 524 #define AR8327_ATU_FUNC_OP_NOOP 0x0 525 #define AR8327_ATU_FUNC_OP_FLUSH 0x1 526 #define AR8327_ATU_FUNC_OP_LOAD 0x2 527 #define AR8327_ATU_FUNC_OP_PURGE 0x3 528 #define AR8327_ATU_FUNC_OP_FLUSH_LOCKED 0x4 529 #define AR8327_ATU_FUNC_OP_FLUSH_UNICAST 0x5 530 #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 531 #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 532 #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 533 #define AR8327_ATU_FUNC_FLUSH_STATIC_EN BIT(4) 534 #define AR8327_ATU_FUNC_ENTRY_TYPE BIT(5) 535 #define AR8327_ATU_FUNC_PORT_NUM BITS(8, 4) 536 #define AR8327_ATU_FUNC_PORT_NUM_S 8 537 #define AR8327_ATU_FUNC_FULL_VIOLATION BIT(12) 538 #define AR8327_ATU_FUNC_MULTI_EN BIT(13) /* for GET_NEXT */ 539 #define AR8327_ATU_FUNC_PORT_EN BIT(14) /* for GET_NEXT */ 540 #define AR8327_ATU_FUNC_VID_EN BIT(15) /* for GET_NEXT */ 541 #define AR8327_ATU_FUNC_ATU_INDEX BITS(16, 5) 542 #define AR8327_ATU_FUNC_ATU_INDEX_S 16 543 #define AR8327_ATU_FUNC_TRUNK_PORT_NUM BITS(22, 3) /* for CHANGE_TRUNK */ 544 #define AR8327_ATU_FUNC_TRUNK_PORT_NUM_S 22 545 #define AR8327_ATU_FUNC_BUSY BIT(31) 546 547 #define AR8327_REG_VTU_FUNC0 0x0610 548 #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) 549 #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) 550 #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 551 #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 552 #define AR8327_VTU_FUNC0_EG_MODE_TAG 2 553 #define AR8327_VTU_FUNC0_EG_MODE_NOT 3 554 #define AR8327_VTU_FUNC0_IVL (1 << 19) 555 #define AR8327_VTU_FUNC0_VALID (1 << 20) 556 557 #define AR8327_REG_VTU_FUNC1 0x0614 558 #define AR8327_VTU_FUNC1_OP BITS(0, 3) 559 #define AR8327_VTU_FUNC1_OP_NOOP 0 560 #define AR8327_VTU_FUNC1_OP_FLUSH 1 561 #define AR8327_VTU_FUNC1_OP_LOAD 2 562 #define AR8327_VTU_FUNC1_OP_PURGE 3 563 #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 564 #define AR8327_VTU_FUNC1_OP_GET_NEXT 5 565 #define AR8327_VTU_FUNC1_OP_GET_ONE 6 566 #define AR8327_VTU_FUNC1_FULL (1 << 4) 567 #define AR8327_VTU_FUNC1_PORT (1 << 8, 4) 568 #define AR8327_VTU_FUNC1_PORT_S 8 569 #define AR8327_VTU_FUNC1_VID (1 << 16, 12) 570 #define AR8327_VTU_FUNC1_VID_S 16 571 #define AR8327_VTU_FUNC1_BUSY (1U << 31) 572 573 #define AR8327_REG_FWD_CTRL0 0x620 574 #define AR8327_FWD_CTRL0_CPU_PORT_EN (1 << 10) 575 #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) 576 #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 577 578 #define AR8327_REG_FWD_CTRL1 0x624 579 #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) 580 #define AR8327_FWD_CTRL1_UC_FLOOD_S 0 581 #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) 582 #define AR8327_FWD_CTRL1_MC_FLOOD_S 8 583 #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) 584 #define AR8327_FWD_CTRL1_BC_FLOOD_S 16 585 #define AR8327_FWD_CTRL1_IGMP BITS(24, 7) 586 #define AR8327_FWD_CTRL1_IGMP_S 24 587 588 #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) 589 #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) 590 #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) 591 #define AR8327_PORT_LOOKUP_IN_MODE_S 8 592 #define AR8327_PORT_LOOKUP_STATE BITS(16, 3) 593 #define AR8327_PORT_LOOKUP_STATE_S 16 594 #define AR8327_PORT_LOOKUP_LEARN (1 << 20) 595 #define AR8327_PORT_LOOKUP_ING_MIRROR_EN (1 << 25) 596 597 #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) 598 599 #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) 600 #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN (1 << 16) 601 602 #define AR8327_REG_PORT_STATS_BASE(_i) (0x1000 + (_i) * 0x100) 603 604 #endif /* __AR8X16_SWITCHREG_H__ */ 605