1a043e8c7SAdrian Chadd /*- 2a043e8c7SAdrian Chadd * Copyright (c) 2011 Aleksandr Rybalko. 3a043e8c7SAdrian Chadd * All rights reserved. 4a043e8c7SAdrian Chadd * 5a043e8c7SAdrian Chadd * Redistribution and use in source and binary forms, with or without 6a043e8c7SAdrian Chadd * modification, are permitted provided that the following conditions 7a043e8c7SAdrian Chadd * are met: 8a043e8c7SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 9a043e8c7SAdrian Chadd * notice, this list of conditions and the following disclaimer. 10a043e8c7SAdrian Chadd * 2. Redistributions in binary form must reproduce the above copyright 11a043e8c7SAdrian Chadd * notice, this list of conditions and the following disclaimer in the 12a043e8c7SAdrian Chadd * documentation and/or other materials provided with the distribution. 13a043e8c7SAdrian Chadd * 14a043e8c7SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15a043e8c7SAdrian Chadd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16a043e8c7SAdrian Chadd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17a043e8c7SAdrian Chadd * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18a043e8c7SAdrian Chadd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19a043e8c7SAdrian Chadd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20a043e8c7SAdrian Chadd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21a043e8c7SAdrian Chadd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22a043e8c7SAdrian Chadd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23a043e8c7SAdrian Chadd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24a043e8c7SAdrian Chadd * SUCH DAMAGE. 25a043e8c7SAdrian Chadd * 26a043e8c7SAdrian Chadd * $FreeBSD$ 27a043e8c7SAdrian Chadd */ 28a043e8c7SAdrian Chadd 29a043e8c7SAdrian Chadd #ifndef __AR8X16_SWITCHREG_H__ 30a043e8c7SAdrian Chadd #define __AR8X16_SWITCHREG_H__ 31a043e8c7SAdrian Chadd 32a043e8c7SAdrian Chadd /* Atheros specific MII registers */ 33a043e8c7SAdrian Chadd #define MII_ATH_DBG_ADDR 0x1d 34a043e8c7SAdrian Chadd #define MII_ATH_DBG_DATA 0x1e 35a043e8c7SAdrian Chadd 36a043e8c7SAdrian Chadd #define AR8X16_REG_MASK_CTRL 0x0000 37a043e8c7SAdrian Chadd #define AR8X16_MASK_CTRL_REV_MASK 0x000000ff 38a043e8c7SAdrian Chadd #define AR8X16_MASK_CTRL_VER_MASK 0x0000ff00 39a043e8c7SAdrian Chadd #define AR8X16_MASK_CTRL_VER_SHIFT 8 40a043e8c7SAdrian Chadd #define AR8X16_MASK_CTRL_SOFT_RESET (1 << 31) 41a043e8c7SAdrian Chadd 42a043e8c7SAdrian Chadd #define AR8X16_REG_MODE 0x0008 43a043e8c7SAdrian Chadd /* DIR-615 E4 U-Boot */ 44a043e8c7SAdrian Chadd #define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0 45a043e8c7SAdrian Chadd /* From Ubiquiti RSPRO */ 46a043e8c7SAdrian Chadd #define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea 47a043e8c7SAdrian Chadd #define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2 48a043e8c7SAdrian Chadd /* AVM Fritz!Box 7390 */ 49a043e8c7SAdrian Chadd #define AR8X16_MODE_GMII 0x010e5b71 50a043e8c7SAdrian Chadd /* from avm_cpmac/linux_ar_reg.h */ 51a043e8c7SAdrian Chadd #define AR8X16_MODE_RESERVED 0x000e1b20 52a043e8c7SAdrian Chadd #define AR8X16_MODE_MAC0_GMII_EN (1u << 0) 53a043e8c7SAdrian Chadd #define AR8X16_MODE_MAC0_RGMII_EN (1u << 1) 54a043e8c7SAdrian Chadd #define AR8X16_MODE_PHY4_GMII_EN (1u << 2) 55a043e8c7SAdrian Chadd #define AR8X16_MODE_PHY4_RGMII_EN (1u << 3) 56a043e8c7SAdrian Chadd #define AR8X16_MODE_MAC0_MAC_MODE (1u << 4) 57a043e8c7SAdrian Chadd #define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6) 58a043e8c7SAdrian Chadd #define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7) 59a043e8c7SAdrian Chadd #define AR8X16_MODE_MAC5_MAC_MODE (1u << 14) 60a043e8c7SAdrian Chadd #define AR8X16_MODE_MAC5_PHY_MODE (1u << 15) 61a043e8c7SAdrian Chadd #define AR8X16_MODE_TXDELAY_S0 (1u << 21) 62a043e8c7SAdrian Chadd #define AR8X16_MODE_TXDELAY_S1 (1u << 22) 63a043e8c7SAdrian Chadd #define AR8X16_MODE_RXDELAY_S0 (1u << 23) 64a043e8c7SAdrian Chadd #define AR8X16_MODE_LED_OPEN_EN (1u << 24) 65a043e8c7SAdrian Chadd #define AR8X16_MODE_SPI_EN (1u << 25) 66a043e8c7SAdrian Chadd #define AR8X16_MODE_RXDELAY_S1 (1u << 26) 67a043e8c7SAdrian Chadd #define AR8X16_MODE_POWER_ON_SEL (1u << 31) 68a043e8c7SAdrian Chadd 69a043e8c7SAdrian Chadd #define AR8X16_REG_ISR 0x0010 70a043e8c7SAdrian Chadd #define AR8X16_REG_IMR 0x0014 71a043e8c7SAdrian Chadd 72a043e8c7SAdrian Chadd #define AR8X16_REG_SW_MAC_ADDR0 0x0020 73a043e8c7SAdrian Chadd #define AR8X16_REG_SW_MAC_ADDR1 0x0024 74a043e8c7SAdrian Chadd 75a043e8c7SAdrian Chadd #define AR8X16_REG_FLOOD_MASK 0x002c 76a043e8c7SAdrian Chadd #define AR8X16_FLOOD_MASK_BCAST_TO_CPU (1 << 26) 77a043e8c7SAdrian Chadd 78a043e8c7SAdrian Chadd #define AR8X16_REG_GLOBAL_CTRL 0x0030 79a043e8c7SAdrian Chadd #define AR8216_GLOBAL_CTRL_MTU_MASK 0x00000fff 80a043e8c7SAdrian Chadd #define AR8316_GLOBAL_CTRL_MTU_MASK 0x00007fff 81a043e8c7SAdrian Chadd #define AR8236_GLOBAL_CTRL_MTU_MASK 0x00007fff 82a043e8c7SAdrian Chadd 83a043e8c7SAdrian Chadd #define AR8X16_REG_VLAN_CTRL 0x0040 84a043e8c7SAdrian Chadd #define AR8X16_VLAN_OP 0x00000007 85a043e8c7SAdrian Chadd #define AR8X16_VLAN_OP_NOOP 0x0 86a043e8c7SAdrian Chadd #define AR8X16_VLAN_OP_FLUSH 0x1 87a043e8c7SAdrian Chadd #define AR8X16_VLAN_OP_LOAD 0x2 88a043e8c7SAdrian Chadd #define AR8X16_VLAN_OP_PURGE 0x3 89a043e8c7SAdrian Chadd #define AR8X16_VLAN_OP_REMOVE_PORT 0x4 90a043e8c7SAdrian Chadd #define AR8X16_VLAN_OP_GET_NEXT 0x5 91a043e8c7SAdrian Chadd #define AR8X16_VLAN_OP_GET 0x6 92a043e8c7SAdrian Chadd #define AR8X16_VLAN_ACTIVE (1 << 3) 93a043e8c7SAdrian Chadd #define AR8X16_VLAN_FULL (1 << 4) 94a043e8c7SAdrian Chadd #define AR8X16_VLAN_PORT 0x00000f00 95a043e8c7SAdrian Chadd #define AR8X16_VLAN_PORT_SHIFT 8 96a043e8c7SAdrian Chadd #define AR8X16_VLAN_VID 0x0fff0000 97a043e8c7SAdrian Chadd #define AR8X16_VLAN_VID_SHIFT 16 98a043e8c7SAdrian Chadd #define AR8X16_VLAN_PRIO 0x70000000 99a043e8c7SAdrian Chadd #define AR8X16_VLAN_PRIO_SHIFT 28 100a043e8c7SAdrian Chadd #define AR8X16_VLAN_PRIO_EN (1 << 31) 101a043e8c7SAdrian Chadd 102a043e8c7SAdrian Chadd #define AR8X16_REG_VLAN_DATA 0x0044 103a043e8c7SAdrian Chadd #define AR8X16_VLAN_MEMBER 0x000003ff 104a043e8c7SAdrian Chadd #define AR8X16_VLAN_VALID (1 << 11) 105a043e8c7SAdrian Chadd 106a043e8c7SAdrian Chadd #define AR8X16_REG_ARL_CTRL0 0x0050 107a043e8c7SAdrian Chadd #define AR8X16_REG_ARL_CTRL1 0x0054 108a043e8c7SAdrian Chadd #define AR8X16_REG_ARL_CTRL2 0x0058 109a043e8c7SAdrian Chadd 110a043e8c7SAdrian Chadd #define AR8X16_REG_AT_CTRL 0x005c 111a043e8c7SAdrian Chadd #define AR8X16_AT_CTRL_ARP_EN (1 << 20) 112a043e8c7SAdrian Chadd 113a043e8c7SAdrian Chadd #define AR8X16_REG_IP_PRIORITY_1 0x0060 114a043e8c7SAdrian Chadd #define AR8X16_REG_IP_PRIORITY_2 0x0064 115a043e8c7SAdrian Chadd #define AR8X16_REG_IP_PRIORITY_3 0x0068 116a043e8c7SAdrian Chadd #define AR8X16_REG_IP_PRIORITY_4 0x006C 117a043e8c7SAdrian Chadd 118a043e8c7SAdrian Chadd #define AR8X16_REG_TAG_PRIO 0x0070 119a043e8c7SAdrian Chadd 120a043e8c7SAdrian Chadd #define AR8X16_REG_SERVICE_TAG 0x0074 121a043e8c7SAdrian Chadd #define AR8X16_SERVICE_TAG_MASK 0x0000ffff 122a043e8c7SAdrian Chadd 123a043e8c7SAdrian Chadd #define AR8X16_REG_CPU_PORT 0x0078 124a043e8c7SAdrian Chadd #define AR8X16_MIRROR_PORT_SHIFT 4 125*67a8db4dSAdrian Chadd #define AR8X16_MIRROR_PORT_MASK (0xf << AR8X16_MIRROR_PORT_SHIFT) 126*67a8db4dSAdrian Chadd #define AR8X16_CPU_MIRROR_PORT(_p) ((_p) << AR8X16_MIRROR_PORT_SHIFT) 127*67a8db4dSAdrian Chadd #define AR8X16_CPU_MIRROR_DIS AR8X16_CPU_MIRROR_PORT(0xf) 128a043e8c7SAdrian Chadd #define AR8X16_CPU_PORT_EN (1 << 8) 129a043e8c7SAdrian Chadd 130a043e8c7SAdrian Chadd #define AR8X16_REG_MIB_FUNC0 0x0080 131a043e8c7SAdrian Chadd #define AR8X16_MIB_TIMER_MASK 0x0000ffff 132a043e8c7SAdrian Chadd #define AR8X16_MIB_AT_HALF_EN (1 << 16) 133a043e8c7SAdrian Chadd #define AR8X16_MIB_BUSY (1 << 17) 134a043e8c7SAdrian Chadd #define AR8X16_MIB_FUNC_SHIFT 24 135a043e8c7SAdrian Chadd #define AR8X16_MIB_FUNC_NO_OP 0x0 136a043e8c7SAdrian Chadd #define AR8X16_MIB_FUNC_FLUSH 0x1 137a043e8c7SAdrian Chadd #define AR8X16_MIB_FUNC_CAPTURE 0x3 138a043e8c7SAdrian Chadd #define AR8X16_MIB_FUNC_XXX (1 << 30) /* 0x40000000 */ 139a043e8c7SAdrian Chadd 140a043e8c7SAdrian Chadd #define AR8X16_REG_MDIO_HIGH_ADDR 0x0094 141a043e8c7SAdrian Chadd 142a043e8c7SAdrian Chadd #define AR8X16_REG_MDIO_CTRL 0x0098 143a043e8c7SAdrian Chadd #define AR8X16_MDIO_CTRL_DATA_MASK 0x0000ffff 144a043e8c7SAdrian Chadd #define AR8X16_MDIO_CTRL_REG_ADDR_SHIFT 16 145a043e8c7SAdrian Chadd #define AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT 21 146a043e8c7SAdrian Chadd #define AR8X16_MDIO_CTRL_CMD_WRITE 0 147a043e8c7SAdrian Chadd #define AR8X16_MDIO_CTRL_CMD_READ (1 << 27) 148a043e8c7SAdrian Chadd #define AR8X16_MDIO_CTRL_MASTER_EN (1 << 30) 149a043e8c7SAdrian Chadd #define AR8X16_MDIO_CTRL_BUSY (1 << 31) 150a043e8c7SAdrian Chadd 151a043e8c7SAdrian Chadd #define AR8X16_REG_PORT_BASE(_p) (0x0100 + (_p) * 0x0100) 152a043e8c7SAdrian Chadd 153a043e8c7SAdrian Chadd #define AR8X16_REG_PORT_STS(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0000) 154a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_SPEED_MASK 0x00000003 155a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_SPEED_10 0 156a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_SPEED_100 1 157a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_SPEED_1000 2 158a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_TXMAC (1 << 2) 159a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_RXMAC (1 << 3) 160a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_TXFLOW (1 << 4) 161a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_RXFLOW (1 << 5) 162a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_DUPLEX (1 << 6) 163a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_LINK_UP (1 << 8) 164a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_LINK_AUTO (1 << 9) 165a043e8c7SAdrian Chadd #define AR8X16_PORT_STS_LINK_PAUSE (1 << 10) 166a043e8c7SAdrian Chadd 167a043e8c7SAdrian Chadd #define AR8X16_REG_PORT_CTRL(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0004) 168a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_STATE_MASK 0x00000007 169a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_STATE_DISABLED 0 170a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_STATE_BLOCK 1 171a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_STATE_LISTEN 2 172a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_STATE_LEARN 3 173a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_STATE_FORWARD 4 174a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7) 175a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8 176a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0 177a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1 178a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD 2 179a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_DOUBLE_TAG 3 180a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_IGMP_SNOOP (1 << 10) 181a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_HEADER (1 << 11) 182a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_MAC_LOOP (1 << 12) 183a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_SINGLE_VLAN (1 << 13) 184a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_LEARN (1 << 14) 185a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_DOUBLE_TAG (1 << 15) 186a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_MIRROR_TX (1 << 16) 187a043e8c7SAdrian Chadd #define AR8X16_PORT_CTRL_MIRROR_RX (1 << 17) 188a043e8c7SAdrian Chadd 189a043e8c7SAdrian Chadd #define AR8X16_REG_PORT_VLAN(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0008) 190a043e8c7SAdrian Chadd 191a043e8c7SAdrian Chadd #define AR8X16_PORT_VLAN_DEFAULT_ID_SHIFT 0 192a043e8c7SAdrian Chadd #define AR8X16_PORT_VLAN_DEST_PORTS_SHIFT 16 193a043e8c7SAdrian Chadd #define AR8X16_PORT_VLAN_MODE_MASK 0xc0000000 194a043e8c7SAdrian Chadd #define AR8X16_PORT_VLAN_MODE_SHIFT 30 195a043e8c7SAdrian Chadd #define AR8X16_PORT_VLAN_MODE_PORT_ONLY 0 196a043e8c7SAdrian Chadd #define AR8X16_PORT_VLAN_MODE_PORT_FALLBACK 1 197a043e8c7SAdrian Chadd #define AR8X16_PORT_VLAN_MODE_VLAN_ONLY 2 198a043e8c7SAdrian Chadd #define AR8X16_PORT_VLAN_MODE_SECURE 3 199a043e8c7SAdrian Chadd 200a043e8c7SAdrian Chadd #define AR8X16_REG_PORT_RATE_LIM(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x000c) 201a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_128KB 0 202a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_256KB 1 203a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_512KB 2 204a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_1MB 3 205a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_2MB 4 206a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_4MB 5 207a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_8MB 6 208a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_16MB 7 209a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_32MB 8 210a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_64MB 9 211a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_IN_EN (1 << 24) 212a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_OUT_EN (1 << 23) 213a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_IN_MASK 0x000f0000 214a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_IN_SHIFT 16 215a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_OUT_MASK 0x0000000f 216a043e8c7SAdrian Chadd #define AR8X16_PORT_RATE_LIM_OUT_SHIFT 0 217a043e8c7SAdrian Chadd 218a043e8c7SAdrian Chadd #define AR8X16_REG_PORT_PRIORITY(_p) (AR8X16_REG_PORT_BASE((_p)) + 0x0010) 219a043e8c7SAdrian Chadd 220a043e8c7SAdrian Chadd #define AR8X16_REG_STATS_BASE(_p) (0x20000 + (_p) * 0x100) 221a043e8c7SAdrian Chadd 222a043e8c7SAdrian Chadd #define AR8X16_STATS_RXBROAD 0x0000 223a043e8c7SAdrian Chadd #define AR8X16_STATS_RXPAUSE 0x0004 224a043e8c7SAdrian Chadd #define AR8X16_STATS_RXMULTI 0x0008 225a043e8c7SAdrian Chadd #define AR8X16_STATS_RXFCSERR 0x000c 226a043e8c7SAdrian Chadd #define AR8X16_STATS_RXALIGNERR 0x0010 227a043e8c7SAdrian Chadd #define AR8X16_STATS_RXRUNT 0x0014 228a043e8c7SAdrian Chadd #define AR8X16_STATS_RXFRAGMENT 0x0018 229a043e8c7SAdrian Chadd #define AR8X16_STATS_RX64BYTE 0x001c 230a043e8c7SAdrian Chadd #define AR8X16_STATS_RX128BYTE 0x0020 231a043e8c7SAdrian Chadd #define AR8X16_STATS_RX256BYTE 0x0024 232a043e8c7SAdrian Chadd #define AR8X16_STATS_RX512BYTE 0x0028 233a043e8c7SAdrian Chadd #define AR8X16_STATS_RX1024BYTE 0x002c 234a043e8c7SAdrian Chadd #define AR8X16_STATS_RX1518BYTE 0x0030 235a043e8c7SAdrian Chadd #define AR8X16_STATS_RXMAXBYTE 0x0034 236a043e8c7SAdrian Chadd #define AR8X16_STATS_RXTOOLONG 0x0038 237a043e8c7SAdrian Chadd #define AR8X16_STATS_RXGOODBYTE 0x003c 238a043e8c7SAdrian Chadd #define AR8X16_STATS_RXBADBYTE 0x0044 239a043e8c7SAdrian Chadd #define AR8X16_STATS_RXOVERFLOW 0x004c 240a043e8c7SAdrian Chadd #define AR8X16_STATS_FILTERED 0x0050 241a043e8c7SAdrian Chadd #define AR8X16_STATS_TXBROAD 0x0054 242a043e8c7SAdrian Chadd #define AR8X16_STATS_TXPAUSE 0x0058 243a043e8c7SAdrian Chadd #define AR8X16_STATS_TXMULTI 0x005c 244a043e8c7SAdrian Chadd #define AR8X16_STATS_TXUNDERRUN 0x0060 245a043e8c7SAdrian Chadd #define AR8X16_STATS_TX64BYTE 0x0064 246a043e8c7SAdrian Chadd #define AR8X16_STATS_TX128BYTE 0x0068 247a043e8c7SAdrian Chadd #define AR8X16_STATS_TX256BYTE 0x006c 248a043e8c7SAdrian Chadd #define AR8X16_STATS_TX512BYTE 0x0070 249a043e8c7SAdrian Chadd #define AR8X16_STATS_TX1024BYTE 0x0074 250a043e8c7SAdrian Chadd #define AR8X16_STATS_TX1518BYTE 0x0078 251a043e8c7SAdrian Chadd #define AR8X16_STATS_TXMAXBYTE 0x007c 252a043e8c7SAdrian Chadd #define AR8X16_STATS_TXOVERSIZE 0x0080 253a043e8c7SAdrian Chadd #define AR8X16_STATS_TXBYTE 0x0084 254a043e8c7SAdrian Chadd #define AR8X16_STATS_TXCOLLISION 0x008c 255a043e8c7SAdrian Chadd #define AR8X16_STATS_TXABORTCOL 0x0090 256a043e8c7SAdrian Chadd #define AR8X16_STATS_TXMULTICOL 0x0094 257a043e8c7SAdrian Chadd #define AR8X16_STATS_TXSINGLECOL 0x0098 258a043e8c7SAdrian Chadd #define AR8X16_STATS_TXEXCDEFER 0x009c 259a043e8c7SAdrian Chadd #define AR8X16_STATS_TXDEFER 0x00a0 260a043e8c7SAdrian Chadd #define AR8X16_STATS_TXLATECOL 0x00a4 261a043e8c7SAdrian Chadd 262a043e8c7SAdrian Chadd #define AR8X16_PORT_CPU 0 263a043e8c7SAdrian Chadd #define AR8X16_NUM_PORTS 6 264a043e8c7SAdrian Chadd #define AR8X16_NUM_PHYS 5 265a043e8c7SAdrian Chadd #define AR8X16_MAGIC 0xc000050e 266a043e8c7SAdrian Chadd 267a043e8c7SAdrian Chadd #define AR8X16_PHY_ID1 0x004d 268a043e8c7SAdrian Chadd #define AR8X16_PHY_ID2 0xd041 269a043e8c7SAdrian Chadd 270a043e8c7SAdrian Chadd #define AR8X16_PORT_MASK(_port) (1 << (_port)) 271a043e8c7SAdrian Chadd #define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1) 272a043e8c7SAdrian Chadd #define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port))) 273a043e8c7SAdrian Chadd 274a043e8c7SAdrian Chadd #define AR8X16_MAX_VLANS 16 275a043e8c7SAdrian Chadd 276a043e8c7SAdrian Chadd #endif /* __AR8X16_SWITCHREG_H__ */ 277a043e8c7SAdrian Chadd 278