1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011-2012 Stefan Bethke. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/errno.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/socket.h> 37 #include <sys/sockio.h> 38 #include <sys/sysctl.h> 39 #include <sys/systm.h> 40 41 #include <net/if.h> 42 #include <net/if_arp.h> 43 #include <net/ethernet.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 #include <net/if_types.h> 47 48 #include <machine/bus.h> 49 #include <dev/iicbus/iic.h> 50 #include <dev/iicbus/iiconf.h> 51 #include <dev/iicbus/iicbus.h> 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include <dev/mdio/mdio.h> 55 56 #include <dev/etherswitch/etherswitch.h> 57 58 #include <dev/etherswitch/arswitch/arswitchreg.h> 59 #include <dev/etherswitch/arswitch/arswitchvar.h> 60 #include <dev/etherswitch/arswitch/arswitch_reg.h> 61 62 #include "mdio_if.h" 63 #include "miibus_if.h" 64 #include "etherswitch_if.h" 65 66 static inline void 67 arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy, 68 uint16_t *reg) 69 { 70 struct arswitch_softc *sc = device_get_softc(dev); 71 uint16_t page; 72 73 page = (addr >> 9) & 0x1ff; 74 *phy = (addr >> 6) & 0x7; 75 *reg = (addr >> 1) & 0x1f; 76 77 if (sc->page != page) { 78 MDIO_WRITEREG(device_get_parent(dev), 0x18, 0, page); 79 DELAY(2000); 80 sc->page = page; 81 } 82 } 83 84 /* 85 * Read half a register. Some of the registers define control bits, and 86 * the sequence of half-word accesses matters. The register addresses 87 * are word-even (mod 4). 88 */ 89 static inline int 90 arswitch_readreg16(device_t dev, int addr) 91 { 92 uint16_t phy, reg; 93 94 arswitch_split_setpage(dev, addr, &phy, ®); 95 return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg)); 96 } 97 98 /* 99 * Write half a register. See above! 100 */ 101 static inline int 102 arswitch_writereg16(device_t dev, int addr, int data) 103 { 104 uint16_t phy, reg; 105 106 arswitch_split_setpage(dev, addr, &phy, ®); 107 return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data)); 108 } 109 110 /* 111 * XXX NOTE: 112 * 113 * This may not work for AR7240 series embedded switches - 114 * the per-PHY register space doesn't seem to be exposed. 115 * 116 * In that instance, it may be required to speak via 117 * the internal switch PHY MDIO bus indirection. 118 */ 119 void 120 arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr, 121 uint16_t dbg_data) 122 { 123 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 124 MII_ATH_DBG_ADDR, dbg_addr); 125 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 126 MII_ATH_DBG_DATA, dbg_data); 127 } 128 129 void 130 arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr, 131 uint16_t dbg_data) 132 { 133 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 134 MII_ATH_MMD_ADDR, dbg_addr); 135 (void) MDIO_WRITEREG(device_get_parent(dev), phy, 136 MII_ATH_MMD_DATA, dbg_data); 137 } 138 139 static uint32_t 140 arswitch_reg_read32(device_t dev, int phy, int reg) 141 { 142 uint16_t lo, hi; 143 lo = MDIO_READREG(device_get_parent(dev), phy, reg); 144 hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1); 145 146 return (hi << 16) | lo; 147 } 148 149 static int 150 arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value) 151 { 152 struct arswitch_softc *sc; 153 int r; 154 uint16_t lo, hi; 155 156 sc = device_get_softc(dev); 157 lo = value & 0xffff; 158 hi = (uint16_t) (value >> 16); 159 160 if (sc->mii_lo_first) { 161 r = MDIO_WRITEREG(device_get_parent(dev), 162 phy, reg, lo); 163 r |= MDIO_WRITEREG(device_get_parent(dev), 164 phy, reg + 1, hi); 165 } else { 166 r = MDIO_WRITEREG(device_get_parent(dev), 167 phy, reg + 1, hi); 168 r |= MDIO_WRITEREG(device_get_parent(dev), 169 phy, reg, lo); 170 } 171 172 return r; 173 } 174 175 int 176 arswitch_readreg(device_t dev, int addr) 177 { 178 uint16_t phy, reg; 179 180 arswitch_split_setpage(dev, addr, &phy, ®); 181 return arswitch_reg_read32(dev, 0x10 | phy, reg); 182 } 183 184 int 185 arswitch_writereg(device_t dev, int addr, int value) 186 { 187 uint16_t phy, reg; 188 189 arswitch_split_setpage(dev, addr, &phy, ®); 190 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); 191 } 192 193 /* 194 * Read/write 16 bit values in the switch register space. 195 * 196 * Some of the registers are control registers (eg the MDIO 197 * data versus control space) and so need to be treated 198 * differently. 199 */ 200 int 201 arswitch_readreg_lsb(device_t dev, int addr) 202 { 203 204 return (arswitch_readreg16(dev, addr)); 205 } 206 207 int 208 arswitch_readreg_msb(device_t dev, int addr) 209 { 210 211 return (arswitch_readreg16(dev, addr + 2) << 16); 212 } 213 214 int 215 arswitch_writereg_lsb(device_t dev, int addr, int data) 216 { 217 218 return (arswitch_writereg16(dev, addr, data & 0xffff)); 219 } 220 221 int 222 arswitch_writereg_msb(device_t dev, int addr, int data) 223 { 224 225 return (arswitch_writereg16(dev, addr + 2, (data >> 16) & 0xffff)); 226 } 227 228 int 229 arswitch_modifyreg(device_t dev, int addr, int mask, int set) 230 { 231 int value; 232 uint16_t phy, reg; 233 234 ARSWITCH_LOCK_ASSERT((struct arswitch_softc *)device_get_softc(dev), 235 MA_OWNED); 236 237 arswitch_split_setpage(dev, addr, &phy, ®); 238 239 value = arswitch_reg_read32(dev, 0x10 | phy, reg); 240 value &= ~mask; 241 value |= set; 242 return (arswitch_reg_write32(dev, 0x10 | phy, reg, value)); 243 } 244 245 int 246 arswitch_waitreg(device_t dev, int addr, int mask, int val, int timeout) 247 { 248 struct arswitch_softc *sc = device_get_softc(dev); 249 int err, v; 250 uint16_t phy, reg; 251 252 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); 253 254 arswitch_split_setpage(dev, addr, &phy, ®); 255 256 err = -1; 257 while (1) { 258 v = arswitch_reg_read32(dev, 0x10 | phy, reg); 259 v &= mask; 260 if (v == val) { 261 err = 0; 262 break; 263 } 264 if (!timeout) 265 break; 266 DELAY(1); 267 timeout--; 268 } 269 if (err != 0) { 270 DPRINTF(sc, ARSWITCH_DBG_ANY, 271 "%s: waitreg failed; addr=0x%08x, mask=0x%08x, val=0x%08x\n", 272 __func__, addr, mask, val); 273 } 274 return (err); 275 } 276