1 /*- 2 * Copyright (c) 2011-2012 Stefan Bethke. 3 * Copyright (c) 2014 Adrian Chadd. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/errno.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/socket.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/systm.h> 39 40 #include <net/if.h> 41 #include <net/if_arp.h> 42 #include <net/ethernet.h> 43 #include <net/if_dl.h> 44 #include <net/if_media.h> 45 #include <net/if_types.h> 46 47 #include <machine/bus.h> 48 #include <dev/iicbus/iic.h> 49 #include <dev/iicbus/iiconf.h> 50 #include <dev/iicbus/iicbus.h> 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include <dev/etherswitch/mdio.h> 54 55 #include <dev/etherswitch/etherswitch.h> 56 57 #include <dev/etherswitch/arswitch/arswitchreg.h> 58 #include <dev/etherswitch/arswitch/arswitchvar.h> 59 #include <dev/etherswitch/arswitch/arswitch_reg.h> 60 #include <dev/etherswitch/arswitch/arswitch_phy.h> 61 #include <dev/etherswitch/arswitch/arswitch_vlans.h> 62 63 #include <dev/etherswitch/arswitch/arswitch_8327.h> 64 65 #include "mdio_if.h" 66 #include "miibus_if.h" 67 #include "etherswitch_if.h" 68 69 70 static int 71 ar8327_vlan_op(struct arswitch_softc *sc, uint32_t op, uint32_t vid, 72 uint32_t data) 73 { 74 int err; 75 76 /* 77 * Wait for the "done" bit to finish. 78 */ 79 if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1, 80 AR8327_VTU_FUNC1_BUSY, 0, 5)) 81 return (EBUSY); 82 83 /* 84 * If it's a "load" operation, then ensure 'data' is loaded 85 * in first. 86 */ 87 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD) { 88 err = arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC0, data); 89 if (err) 90 return (err); 91 } 92 93 /* 94 * Set the VID. 95 */ 96 op |= ((vid & 0xfff) << AR8327_VTU_FUNC1_VID_S); 97 98 /* 99 * Set busy bit to start loading in the command. 100 */ 101 op |= AR8327_VTU_FUNC1_BUSY; 102 arswitch_writereg(sc->sc_dev, AR8327_REG_VTU_FUNC1, op); 103 104 /* 105 * Finally - wait for it to load. 106 */ 107 if (arswitch_waitreg(sc->sc_dev, AR8327_REG_VTU_FUNC1, 108 AR8327_VTU_FUNC1_BUSY, 0, 5)) 109 return (EBUSY); 110 111 return (0); 112 } 113 114 static void 115 ar8327_phy_fixup(struct arswitch_softc *sc, int phy) 116 { 117 if (bootverbose) 118 device_printf(sc->sc_dev, 119 "%s: called; phy=%d; chiprev=%d\n", __func__, 120 phy, 121 sc->chip_rev); 122 switch (sc->chip_rev) { 123 case 1: 124 /* For 100M waveform */ 125 arswitch_writedbg(sc->sc_dev, phy, 0, 0x02ea); 126 /* Turn on Gigabit clock */ 127 arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x68a0); 128 break; 129 130 case 2: 131 arswitch_writemmd(sc->sc_dev, phy, 0x7, 0x3c); 132 arswitch_writemmd(sc->sc_dev, phy, 0x4007, 0x0); 133 /* fallthrough */ 134 case 4: 135 arswitch_writemmd(sc->sc_dev, phy, 0x3, 0x800d); 136 arswitch_writemmd(sc->sc_dev, phy, 0x4003, 0x803f); 137 138 arswitch_writedbg(sc->sc_dev, phy, 0x3d, 0x6860); 139 arswitch_writedbg(sc->sc_dev, phy, 0x5, 0x2c46); 140 arswitch_writedbg(sc->sc_dev, phy, 0x3c, 0x6000); 141 break; 142 } 143 } 144 145 static uint32_t 146 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg) 147 { 148 uint32_t t; 149 150 if (!cfg) 151 return (0); 152 153 t = 0; 154 switch (cfg->mode) { 155 case AR8327_PAD_NC: 156 break; 157 158 case AR8327_PAD_MAC2MAC_MII: 159 t = AR8327_PAD_MAC_MII_EN; 160 if (cfg->rxclk_sel) 161 t |= AR8327_PAD_MAC_MII_RXCLK_SEL; 162 if (cfg->txclk_sel) 163 t |= AR8327_PAD_MAC_MII_TXCLK_SEL; 164 break; 165 166 case AR8327_PAD_MAC2MAC_GMII: 167 t = AR8327_PAD_MAC_GMII_EN; 168 if (cfg->rxclk_sel) 169 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL; 170 if (cfg->txclk_sel) 171 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL; 172 break; 173 174 case AR8327_PAD_MAC_SGMII: 175 t = AR8327_PAD_SGMII_EN; 176 177 /* 178 * WAR for the Qualcomm Atheros AP136 board. 179 * It seems that RGMII TX/RX delay settings needs to be 180 * applied for SGMII mode as well, The ethernet is not 181 * reliable without this. 182 */ 183 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; 184 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; 185 if (cfg->rxclk_delay_en) 186 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; 187 if (cfg->txclk_delay_en) 188 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; 189 190 if (cfg->sgmii_delay_en) 191 t |= AR8327_PAD_SGMII_DELAY_EN; 192 193 break; 194 195 case AR8327_PAD_MAC2PHY_MII: 196 t = AR8327_PAD_PHY_MII_EN; 197 if (cfg->rxclk_sel) 198 t |= AR8327_PAD_PHY_MII_RXCLK_SEL; 199 if (cfg->txclk_sel) 200 t |= AR8327_PAD_PHY_MII_TXCLK_SEL; 201 break; 202 203 case AR8327_PAD_MAC2PHY_GMII: 204 t = AR8327_PAD_PHY_GMII_EN; 205 if (cfg->pipe_rxclk_sel) 206 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL; 207 if (cfg->rxclk_sel) 208 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL; 209 if (cfg->txclk_sel) 210 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL; 211 break; 212 213 case AR8327_PAD_MAC_RGMII: 214 t = AR8327_PAD_RGMII_EN; 215 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; 216 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; 217 if (cfg->rxclk_delay_en) 218 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; 219 if (cfg->txclk_delay_en) 220 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; 221 break; 222 223 case AR8327_PAD_PHY_GMII: 224 t = AR8327_PAD_PHYX_GMII_EN; 225 break; 226 227 case AR8327_PAD_PHY_RGMII: 228 t = AR8327_PAD_PHYX_RGMII_EN; 229 break; 230 231 case AR8327_PAD_PHY_MII: 232 t = AR8327_PAD_PHYX_MII_EN; 233 break; 234 } 235 236 return (t); 237 } 238 239 /* 240 * Map the hard-coded port config from the switch setup to 241 * the chipset port config (status, duplex, flow, etc.) 242 */ 243 static uint32_t 244 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg) 245 { 246 uint32_t t; 247 248 if (!cfg->force_link) 249 return (AR8X16_PORT_STS_LINK_AUTO); 250 251 t = AR8X16_PORT_STS_TXMAC | AR8X16_PORT_STS_RXMAC; 252 t |= cfg->duplex ? AR8X16_PORT_STS_DUPLEX : 0; 253 t |= cfg->rxpause ? AR8X16_PORT_STS_RXFLOW : 0; 254 t |= cfg->txpause ? AR8X16_PORT_STS_TXFLOW : 0; 255 256 switch (cfg->speed) { 257 case AR8327_PORT_SPEED_10: 258 t |= AR8X16_PORT_STS_SPEED_10; 259 break; 260 case AR8327_PORT_SPEED_100: 261 t |= AR8X16_PORT_STS_SPEED_100; 262 break; 263 case AR8327_PORT_SPEED_1000: 264 t |= AR8X16_PORT_STS_SPEED_1000; 265 break; 266 } 267 268 return (t); 269 } 270 271 /* 272 * Fetch the port data for the given port. 273 * 274 * This goes and does dirty things with the hints space 275 * to determine what the configuration parameters should be. 276 * 277 * Returns 1 if the structure was successfully parsed and 278 * the contents are valid; 0 otherwise. 279 */ 280 static int 281 ar8327_fetch_pdata_port(struct arswitch_softc *sc, 282 struct ar8327_port_cfg *pcfg, 283 int port) 284 { 285 int val; 286 char sbuf[128]; 287 288 /* Check if force_link exists */ 289 val = 0; 290 snprintf(sbuf, 128, "port.%d.force_link", port); 291 (void) resource_int_value(device_get_name(sc->sc_dev), 292 device_get_unit(sc->sc_dev), 293 sbuf, &val); 294 if (val != 1) 295 return (0); 296 pcfg->force_link = 1; 297 298 /* force_link is set; let's parse the rest of the fields */ 299 snprintf(sbuf, 128, "port.%d.speed", port); 300 if (resource_int_value(device_get_name(sc->sc_dev), 301 device_get_unit(sc->sc_dev), 302 sbuf, &val) == 0) { 303 switch (val) { 304 case 10: 305 pcfg->speed = AR8327_PORT_SPEED_10; 306 break; 307 case 100: 308 pcfg->speed = AR8327_PORT_SPEED_100; 309 break; 310 case 1000: 311 pcfg->speed = AR8327_PORT_SPEED_1000; 312 break; 313 default: 314 device_printf(sc->sc_dev, 315 "%s: invalid port %d duplex value (%d)\n", 316 __func__, 317 port, 318 val); 319 return (0); 320 } 321 } 322 323 snprintf(sbuf, 128, "port.%d.duplex", port); 324 if (resource_int_value(device_get_name(sc->sc_dev), 325 device_get_unit(sc->sc_dev), 326 sbuf, &val) == 0) 327 pcfg->duplex = val; 328 329 snprintf(sbuf, 128, "port.%d.txpause", port); 330 if (resource_int_value(device_get_name(sc->sc_dev), 331 device_get_unit(sc->sc_dev), 332 sbuf, &val) == 0) 333 pcfg->txpause = val; 334 335 snprintf(sbuf, 128, "port.%d.rxpause", port); 336 if (resource_int_value(device_get_name(sc->sc_dev), 337 device_get_unit(sc->sc_dev), 338 sbuf, &val) == 0) 339 pcfg->rxpause = val; 340 341 #if 1 342 device_printf(sc->sc_dev, 343 "%s: port %d: speed=%d, duplex=%d, txpause=%d, rxpause=%d\n", 344 __func__, 345 port, 346 pcfg->speed, 347 pcfg->duplex, 348 pcfg->txpause, 349 pcfg->rxpause); 350 #endif 351 352 return (1); 353 } 354 355 /* 356 * Parse the pad configuration from the boot hints. 357 * 358 * The (mostly optional) fields are: 359 * 360 * uint32_t mode; 361 * uint32_t rxclk_sel; 362 * uint32_t txclk_sel; 363 * uint32_t txclk_delay_sel; 364 * uint32_t rxclk_delay_sel; 365 * uint32_t txclk_delay_en; 366 * uint32_t rxclk_delay_en; 367 * uint32_t sgmii_delay_en; 368 * uint32_t pipe_rxclk_sel; 369 * 370 * If mode isn't in the hints, 0 is returned. 371 * Else the structure is fleshed out and 1 is returned. 372 */ 373 static int 374 ar8327_fetch_pdata_pad(struct arswitch_softc *sc, 375 struct ar8327_pad_cfg *pc, 376 int pad) 377 { 378 int val; 379 char sbuf[128]; 380 381 /* Check if mode exists */ 382 val = 0; 383 snprintf(sbuf, 128, "pad.%d.mode", pad); 384 if (resource_int_value(device_get_name(sc->sc_dev), 385 device_get_unit(sc->sc_dev), 386 sbuf, &val) != 0) 387 return (0); 388 389 /* assume that 'mode' exists and was found */ 390 pc->mode = val; 391 392 snprintf(sbuf, 128, "pad.%d.rxclk_sel", pad); 393 if (resource_int_value(device_get_name(sc->sc_dev), 394 device_get_unit(sc->sc_dev), 395 sbuf, &val) == 0) 396 pc->rxclk_sel = val; 397 398 snprintf(sbuf, 128, "pad.%d.txclk_sel", pad); 399 if (resource_int_value(device_get_name(sc->sc_dev), 400 device_get_unit(sc->sc_dev), 401 sbuf, &val) == 0) 402 pc->txclk_sel = val; 403 404 snprintf(sbuf, 128, "pad.%d.txclk_delay_sel", pad); 405 if (resource_int_value(device_get_name(sc->sc_dev), 406 device_get_unit(sc->sc_dev), 407 sbuf, &val) == 0) 408 pc->txclk_delay_sel = val; 409 410 snprintf(sbuf, 128, "pad.%d.rxclk_delay_sel", pad); 411 if (resource_int_value(device_get_name(sc->sc_dev), 412 device_get_unit(sc->sc_dev), 413 sbuf, &val) == 0) 414 pc->rxclk_delay_sel = val; 415 416 snprintf(sbuf, 128, "pad.%d.txclk_delay_en", pad); 417 if (resource_int_value(device_get_name(sc->sc_dev), 418 device_get_unit(sc->sc_dev), 419 sbuf, &val) == 0) 420 pc->txclk_delay_en = val; 421 422 snprintf(sbuf, 128, "pad.%d.rxclk_delay_en", pad); 423 if (resource_int_value(device_get_name(sc->sc_dev), 424 device_get_unit(sc->sc_dev), 425 sbuf, &val) == 0) 426 pc->rxclk_delay_en = val; 427 428 snprintf(sbuf, 128, "pad.%d.sgmii_delay_en", pad); 429 if (resource_int_value(device_get_name(sc->sc_dev), 430 device_get_unit(sc->sc_dev), 431 sbuf, &val) == 0) 432 pc->sgmii_delay_en = val; 433 434 snprintf(sbuf, 128, "pad.%d.pipe_rxclk_sel", pad); 435 if (resource_int_value(device_get_name(sc->sc_dev), 436 device_get_unit(sc->sc_dev), 437 sbuf, &val) == 0) 438 pc->pipe_rxclk_sel = val; 439 440 if (bootverbose) { 441 device_printf(sc->sc_dev, 442 "%s: pad %d: mode=%d, rxclk_sel=%d, txclk_sel=%d, " 443 "txclk_delay_sel=%d, rxclk_delay_sel=%d, txclk_delay_en=%d, " 444 "rxclk_enable_en=%d, sgmii_delay_en=%d, pipe_rxclk_sel=%d\n", 445 __func__, 446 pad, 447 pc->mode, 448 pc->rxclk_sel, 449 pc->txclk_sel, 450 pc->txclk_delay_sel, 451 pc->rxclk_delay_sel, 452 pc->txclk_delay_en, 453 pc->rxclk_delay_en, 454 pc->sgmii_delay_en, 455 pc->pipe_rxclk_sel); 456 } 457 458 return (1); 459 } 460 461 /* 462 * Fetch the SGMII configuration block from the boot hints. 463 */ 464 static int 465 ar8327_fetch_pdata_sgmii(struct arswitch_softc *sc, 466 struct ar8327_sgmii_cfg *scfg) 467 { 468 int val; 469 470 /* sgmii_ctrl */ 471 val = 0; 472 if (resource_int_value(device_get_name(sc->sc_dev), 473 device_get_unit(sc->sc_dev), 474 "sgmii.ctrl", &val) != 0) 475 return (0); 476 scfg->sgmii_ctrl = val; 477 478 /* serdes_aen */ 479 val = 0; 480 if (resource_int_value(device_get_name(sc->sc_dev), 481 device_get_unit(sc->sc_dev), 482 "sgmii.serdes_aen", &val) != 0) 483 return (0); 484 scfg->serdes_aen = val; 485 486 return (1); 487 } 488 489 /* 490 * Fetch the LED configuration from the boot hints. 491 */ 492 static int 493 ar8327_fetch_pdata_led(struct arswitch_softc *sc, 494 struct ar8327_led_cfg *lcfg) 495 { 496 int val; 497 498 val = 0; 499 if (resource_int_value(device_get_name(sc->sc_dev), 500 device_get_unit(sc->sc_dev), 501 "led.ctrl0", &val) != 0) 502 return (0); 503 lcfg->led_ctrl0 = val; 504 505 val = 0; 506 if (resource_int_value(device_get_name(sc->sc_dev), 507 device_get_unit(sc->sc_dev), 508 "led.ctrl1", &val) != 0) 509 return (0); 510 lcfg->led_ctrl1 = val; 511 512 val = 0; 513 if (resource_int_value(device_get_name(sc->sc_dev), 514 device_get_unit(sc->sc_dev), 515 "led.ctrl2", &val) != 0) 516 return (0); 517 lcfg->led_ctrl2 = val; 518 519 val = 0; 520 if (resource_int_value(device_get_name(sc->sc_dev), 521 device_get_unit(sc->sc_dev), 522 "led.ctrl3", &val) != 0) 523 return (0); 524 lcfg->led_ctrl3 = val; 525 526 val = 0; 527 if (resource_int_value(device_get_name(sc->sc_dev), 528 device_get_unit(sc->sc_dev), 529 "led.open_drain", &val) != 0) 530 return (0); 531 lcfg->open_drain = val; 532 533 return (1); 534 } 535 536 /* 537 * Initialise the ar8327 specific hardware features from 538 * the hints provided in the boot environment. 539 */ 540 static int 541 ar8327_init_pdata(struct arswitch_softc *sc) 542 { 543 struct ar8327_pad_cfg pc; 544 struct ar8327_port_cfg port_cfg; 545 struct ar8327_sgmii_cfg scfg; 546 struct ar8327_led_cfg lcfg; 547 uint32_t t, new_pos, pos; 548 549 /* Port 0 */ 550 bzero(&port_cfg, sizeof(port_cfg)); 551 sc->ar8327.port0_status = 0; 552 if (ar8327_fetch_pdata_port(sc, &port_cfg, 0)) 553 sc->ar8327.port0_status = ar8327_get_port_init_status(&port_cfg); 554 555 /* Port 6 */ 556 bzero(&port_cfg, sizeof(port_cfg)); 557 sc->ar8327.port6_status = 0; 558 if (ar8327_fetch_pdata_port(sc, &port_cfg, 6)) 559 sc->ar8327.port6_status = ar8327_get_port_init_status(&port_cfg); 560 561 /* Pad 0 */ 562 bzero(&pc, sizeof(pc)); 563 t = 0; 564 if (ar8327_fetch_pdata_pad(sc, &pc, 0)) 565 t = ar8327_get_pad_cfg(&pc); 566 #if 0 567 if (AR8X16_IS_SWITCH(sc, AR8337)) 568 t |= AR8337_PAD_MAC06_EXCHANGE_EN; 569 #endif 570 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD0_MODE, t); 571 572 /* Pad 5 */ 573 bzero(&pc, sizeof(pc)); 574 t = 0; 575 if (ar8327_fetch_pdata_pad(sc, &pc, 5)) 576 t = ar8327_get_pad_cfg(&pc); 577 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD5_MODE, t); 578 579 /* Pad 6 */ 580 bzero(&pc, sizeof(pc)); 581 t = 0; 582 if (ar8327_fetch_pdata_pad(sc, &pc, 6)) 583 t = ar8327_get_pad_cfg(&pc); 584 arswitch_writereg(sc->sc_dev, AR8327_REG_PAD6_MODE, t); 585 586 pos = arswitch_readreg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP); 587 new_pos = pos; 588 589 /* XXX LED config */ 590 bzero(&lcfg, sizeof(lcfg)); 591 if (ar8327_fetch_pdata_led(sc, &lcfg)) { 592 if (lcfg.open_drain) 593 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN; 594 else 595 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN; 596 597 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL0, 598 lcfg.led_ctrl0); 599 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL1, 600 lcfg.led_ctrl1); 601 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL2, 602 lcfg.led_ctrl2); 603 arswitch_writereg(sc->sc_dev, AR8327_REG_LED_CTRL3, 604 lcfg.led_ctrl3); 605 606 if (new_pos != pos) 607 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL; 608 } 609 610 /* SGMII config */ 611 bzero(&scfg, sizeof(scfg)); 612 if (ar8327_fetch_pdata_sgmii(sc, &scfg)) { 613 device_printf(sc->sc_dev, "%s: SGMII cfg?\n", __func__); 614 t = scfg.sgmii_ctrl; 615 if (sc->chip_rev == 1) 616 t |= AR8327_SGMII_CTRL_EN_PLL | 617 AR8327_SGMII_CTRL_EN_RX | 618 AR8327_SGMII_CTRL_EN_TX; 619 else 620 t &= ~(AR8327_SGMII_CTRL_EN_PLL | 621 AR8327_SGMII_CTRL_EN_RX | 622 AR8327_SGMII_CTRL_EN_TX); 623 624 arswitch_writereg(sc->sc_dev, AR8327_REG_SGMII_CTRL, t); 625 626 if (scfg.serdes_aen) 627 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN; 628 else 629 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN; 630 } 631 632 arswitch_writereg(sc->sc_dev, AR8327_REG_POWER_ON_STRIP, new_pos); 633 634 return (0); 635 } 636 637 static int 638 ar8327_hw_setup(struct arswitch_softc *sc) 639 { 640 int i; 641 int err; 642 643 /* pdata fetch and setup */ 644 err = ar8327_init_pdata(sc); 645 if (err != 0) 646 return (err); 647 648 /* XXX init leds */ 649 650 for (i = 0; i < AR8327_NUM_PHYS; i++) { 651 /* phy fixup */ 652 ar8327_phy_fixup(sc, i); 653 654 /* start PHY autonegotiation? */ 655 /* XXX is this done as part of the normal PHY setup? */ 656 657 }; 658 659 /* Let things settle */ 660 DELAY(1000); 661 662 return (0); 663 } 664 665 /* 666 * Initialise other global values, for the AR8327. 667 */ 668 static int 669 ar8327_hw_global_setup(struct arswitch_softc *sc) 670 { 671 uint32_t t; 672 673 /* enable CPU port and disable mirror port */ 674 t = AR8327_FWD_CTRL0_CPU_PORT_EN | 675 AR8327_FWD_CTRL0_MIRROR_PORT; 676 arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL0, t); 677 678 /* forward multicast and broadcast frames to CPU */ 679 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) | 680 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) | 681 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S); 682 arswitch_writereg(sc->sc_dev, AR8327_REG_FWD_CTRL1, t); 683 684 /* enable jumbo frames */ 685 /* XXX need to macro-shift the value! */ 686 arswitch_modifyreg(sc->sc_dev, AR8327_REG_MAX_FRAME_SIZE, 687 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2); 688 689 /* Enable MIB counters */ 690 arswitch_modifyreg(sc->sc_dev, AR8327_REG_MODULE_EN, 691 AR8327_MODULE_EN_MIB, AR8327_MODULE_EN_MIB); 692 693 /* Disable EEE on all ports due to stability issues */ 694 t = arswitch_readreg(sc->sc_dev, AR8327_REG_EEE_CTRL); 695 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) | 696 AR8327_EEE_CTRL_DISABLE_PHY(1) | 697 AR8327_EEE_CTRL_DISABLE_PHY(2) | 698 AR8327_EEE_CTRL_DISABLE_PHY(3) | 699 AR8327_EEE_CTRL_DISABLE_PHY(4); 700 arswitch_writereg(sc->sc_dev, AR8327_REG_EEE_CTRL, t); 701 702 /* Set the right number of ports */ 703 /* GMAC0 (CPU), GMAC1..5 (PHYs), GMAC6 (CPU) */ 704 sc->info.es_nports = 7; 705 706 return (0); 707 } 708 709 /* 710 * Port setup. Called at attach time. 711 */ 712 static void 713 ar8327_port_init(struct arswitch_softc *sc, int port) 714 { 715 uint32_t t; 716 int ports; 717 718 /* For now, port can see all other ports */ 719 ports = 0x7f; 720 721 if (port == AR8X16_PORT_CPU) 722 t = sc->ar8327.port0_status; 723 else if (port == 6) 724 t = sc->ar8327.port6_status; 725 else 726 t = AR8X16_PORT_STS_LINK_AUTO; 727 728 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_STATUS(port), t); 729 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_HEADER(port), 0); 730 731 /* 732 * Default to 1 port group. 733 */ 734 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S; 735 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S; 736 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t); 737 738 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S; 739 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(port), t); 740 741 /* 742 * This doesn't configure any ports which this port can "see". 743 * bits 0-6 control which ports a frame coming into this port 744 * can be sent out to. 745 * 746 * So by doing this, we're making it impossible to send frames out 747 * to that port. 748 */ 749 t = AR8327_PORT_LOOKUP_LEARN; 750 t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; 751 752 /* So this allows traffic to any port except ourselves */ 753 t |= (ports & ~(1 << port)); 754 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), t); 755 } 756 757 static int 758 ar8327_port_vlan_setup(struct arswitch_softc *sc, etherswitch_port_t *p) 759 { 760 761 /* Check: ADDTAG/STRIPTAG - exclusive */ 762 763 ARSWITCH_LOCK(sc); 764 765 /* Set the PVID. */ 766 if (p->es_pvid != 0) 767 sc->hal.arswitch_vlan_set_pvid(sc, p->es_port, p->es_pvid); 768 769 /* 770 * DOUBLE_TAG 771 * VLAN_MODE_ADD 772 * VLAN_MODE_STRIP 773 */ 774 ARSWITCH_UNLOCK(sc); 775 return (0); 776 } 777 778 /* 779 * Get the port VLAN configuration. 780 */ 781 static int 782 ar8327_port_vlan_get(struct arswitch_softc *sc, etherswitch_port_t *p) 783 { 784 785 ARSWITCH_LOCK(sc); 786 787 /* Retrieve the PVID */ 788 sc->hal.arswitch_vlan_get_pvid(sc, p->es_port, &p->es_pvid); 789 790 /* Retrieve the current port configuration from the VTU */ 791 /* 792 * DOUBLE_TAG 793 * VLAN_MODE_ADD 794 * VLAN_MODE_STRIP 795 */ 796 797 ARSWITCH_UNLOCK(sc); 798 return (0); 799 } 800 801 static void 802 ar8327_port_disable_mirror(struct arswitch_softc *sc, int port) 803 { 804 805 arswitch_modifyreg(sc->sc_dev, 806 AR8327_REG_PORT_LOOKUP(port), 807 AR8327_PORT_LOOKUP_ING_MIRROR_EN, 808 0); 809 arswitch_modifyreg(sc->sc_dev, 810 AR8327_REG_PORT_HOL_CTRL1(port), 811 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN, 812 0); 813 } 814 815 static void 816 ar8327_reset_vlans(struct arswitch_softc *sc) 817 { 818 int i; 819 uint32_t t; 820 int ports; 821 822 ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED); 823 ARSWITCH_LOCK(sc); 824 825 /* Clear the existing VLAN configuration */ 826 memset(sc->vid, 0, sizeof(sc->vid)); 827 828 /* 829 * Disable mirroring. 830 */ 831 arswitch_modifyreg(sc->sc_dev, AR8327_REG_FWD_CTRL0, 832 AR8327_FWD_CTRL0_MIRROR_PORT, 833 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S)); 834 835 /* 836 * XXX TODO: disable any Q-in-Q port configuration, 837 * tagging, egress filters, etc. 838 */ 839 840 /* 841 * For now, let's default to one portgroup, just so traffic 842 * flows. All ports can see other ports. There are two CPU GMACs 843 * (GMAC0, GMAC6), GMAC1..GMAC5 are external PHYs. 844 * 845 * (ETHERSWITCH_VLAN_PORT) 846 */ 847 ports = 0x7f; 848 849 /* 850 * XXX TODO: set things up correctly for vlans! 851 */ 852 for (i = 0; i < AR8327_NUM_PORTS; i++) { 853 int egress, ingress; 854 855 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) { 856 sc->vid[i] = i | ETHERSWITCH_VID_VALID; 857 /* set egress == out_keep */ 858 ingress = AR8X16_PORT_VLAN_MODE_PORT_ONLY; 859 /* in_port_only, forward */ 860 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH; 861 } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 862 ingress = AR8X16_PORT_VLAN_MODE_SECURE; 863 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD; 864 } else { 865 /* set egress == out_keep */ 866 ingress = AR8X16_PORT_VLAN_MODE_PORT_ONLY; 867 /* in_port_only, forward */ 868 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH; 869 } 870 871 /* set pvid = 1; there's only one vlangroup to start with */ 872 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S; 873 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S; 874 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(i), t); 875 876 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP; 877 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S; 878 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(i), t); 879 880 /* Ports can see other ports */ 881 /* XXX not entirely true for dot1q? */ 882 t = (ports & ~(1 << i)); /* all ports besides us */ 883 t |= AR8327_PORT_LOOKUP_LEARN; 884 885 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S; 886 t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; 887 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(i), t); 888 } 889 890 /* 891 * Disable port mirroring entirely. 892 */ 893 for (i = 0; i < AR8327_NUM_PORTS; i++) { 894 ar8327_port_disable_mirror(sc, i); 895 } 896 897 /* 898 * If dot1q - set pvid; dot1q, etc. 899 */ 900 sc->vid[0] = 1; 901 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) { 902 for (i = 0; i < AR8327_NUM_PORTS; i++) { 903 /* Each port - pvid 1 */ 904 sc->hal.arswitch_vlan_set_pvid(sc, i, sc->vid[0]); 905 } 906 /* Initialise vlan1 - all ports, untagged */ 907 sc->hal.arswitch_set_dot1q_vlan(sc, ports, ports, sc->vid[0]); 908 sc->vid[0] |= ETHERSWITCH_VID_VALID; 909 } 910 911 ARSWITCH_UNLOCK(sc); 912 } 913 914 static int 915 ar8327_vlan_get_port(struct arswitch_softc *sc, uint32_t *ports, int vid) 916 { 917 int port; 918 uint32_t reg; 919 920 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); 921 922 /* For port based vlans the vlanid is the same as the port index. */ 923 port = vid & ETHERSWITCH_VID_MASK; 924 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port)); 925 *ports = reg & 0x7f; 926 return (0); 927 } 928 929 static int 930 ar8327_vlan_set_port(struct arswitch_softc *sc, uint32_t ports, int vid) 931 { 932 int err, port; 933 934 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); 935 936 /* For port based vlans the vlanid is the same as the port index. */ 937 port = vid & ETHERSWITCH_VID_MASK; 938 939 err = arswitch_modifyreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), 940 0x7f, /* vlan membership mask */ 941 (ports & 0x7f)); 942 943 if (err) 944 return (err); 945 return (0); 946 } 947 948 static int 949 ar8327_vlan_getvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg) 950 { 951 952 return (ar8xxx_getvgroup(sc, vg)); 953 } 954 955 static int 956 ar8327_vlan_setvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg) 957 { 958 959 return (ar8xxx_setvgroup(sc, vg)); 960 } 961 962 static int 963 ar8327_get_pvid(struct arswitch_softc *sc, int port, int *pvid) 964 { 965 uint32_t reg; 966 967 ARSWITCH_LOCK_ASSERT(sc, MA_OWNED); 968 969 /* 970 * XXX for now, assuming it's CVID; likely very wrong! 971 */ 972 port = port & ETHERSWITCH_VID_MASK; 973 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port)); 974 reg = reg >> AR8327_PORT_VLAN0_DEF_CVID_S; 975 reg = reg & 0xfff; 976 977 *pvid = reg; 978 return (0); 979 } 980 981 static int 982 ar8327_set_pvid(struct arswitch_softc *sc, int port, int pvid) 983 { 984 uint32_t t; 985 986 /* Limit pvid to valid values */ 987 pvid &= 0x7f; 988 989 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S; 990 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S; 991 arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t); 992 993 return (0); 994 } 995 996 static int 997 ar8327_atu_flush(struct arswitch_softc *sc) 998 { 999 1000 int ret; 1001 1002 ret = arswitch_waitreg(sc->sc_dev, 1003 AR8327_REG_ATU_FUNC, 1004 AR8327_ATU_FUNC_BUSY, 1005 0, 1006 1000); 1007 1008 if (ret) 1009 device_printf(sc->sc_dev, "%s: waitreg failed\n", __func__); 1010 1011 if (!ret) 1012 arswitch_writereg(sc->sc_dev, 1013 AR8327_REG_ATU_FUNC, 1014 AR8327_ATU_FUNC_OP_FLUSH); 1015 return (ret); 1016 } 1017 1018 static int 1019 ar8327_flush_dot1q_vlan(struct arswitch_softc *sc) 1020 { 1021 1022 return (ar8327_vlan_op(sc, AR8327_VTU_FUNC1_OP_FLUSH, 0, 0)); 1023 } 1024 1025 static int 1026 ar8327_purge_dot1q_vlan(struct arswitch_softc *sc, int vid) 1027 { 1028 1029 return (ar8327_vlan_op(sc, AR8327_VTU_FUNC1_OP_PURGE, vid, 0)); 1030 } 1031 1032 static int 1033 ar8327_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports, 1034 uint32_t *untagged_ports, int vid) 1035 { 1036 int i, r; 1037 uint32_t op, reg, val; 1038 1039 op = AR8327_VTU_FUNC1_OP_GET_ONE; 1040 1041 /* Filter out the vid flags; only grab the VLAN ID */ 1042 vid &= 0xfff; 1043 1044 /* XXX TODO: the VTU here stores egress mode - keep, tag, untagged, none */ 1045 r = ar8327_vlan_op(sc, op, vid, 0); 1046 if (r != 0) { 1047 device_printf(sc->sc_dev, "%s: %d: op failed\n", __func__, vid); 1048 } 1049 1050 reg = arswitch_readreg(sc->sc_dev, AR8327_REG_VTU_FUNC0); 1051 DPRINTF(sc->sc_dev, "%s: %d: reg=0x%08x\n", __func__, vid, reg); 1052 1053 /* 1054 * If any of the bits are set, update the port mask. 1055 * Worry about the port config itself when getport() is called. 1056 */ 1057 *ports = 0; 1058 for (i = 0; i < AR8327_NUM_PORTS; i++) { 1059 val = reg >> AR8327_VTU_FUNC0_EG_MODE_S(i); 1060 val = val & 0x3; 1061 /* XXX KEEP (unmodified?) */ 1062 if (val == AR8327_VTU_FUNC0_EG_MODE_TAG) { 1063 *ports |= (1 << i); 1064 } else if (val == AR8327_VTU_FUNC0_EG_MODE_UNTAG) { 1065 *ports |= (1 << i); 1066 *untagged_ports |= (1 << i); 1067 } 1068 } 1069 1070 return (0); 1071 } 1072 1073 static int 1074 ar8327_set_dot1q_vlan(struct arswitch_softc *sc, uint32_t ports, 1075 uint32_t untagged_ports, int vid) 1076 { 1077 int i; 1078 uint32_t op, val, mode; 1079 1080 op = AR8327_VTU_FUNC1_OP_LOAD; 1081 vid &= 0xfff; 1082 1083 DPRINTF(sc->sc_dev, 1084 "%s: vid: %d, ports=0x%08x, untagged_ports=0x%08x\n", 1085 __func__, 1086 vid, 1087 ports, 1088 untagged_ports); 1089 1090 /* 1091 * Mark it as valid; and that it should use per-VLAN MAC table, 1092 * not VID=0 when doing MAC lookups 1093 */ 1094 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL; 1095 1096 for (i = 0; i < AR8327_NUM_PORTS; i++) { 1097 if ((ports & BIT(i)) == 0) 1098 mode = AR8327_VTU_FUNC0_EG_MODE_NOT; 1099 else if (untagged_ports & BIT(i)) 1100 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG; 1101 else 1102 mode = AR8327_VTU_FUNC0_EG_MODE_TAG; 1103 1104 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i); 1105 } 1106 1107 return (ar8327_vlan_op(sc, op, vid, val)); 1108 } 1109 1110 void 1111 ar8327_attach(struct arswitch_softc *sc) 1112 { 1113 1114 sc->hal.arswitch_hw_setup = ar8327_hw_setup; 1115 sc->hal.arswitch_hw_global_setup = ar8327_hw_global_setup; 1116 1117 sc->hal.arswitch_port_init = ar8327_port_init; 1118 1119 sc->hal.arswitch_vlan_getvgroup = ar8327_vlan_getvgroup; 1120 sc->hal.arswitch_vlan_setvgroup = ar8327_vlan_setvgroup; 1121 sc->hal.arswitch_port_vlan_setup = ar8327_port_vlan_setup; 1122 sc->hal.arswitch_port_vlan_get = ar8327_port_vlan_get; 1123 sc->hal.arswitch_flush_dot1q_vlan = ar8327_flush_dot1q_vlan; 1124 sc->hal.arswitch_purge_dot1q_vlan = ar8327_purge_dot1q_vlan; 1125 sc->hal.arswitch_set_dot1q_vlan = ar8327_set_dot1q_vlan; 1126 sc->hal.arswitch_get_dot1q_vlan = ar8327_get_dot1q_vlan; 1127 1128 sc->hal.arswitch_vlan_init_hw = ar8327_reset_vlans; 1129 sc->hal.arswitch_vlan_get_pvid = ar8327_get_pvid; 1130 sc->hal.arswitch_vlan_set_pvid = ar8327_set_pvid; 1131 1132 sc->hal.arswitch_get_port_vlan = ar8327_vlan_get_port; 1133 sc->hal.arswitch_set_port_vlan = ar8327_vlan_set_port; 1134 1135 sc->hal.arswitch_atu_flush = ar8327_atu_flush; 1136 1137 /* 1138 * Reading the PHY via the MDIO interface currently doesn't 1139 * work correctly. 1140 * 1141 * So for now, just go direct to the PHY registers themselves. 1142 * This has always worked on external devices, but not internal 1143 * devices (AR934x, AR724x, AR933x.) 1144 */ 1145 sc->hal.arswitch_phy_read = arswitch_readphy_external; 1146 sc->hal.arswitch_phy_write = arswitch_writephy_external; 1147 1148 /* Set the switch vlan capabilities. */ 1149 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q | 1150 ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOUBLE_TAG; 1151 sc->info.es_nvlangroups = AR8X16_MAX_VLANS; 1152 } 1153