1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011-2012 Stefan Bethke. 5 * Copyright (c) 2012 Adrian Chadd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/errno.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/socket.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/systm.h> 39 40 #include <net/if.h> 41 #include <net/if_arp.h> 42 #include <net/ethernet.h> 43 #include <net/if_dl.h> 44 #include <net/if_media.h> 45 #include <net/if_types.h> 46 47 #include <machine/bus.h> 48 #include <dev/iicbus/iic.h> 49 #include <dev/iicbus/iiconf.h> 50 #include <dev/iicbus/iicbus.h> 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 #include <dev/mdio/mdio.h> 54 55 #include <dev/etherswitch/etherswitch.h> 56 57 #include <dev/etherswitch/arswitch/arswitchreg.h> 58 #include <dev/etherswitch/arswitch/arswitchvar.h> 59 #include <dev/etherswitch/arswitch/arswitch_reg.h> 60 #include <dev/etherswitch/arswitch/arswitch_8316.h> 61 62 #include "mdio_if.h" 63 #include "miibus_if.h" 64 #include "etherswitch_if.h" 65 66 /* 67 * AR8316 specific functions 68 */ 69 static int 70 ar8316_hw_setup(struct arswitch_softc *sc) 71 { 72 73 /* 74 * Configure the switch mode based on whether: 75 * 76 * + The switch port is GMII/RGMII; 77 * + Port 4 is either connected to the CPU or to the internal switch. 78 */ 79 if (sc->is_rgmii && sc->phy4cpu) { 80 arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE, 81 AR8X16_MODE_RGMII_PORT4_ISO); 82 device_printf(sc->sc_dev, 83 "%s: MAC port == RGMII, port 4 = dedicated PHY\n", 84 __func__); 85 } else if (sc->is_rgmii) { 86 arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE, 87 AR8X16_MODE_RGMII_PORT4_SWITCH); 88 device_printf(sc->sc_dev, 89 "%s: MAC port == RGMII, port 4 = switch port\n", 90 __func__); 91 } else if (sc->is_gmii) { 92 arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE, 93 AR8X16_MODE_GMII); 94 device_printf(sc->sc_dev, "%s: MAC port == GMII\n", __func__); 95 } else { 96 device_printf(sc->sc_dev, "%s: unknown switch PHY config\n", 97 __func__); 98 return (ENXIO); 99 } 100 101 DELAY(1000); /* 1ms wait for things to settle */ 102 103 /* 104 * If port 4 is RGMII, force workaround 105 */ 106 if (sc->is_rgmii && sc->phy4cpu) { 107 device_printf(sc->sc_dev, 108 "%s: port 4 RGMII workaround\n", 109 __func__); 110 111 /* work around for phy4 rgmii mode */ 112 arswitch_writedbg(sc->sc_dev, 4, 0x12, 0x480c); 113 /* rx delay */ 114 arswitch_writedbg(sc->sc_dev, 4, 0x0, 0x824e); 115 /* tx delay */ 116 arswitch_writedbg(sc->sc_dev, 4, 0x5, 0x3d47); 117 DELAY(1000); /* 1ms, again to let things settle */ 118 } 119 120 return (0); 121 } 122 123 /* 124 * Initialise other global values, for the AR8316. 125 */ 126 static int 127 ar8316_hw_global_setup(struct arswitch_softc *sc) 128 { 129 130 ARSWITCH_LOCK(sc); 131 132 arswitch_writereg(sc->sc_dev, 0x38, AR8X16_MAGIC); 133 134 /* Enable CPU port and disable mirror port. */ 135 arswitch_writereg(sc->sc_dev, AR8X16_REG_CPU_PORT, 136 AR8X16_CPU_PORT_EN | AR8X16_CPU_MIRROR_DIS); 137 138 /* Setup TAG priority mapping. */ 139 arswitch_writereg(sc->sc_dev, AR8X16_REG_TAG_PRIO, 0xfa50); 140 141 /* 142 * Flood address table misses to all ports, and enable forwarding of 143 * broadcasts to the cpu port. 144 */ 145 arswitch_writereg(sc->sc_dev, AR8X16_REG_FLOOD_MASK, 146 AR8X16_FLOOD_MASK_BCAST_TO_CPU | 0x003f003f); 147 148 /* Enable jumbo frames. */ 149 arswitch_modifyreg(sc->sc_dev, AR8X16_REG_GLOBAL_CTRL, 150 AR8316_GLOBAL_CTRL_MTU_MASK, 9018 + 8 + 2); 151 152 /* Setup service TAG. */ 153 arswitch_modifyreg(sc->sc_dev, AR8X16_REG_SERVICE_TAG, 154 AR8X16_SERVICE_TAG_MASK, 0); 155 156 ARSWITCH_UNLOCK(sc); 157 return (0); 158 } 159 160 void 161 ar8316_attach(struct arswitch_softc *sc) 162 { 163 164 sc->hal.arswitch_hw_setup = ar8316_hw_setup; 165 sc->hal.arswitch_hw_global_setup = ar8316_hw_global_setup; 166 167 /* Set the switch vlan capabilities. */ 168 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q | 169 ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOUBLE_TAG; 170 sc->info.es_nvlangroups = AR8X16_MAX_VLANS; 171 } 172