1*a043e8c7SAdrian Chadd /*- 2*a043e8c7SAdrian Chadd * Copyright (c) 2011-2012 Stefan Bethke. 3*a043e8c7SAdrian Chadd * Copyright (c) 2012 Adrian Chadd. 4*a043e8c7SAdrian Chadd * All rights reserved. 5*a043e8c7SAdrian Chadd * 6*a043e8c7SAdrian Chadd * Redistribution and use in source and binary forms, with or without 7*a043e8c7SAdrian Chadd * modification, are permitted provided that the following conditions 8*a043e8c7SAdrian Chadd * are met: 9*a043e8c7SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 10*a043e8c7SAdrian Chadd * notice, this list of conditions and the following disclaimer. 11*a043e8c7SAdrian Chadd * 2. Redistributions in binary form must reproduce the above copyright 12*a043e8c7SAdrian Chadd * notice, this list of conditions and the following disclaimer in the 13*a043e8c7SAdrian Chadd * documentation and/or other materials provided with the distribution. 14*a043e8c7SAdrian Chadd * 15*a043e8c7SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16*a043e8c7SAdrian Chadd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17*a043e8c7SAdrian Chadd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18*a043e8c7SAdrian Chadd * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19*a043e8c7SAdrian Chadd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20*a043e8c7SAdrian Chadd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21*a043e8c7SAdrian Chadd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22*a043e8c7SAdrian Chadd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23*a043e8c7SAdrian Chadd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24*a043e8c7SAdrian Chadd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25*a043e8c7SAdrian Chadd * SUCH DAMAGE. 26*a043e8c7SAdrian Chadd * 27*a043e8c7SAdrian Chadd * $FreeBSD$ 28*a043e8c7SAdrian Chadd */ 29*a043e8c7SAdrian Chadd 30*a043e8c7SAdrian Chadd #include <sys/param.h> 31*a043e8c7SAdrian Chadd #include <sys/bus.h> 32*a043e8c7SAdrian Chadd #include <sys/errno.h> 33*a043e8c7SAdrian Chadd #include <sys/kernel.h> 34*a043e8c7SAdrian Chadd #include <sys/module.h> 35*a043e8c7SAdrian Chadd #include <sys/socket.h> 36*a043e8c7SAdrian Chadd #include <sys/sockio.h> 37*a043e8c7SAdrian Chadd #include <sys/sysctl.h> 38*a043e8c7SAdrian Chadd #include <sys/systm.h> 39*a043e8c7SAdrian Chadd 40*a043e8c7SAdrian Chadd #include <net/if.h> 41*a043e8c7SAdrian Chadd #include <net/if_arp.h> 42*a043e8c7SAdrian Chadd #include <net/ethernet.h> 43*a043e8c7SAdrian Chadd #include <net/if_dl.h> 44*a043e8c7SAdrian Chadd #include <net/if_media.h> 45*a043e8c7SAdrian Chadd #include <net/if_types.h> 46*a043e8c7SAdrian Chadd 47*a043e8c7SAdrian Chadd #include <machine/bus.h> 48*a043e8c7SAdrian Chadd #include <dev/iicbus/iic.h> 49*a043e8c7SAdrian Chadd #include <dev/iicbus/iiconf.h> 50*a043e8c7SAdrian Chadd #include <dev/iicbus/iicbus.h> 51*a043e8c7SAdrian Chadd #include <dev/mii/mii.h> 52*a043e8c7SAdrian Chadd #include <dev/mii/miivar.h> 53*a043e8c7SAdrian Chadd #include <dev/etherswitch/mdio.h> 54*a043e8c7SAdrian Chadd 55*a043e8c7SAdrian Chadd #include <dev/etherswitch/etherswitch.h> 56*a043e8c7SAdrian Chadd 57*a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitchreg.h> 58*a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitchvar.h> 59*a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitch_reg.h> 60*a043e8c7SAdrian Chadd #include <dev/etherswitch/arswitch/arswitch_8316.h> 61*a043e8c7SAdrian Chadd 62*a043e8c7SAdrian Chadd #include "mdio_if.h" 63*a043e8c7SAdrian Chadd #include "miibus_if.h" 64*a043e8c7SAdrian Chadd #include "etherswitch_if.h" 65*a043e8c7SAdrian Chadd 66*a043e8c7SAdrian Chadd /* 67*a043e8c7SAdrian Chadd * AR8316 specific functions 68*a043e8c7SAdrian Chadd */ 69*a043e8c7SAdrian Chadd static int 70*a043e8c7SAdrian Chadd ar8316_hw_setup(struct arswitch_softc *sc) 71*a043e8c7SAdrian Chadd { 72*a043e8c7SAdrian Chadd 73*a043e8c7SAdrian Chadd /* 74*a043e8c7SAdrian Chadd * Configure the switch mode based on whether: 75*a043e8c7SAdrian Chadd * 76*a043e8c7SAdrian Chadd * + The switch port is GMII/RGMII; 77*a043e8c7SAdrian Chadd * + Port 4 is either connected to the CPU or to the internal switch. 78*a043e8c7SAdrian Chadd */ 79*a043e8c7SAdrian Chadd if (sc->is_rgmii && sc->phy4cpu) { 80*a043e8c7SAdrian Chadd arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE, 81*a043e8c7SAdrian Chadd AR8X16_MODE_RGMII_PORT4_ISO); 82*a043e8c7SAdrian Chadd device_printf(sc->sc_dev, 83*a043e8c7SAdrian Chadd "%s: MAC port == RGMII, port 4 = dedicated PHY\n", 84*a043e8c7SAdrian Chadd __func__); 85*a043e8c7SAdrian Chadd } else if (sc->is_rgmii) { 86*a043e8c7SAdrian Chadd arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE, 87*a043e8c7SAdrian Chadd AR8X16_MODE_RGMII_PORT4_SWITCH); 88*a043e8c7SAdrian Chadd device_printf(sc->sc_dev, 89*a043e8c7SAdrian Chadd "%s: MAC port == RGMII, port 4 = switch port\n", 90*a043e8c7SAdrian Chadd __func__); 91*a043e8c7SAdrian Chadd } else if (sc->is_gmii) { 92*a043e8c7SAdrian Chadd arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE, 93*a043e8c7SAdrian Chadd AR8X16_MODE_GMII); 94*a043e8c7SAdrian Chadd device_printf(sc->sc_dev, "%s: MAC port == GMII\n", __func__); 95*a043e8c7SAdrian Chadd } else { 96*a043e8c7SAdrian Chadd device_printf(sc->sc_dev, "%s: unknown switch PHY config\n", 97*a043e8c7SAdrian Chadd __func__); 98*a043e8c7SAdrian Chadd return (ENXIO); 99*a043e8c7SAdrian Chadd } 100*a043e8c7SAdrian Chadd 101*a043e8c7SAdrian Chadd DELAY(1000); /* 1ms wait for things to settle */ 102*a043e8c7SAdrian Chadd 103*a043e8c7SAdrian Chadd /* 104*a043e8c7SAdrian Chadd * If port 4 is RGMII, force workaround 105*a043e8c7SAdrian Chadd */ 106*a043e8c7SAdrian Chadd if (sc->is_rgmii && sc->phy4cpu) { 107*a043e8c7SAdrian Chadd device_printf(sc->sc_dev, 108*a043e8c7SAdrian Chadd "%s: port 4 RGMII workaround\n", 109*a043e8c7SAdrian Chadd __func__); 110*a043e8c7SAdrian Chadd 111*a043e8c7SAdrian Chadd /* work around for phy4 rgmii mode */ 112*a043e8c7SAdrian Chadd arswitch_writedbg(sc->sc_dev, 4, 0x12, 0x480c); 113*a043e8c7SAdrian Chadd /* rx delay */ 114*a043e8c7SAdrian Chadd arswitch_writedbg(sc->sc_dev, 4, 0x0, 0x824e); 115*a043e8c7SAdrian Chadd /* tx delay */ 116*a043e8c7SAdrian Chadd arswitch_writedbg(sc->sc_dev, 4, 0x5, 0x3d47); 117*a043e8c7SAdrian Chadd DELAY(1000); /* 1ms, again to let things settle */ 118*a043e8c7SAdrian Chadd } 119*a043e8c7SAdrian Chadd 120*a043e8c7SAdrian Chadd return (0); 121*a043e8c7SAdrian Chadd } 122*a043e8c7SAdrian Chadd 123*a043e8c7SAdrian Chadd /* 124*a043e8c7SAdrian Chadd * Initialise other global values, for the AR8316. 125*a043e8c7SAdrian Chadd */ 126*a043e8c7SAdrian Chadd static int 127*a043e8c7SAdrian Chadd ar8316_hw_global_setup(struct arswitch_softc *sc) 128*a043e8c7SAdrian Chadd { 129*a043e8c7SAdrian Chadd 130*a043e8c7SAdrian Chadd arswitch_writereg(sc->sc_dev, 0x38, 0xc000050e); 131*a043e8c7SAdrian Chadd arswitch_writereg(sc->sc_dev, AR8X16_REG_FLOOD_MASK, 0x003f003f); 132*a043e8c7SAdrian Chadd arswitch_modifyreg(sc->sc_dev, AR8X16_REG_GLOBAL_CTRL, 133*a043e8c7SAdrian Chadd AR8316_GLOBAL_CTRL_MTU_MASK, 9018 + 8 + 2); 134*a043e8c7SAdrian Chadd 135*a043e8c7SAdrian Chadd return (0); 136*a043e8c7SAdrian Chadd } 137*a043e8c7SAdrian Chadd 138*a043e8c7SAdrian Chadd void 139*a043e8c7SAdrian Chadd ar8316_attach(struct arswitch_softc *sc) 140*a043e8c7SAdrian Chadd { 141*a043e8c7SAdrian Chadd 142*a043e8c7SAdrian Chadd sc->hal.arswitch_hw_setup = ar8316_hw_setup; 143*a043e8c7SAdrian Chadd sc->hal.arswitch_hw_global_setup = ar8316_hw_global_setup; 144*a043e8c7SAdrian Chadd } 145