1e388de98SAdrian Chadd /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 3e388de98SAdrian Chadd * 4e388de98SAdrian Chadd * Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>. 5e388de98SAdrian Chadd * 6e388de98SAdrian Chadd * Redistribution and use in source and binary forms, with or without 7e388de98SAdrian Chadd * modification, are permitted provided that the following conditions 8e388de98SAdrian Chadd * are met: 9e388de98SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 10e388de98SAdrian Chadd * notice, this list of conditions and the following disclaimer. 11e388de98SAdrian Chadd * 2. Redistributions in binary form must reproduce the above copyright 12e388de98SAdrian Chadd * notice, this list of conditions and the following disclaimer in the 13e388de98SAdrian Chadd * documentation and/or other materials provided with the distribution. 14e388de98SAdrian Chadd * 15e388de98SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16e388de98SAdrian Chadd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17e388de98SAdrian Chadd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18e388de98SAdrian Chadd * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19e388de98SAdrian Chadd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20e388de98SAdrian Chadd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21e388de98SAdrian Chadd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22e388de98SAdrian Chadd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23e388de98SAdrian Chadd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24e388de98SAdrian Chadd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25e388de98SAdrian Chadd * SUCH DAMAGE. 26e388de98SAdrian Chadd */ 27e388de98SAdrian Chadd 28e388de98SAdrian Chadd #include <sys/param.h> 29e388de98SAdrian Chadd #include <sys/bus.h> 30e388de98SAdrian Chadd #include <sys/errno.h> 31e388de98SAdrian Chadd #include <sys/kernel.h> 32e388de98SAdrian Chadd #include <sys/malloc.h> 33e388de98SAdrian Chadd #include <sys/module.h> 34e388de98SAdrian Chadd #include <sys/socket.h> 35e388de98SAdrian Chadd #include <sys/sockio.h> 36e388de98SAdrian Chadd #include <sys/sysctl.h> 37e388de98SAdrian Chadd #include <sys/systm.h> 38e388de98SAdrian Chadd 39e388de98SAdrian Chadd #include <net/if.h> 40e388de98SAdrian Chadd #include <net/if_var.h> 41e388de98SAdrian Chadd #include <net/if_arp.h> 42e388de98SAdrian Chadd #include <net/ethernet.h> 43e388de98SAdrian Chadd #include <net/if_dl.h> 44e388de98SAdrian Chadd #include <net/if_media.h> 45e388de98SAdrian Chadd #include <net/if_types.h> 46e388de98SAdrian Chadd 47e388de98SAdrian Chadd #include <machine/bus.h> 48e388de98SAdrian Chadd #include <dev/iicbus/iic.h> 49e388de98SAdrian Chadd #include <dev/iicbus/iiconf.h> 50e388de98SAdrian Chadd #include <dev/iicbus/iicbus.h> 51e388de98SAdrian Chadd #include <dev/mii/mii.h> 52e388de98SAdrian Chadd #include <dev/mii/miivar.h> 53e388de98SAdrian Chadd #include <dev/mdio/mdio.h> 54*be82b3a0SEmmanuel Vadot #include <dev/clk/clk.h> 55e388de98SAdrian Chadd #include <dev/extres/hwreset/hwreset.h> 56e388de98SAdrian Chadd 57e388de98SAdrian Chadd #include <dev/fdt/fdt_common.h> 58e388de98SAdrian Chadd #include <dev/ofw/ofw_bus.h> 59e388de98SAdrian Chadd #include <dev/ofw/ofw_bus_subr.h> 60e388de98SAdrian Chadd 61e388de98SAdrian Chadd #include <dev/etherswitch/etherswitch.h> 62e388de98SAdrian Chadd 63e388de98SAdrian Chadd #include <dev/etherswitch/ar40xx/ar40xx_var.h> 64e388de98SAdrian Chadd #include <dev/etherswitch/ar40xx/ar40xx_reg.h> 65e388de98SAdrian Chadd #include <dev/etherswitch/ar40xx/ar40xx_hw.h> 66e388de98SAdrian Chadd #include <dev/etherswitch/ar40xx/ar40xx_hw_mib.h> 67e388de98SAdrian Chadd 68e388de98SAdrian Chadd #include "mdio_if.h" 69e388de98SAdrian Chadd #include "miibus_if.h" 70e388de98SAdrian Chadd #include "etherswitch_if.h" 71e388de98SAdrian Chadd 72e388de98SAdrian Chadd 73e388de98SAdrian Chadd #define MIB_DESC(_s , _o, _n) \ 74e388de98SAdrian Chadd { \ 75e388de98SAdrian Chadd .size = (_s), \ 76e388de98SAdrian Chadd .offset = (_o), \ 77e388de98SAdrian Chadd .name = (_n), \ 78e388de98SAdrian Chadd } 79e388de98SAdrian Chadd 80e388de98SAdrian Chadd static const struct ar40xx_mib_desc ar40xx_mibs[] = { 81e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"), 82e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"), 83e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"), 84e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"), 85e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"), 86e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"), 87e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"), 88e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"), 89e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"), 90e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"), 91e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"), 92e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"), 93e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"), 94e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"), 95e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"), 96e388de98SAdrian Chadd MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"), 97e388de98SAdrian Chadd MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"), 98e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"), 99e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"), 100e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"), 101e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"), 102e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"), 103e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"), 104e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"), 105e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"), 106e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"), 107e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"), 108e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"), 109e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"), 110e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"), 111e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"), 112e388de98SAdrian Chadd MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"), 113e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"), 114e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"), 115e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"), 116e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"), 117e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"), 118e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"), 119e388de98SAdrian Chadd MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"), 120e388de98SAdrian Chadd }; 121e388de98SAdrian Chadd 122e388de98SAdrian Chadd 123e388de98SAdrian Chadd int 124e388de98SAdrian Chadd ar40xx_hw_mib_op(struct ar40xx_softc *sc, uint32_t op) 125e388de98SAdrian Chadd { 126e388de98SAdrian Chadd uint32_t reg; 127e388de98SAdrian Chadd int ret; 128e388de98SAdrian Chadd 129e388de98SAdrian Chadd AR40XX_LOCK_ASSERT(sc); 130e388de98SAdrian Chadd 131e388de98SAdrian Chadd /* Trigger capturing statistics on all ports */ 132e388de98SAdrian Chadd AR40XX_REG_BARRIER_READ(sc); 133e388de98SAdrian Chadd reg = AR40XX_REG_READ(sc, AR40XX_REG_MIB_FUNC); 134e388de98SAdrian Chadd reg &= ~AR40XX_MIB_FUNC; 135e388de98SAdrian Chadd reg |= (op << AR40XX_MIB_FUNC_S); 136e388de98SAdrian Chadd AR40XX_REG_WRITE(sc, AR40XX_REG_MIB_FUNC, reg); 137e388de98SAdrian Chadd AR40XX_REG_BARRIER_WRITE(sc); 138e388de98SAdrian Chadd 139e388de98SAdrian Chadd /* Now wait */ 140e388de98SAdrian Chadd ret = ar40xx_hw_wait_bit(sc, AR40XX_REG_MIB_FUNC, 141e388de98SAdrian Chadd AR40XX_MIB_BUSY, 0); 142e388de98SAdrian Chadd if (ret != 0) { 143e388de98SAdrian Chadd device_printf(sc->sc_dev, 144e388de98SAdrian Chadd "%s: ERROR: timeout waiting for MIB load\n", 145e388de98SAdrian Chadd __func__); 146e388de98SAdrian Chadd } 147e388de98SAdrian Chadd 148e388de98SAdrian Chadd return ret; 149e388de98SAdrian Chadd } 150e388de98SAdrian Chadd 151e388de98SAdrian Chadd int 152e388de98SAdrian Chadd ar40xx_hw_mib_capture(struct ar40xx_softc *sc) 153e388de98SAdrian Chadd { 154e388de98SAdrian Chadd int ret; 155e388de98SAdrian Chadd 156e388de98SAdrian Chadd ret = ar40xx_hw_mib_op(sc, AR40XX_MIB_FUNC_CAPTURE); 157e388de98SAdrian Chadd return (ret); 158e388de98SAdrian Chadd } 159e388de98SAdrian Chadd 160e388de98SAdrian Chadd int 161e388de98SAdrian Chadd ar40xx_hw_mib_flush(struct ar40xx_softc *sc) 162e388de98SAdrian Chadd { 163e388de98SAdrian Chadd int ret; 164e388de98SAdrian Chadd 165e388de98SAdrian Chadd ret = ar40xx_hw_mib_op(sc, AR40XX_MIB_FUNC_FLUSH); 166e388de98SAdrian Chadd return (ret); 167e388de98SAdrian Chadd } 168e388de98SAdrian Chadd 169e388de98SAdrian Chadd int 170e388de98SAdrian Chadd ar40xx_hw_mib_fetch(struct ar40xx_softc *sc, int port) 171e388de98SAdrian Chadd { 172e388de98SAdrian Chadd uint64_t val; 173e388de98SAdrian Chadd uint32_t base, reg; 174e388de98SAdrian Chadd int i; 175e388de98SAdrian Chadd 176e388de98SAdrian Chadd base = AR40XX_REG_PORT_STATS_START 177e388de98SAdrian Chadd + (AR40XX_REG_PORT_STATS_LEN * port); 178e388de98SAdrian Chadd 179e388de98SAdrian Chadd /* For now just print them out, we'll store them later */ 180e388de98SAdrian Chadd AR40XX_REG_BARRIER_READ(sc); 181e388de98SAdrian Chadd for (i = 0; i < nitems(ar40xx_mibs); i++) { 182e388de98SAdrian Chadd val = 0; 183e388de98SAdrian Chadd 184e388de98SAdrian Chadd val = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset); 185e388de98SAdrian Chadd if (ar40xx_mibs[i].size == 2) { 186e388de98SAdrian Chadd reg = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset + 4); 187e388de98SAdrian Chadd val |= ((uint64_t) reg << 32); 188e388de98SAdrian Chadd } 189e388de98SAdrian Chadd 190e388de98SAdrian Chadd device_printf(sc->sc_dev, "%s[%d] = %llu\n", ar40xx_mibs[i].name, port, val); 191e388de98SAdrian Chadd } 192e388de98SAdrian Chadd 193e388de98SAdrian Chadd return (0); 194e388de98SAdrian Chadd } 195