1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.4 2007/10/23 14:28:42 sephe Exp $ 37 * $FreeBSD$ 38 */ 39 40 #ifndef _IF_ETVAR_H 41 #define _IF_ETVAR_H 42 43 #define ET_RING_ALIGN 4096 44 #define ET_STATUS_ALIGN 8 45 #define ET_NSEG_MAX 32 /* XXX no limit actually */ 46 #define ET_NSEG_SPARE 4 47 48 #define ET_TX_NDESC 512 49 #define ET_RX_NDESC 512 50 #define ET_RX_NRING 2 51 #define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 52 53 #define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 54 #define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 55 #define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 56 57 #define ET_JUMBO_FRAMELEN (ET_MEM_SIZE - ET_MEM_RXSIZE_MIN - \ 58 ET_MEM_TXSIZE_EX) 59 #define ET_JUMBO_MTU (ET_JUMBO_FRAMELEN - ETHER_HDR_LEN - \ 60 EVL_ENCAPLEN - ETHER_CRC_LEN) 61 62 #define ET_FRAMELEN(mtu) (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + \ 63 (mtu) + ETHER_CRC_LEN) 64 65 #define ET_JSLOTS (ET_RX_NDESC + 128) 66 #define ET_JLEN (ET_JUMBO_FRAMELEN + ETHER_ALIGN) 67 #define ET_JUMBO_MEM_SIZE (ET_JSLOTS * ET_JLEN) 68 69 #define CSR_WRITE_4(sc, reg, val) \ 70 bus_write_4((sc)->sc_mem_res, (reg), (val)) 71 #define CSR_READ_4(sc, reg) \ 72 bus_read_4((sc)->sc_mem_res, (reg)) 73 74 #define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 75 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 76 77 struct et_txdesc { 78 uint32_t td_addr_hi; 79 uint32_t td_addr_lo; 80 uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 81 uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 82 }; 83 84 #define ET_TDCTRL1_LEN_MASK 0x0000FFFF 85 86 #define ET_TDCTRL2_LAST_FRAG 0x00000001 87 #define ET_TDCTRL2_FIRST_FRAG 0x00000002 88 #define ET_TDCTRL2_INTR 0x00000004 89 #define ET_TDCTRL2_CTRL_WORD 0x00000008 90 #define ET_TDCTRL2_HDX_BACKP 0x00000010 91 #define ET_TDCTRL2_XMIT_PAUSE 0x00000020 92 #define ET_TDCTRL2_FRAME_ERR 0x00000040 93 #define ET_TDCTRL2_NO_CRC 0x00000080 94 #define ET_TDCTRL2_MAC_OVRRD 0x00000100 95 #define ET_TDCTRL2_PAD_PACKET 0x00000200 96 #define ET_TDCTRL2_JUMBO_PACKET 0x00000400 97 #define ET_TDCTRL2_INS_VLAN 0x00000800 98 #define ET_TDCTRL2_CSUM_IP 0x00001000 99 #define ET_TDCTRL2_CSUM_TCP 0x00002000 100 #define ET_TDCTRL2_CSUM_UDP 0x00004000 101 102 struct et_rxdesc { 103 uint32_t rd_addr_lo; 104 uint32_t rd_addr_hi; 105 uint32_t rd_ctrl; /* ET_RDCTRL_ */ 106 }; 107 108 #define ET_RDCTRL_BUFIDX_MASK 0x000003FF 109 110 struct et_rxstat { 111 uint32_t rxst_info1; 112 uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 113 }; 114 115 #define ET_RXST_INFO1_HASH_PASS 0x00000001 116 #define ET_RXST_INFO1_IPCSUM 0x00000002 117 #define ET_RXST_INFO1_IPCSUM_OK 0x00000004 118 #define ET_RXST_INFO1_TCPCSUM 0x00000008 119 #define ET_RXST_INFO1_TCPCSUM_OK 0x00000010 120 #define ET_RXST_INFO1_WOL 0x00000020 121 #define ET_RXST_INFO1_RXMAC_ERR 0x00000040 122 #define ET_RXST_INFO1_DROP 0x00000080 123 #define ET_RXST_INFO1_FRAME_TRUNC 0x00000100 124 #define ET_RXST_INFO1_JUMBO 0x00000200 125 #define ET_RXST_INFO1_VLAN 0x00000400 126 #define ET_RXST_INFO1_PREV_FRMAE_DROP 0x00010000 127 #define ET_RXST_INFO1_SHORT 0x00020000 128 #define ET_RXST_INFO1_BAD_CARRIER 0x00040000 129 #define ET_RXST_INFO1_CODE_ERR 0x00080000 130 #define ET_RXST_INFO1_CRC_ERR 0x00100000 131 #define ET_RXST_INFO1_LEN_MISMATCH 0x00200000 132 #define ET_RXST_INFO1_TOO_LONG 0x00400000 133 #define ET_RXST_INFO1_OK 0x00800000 134 #define ET_RXST_INFO1_MULTICAST 0x01000000 135 #define ET_RXST_INFO1_BROADCAST 0x02000000 136 #define ET_RXST_INFO1_DRIBBLE 0x04000000 137 #define ET_RXST_INFO1_CTL_FRAME 0x08000000 138 #define ET_RXST_INFO1_PAUSE_FRAME 0x10000000 139 #define ET_RXST_INFO1_UNKWN_CTL_FRAME 0x20000000 140 #define ET_RXST_INFO1_VLAN_TAG 0x40000000 141 #define ET_RXST_INFO1_LONG_EVENT 0x80000000 142 143 #define ET_RXST_INFO2_LEN_MASK 0x0000FFFF 144 #define ET_RXST_INFO2_LEN_SHIFT 0 145 #define ET_RXST_INFO2_BUFIDX_MASK 0x03FF0000 146 #define ET_RXST_INFO2_BUFIDX_SHIFT 16 147 #define ET_RXST_INFO2_RINGIDX_MASK 0x0C000000 148 #define ET_RXST_INFO2_RINGIDX_SHIFT 26 149 150 struct et_rxstatus { 151 uint32_t rxs_ring; 152 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 153 }; 154 155 #define ET_RXS_STATRING_INDEX_MASK 0x0FFF0000 156 #define ET_RXS_STATRING_INDEX_SHIFT 16 157 #define ET_RXS_STATRING_WRAP 0x10000000 158 159 struct et_txbuf { 160 struct mbuf *tb_mbuf; 161 bus_dmamap_t tb_dmap; 162 }; 163 164 struct et_rxbuf { 165 struct mbuf *rb_mbuf; 166 bus_dmamap_t rb_dmap; 167 }; 168 169 struct et_txstatus_data { 170 uint32_t *txsd_status; 171 bus_addr_t txsd_paddr; 172 bus_dma_tag_t txsd_dtag; 173 bus_dmamap_t txsd_dmap; 174 }; 175 176 struct et_rxstatus_data { 177 struct et_rxstatus *rxsd_status; 178 bus_addr_t rxsd_paddr; 179 bus_dma_tag_t rxsd_dtag; 180 bus_dmamap_t rxsd_dmap; 181 }; 182 183 struct et_rxstat_ring { 184 struct et_rxstat *rsr_stat; 185 bus_addr_t rsr_paddr; 186 bus_dma_tag_t rsr_dtag; 187 bus_dmamap_t rsr_dmap; 188 189 int rsr_index; 190 int rsr_wrap; 191 }; 192 193 struct et_txdesc_ring { 194 struct et_txdesc *tr_desc; 195 bus_addr_t tr_paddr; 196 bus_dma_tag_t tr_dtag; 197 bus_dmamap_t tr_dmap; 198 199 int tr_ready_index; 200 int tr_ready_wrap; 201 }; 202 203 struct et_rxdesc_ring { 204 struct et_rxdesc *rr_desc; 205 bus_addr_t rr_paddr; 206 bus_dma_tag_t rr_dtag; 207 bus_dmamap_t rr_dmap; 208 209 uint32_t rr_posreg; 210 int rr_index; 211 int rr_wrap; 212 }; 213 214 struct et_txbuf_data { 215 struct et_txbuf tbd_buf[ET_TX_NDESC]; 216 217 int tbd_start_index; 218 int tbd_start_wrap; 219 int tbd_used; 220 }; 221 222 struct et_softc; 223 struct et_rxbuf_data; 224 225 struct et_rxbuf_data { 226 struct et_rxbuf rbd_buf[ET_RX_NDESC]; 227 228 struct et_softc *rbd_softc; 229 struct et_rxdesc_ring *rbd_ring; 230 231 int rbd_bufsize; 232 int (*rbd_newbuf)(struct et_rxbuf_data *, int); 233 void (*rbd_discard)(struct et_rxbuf_data *, int); 234 }; 235 236 struct et_hw_stats { 237 /* RX/TX stats. */ 238 uint64_t pkts_64; 239 uint64_t pkts_65; 240 uint64_t pkts_128; 241 uint64_t pkts_256; 242 uint64_t pkts_512; 243 uint64_t pkts_1024; 244 uint64_t pkts_1519; 245 /* RX stats. */ 246 uint64_t rx_bytes; 247 uint64_t rx_frames; 248 uint32_t rx_crcerrs; 249 uint64_t rx_mcast; 250 uint64_t rx_bcast; 251 uint32_t rx_control; 252 uint32_t rx_pause; 253 uint32_t rx_unknown_control; 254 uint32_t rx_alignerrs; 255 uint32_t rx_lenerrs; 256 uint32_t rx_codeerrs; 257 uint32_t rx_cserrs; 258 uint32_t rx_runts; 259 uint64_t rx_oversize; 260 uint32_t rx_fragments; 261 uint32_t rx_jabbers; 262 uint32_t rx_drop; 263 /* TX stats. */ 264 uint64_t tx_bytes; 265 uint64_t tx_frames; 266 uint64_t tx_mcast; 267 uint64_t tx_bcast; 268 uint32_t tx_pause; 269 uint32_t tx_deferred; 270 uint32_t tx_excess_deferred; 271 uint32_t tx_single_colls; 272 uint32_t tx_multi_colls; 273 uint32_t tx_late_colls; 274 uint32_t tx_excess_colls; 275 uint32_t tx_total_colls; 276 uint32_t tx_pause_honored; 277 uint32_t tx_drop; 278 uint32_t tx_jabbers; 279 uint32_t tx_crcerrs; 280 uint32_t tx_control; 281 uint64_t tx_oversize; 282 uint32_t tx_undersize; 283 uint32_t tx_fragments; 284 }; 285 286 struct et_softc { 287 struct ifnet *ifp; 288 device_t dev; 289 struct mtx sc_mtx; 290 device_t sc_miibus; 291 void *sc_irq_handle; 292 struct resource *sc_irq_res; 293 struct resource *sc_mem_res; 294 295 int sc_if_flags; 296 uint32_t sc_flags; /* ET_FLAG_ */ 297 int sc_expcap; 298 299 int sc_mem_rid; 300 301 int sc_irq_rid; 302 303 struct callout sc_tick; 304 305 int watchdog_timer; 306 307 bus_dma_tag_t sc_dtag; 308 309 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 310 struct et_rxstat_ring sc_rxstat_ring; 311 struct et_rxstatus_data sc_rx_status; 312 313 struct et_txdesc_ring sc_tx_ring; 314 struct et_txstatus_data sc_tx_status; 315 316 bus_dma_tag_t sc_mbuf_dtag; 317 bus_dma_tag_t sc_rx_mini_tag; 318 bus_dmamap_t sc_rx_mini_sparemap; 319 bus_dma_tag_t sc_rx_tag; 320 bus_dmamap_t sc_rx_sparemap; 321 bus_dma_tag_t sc_tx_tag; 322 struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 323 struct et_txbuf_data sc_tx_data; 324 325 struct et_hw_stats sc_stats; 326 uint32_t sc_tx; 327 uint32_t sc_tx_intr; 328 329 /* 330 * Sysctl variables 331 */ 332 int sc_rx_intr_npkts; 333 int sc_rx_intr_delay; 334 int sc_tx_intr_nsegs; 335 uint32_t sc_timer; 336 }; 337 338 #define ET_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 339 #define ET_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 340 #define ET_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 341 342 #define ET_FLAG_PCIE 0x0001 343 #define ET_FLAG_MSI 0x0002 344 #define ET_FLAG_FASTETHER 0x0004 345 #define ET_FLAG_TXRX_ENABLED 0x0100 346 #define ET_FLAG_JUMBO 0x0200 347 #define ET_FLAG_LINK 0x8000 348 349 #endif /* !_IF_ETVAR_H */ 350