1 /*- 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.3 2007/10/23 14:28:42 sephe Exp $ 35 * $FreeBSD$ 36 */ 37 /*- 38 * Portions of this code is derived from NetBSD which is covered by 39 * the following license: 40 * 41 * Copyright (c) 2004, 2005 David Young. All rights reserved. 42 * 43 * Programmed for NetBSD by David Young. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. The name of David Young may not be used to endorse or promote 54 * products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 58 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 59 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 60 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 61 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 62 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 63 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 65 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 67 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 68 * OF SUCH DAMAGE. 69 * 70 * $DragonFly: src/sys/sys/bitops.h,v 1.1 2007/10/14 04:15:17 sephe Exp $ 71 */ 72 73 #ifndef _IF_ETREG_H 74 #define _IF_ETREG_H 75 76 /* 77 * __BIT(n): Return a bitmask with bit n set, where the least 78 * significant bit is bit 0. 79 * 80 * __BITS(m, n): Return a bitmask with bits m through n, inclusive, 81 * set. It does not matter whether m>n or m<=n. The 82 * least significant bit is bit 0. 83 * 84 * A "bitfield" is a span of consecutive bits defined by a bitmask, 85 * where 1s select the bits in the bitfield. __SHIFTIN, __SHIFTOUT, 86 * and __SHIFTOUT_MASK help read and write bitfields from device 87 * registers. 88 * 89 * __SHIFTIN(v, mask): Left-shift bits `v' into the bitfield 90 * defined by `mask', and return them. No 91 * side-effects. 92 * 93 * __SHIFTOUT(v, mask): Extract and return the bitfield selected 94 * by `mask' from `v', right-shifting the 95 * bits so that the rightmost selected bit 96 * is at bit 0. No side-effects. 97 * 98 * __SHIFTOUT_MASK(mask): Right-shift the bits in `mask' so that 99 * the rightmost non-zero bit is at bit 100 * 0. This is useful for finding the 101 * greatest unsigned value that a bitfield 102 * can hold. No side-effects. Note that 103 * __SHIFTOUT_MASK(m) = __SHIFTOUT(m, m). 104 */ 105 106 /* __BIT(n): nth bit, where __BIT(0) == 0x1. */ 107 #define __BIT(__n) (((__n) == 32) ? 0 : ((uint32_t)1 << (__n))) 108 109 /* __BITS(m, n): bits m through n, m < n. */ 110 #define __BITS(__m, __n) \ 111 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1)) 112 113 /* Find least significant bit that is set */ 114 #define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 115 116 #define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) 117 #define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) 118 #define __SHIFTOUT_MASK(__mask) __SHIFTOUT((__mask), (__mask)) 119 120 #define ET_MEM_TXSIZE_EX 182 121 #define ET_MEM_RXSIZE_MIN 608 122 #define ET_MEM_RXSIZE_DEFAULT 11216 123 #define ET_MEM_SIZE 16384 124 #define ET_MEM_UNIT 16 125 126 /* 127 * PCI registers 128 * 129 * ET_PCIV_ACK_LATENCY_{128,256} are from 130 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-5 131 * 132 * ET_PCIV_REPLAY_TIMER_{128,256} are from 133 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4 134 */ 135 #define ET_PCIR_BAR PCIR_BAR(0) 136 137 #define ET_PCIR_DEVICE_CAPS 0x4c 138 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */ 139 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0 140 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1 141 142 #define ET_PCIR_DEVICE_CTRL 0x50 143 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */ 144 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000 145 146 #define ET_PCIR_MAC_ADDR0 0xa4 147 #define ET_PCIR_MAC_ADDR1 0xa8 148 149 #define ET_PCIR_EEPROM_STATUS 0xb2 /* XXX undocumented */ 150 #define ET_PCIM_EEPROM_STATUS_ERROR 0x4c 151 152 #define ET_PCIR_ACK_LATENCY 0xc0 153 #define ET_PCIV_ACK_LATENCY_128 237 154 #define ET_PCIV_ACK_LATENCY_256 416 155 156 #define ET_PCIR_REPLAY_TIMER 0xc2 157 #define ET_REPLAY_TIMER_RX_L0S_ADJ 250 /* XXX infered from default */ 158 #define ET_PCIV_REPLAY_TIMER_128 (711 + ET_REPLAY_TIMER_RX_L0S_ADJ) 159 #define ET_PCIV_REPLAY_TIMER_256 (1248 + ET_REPLAY_TIMER_RX_L0S_ADJ) 160 161 #define ET_PCIR_L0S_L1_LATENCY 0xcf 162 #define ET_PCIM_L0S_LATENCY __BITS(2, 0) 163 #define ET_PCIM_L1_LATENCY __BITS(5, 3) 164 #define ET_PCIV_L0S_LATENCY(l) __SHIFTIN((l) - 1, ET_PCIM_L0S_LATENCY) 165 #define ET_PCIV_L1_LATENCY(l) __SHIFTIN((l) - 1, ET_PCIM_L1_LATENCY) 166 167 /* 168 * CSR 169 */ 170 #define ET_TXQUEUE_START 0x0000 171 #define ET_TXQUEUE_END 0x0004 172 #define ET_RXQUEUE_START 0x0008 173 #define ET_RXQUEUE_END 0x000c 174 #define ET_QUEUE_ADDR(addr) (((addr) / ET_MEM_UNIT) - 1) 175 #define ET_QUEUE_ADDR_START 0 176 #define ET_QUEUE_ADDR_END ET_QUEUE_ADDR(ET_MEM_SIZE) 177 178 #define ET_PM 0x0010 179 #define ET_PM_SYSCLK_GATE __BIT(3) 180 #define ET_PM_TXCLK_GATE __BIT(4) 181 #define ET_PM_RXCLK_GATE __BIT(5) 182 183 #define ET_INTR_STATUS 0x0018 184 #define ET_INTR_MASK 0x001c 185 186 #define ET_SWRST 0x0028 187 #define ET_SWRST_TXDMA __BIT(0) 188 #define ET_SWRST_RXDMA __BIT(1) 189 #define ET_SWRST_TXMAC __BIT(2) 190 #define ET_SWRST_RXMAC __BIT(3) 191 #define ET_SWRST_MAC __BIT(4) 192 #define ET_SWRST_MAC_STAT __BIT(5) 193 #define ET_SWRST_MMC __BIT(6) 194 #define ET_SWRST_SELFCLR_DISABLE __BIT(31) 195 196 #define ET_MSI_CFG 0x0030 197 198 #define ET_LOOPBACK 0x0034 199 200 #define ET_TIMER 0x0038 201 202 #define ET_TXDMA_CTRL 0x1000 203 #define ET_TXDMA_CTRL_HALT __BIT(0) 204 #define ET_TXDMA_CTRL_CACHE_THR __BITS(7, 4) 205 #define ET_TXDMA_CTRL_SINGLE_EPKT __BIT(8) /* ??? */ 206 207 #define ET_TX_RING_HI 0x1004 208 #define ET_TX_RING_LO 0x1008 209 #define ET_TX_RING_CNT 0x100c 210 211 #define ET_TX_STATUS_HI 0x101c 212 #define ET_TX_STATUS_LO 0x1020 213 214 #define ET_TX_READY_POS 0x1024 215 #define ET_TX_READY_POS_INDEX __BITS(9, 0) 216 #define ET_TX_READY_POS_WRAP __BIT(10) 217 218 #define ET_TX_DONE_POS 0x1060 219 #define ET_TX_DONE_POS_INDEX __BITS(9, 0) 220 #define ET_TX_DONE_POS_WRAP __BIT(10) 221 222 #define ET_RXDMA_CTRL 0x2000 223 #define ET_RXDMA_CTRL_HALT __BIT(0) 224 #define ET_RXDMA_CTRL_RING0_SIZE __BITS(9, 8) 225 #define ET_RXDMA_CTRL_RING0_128 0 /* 127 */ 226 #define ET_RXDMA_CTRL_RING0_256 1 /* 255 */ 227 #define ET_RXDMA_CTRL_RING0_512 2 /* 511 */ 228 #define ET_RXDMA_CTRL_RING0_1024 3 /* 1023 */ 229 #define ET_RXDMA_CTRL_RING0_ENABLE __BIT(10) 230 #define ET_RXDMA_CTRL_RING1_SIZE __BITS(12, 11) 231 #define ET_RXDMA_CTRL_RING1_2048 0 /* 2047 */ 232 #define ET_RXDMA_CTRL_RING1_4096 1 /* 4095 */ 233 #define ET_RXDMA_CTRL_RING1_8192 2 /* 8191 */ 234 #define ET_RXDMA_CTRL_RING1_16384 3 /* 16383 (9022?) */ 235 #define ET_RXDMA_CTRL_RING1_ENABLE __BIT(13) 236 #define ET_RXDMA_CTRL_HALTED __BIT(17) 237 238 #define ET_RX_STATUS_LO 0x2004 239 #define ET_RX_STATUS_HI 0x2008 240 241 #define ET_RX_INTR_NPKTS 0x200c 242 #define ET_RX_INTR_DELAY 0x2010 243 244 #define ET_RXSTAT_LO 0x2020 245 #define ET_RXSTAT_HI 0x2024 246 #define ET_RXSTAT_CNT 0x2028 247 248 #define ET_RXSTAT_POS 0x2030 249 #define ET_RXSTAT_POS_INDEX __BITS(11, 0) 250 #define ET_RXSTAT_POS_WRAP __BIT(12) 251 252 #define ET_RXSTAT_MINCNT 0x2038 253 254 #define ET_RX_RING0_LO 0x203c 255 #define ET_RX_RING0_HI 0x2040 256 #define ET_RX_RING0_CNT 0x2044 257 258 #define ET_RX_RING0_POS 0x204c 259 #define ET_RX_RING0_POS_INDEX __BITS(9, 0) 260 #define ET_RX_RING0_POS_WRAP __BIT(10) 261 262 #define ET_RX_RING0_MINCNT 0x2054 263 264 #define ET_RX_RING1_LO 0x2058 265 #define ET_RX_RING1_HI 0x205c 266 #define ET_RX_RING1_CNT 0x2060 267 268 #define ET_RX_RING1_POS 0x2068 269 #define ET_RX_RING1_POS_INDEX __BITS(9, 0) 270 #define ET_RX_RING1_POS_WRAP __BIT(10) 271 272 #define ET_RX_RING1_MINCNT 0x2070 273 274 #define ET_TXMAC_CTRL 0x3000 275 #define ET_TXMAC_CTRL_ENABLE __BIT(0) 276 #define ET_TXMAC_CTRL_FC_DISABLE __BIT(3) 277 278 #define ET_TXMAC_FLOWCTRL 0x3010 279 280 #define ET_RXMAC_CTRL 0x4000 281 #define ET_RXMAC_CTRL_ENABLE __BIT(0) 282 #define ET_RXMAC_CTRL_NO_PKTFILT __BIT(2) 283 #define ET_RXMAC_CTRL_WOL_DISABLE __BIT(3) 284 285 #define ET_WOL_CRC 0x4004 286 #define ET_WOL_SA_LO 0x4010 287 #define ET_WOL_SA_HI 0x4014 288 #define ET_WOL_MASK 0x4018 289 290 #define ET_UCAST_FILTADDR1 0x4068 291 #define ET_UCAST_FILTADDR2 0x406c 292 #define ET_UCAST_FILTADDR3 0x4070 293 294 #define ET_MULTI_HASH 0x4074 295 296 #define ET_PKTFILT 0x4084 297 #define ET_PKTFILT_BCAST __BIT(0) 298 #define ET_PKTFILT_MCAST __BIT(1) 299 #define ET_PKTFILT_UCAST __BIT(2) 300 #define ET_PKTFILT_FRAG __BIT(3) 301 #define ET_PKTFILT_MINLEN __BITS(22, 16) 302 303 #define ET_RXMAC_MC_SEGSZ 0x4088 304 #define ET_RXMAC_MC_SEGSZ_ENABLE __BIT(0) 305 #define ET_RXMAC_MC_SEGSZ_FC __BIT(1) 306 #define ET_RXMAC_MC_SEGSZ_MAX __BITS(9, 2) 307 #define ET_RXMAC_SEGSZ(segsz) ((segsz) / ET_MEM_UNIT) 308 #define ET_RXMAC_CUT_THRU_FRMLEN 8074 309 310 #define ET_RXMAC_MC_WATERMARK 0x408c 311 #define ET_RXMAC_SPACE_AVL 0x4094 312 313 #define ET_RXMAC_MGT 0x4098 314 #define ET_RXMAC_MGT_PASS_ECRC __BIT(4) 315 #define ET_RXMAC_MGT_PASS_ELEN __BIT(5) 316 #define ET_RXMAC_MGT_PASS_ETRUNC __BIT(16) 317 #define ET_RXMAC_MGT_CHECK_PKT __BIT(17) 318 319 #define ET_MAC_CFG1 0x5000 320 #define ET_MAC_CFG1_TXEN __BIT(0) 321 #define ET_MAC_CFG1_SYNC_TXEN __BIT(1) 322 #define ET_MAC_CFG1_RXEN __BIT(2) 323 #define ET_MAC_CFG1_SYNC_RXEN __BIT(3) 324 #define ET_MAC_CFG1_TXFLOW __BIT(4) 325 #define ET_MAC_CFG1_RXFLOW __BIT(5) 326 #define ET_MAC_CFG1_LOOPBACK __BIT(8) 327 #define ET_MAC_CFG1_RST_TXFUNC __BIT(16) 328 #define ET_MAC_CFG1_RST_RXFUNC __BIT(17) 329 #define ET_MAC_CFG1_RST_TXMC __BIT(18) 330 #define ET_MAC_CFG1_RST_RXMC __BIT(19) 331 #define ET_MAC_CFG1_SIM_RST __BIT(30) 332 #define ET_MAC_CFG1_SOFT_RST __BIT(31) 333 334 #define ET_MAC_CFG2 0x5004 335 #define ET_MAC_CFG2_FDX __BIT(0) 336 #define ET_MAC_CFG2_CRC __BIT(1) 337 #define ET_MAC_CFG2_PADCRC __BIT(2) 338 #define ET_MAC_CFG2_LENCHK __BIT(4) 339 #define ET_MAC_CFG2_BIGFRM __BIT(5) 340 #define ET_MAC_CFG2_MODE_MII __BIT(8) 341 #define ET_MAC_CFG2_MODE_GMII __BIT(9) 342 #define ET_MAC_CFG2_PREAMBLE_LEN __BITS(15, 12) 343 344 #define ET_IPG 0x5008 345 #define ET_IPG_B2B __BITS(6, 0) 346 #define ET_IPG_MINIFG __BITS(15, 8) 347 #define ET_IPG_NONB2B_2 __BITS(22, 16) 348 #define ET_IPG_NONB2B_1 __BITS(30, 24) 349 350 #define ET_MAC_HDX 0x500c 351 #define ET_MAC_HDX_COLLWIN __BITS(9, 0) 352 #define ET_MAC_HDX_REXMIT_MAX __BITS(15, 12) 353 #define ET_MAC_HDX_EXC_DEFER __BIT(16) 354 #define ET_MAC_HDX_NOBACKOFF __BIT(17) 355 #define ET_MAC_HDX_BP_NOBACKOFF __BIT(18) 356 #define ET_MAC_HDX_ALT_BEB __BIT(19) 357 #define ET_MAC_HDX_ALT_BEB_TRUNC __BITS(23, 20) 358 359 #define ET_MAX_FRMLEN 0x5010 360 361 #define ET_MII_CFG 0x5020 362 #define ET_MII_CFG_CLKRST __BITS(2, 0) 363 #define ET_MII_CFG_PREAMBLE_SUP __BIT(4) 364 #define ET_MII_CFG_SCAN_AUTOINC __BIT(5) 365 #define ET_MII_CFG_RST __BIT(31) 366 367 #define ET_MII_CMD 0x5024 368 #define ET_MII_CMD_READ __BIT(0) 369 370 #define ET_MII_ADDR 0x5028 371 #define ET_MII_ADDR_REG __BITS(4, 0) 372 #define ET_MII_ADDR_PHY __BITS(12, 8) 373 374 #define ET_MII_CTRL 0x502c 375 #define ET_MII_CTRL_VALUE __BITS(15, 0) 376 377 #define ET_MII_STAT 0x5030 378 #define ET_MII_STAT_VALUE __BITS(15, 0) 379 380 #define ET_MII_IND 0x5034 381 #define ET_MII_IND_BUSY __BIT(0) 382 #define ET_MII_IND_INVALID __BIT(2) 383 384 #define ET_MAC_CTRL 0x5038 385 #define ET_MAC_CTRL_MODE_MII __BIT(24) 386 #define ET_MAC_CTRL_LHDX __BIT(25) 387 #define ET_MAC_CTRL_GHDX __BIT(26) 388 389 #define ET_MAC_ADDR1 0x5040 390 #define ET_MAC_ADDR2 0x5044 391 392 #define ET_MMC_CTRL 0x7000 393 #define ET_MMC_CTRL_ENABLE __BIT(0) 394 #define ET_MMC_CTRL_ARB_DISABLE __BIT(1) 395 #define ET_MMC_CTRL_RXMAC_DISABLE __BIT(2) 396 #define ET_MMC_CTRL_TXMAC_DISABLE __BIT(3) 397 #define ET_MMC_CTRL_TXDMA_DISABLE __BIT(4) 398 #define ET_MMC_CTRL_RXDMA_DISABLE __BIT(5) 399 #define ET_MMC_CTRL_FORCE_CE __BIT(6) 400 401 /* 402 * Interrupts 403 */ 404 #define ET_INTR_TXEOF __BIT(3) 405 #define ET_INTR_TXDMA_ERROR __BIT(4) 406 #define ET_INTR_RXEOF __BIT(5) 407 #define ET_INTR_RXRING0_LOW __BIT(6) 408 #define ET_INTR_RXRING1_LOW __BIT(7) 409 #define ET_INTR_RXSTAT_LOW __BIT(8) 410 #define ET_INTR_RXDMA_ERROR __BIT(9) 411 #define ET_INTR_TIMER __BIT(14) 412 #define ET_INTR_WOL __BIT(15) 413 #define ET_INTR_PHY __BIT(16) 414 #define ET_INTR_TXMAC __BIT(17) 415 #define ET_INTR_RXMAC __BIT(18) 416 #define ET_INTR_MAC_STATS __BIT(19) 417 #define ET_INTR_SLAVE_TO __BIT(20) 418 419 #define ET_INTRS (ET_INTR_TXEOF | \ 420 ET_INTR_RXEOF | \ 421 ET_INTR_TIMER) 422 423 /* 424 * RX ring position uses same layout 425 */ 426 #define ET_RX_RING_POS_INDEX __BITS(9, 0) 427 #define ET_RX_RING_POS_WRAP __BIT(10) 428 429 /* 430 * PCI IDs 431 */ 432 #define PCI_VENDOR_LUCENT 0x11c1 433 #define PCI_PRODUCT_LUCENT_ET1310 0xed00 /* ET1310 10/100/1000M Ethernet */ 434 #define PCI_PRODUCT_LUCENT_ET1310_FAST 0xed01 /* ET1310 10/100M Ethernet */ 435 436 #endif /* !_IF_ETREG_H */ 437