xref: /freebsd/sys/dev/et/if_et.c (revision 69c5bce6ee1ec42997757e7f1334767d217c5d7d)
1 /*-
2  * Copyright (c) 2007 Sepherosa Ziehau.  All rights reserved.
3  *
4  * This code is derived from software contributed to The DragonFly Project
5  * by Sepherosa Ziehau <sepherosa@gmail.com>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in
15  *    the documentation and/or other materials provided with the
16  *    distribution.
17  * 3. Neither the name of The DragonFly Project nor the names of its
18  *    contributors may be used to endorse or promote products derived
19  *    from this software without specific, prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32  * SUCH DAMAGE.
33  *
34  * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $
35  */
36 
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
39 
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/endian.h>
43 #include <sys/kernel.h>
44 #include <sys/bus.h>
45 #include <sys/malloc.h>
46 #include <sys/mbuf.h>
47 #include <sys/proc.h>
48 #include <sys/rman.h>
49 #include <sys/module.h>
50 #include <sys/socket.h>
51 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
53 
54 #include <net/ethernet.h>
55 #include <net/if.h>
56 #include <net/if_dl.h>
57 #include <net/if_types.h>
58 #include <net/bpf.h>
59 #include <net/if_arp.h>
60 #include <net/if_media.h>
61 #include <net/if_vlan_var.h>
62 
63 #include <machine/bus.h>
64 
65 #include <dev/mii/mii.h>
66 #include <dev/mii/miivar.h>
67 
68 #include <dev/pci/pcireg.h>
69 #include <dev/pci/pcivar.h>
70 
71 #include <dev/et/if_etreg.h>
72 #include <dev/et/if_etvar.h>
73 
74 #include "miibus_if.h"
75 
76 MODULE_DEPEND(et, pci, 1, 1, 1);
77 MODULE_DEPEND(et, ether, 1, 1, 1);
78 MODULE_DEPEND(et, miibus, 1, 1, 1);
79 
80 /* Tunables. */
81 static int msi_disable = 0;
82 TUNABLE_INT("hw.et.msi_disable", &msi_disable);
83 
84 #define	ET_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
85 
86 static int	et_probe(device_t);
87 static int	et_attach(device_t);
88 static int	et_detach(device_t);
89 static int	et_shutdown(device_t);
90 
91 static int	et_miibus_readreg(device_t, int, int);
92 static int	et_miibus_writereg(device_t, int, int, int);
93 static void	et_miibus_statchg(device_t);
94 
95 static void	et_init_locked(struct et_softc *);
96 static void	et_init(void *);
97 static int	et_ioctl(struct ifnet *, u_long, caddr_t);
98 static void	et_start_locked(struct ifnet *);
99 static void	et_start(struct ifnet *);
100 static void	et_watchdog(struct et_softc *);
101 static int	et_ifmedia_upd_locked(struct ifnet *);
102 static int	et_ifmedia_upd(struct ifnet *);
103 static void	et_ifmedia_sts(struct ifnet *, struct ifmediareq *);
104 
105 static void	et_add_sysctls(struct et_softc *);
106 static int	et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS);
107 static int	et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS);
108 
109 static void	et_intr(void *);
110 static void	et_enable_intrs(struct et_softc *, uint32_t);
111 static void	et_disable_intrs(struct et_softc *);
112 static void	et_rxeof(struct et_softc *);
113 static void	et_txeof(struct et_softc *);
114 
115 static int	et_dma_alloc(device_t);
116 static void	et_dma_free(device_t);
117 static int	et_dma_mem_create(device_t, bus_size_t, bus_dma_tag_t *,
118 				  void **, bus_addr_t *, bus_dmamap_t *);
119 static void	et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t);
120 static int	et_dma_mbuf_create(device_t);
121 static void	et_dma_mbuf_destroy(device_t, int, const int[]);
122 static void	et_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
123 static void	et_dma_buf_addr(void *, bus_dma_segment_t *, int,
124 				bus_size_t, int);
125 static int	et_init_tx_ring(struct et_softc *);
126 static int	et_init_rx_ring(struct et_softc *);
127 static void	et_free_tx_ring(struct et_softc *);
128 static void	et_free_rx_ring(struct et_softc *);
129 static int	et_encap(struct et_softc *, struct mbuf **);
130 static int	et_newbuf(struct et_rxbuf_data *, int, int, int);
131 static int	et_newbuf_cluster(struct et_rxbuf_data *, int, int);
132 static int	et_newbuf_hdr(struct et_rxbuf_data *, int, int);
133 
134 static void	et_stop(struct et_softc *);
135 static int	et_chip_init(struct et_softc *);
136 static void	et_chip_attach(struct et_softc *);
137 static void	et_init_mac(struct et_softc *);
138 static void	et_init_rxmac(struct et_softc *);
139 static void	et_init_txmac(struct et_softc *);
140 static int	et_init_rxdma(struct et_softc *);
141 static int	et_init_txdma(struct et_softc *);
142 static int	et_start_rxdma(struct et_softc *);
143 static int	et_start_txdma(struct et_softc *);
144 static int	et_stop_rxdma(struct et_softc *);
145 static int	et_stop_txdma(struct et_softc *);
146 static int	et_enable_txrx(struct et_softc *, int);
147 static void	et_reset(struct et_softc *);
148 static int	et_bus_config(struct et_softc *);
149 static void	et_get_eaddr(device_t, uint8_t[]);
150 static void	et_setmulti(struct et_softc *);
151 static void	et_tick(void *);
152 static void	et_setmedia(struct et_softc *);
153 static void	et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t);
154 
155 static const struct et_dev {
156 	uint16_t	vid;
157 	uint16_t	did;
158 	const char	*desc;
159 } et_devices[] = {
160 	{ PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310,
161 	  "Agere ET1310 Gigabit Ethernet" },
162 	{ PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST,
163 	  "Agere ET1310 Fast Ethernet" },
164 	{ 0, 0, NULL }
165 };
166 
167 static device_method_t et_methods[] = {
168 	DEVMETHOD(device_probe,		et_probe),
169 	DEVMETHOD(device_attach,	et_attach),
170 	DEVMETHOD(device_detach,	et_detach),
171 	DEVMETHOD(device_shutdown,	et_shutdown),
172 
173 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
174 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
175 
176 	DEVMETHOD(miibus_readreg,	et_miibus_readreg),
177 	DEVMETHOD(miibus_writereg,	et_miibus_writereg),
178 	DEVMETHOD(miibus_statchg,	et_miibus_statchg),
179 
180 	{ 0, 0 }
181 };
182 
183 static driver_t et_driver = {
184 	"et",
185 	et_methods,
186 	sizeof(struct et_softc)
187 };
188 
189 static devclass_t et_devclass;
190 
191 DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0);
192 DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0);
193 
194 static int	et_rx_intr_npkts = 32;
195 static int	et_rx_intr_delay = 20;		/* x10 usec */
196 static int	et_tx_intr_nsegs = 126;
197 static uint32_t	et_timer = 1000 * 1000 * 1000;	/* nanosec */
198 
199 TUNABLE_INT("hw.et.timer", &et_timer);
200 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts);
201 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay);
202 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs);
203 
204 struct et_bsize {
205 	int		bufsize;
206 	et_newbuf_t	newbuf;
207 };
208 
209 static const struct et_bsize	et_bufsize_std[ET_RX_NRING] = {
210 	{ .bufsize = ET_RXDMA_CTRL_RING0_128,
211 	  .newbuf = et_newbuf_hdr },
212 	{ .bufsize = ET_RXDMA_CTRL_RING1_2048,
213 	  .newbuf = et_newbuf_cluster },
214 };
215 
216 static int
217 et_probe(device_t dev)
218 {
219 	const struct et_dev *d;
220 	uint16_t did, vid;
221 
222 	vid = pci_get_vendor(dev);
223 	did = pci_get_device(dev);
224 
225 	for (d = et_devices; d->desc != NULL; ++d) {
226 		if (vid == d->vid && did == d->did) {
227 			device_set_desc(dev, d->desc);
228 			return (0);
229 		}
230 	}
231 	return (ENXIO);
232 }
233 
234 static int
235 et_attach(device_t dev)
236 {
237 	struct et_softc *sc;
238 	struct ifnet *ifp;
239 	uint8_t eaddr[ETHER_ADDR_LEN];
240 	int cap, error, msic;
241 
242 	sc = device_get_softc(dev);
243 	sc->dev = dev;
244 	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
245 	    MTX_DEF);
246 
247 	ifp = sc->ifp = if_alloc(IFT_ETHER);
248 	if (ifp == NULL) {
249 		device_printf(dev, "can not if_alloc()\n");
250 		error = ENOSPC;
251 		goto fail;
252 	}
253 
254 	/*
255 	 * Initialize tunables
256 	 */
257 	sc->sc_rx_intr_npkts = et_rx_intr_npkts;
258 	sc->sc_rx_intr_delay = et_rx_intr_delay;
259 	sc->sc_tx_intr_nsegs = et_tx_intr_nsegs;
260 	sc->sc_timer = et_timer;
261 
262 	/* Enable bus mastering */
263 	pci_enable_busmaster(dev);
264 
265 	/*
266 	 * Allocate IO memory
267 	 */
268 	sc->sc_mem_rid = ET_PCIR_BAR;
269 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
270 						&sc->sc_mem_rid, RF_ACTIVE);
271 	if (sc->sc_mem_res == NULL) {
272 		device_printf(dev, "can't allocate IO memory\n");
273 		return (ENXIO);
274 	}
275 
276 	msic = 0;
277 	if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) {
278 		sc->sc_expcap = cap;
279 		sc->sc_flags |= ET_FLAG_PCIE;
280 		msic = pci_msi_count(dev);
281 		if (bootverbose)
282 			device_printf(dev, "MSI count: %d\n", msic);
283 	}
284 	if (msic > 0 && msi_disable == 0) {
285 		msic = 1;
286 		if (pci_alloc_msi(dev, &msic) == 0) {
287 			if (msic == 1) {
288 				device_printf(dev, "Using %d MSI message\n",
289 				    msic);
290 				sc->sc_flags |= ET_FLAG_MSI;
291 			} else
292 				pci_release_msi(dev);
293 		}
294 	}
295 
296 	/*
297 	 * Allocate IRQ
298 	 */
299 	if ((sc->sc_flags & ET_FLAG_MSI) == 0) {
300 		sc->sc_irq_rid = 0;
301 		sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
302 		    &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE);
303 	} else {
304 		sc->sc_irq_rid = 1;
305 		sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
306 		    &sc->sc_irq_rid, RF_ACTIVE);
307 	}
308 	if (sc->sc_irq_res == NULL) {
309 		device_printf(dev, "can't allocate irq\n");
310 		error = ENXIO;
311 		goto fail;
312 	}
313 
314 	error = et_bus_config(sc);
315 	if (error)
316 		goto fail;
317 
318 	et_get_eaddr(dev, eaddr);
319 
320 	CSR_WRITE_4(sc, ET_PM,
321 		    ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE);
322 
323 	et_reset(sc);
324 
325 	et_disable_intrs(sc);
326 
327 	error = et_dma_alloc(dev);
328 	if (error)
329 		goto fail;
330 
331 	ifp->if_softc = sc;
332 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
333 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
334 	ifp->if_init = et_init;
335 	ifp->if_ioctl = et_ioctl;
336 	ifp->if_start = et_start;
337 	ifp->if_mtu = ETHERMTU;
338 	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU;
339 	ifp->if_capenable = ifp->if_capabilities;
340 	IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC);
341 	IFQ_SET_READY(&ifp->if_snd);
342 
343 	et_chip_attach(sc);
344 
345 	error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd,
346 	    et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
347 	if (error) {
348 		device_printf(dev, "attaching PHYs failed\n");
349 		goto fail;
350 	}
351 
352 	ether_ifattach(ifp, eaddr);
353 	callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0);
354 
355 	error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE,
356 	    NULL, et_intr, sc, &sc->sc_irq_handle);
357 	if (error) {
358 		ether_ifdetach(ifp);
359 		device_printf(dev, "can't setup intr\n");
360 		goto fail;
361 	}
362 
363 	et_add_sysctls(sc);
364 
365 	return (0);
366 fail:
367 	et_detach(dev);
368 	return (error);
369 }
370 
371 static int
372 et_detach(device_t dev)
373 {
374 	struct et_softc *sc = device_get_softc(dev);
375 
376 	if (device_is_attached(dev)) {
377 		struct ifnet *ifp = sc->ifp;
378 
379 		ET_LOCK(sc);
380 		et_stop(sc);
381 		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
382 		ET_UNLOCK(sc);
383 
384 		ether_ifdetach(ifp);
385 	}
386 
387 	if (sc->sc_miibus != NULL)
388 		device_delete_child(dev, sc->sc_miibus);
389 	bus_generic_detach(dev);
390 
391 	if (sc->sc_irq_res != NULL) {
392 		bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
393 				     sc->sc_irq_res);
394 	}
395 	if ((sc->sc_flags & ET_FLAG_MSI) != 0)
396 		pci_release_msi(dev);
397 
398 	if (sc->sc_mem_res != NULL) {
399 		bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
400 				     sc->sc_mem_res);
401 	}
402 
403 	if (sc->ifp != NULL)
404 		if_free(sc->ifp);
405 
406 	et_dma_free(dev);
407 
408 	mtx_destroy(&sc->sc_mtx);
409 
410 	return (0);
411 }
412 
413 static int
414 et_shutdown(device_t dev)
415 {
416 	struct et_softc *sc = device_get_softc(dev);
417 
418 	ET_LOCK(sc);
419 	et_stop(sc);
420 	ET_UNLOCK(sc);
421 	return (0);
422 }
423 
424 static int
425 et_miibus_readreg(device_t dev, int phy, int reg)
426 {
427 	struct et_softc *sc = device_get_softc(dev);
428 	uint32_t val;
429 	int i, ret;
430 
431 	/* Stop any pending operations */
432 	CSR_WRITE_4(sc, ET_MII_CMD, 0);
433 
434 	val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK;
435 	val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK;
436 	CSR_WRITE_4(sc, ET_MII_ADDR, val);
437 
438 	/* Start reading */
439 	CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ);
440 
441 #define NRETRY	50
442 
443 	for (i = 0; i < NRETRY; ++i) {
444 		val = CSR_READ_4(sc, ET_MII_IND);
445 		if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0)
446 			break;
447 		DELAY(50);
448 	}
449 	if (i == NRETRY) {
450 		if_printf(sc->ifp,
451 			  "read phy %d, reg %d timed out\n", phy, reg);
452 		ret = 0;
453 		goto back;
454 	}
455 
456 #undef NRETRY
457 
458 	val = CSR_READ_4(sc, ET_MII_STAT);
459 	ret = val & ET_MII_STAT_VALUE_MASK;
460 
461 back:
462 	/* Make sure that the current operation is stopped */
463 	CSR_WRITE_4(sc, ET_MII_CMD, 0);
464 	return (ret);
465 }
466 
467 static int
468 et_miibus_writereg(device_t dev, int phy, int reg, int val0)
469 {
470 	struct et_softc *sc = device_get_softc(dev);
471 	uint32_t val;
472 	int i;
473 
474 	/* Stop any pending operations */
475 	CSR_WRITE_4(sc, ET_MII_CMD, 0);
476 
477 	val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK;
478 	val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK;
479 	CSR_WRITE_4(sc, ET_MII_ADDR, val);
480 
481 	/* Start writing */
482 	CSR_WRITE_4(sc, ET_MII_CTRL,
483 	    (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK);
484 
485 #define NRETRY 100
486 
487 	for (i = 0; i < NRETRY; ++i) {
488 		val = CSR_READ_4(sc, ET_MII_IND);
489 		if ((val & ET_MII_IND_BUSY) == 0)
490 			break;
491 		DELAY(50);
492 	}
493 	if (i == NRETRY) {
494 		if_printf(sc->ifp,
495 			  "write phy %d, reg %d timed out\n", phy, reg);
496 		et_miibus_readreg(dev, phy, reg);
497 	}
498 
499 #undef NRETRY
500 
501 	/* Make sure that the current operation is stopped */
502 	CSR_WRITE_4(sc, ET_MII_CMD, 0);
503 	return (0);
504 }
505 
506 static void
507 et_miibus_statchg(device_t dev)
508 {
509 	et_setmedia(device_get_softc(dev));
510 }
511 
512 static int
513 et_ifmedia_upd_locked(struct ifnet *ifp)
514 {
515 	struct et_softc *sc = ifp->if_softc;
516 	struct mii_data *mii = device_get_softc(sc->sc_miibus);
517 	struct mii_softc *miisc;
518 
519 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
520 		PHY_RESET(miisc);
521 	return (mii_mediachg(mii));
522 }
523 
524 static int
525 et_ifmedia_upd(struct ifnet *ifp)
526 {
527 	struct et_softc *sc = ifp->if_softc;
528 	int res;
529 
530 	ET_LOCK(sc);
531 	res = et_ifmedia_upd_locked(ifp);
532 	ET_UNLOCK(sc);
533 
534 	return (res);
535 }
536 
537 static void
538 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
539 {
540 	struct et_softc *sc = ifp->if_softc;
541 	struct mii_data *mii = device_get_softc(sc->sc_miibus);
542 
543 	ET_LOCK(sc);
544 	mii_pollstat(mii);
545 	ifmr->ifm_active = mii->mii_media_active;
546 	ifmr->ifm_status = mii->mii_media_status;
547 	ET_UNLOCK(sc);
548 }
549 
550 static void
551 et_stop(struct et_softc *sc)
552 {
553 	struct ifnet *ifp = sc->ifp;
554 
555 	ET_LOCK_ASSERT(sc);
556 
557 	callout_stop(&sc->sc_tick);
558 
559 	et_stop_rxdma(sc);
560 	et_stop_txdma(sc);
561 
562 	et_disable_intrs(sc);
563 
564 	et_free_tx_ring(sc);
565 	et_free_rx_ring(sc);
566 
567 	et_reset(sc);
568 
569 	sc->sc_tx = 0;
570 	sc->sc_tx_intr = 0;
571 	sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED;
572 
573 	sc->watchdog_timer = 0;
574 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
575 }
576 
577 static int
578 et_bus_config(struct et_softc *sc)
579 {
580 	uint32_t val, max_plsz;
581 	uint16_t ack_latency, replay_timer;
582 
583 	/*
584 	 * Test whether EEPROM is valid
585 	 * NOTE: Read twice to get the correct value
586 	 */
587 	pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1);
588 	val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1);
589 	if (val & ET_PCIM_EEPROM_STATUS_ERROR) {
590 		device_printf(sc->dev, "EEPROM status error 0x%02x\n", val);
591 		return (ENXIO);
592 	}
593 
594 	/* TODO: LED */
595 
596 	if ((sc->sc_flags & ET_FLAG_PCIE) == 0)
597 		return (0);
598 
599 	/*
600 	 * Configure ACK latency and replay timer according to
601 	 * max playload size
602 	 */
603 	val = pci_read_config(sc->dev,
604 	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CAP, 4);
605 	max_plsz = val & PCIM_EXP_CAP_MAX_PAYLOAD;
606 
607 	switch (max_plsz) {
608 	case ET_PCIV_DEVICE_CAPS_PLSZ_128:
609 		ack_latency = ET_PCIV_ACK_LATENCY_128;
610 		replay_timer = ET_PCIV_REPLAY_TIMER_128;
611 		break;
612 
613 	case ET_PCIV_DEVICE_CAPS_PLSZ_256:
614 		ack_latency = ET_PCIV_ACK_LATENCY_256;
615 		replay_timer = ET_PCIV_REPLAY_TIMER_256;
616 		break;
617 
618 	default:
619 		ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2);
620 		replay_timer = pci_read_config(sc->dev,
621 		    ET_PCIR_REPLAY_TIMER, 2);
622 		device_printf(sc->dev, "ack latency %u, replay timer %u\n",
623 			      ack_latency, replay_timer);
624 		break;
625 	}
626 	if (ack_latency != 0) {
627 		pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2);
628 		pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer,
629 		    2);
630 	}
631 
632 	/*
633 	 * Set L0s and L1 latency timer to 2us
634 	 */
635 	val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4);
636 	val &= ~(PCIM_LINK_CAP_L0S_EXIT | PCIM_LINK_CAP_L1_EXIT);
637 	/* L0s exit latency : 2us */
638 	val |= 0x00005000;
639 	/* L1 exit latency : 2us */
640 	val |= 0x00028000;
641 	pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4);
642 
643 	/*
644 	 * Set max read request size to 2048 bytes
645 	 */
646 	val = pci_read_config(sc->dev,
647 	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
648 	val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
649 	val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K;
650 	pci_write_config(sc->dev,
651 	    sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, val, 2);
652 
653 	return (0);
654 }
655 
656 static void
657 et_get_eaddr(device_t dev, uint8_t eaddr[])
658 {
659 	uint32_t val;
660 	int i;
661 
662 	val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4);
663 	for (i = 0; i < 4; ++i)
664 		eaddr[i] = (val >> (8 * i)) & 0xff;
665 
666 	val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2);
667 	for (; i < ETHER_ADDR_LEN; ++i)
668 		eaddr[i] = (val >> (8 * (i - 4))) & 0xff;
669 }
670 
671 static void
672 et_reset(struct et_softc *sc)
673 {
674 	CSR_WRITE_4(sc, ET_MAC_CFG1,
675 		    ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
676 		    ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
677 		    ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
678 
679 	CSR_WRITE_4(sc, ET_SWRST,
680 		    ET_SWRST_TXDMA | ET_SWRST_RXDMA |
681 		    ET_SWRST_TXMAC | ET_SWRST_RXMAC |
682 		    ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC);
683 
684 	CSR_WRITE_4(sc, ET_MAC_CFG1,
685 		    ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
686 		    ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC);
687 	CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
688 }
689 
690 static void
691 et_disable_intrs(struct et_softc *sc)
692 {
693 	CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
694 }
695 
696 static void
697 et_enable_intrs(struct et_softc *sc, uint32_t intrs)
698 {
699 	CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs);
700 }
701 
702 static int
703 et_dma_alloc(device_t dev)
704 {
705 	struct et_softc *sc = device_get_softc(dev);
706 	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
707 	struct et_txstatus_data *txsd = &sc->sc_tx_status;
708 	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
709 	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
710 	int i, error;
711 
712 	/*
713 	 * Create top level DMA tag
714 	 */
715 	error = bus_dma_tag_create(NULL, 1, 0,
716 				   BUS_SPACE_MAXADDR_32BIT,
717 				   BUS_SPACE_MAXADDR,
718 				   NULL, NULL,
719 				   MAXBSIZE,
720 				   BUS_SPACE_UNRESTRICTED,
721 				   BUS_SPACE_MAXSIZE_32BIT,
722 				   0, NULL, NULL, &sc->sc_dtag);
723 	if (error) {
724 		device_printf(dev, "can't create DMA tag\n");
725 		return (error);
726 	}
727 
728 	/*
729 	 * Create TX ring DMA stuffs
730 	 */
731 	error = et_dma_mem_create(dev, ET_TX_RING_SIZE, &tx_ring->tr_dtag,
732 				  (void **)&tx_ring->tr_desc,
733 				  &tx_ring->tr_paddr, &tx_ring->tr_dmap);
734 	if (error) {
735 		device_printf(dev, "can't create TX ring DMA stuffs\n");
736 		return (error);
737 	}
738 
739 	/*
740 	 * Create TX status DMA stuffs
741 	 */
742 	error = et_dma_mem_create(dev, sizeof(uint32_t), &txsd->txsd_dtag,
743 				  (void **)&txsd->txsd_status,
744 				  &txsd->txsd_paddr, &txsd->txsd_dmap);
745 	if (error) {
746 		device_printf(dev, "can't create TX status DMA stuffs\n");
747 		return (error);
748 	}
749 
750 	/*
751 	 * Create DMA stuffs for RX rings
752 	 */
753 	for (i = 0; i < ET_RX_NRING; ++i) {
754 		static const uint32_t rx_ring_posreg[ET_RX_NRING] =
755 		{ ET_RX_RING0_POS, ET_RX_RING1_POS };
756 
757 		struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
758 
759 		error = et_dma_mem_create(dev, ET_RX_RING_SIZE,
760 					  &rx_ring->rr_dtag,
761 					  (void **)&rx_ring->rr_desc,
762 					  &rx_ring->rr_paddr,
763 					  &rx_ring->rr_dmap);
764 		if (error) {
765 			device_printf(dev, "can't create DMA stuffs for "
766 				      "the %d RX ring\n", i);
767 			return (error);
768 		}
769 		rx_ring->rr_posreg = rx_ring_posreg[i];
770 	}
771 
772 	/*
773 	 * Create RX stat ring DMA stuffs
774 	 */
775 	error = et_dma_mem_create(dev, ET_RXSTAT_RING_SIZE,
776 				  &rxst_ring->rsr_dtag,
777 				  (void **)&rxst_ring->rsr_stat,
778 				  &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap);
779 	if (error) {
780 		device_printf(dev, "can't create RX stat ring DMA stuffs\n");
781 		return (error);
782 	}
783 
784 	/*
785 	 * Create RX status DMA stuffs
786 	 */
787 	error = et_dma_mem_create(dev, sizeof(struct et_rxstatus),
788 				  &rxsd->rxsd_dtag,
789 				  (void **)&rxsd->rxsd_status,
790 				  &rxsd->rxsd_paddr, &rxsd->rxsd_dmap);
791 	if (error) {
792 		device_printf(dev, "can't create RX status DMA stuffs\n");
793 		return (error);
794 	}
795 
796 	/*
797 	 * Create mbuf DMA stuffs
798 	 */
799 	error = et_dma_mbuf_create(dev);
800 	if (error)
801 		return (error);
802 
803 	return (0);
804 }
805 
806 static void
807 et_dma_free(device_t dev)
808 {
809 	struct et_softc *sc = device_get_softc(dev);
810 	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
811 	struct et_txstatus_data *txsd = &sc->sc_tx_status;
812 	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
813 	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
814 	int i, rx_done[ET_RX_NRING];
815 
816 	/*
817 	 * Destroy TX ring DMA stuffs
818 	 */
819 	et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc,
820 			   tx_ring->tr_dmap);
821 
822 	/*
823 	 * Destroy TX status DMA stuffs
824 	 */
825 	et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status,
826 			   txsd->txsd_dmap);
827 
828 	/*
829 	 * Destroy DMA stuffs for RX rings
830 	 */
831 	for (i = 0; i < ET_RX_NRING; ++i) {
832 		struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
833 
834 		et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc,
835 				   rx_ring->rr_dmap);
836 	}
837 
838 	/*
839 	 * Destroy RX stat ring DMA stuffs
840 	 */
841 	et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat,
842 			   rxst_ring->rsr_dmap);
843 
844 	/*
845 	 * Destroy RX status DMA stuffs
846 	 */
847 	et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status,
848 			   rxsd->rxsd_dmap);
849 
850 	/*
851 	 * Destroy mbuf DMA stuffs
852 	 */
853 	for (i = 0; i < ET_RX_NRING; ++i)
854 		rx_done[i] = ET_RX_NDESC;
855 	et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done);
856 
857 	/*
858 	 * Destroy top level DMA tag
859 	 */
860 	if (sc->sc_dtag != NULL)
861 		bus_dma_tag_destroy(sc->sc_dtag);
862 }
863 
864 static int
865 et_dma_mbuf_create(device_t dev)
866 {
867 	struct et_softc *sc = device_get_softc(dev);
868 	struct et_txbuf_data *tbd = &sc->sc_tx_data;
869 	int i, error, rx_done[ET_RX_NRING];
870 
871 	/*
872 	 * Create mbuf DMA tag
873 	 */
874 	error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
875 				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
876 				   NULL, NULL,
877 				   ET_JUMBO_FRAMELEN, ET_NSEG_MAX,
878 				   BUS_SPACE_MAXSIZE_32BIT,
879 				   BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_mbuf_dtag);
880 	if (error) {
881 		device_printf(dev, "can't create mbuf DMA tag\n");
882 		return (error);
883 	}
884 
885 	/*
886 	 * Create spare DMA map for RX mbufs
887 	 */
888 	error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, &sc->sc_mbuf_tmp_dmap);
889 	if (error) {
890 		device_printf(dev, "can't create spare mbuf DMA map\n");
891 		bus_dma_tag_destroy(sc->sc_mbuf_dtag);
892 		sc->sc_mbuf_dtag = NULL;
893 		return (error);
894 	}
895 
896 	/*
897 	 * Create DMA maps for RX mbufs
898 	 */
899 	bzero(rx_done, sizeof(rx_done));
900 	for (i = 0; i < ET_RX_NRING; ++i) {
901 		struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
902 		int j;
903 
904 		for (j = 0; j < ET_RX_NDESC; ++j) {
905 			error = bus_dmamap_create(sc->sc_mbuf_dtag, 0,
906 				&rbd->rbd_buf[j].rb_dmap);
907 			if (error) {
908 				device_printf(dev, "can't create %d RX mbuf "
909 					      "for %d RX ring\n", j, i);
910 				rx_done[i] = j;
911 				et_dma_mbuf_destroy(dev, 0, rx_done);
912 				return (error);
913 			}
914 		}
915 		rx_done[i] = ET_RX_NDESC;
916 
917 		rbd->rbd_softc = sc;
918 		rbd->rbd_ring = &sc->sc_rx_ring[i];
919 	}
920 
921 	/*
922 	 * Create DMA maps for TX mbufs
923 	 */
924 	for (i = 0; i < ET_TX_NDESC; ++i) {
925 		error = bus_dmamap_create(sc->sc_mbuf_dtag, 0,
926 					  &tbd->tbd_buf[i].tb_dmap);
927 		if (error) {
928 			device_printf(dev, "can't create %d TX mbuf "
929 				      "DMA map\n", i);
930 			et_dma_mbuf_destroy(dev, i, rx_done);
931 			return (error);
932 		}
933 	}
934 
935 	return (0);
936 }
937 
938 static void
939 et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[])
940 {
941 	struct et_softc *sc = device_get_softc(dev);
942 	struct et_txbuf_data *tbd = &sc->sc_tx_data;
943 	int i;
944 
945 	if (sc->sc_mbuf_dtag == NULL)
946 		return;
947 
948 	/*
949 	 * Destroy DMA maps for RX mbufs
950 	 */
951 	for (i = 0; i < ET_RX_NRING; ++i) {
952 		struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
953 		int j;
954 
955 		for (j = 0; j < rx_done[i]; ++j) {
956 			struct et_rxbuf *rb = &rbd->rbd_buf[j];
957 
958 			KASSERT(rb->rb_mbuf == NULL,
959 			    ("RX mbuf in %d RX ring is not freed yet\n", i));
960 			bus_dmamap_destroy(sc->sc_mbuf_dtag, rb->rb_dmap);
961 		}
962 	}
963 
964 	/*
965 	 * Destroy DMA maps for TX mbufs
966 	 */
967 	for (i = 0; i < tx_done; ++i) {
968 		struct et_txbuf *tb = &tbd->tbd_buf[i];
969 
970 		KASSERT(tb->tb_mbuf == NULL, ("TX mbuf is not freed yet\n"));
971 		bus_dmamap_destroy(sc->sc_mbuf_dtag, tb->tb_dmap);
972 	}
973 
974 	/*
975 	 * Destroy spare mbuf DMA map
976 	 */
977 	bus_dmamap_destroy(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap);
978 
979 	/*
980 	 * Destroy mbuf DMA tag
981 	 */
982 	bus_dma_tag_destroy(sc->sc_mbuf_dtag);
983 	sc->sc_mbuf_dtag = NULL;
984 }
985 
986 static int
987 et_dma_mem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag,
988 		  void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap)
989 {
990 	struct et_softc *sc = device_get_softc(dev);
991 	int error;
992 
993 	error = bus_dma_tag_create(sc->sc_dtag, ET_ALIGN, 0,
994 				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
995 				   NULL, NULL,
996 				   size, 1, BUS_SPACE_MAXSIZE_32BIT,
997 				   0, NULL, NULL, dtag);
998 	if (error) {
999 		device_printf(dev, "can't create DMA tag\n");
1000 		return (error);
1001 	}
1002 
1003 	error = bus_dmamem_alloc(*dtag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1004 				 dmap);
1005 	if (error) {
1006 		device_printf(dev, "can't allocate DMA mem\n");
1007 		bus_dma_tag_destroy(*dtag);
1008 		*dtag = NULL;
1009 		return (error);
1010 	}
1011 
1012 	error = bus_dmamap_load(*dtag, *dmap, *addr, size,
1013 				et_dma_ring_addr, paddr, BUS_DMA_WAITOK);
1014 	if (error) {
1015 		device_printf(dev, "can't load DMA mem\n");
1016 		bus_dmamem_free(*dtag, *addr, *dmap);
1017 		bus_dma_tag_destroy(*dtag);
1018 		*dtag = NULL;
1019 		return (error);
1020 	}
1021 	return (0);
1022 }
1023 
1024 static void
1025 et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap)
1026 {
1027 	if (dtag != NULL) {
1028 		bus_dmamap_unload(dtag, dmap);
1029 		bus_dmamem_free(dtag, addr, dmap);
1030 		bus_dma_tag_destroy(dtag);
1031 	}
1032 }
1033 
1034 static void
1035 et_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
1036 {
1037 	KASSERT(nseg == 1, ("too many segments\n"));
1038 	*((bus_addr_t *)arg) = seg->ds_addr;
1039 }
1040 
1041 static void
1042 et_chip_attach(struct et_softc *sc)
1043 {
1044 	uint32_t val;
1045 
1046 	/*
1047 	 * Perform minimal initialization
1048 	 */
1049 
1050 	/* Disable loopback */
1051 	CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1052 
1053 	/* Reset MAC */
1054 	CSR_WRITE_4(sc, ET_MAC_CFG1,
1055 		    ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1056 		    ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1057 		    ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1058 
1059 	/*
1060 	 * Setup half duplex mode
1061 	 */
1062 	val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) |
1063 	    (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) |
1064 	    (55 << ET_MAC_HDX_COLLWIN_SHIFT) |
1065 	    ET_MAC_HDX_EXC_DEFER;
1066 	CSR_WRITE_4(sc, ET_MAC_HDX, val);
1067 
1068 	/* Clear MAC control */
1069 	CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1070 
1071 	/* Reset MII */
1072 	CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1073 
1074 	/* Bring MAC out of reset state */
1075 	CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1076 
1077 	/* Enable memory controllers */
1078 	CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1079 }
1080 
1081 static void
1082 et_intr(void *xsc)
1083 {
1084 	struct et_softc *sc = xsc;
1085 	struct ifnet *ifp;
1086 	uint32_t intrs;
1087 
1088 	ET_LOCK(sc);
1089 	ifp = sc->ifp;
1090 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1091 		ET_UNLOCK(sc);
1092 		return;
1093 	}
1094 
1095 	et_disable_intrs(sc);
1096 
1097 	intrs = CSR_READ_4(sc, ET_INTR_STATUS);
1098 	intrs &= ET_INTRS;
1099 	if (intrs == 0)	/* Not interested */
1100 		goto back;
1101 
1102 	if (intrs & ET_INTR_RXEOF)
1103 		et_rxeof(sc);
1104 	if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER))
1105 		et_txeof(sc);
1106 	if (intrs & ET_INTR_TIMER)
1107 		CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1108 back:
1109 	et_enable_intrs(sc, ET_INTRS);
1110 	ET_UNLOCK(sc);
1111 }
1112 
1113 static void
1114 et_init_locked(struct et_softc *sc)
1115 {
1116 	struct ifnet *ifp = sc->ifp;
1117 	const struct et_bsize *arr;
1118 	int error, i;
1119 
1120 	ET_LOCK_ASSERT(sc);
1121 
1122 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1123 		return;
1124 
1125 	et_stop(sc);
1126 
1127 	arr = et_bufsize_std;
1128 	for (i = 0; i < ET_RX_NRING; ++i) {
1129 		sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize;
1130 		sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf;
1131 	}
1132 
1133 	error = et_init_tx_ring(sc);
1134 	if (error)
1135 		goto back;
1136 
1137 	error = et_init_rx_ring(sc);
1138 	if (error)
1139 		goto back;
1140 
1141 	error = et_chip_init(sc);
1142 	if (error)
1143 		goto back;
1144 
1145 	error = et_enable_txrx(sc, 1);
1146 	if (error)
1147 		goto back;
1148 
1149 	et_enable_intrs(sc, ET_INTRS);
1150 
1151 	callout_reset(&sc->sc_tick, hz, et_tick, sc);
1152 
1153 	CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1154 
1155 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1156 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1157 back:
1158 	if (error)
1159 		et_stop(sc);
1160 }
1161 
1162 static void
1163 et_init(void *xsc)
1164 {
1165 	struct et_softc *sc = xsc;
1166 
1167 	ET_LOCK(sc);
1168 	et_init_locked(sc);
1169 	ET_UNLOCK(sc);
1170 }
1171 
1172 static int
1173 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1174 {
1175 	struct et_softc *sc = ifp->if_softc;
1176 	struct mii_data *mii = device_get_softc(sc->sc_miibus);
1177 	struct ifreq *ifr = (struct ifreq *)data;
1178 	int error = 0, mask, max_framelen;
1179 
1180 /* XXX LOCKSUSED */
1181 	switch (cmd) {
1182 	case SIOCSIFFLAGS:
1183 		ET_LOCK(sc);
1184 		if (ifp->if_flags & IFF_UP) {
1185 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1186 				if ((ifp->if_flags ^ sc->sc_if_flags) &
1187 				(IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST))
1188 					et_setmulti(sc);
1189 			} else {
1190 				et_init_locked(sc);
1191 			}
1192 		} else {
1193 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1194 				et_stop(sc);
1195 		}
1196 		sc->sc_if_flags = ifp->if_flags;
1197 		ET_UNLOCK(sc);
1198 		break;
1199 
1200 	case SIOCSIFMEDIA:
1201 	case SIOCGIFMEDIA:
1202 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1203 		break;
1204 
1205 	case SIOCADDMULTI:
1206 	case SIOCDELMULTI:
1207 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1208 			ET_LOCK(sc);
1209 			et_setmulti(sc);
1210 			ET_UNLOCK(sc);
1211 			error = 0;
1212 		}
1213 		break;
1214 
1215 	case SIOCSIFMTU:
1216 #if 0
1217 		if (sc->sc_flags & ET_FLAG_JUMBO)
1218 			max_framelen = ET_JUMBO_FRAMELEN;
1219 		else
1220 #endif
1221 			max_framelen = MCLBYTES - 1;
1222 
1223 		if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) {
1224 			error = EOPNOTSUPP;
1225 			break;
1226 		}
1227 
1228 		if (ifp->if_mtu != ifr->ifr_mtu) {
1229 			ifp->if_mtu = ifr->ifr_mtu;
1230 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1231 			et_init(sc);
1232 		}
1233 		break;
1234 
1235 	case SIOCSIFCAP:
1236 		ET_LOCK(sc);
1237 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1238 		if ((mask & IFCAP_TXCSUM) != 0 &&
1239 		    (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1240 			ifp->if_capenable ^= IFCAP_TXCSUM;
1241 			if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
1242 				ifp->if_hwassist |= ET_CSUM_FEATURES;
1243 			else
1244 				ifp->if_hwassist &= ~ET_CSUM_FEATURES;
1245 		}
1246 		ET_UNLOCK(sc);
1247 		break;
1248 
1249 	default:
1250 		error = ether_ioctl(ifp, cmd, data);
1251 		break;
1252 	}
1253 	return (error);
1254 }
1255 
1256 static void
1257 et_start_locked(struct ifnet *ifp)
1258 {
1259 	struct et_softc *sc = ifp->if_softc;
1260 	struct et_txbuf_data *tbd;
1261 	int trans;
1262 
1263 	ET_LOCK_ASSERT(sc);
1264 	tbd = &sc->sc_tx_data;
1265 
1266 	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
1267 		return;
1268 
1269 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING)
1270 		return;
1271 
1272 	trans = 0;
1273 	for (;;) {
1274 		struct mbuf *m;
1275 
1276 		if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) {
1277 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1278 			break;
1279 		}
1280 
1281 		IFQ_DEQUEUE(&ifp->if_snd, m);
1282 		if (m == NULL)
1283 			break;
1284 
1285 		if (et_encap(sc, &m)) {
1286 			ifp->if_oerrors++;
1287 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1288 			break;
1289 		}
1290 		trans = 1;
1291 
1292 		BPF_MTAP(ifp, m);
1293 	}
1294 
1295 	if (trans)
1296 		sc->watchdog_timer = 5;
1297 }
1298 
1299 static void
1300 et_start(struct ifnet *ifp)
1301 {
1302 	struct et_softc *sc = ifp->if_softc;
1303 
1304 	ET_LOCK(sc);
1305 	et_start_locked(ifp);
1306 	ET_UNLOCK(sc);
1307 }
1308 
1309 static void
1310 et_watchdog(struct et_softc *sc)
1311 {
1312 	ET_LOCK_ASSERT(sc);
1313 
1314 	if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
1315 		return;
1316 
1317 	if_printf(sc->ifp, "watchdog timed out\n");
1318 
1319 	sc->ifp->if_oerrors++;
1320 	sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1321 	et_init_locked(sc);
1322 	et_start_locked(sc->ifp);
1323 }
1324 
1325 static int
1326 et_stop_rxdma(struct et_softc *sc)
1327 {
1328 	CSR_WRITE_4(sc, ET_RXDMA_CTRL,
1329 		    ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE);
1330 
1331 	DELAY(5);
1332 	if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {
1333 		if_printf(sc->ifp, "can't stop RX DMA engine\n");
1334 		return (ETIMEDOUT);
1335 	}
1336 	return (0);
1337 }
1338 
1339 static int
1340 et_stop_txdma(struct et_softc *sc)
1341 {
1342 	CSR_WRITE_4(sc, ET_TXDMA_CTRL,
1343 		    ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT);
1344 	return (0);
1345 }
1346 
1347 static void
1348 et_free_tx_ring(struct et_softc *sc)
1349 {
1350 	struct et_txbuf_data *tbd = &sc->sc_tx_data;
1351 	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1352 	int i;
1353 
1354 	for (i = 0; i < ET_TX_NDESC; ++i) {
1355 		struct et_txbuf *tb = &tbd->tbd_buf[i];
1356 
1357 		if (tb->tb_mbuf != NULL) {
1358 			bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap);
1359 			m_freem(tb->tb_mbuf);
1360 			tb->tb_mbuf = NULL;
1361 		}
1362 	}
1363 
1364 	bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1365 	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
1366 			BUS_DMASYNC_PREWRITE);
1367 }
1368 
1369 static void
1370 et_free_rx_ring(struct et_softc *sc)
1371 {
1372 	int n;
1373 
1374 	for (n = 0; n < ET_RX_NRING; ++n) {
1375 		struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1376 		struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n];
1377 		int i;
1378 
1379 		for (i = 0; i < ET_RX_NDESC; ++i) {
1380 			struct et_rxbuf *rb = &rbd->rbd_buf[i];
1381 
1382 			if (rb->rb_mbuf != NULL) {
1383 				bus_dmamap_unload(sc->sc_mbuf_dtag,
1384 			  	    rb->rb_dmap);
1385 				m_freem(rb->rb_mbuf);
1386 				rb->rb_mbuf = NULL;
1387 			}
1388 		}
1389 
1390 		bzero(rx_ring->rr_desc, ET_RX_RING_SIZE);
1391 		bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap,
1392 				BUS_DMASYNC_PREWRITE);
1393 	}
1394 }
1395 
1396 static void
1397 et_setmulti(struct et_softc *sc)
1398 {
1399 	struct ifnet *ifp;
1400 	uint32_t hash[4] = { 0, 0, 0, 0 };
1401 	uint32_t rxmac_ctrl, pktfilt;
1402 	struct ifmultiaddr *ifma;
1403 	int i, count;
1404 
1405 	ET_LOCK_ASSERT(sc);
1406 	ifp = sc->ifp;
1407 
1408 	pktfilt = CSR_READ_4(sc, ET_PKTFILT);
1409 	rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL);
1410 
1411 	pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST);
1412 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1413 		rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT;
1414 		goto back;
1415 	}
1416 
1417 	count = 0;
1418 	if_maddr_rlock(ifp);
1419 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1420 		uint32_t *hp, h;
1421 
1422 		if (ifma->ifma_addr->sa_family != AF_LINK)
1423 			continue;
1424 
1425 		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1426 				   ifma->ifma_addr), ETHER_ADDR_LEN);
1427 		h = (h & 0x3f800000) >> 23;
1428 
1429 		hp = &hash[0];
1430 		if (h >= 32 && h < 64) {
1431 			h -= 32;
1432 			hp = &hash[1];
1433 		} else if (h >= 64 && h < 96) {
1434 			h -= 64;
1435 			hp = &hash[2];
1436 		} else if (h >= 96) {
1437 			h -= 96;
1438 			hp = &hash[3];
1439 		}
1440 		*hp |= (1 << h);
1441 
1442 		++count;
1443 	}
1444 	if_maddr_runlock(ifp);
1445 
1446 	for (i = 0; i < 4; ++i)
1447 		CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]);
1448 
1449 	if (count > 0)
1450 		pktfilt |= ET_PKTFILT_MCAST;
1451 	rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT;
1452 back:
1453 	CSR_WRITE_4(sc, ET_PKTFILT, pktfilt);
1454 	CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl);
1455 }
1456 
1457 static int
1458 et_chip_init(struct et_softc *sc)
1459 {
1460 	struct ifnet *ifp = sc->ifp;
1461 	uint32_t rxq_end;
1462 	int error, frame_len, rxmem_size;
1463 
1464 	/*
1465 	 * Split 16Kbytes internal memory between TX and RX
1466 	 * according to frame length.
1467 	 */
1468 	frame_len = ET_FRAMELEN(ifp->if_mtu);
1469 	if (frame_len < 2048) {
1470 		rxmem_size = ET_MEM_RXSIZE_DEFAULT;
1471 	} else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) {
1472 		rxmem_size = ET_MEM_SIZE / 2;
1473 	} else {
1474 		rxmem_size = ET_MEM_SIZE -
1475 		roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT);
1476 	}
1477 	rxq_end = ET_QUEUE_ADDR(rxmem_size);
1478 
1479 	CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START);
1480 	CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end);
1481 	CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1);
1482 	CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END);
1483 
1484 	/* No loopback */
1485 	CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1486 
1487 	/* Clear MSI configure */
1488 	if ((sc->sc_flags & ET_FLAG_MSI) == 0)
1489 		CSR_WRITE_4(sc, ET_MSI_CFG, 0);
1490 
1491 	/* Disable timer */
1492 	CSR_WRITE_4(sc, ET_TIMER, 0);
1493 
1494 	/* Initialize MAC */
1495 	et_init_mac(sc);
1496 
1497 	/* Enable memory controllers */
1498 	CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1499 
1500 	/* Initialize RX MAC */
1501 	et_init_rxmac(sc);
1502 
1503 	/* Initialize TX MAC */
1504 	et_init_txmac(sc);
1505 
1506 	/* Initialize RX DMA engine */
1507 	error = et_init_rxdma(sc);
1508 	if (error)
1509 		return (error);
1510 
1511 	/* Initialize TX DMA engine */
1512 	error = et_init_txdma(sc);
1513 	if (error)
1514 		return (error);
1515 
1516 	return (0);
1517 }
1518 
1519 static int
1520 et_init_tx_ring(struct et_softc *sc)
1521 {
1522 	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1523 	struct et_txstatus_data *txsd = &sc->sc_tx_status;
1524 	struct et_txbuf_data *tbd = &sc->sc_tx_data;
1525 
1526 	bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1527 	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
1528 			BUS_DMASYNC_PREWRITE);
1529 
1530 	tbd->tbd_start_index = 0;
1531 	tbd->tbd_start_wrap = 0;
1532 	tbd->tbd_used = 0;
1533 
1534 	bzero(txsd->txsd_status, sizeof(uint32_t));
1535 	bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap,
1536 			BUS_DMASYNC_PREWRITE);
1537 	return (0);
1538 }
1539 
1540 static int
1541 et_init_rx_ring(struct et_softc *sc)
1542 {
1543 	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1544 	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1545 	int n;
1546 
1547 	for (n = 0; n < ET_RX_NRING; ++n) {
1548 		struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1549 		int i, error;
1550 
1551 		for (i = 0; i < ET_RX_NDESC; ++i) {
1552 			error = rbd->rbd_newbuf(rbd, i, 1);
1553 			if (error) {
1554 				if_printf(sc->ifp, "%d ring %d buf, "
1555 					  "newbuf failed: %d\n", n, i, error);
1556 				return (error);
1557 			}
1558 		}
1559 	}
1560 
1561 	bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus));
1562 	bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap,
1563 			BUS_DMASYNC_PREWRITE);
1564 
1565 	bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE);
1566 	bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap,
1567 			BUS_DMASYNC_PREWRITE);
1568 
1569 	return (0);
1570 }
1571 
1572 static void
1573 et_dma_buf_addr(void *xctx, bus_dma_segment_t *segs, int nsegs,
1574 		bus_size_t mapsz __unused, int error)
1575 {
1576 	struct et_dmamap_ctx *ctx = xctx;
1577 	int i;
1578 
1579 	if (error)
1580 		return;
1581 
1582 	if (nsegs > ctx->nsegs) {
1583 		ctx->nsegs = 0;
1584 		return;
1585 	}
1586 
1587 	ctx->nsegs = nsegs;
1588 	for (i = 0; i < nsegs; ++i)
1589 		ctx->segs[i] = segs[i];
1590 }
1591 
1592 static int
1593 et_init_rxdma(struct et_softc *sc)
1594 {
1595 	struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1596 	struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1597 	struct et_rxdesc_ring *rx_ring;
1598 	int error;
1599 
1600 	error = et_stop_rxdma(sc);
1601 	if (error) {
1602 		if_printf(sc->ifp, "can't init RX DMA engine\n");
1603 		return (error);
1604 	}
1605 
1606 	/*
1607 	 * Install RX status
1608 	 */
1609 	CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr));
1610 	CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr));
1611 
1612 	/*
1613 	 * Install RX stat ring
1614 	 */
1615 	CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr));
1616 	CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr));
1617 	CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1);
1618 	CSR_WRITE_4(sc, ET_RXSTAT_POS, 0);
1619 	CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1);
1620 
1621 	/* Match ET_RXSTAT_POS */
1622 	rxst_ring->rsr_index = 0;
1623 	rxst_ring->rsr_wrap = 0;
1624 
1625 	/*
1626 	 * Install the 2nd RX descriptor ring
1627 	 */
1628 	rx_ring = &sc->sc_rx_ring[1];
1629 	CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1630 	CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1631 	CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1);
1632 	CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP);
1633 	CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1634 
1635 	/* Match ET_RX_RING1_POS */
1636 	rx_ring->rr_index = 0;
1637 	rx_ring->rr_wrap = 1;
1638 
1639 	/*
1640 	 * Install the 1st RX descriptor ring
1641 	 */
1642 	rx_ring = &sc->sc_rx_ring[0];
1643 	CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1644 	CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1645 	CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1);
1646 	CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP);
1647 	CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1648 
1649 	/* Match ET_RX_RING0_POS */
1650 	rx_ring->rr_index = 0;
1651 	rx_ring->rr_wrap = 1;
1652 
1653 	/*
1654 	 * RX intr moderation
1655 	 */
1656 	CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts);
1657 	CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay);
1658 
1659 	return (0);
1660 }
1661 
1662 static int
1663 et_init_txdma(struct et_softc *sc)
1664 {
1665 	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1666 	struct et_txstatus_data *txsd = &sc->sc_tx_status;
1667 	int error;
1668 
1669 	error = et_stop_txdma(sc);
1670 	if (error) {
1671 		if_printf(sc->ifp, "can't init TX DMA engine\n");
1672 		return (error);
1673 	}
1674 
1675 	/*
1676 	 * Install TX descriptor ring
1677 	 */
1678 	CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr));
1679 	CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr));
1680 	CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1);
1681 
1682 	/*
1683 	 * Install TX status
1684 	 */
1685 	CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr));
1686 	CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr));
1687 
1688 	CSR_WRITE_4(sc, ET_TX_READY_POS, 0);
1689 
1690 	/* Match ET_TX_READY_POS */
1691 	tx_ring->tr_ready_index = 0;
1692 	tx_ring->tr_ready_wrap = 0;
1693 
1694 	return (0);
1695 }
1696 
1697 static void
1698 et_init_mac(struct et_softc *sc)
1699 {
1700 	struct ifnet *ifp = sc->ifp;
1701 	const uint8_t *eaddr = IF_LLADDR(ifp);
1702 	uint32_t val;
1703 
1704 	/* Reset MAC */
1705 	CSR_WRITE_4(sc, ET_MAC_CFG1,
1706 		    ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1707 		    ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1708 		    ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1709 
1710 	/*
1711 	 * Setup inter packet gap
1712 	 */
1713 	val = (56 << ET_IPG_NONB2B_1_SHIFT) |
1714 	    (88 << ET_IPG_NONB2B_2_SHIFT) |
1715 	    (80 << ET_IPG_MINIFG_SHIFT) |
1716 	    (96 << ET_IPG_B2B_SHIFT);
1717 	CSR_WRITE_4(sc, ET_IPG, val);
1718 
1719 	/*
1720 	 * Setup half duplex mode
1721 	 */
1722 	val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) |
1723 	    (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) |
1724 	    (55 << ET_MAC_HDX_COLLWIN_SHIFT) |
1725 	    ET_MAC_HDX_EXC_DEFER;
1726 	CSR_WRITE_4(sc, ET_MAC_HDX, val);
1727 
1728 	/* Clear MAC control */
1729 	CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1730 
1731 	/* Reset MII */
1732 	CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1733 
1734 	/*
1735 	 * Set MAC address
1736 	 */
1737 	val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24);
1738 	CSR_WRITE_4(sc, ET_MAC_ADDR1, val);
1739 	val = (eaddr[0] << 16) | (eaddr[1] << 24);
1740 	CSR_WRITE_4(sc, ET_MAC_ADDR2, val);
1741 
1742 	/* Set max frame length */
1743 	CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu));
1744 
1745 	/* Bring MAC out of reset state */
1746 	CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1747 }
1748 
1749 static void
1750 et_init_rxmac(struct et_softc *sc)
1751 {
1752 	struct ifnet *ifp = sc->ifp;
1753 	const uint8_t *eaddr = IF_LLADDR(ifp);
1754 	uint32_t val;
1755 	int i;
1756 
1757 	/* Disable RX MAC and WOL */
1758 	CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE);
1759 
1760 	/*
1761 	 * Clear all WOL related registers
1762 	 */
1763 	for (i = 0; i < 3; ++i)
1764 		CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0);
1765 	for (i = 0; i < 20; ++i)
1766 		CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0);
1767 
1768 	/*
1769 	 * Set WOL source address.  XXX is this necessary?
1770 	 */
1771 	val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5];
1772 	CSR_WRITE_4(sc, ET_WOL_SA_LO, val);
1773 	val = (eaddr[0] << 8) | eaddr[1];
1774 	CSR_WRITE_4(sc, ET_WOL_SA_HI, val);
1775 
1776 	/* Clear packet filters */
1777 	CSR_WRITE_4(sc, ET_PKTFILT, 0);
1778 
1779 	/* No ucast filtering */
1780 	CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0);
1781 	CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0);
1782 	CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0);
1783 
1784 	if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) {
1785 		/*
1786 		 * In order to transmit jumbo packets greater than
1787 		 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between
1788 		 * RX MAC and RX DMA needs to be reduced in size to
1789 		 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen).  In
1790 		 * order to implement this, we must use "cut through"
1791 		 * mode in the RX MAC, which chops packets down into
1792 		 * segments.  In this case we selected 256 bytes,
1793 		 * since this is the size of the PCI-Express TLP's
1794 		 * that the ET1310 uses.
1795 		 */
1796 		val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) |
1797 		      ET_RXMAC_MC_SEGSZ_ENABLE;
1798 	} else {
1799 		val = 0;
1800 	}
1801 	CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val);
1802 
1803 	CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0);
1804 
1805 	/* Initialize RX MAC management register */
1806 	CSR_WRITE_4(sc, ET_RXMAC_MGT, 0);
1807 
1808 	CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0);
1809 
1810 	CSR_WRITE_4(sc, ET_RXMAC_MGT,
1811 		    ET_RXMAC_MGT_PASS_ECRC |
1812 		    ET_RXMAC_MGT_PASS_ELEN |
1813 		    ET_RXMAC_MGT_PASS_ETRUNC |
1814 		    ET_RXMAC_MGT_CHECK_PKT);
1815 
1816 	/*
1817 	 * Configure runt filtering (may not work on certain chip generation)
1818 	 */
1819 	val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) &
1820 	    ET_PKTFILT_MINLEN_MASK;
1821 	val |= ET_PKTFILT_FRAG;
1822 	CSR_WRITE_4(sc, ET_PKTFILT, val);
1823 
1824 	/* Enable RX MAC but leave WOL disabled */
1825 	CSR_WRITE_4(sc, ET_RXMAC_CTRL,
1826 		    ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE);
1827 
1828 	/*
1829 	 * Setup multicast hash and allmulti/promisc mode
1830 	 */
1831 	et_setmulti(sc);
1832 }
1833 
1834 static void
1835 et_init_txmac(struct et_softc *sc)
1836 {
1837 	/* Disable TX MAC and FC(?) */
1838 	CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE);
1839 
1840 	/* No flow control yet */
1841 	CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0);
1842 
1843 	/* Enable TX MAC but leave FC(?) diabled */
1844 	CSR_WRITE_4(sc, ET_TXMAC_CTRL,
1845 		    ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE);
1846 }
1847 
1848 static int
1849 et_start_rxdma(struct et_softc *sc)
1850 {
1851 	uint32_t val = 0;
1852 
1853 	val |= (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) |
1854 	       ET_RXDMA_CTRL_RING0_ENABLE;
1855 	val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) |
1856 	       ET_RXDMA_CTRL_RING1_ENABLE;
1857 
1858 	CSR_WRITE_4(sc, ET_RXDMA_CTRL, val);
1859 
1860 	DELAY(5);
1861 
1862 	if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) {
1863 		if_printf(sc->ifp, "can't start RX DMA engine\n");
1864 		return (ETIMEDOUT);
1865 	}
1866 	return (0);
1867 }
1868 
1869 static int
1870 et_start_txdma(struct et_softc *sc)
1871 {
1872 	CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT);
1873 	return (0);
1874 }
1875 
1876 static int
1877 et_enable_txrx(struct et_softc *sc, int media_upd)
1878 {
1879 	struct ifnet *ifp = sc->ifp;
1880 	uint32_t val;
1881 	int i, error;
1882 
1883 	val = CSR_READ_4(sc, ET_MAC_CFG1);
1884 	val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
1885 	val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
1886 		 ET_MAC_CFG1_LOOPBACK);
1887 	CSR_WRITE_4(sc, ET_MAC_CFG1, val);
1888 
1889 	if (media_upd)
1890 		et_ifmedia_upd_locked(ifp);
1891 	else
1892 		et_setmedia(sc);
1893 
1894 #define NRETRY	50
1895 
1896 	for (i = 0; i < NRETRY; ++i) {
1897 		val = CSR_READ_4(sc, ET_MAC_CFG1);
1898 		if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
1899 		    (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN))
1900 			break;
1901 
1902 		DELAY(100);
1903 	}
1904 	if (i == NRETRY) {
1905 		if_printf(ifp, "can't enable RX/TX\n");
1906 		return (0);
1907 	}
1908 	sc->sc_flags |= ET_FLAG_TXRX_ENABLED;
1909 
1910 #undef NRETRY
1911 
1912 	/*
1913 	 * Start TX/RX DMA engine
1914 	 */
1915 	error = et_start_rxdma(sc);
1916 	if (error)
1917 		return (error);
1918 
1919 	error = et_start_txdma(sc);
1920 	if (error)
1921 		return (error);
1922 
1923 	return (0);
1924 }
1925 
1926 static void
1927 et_rxeof(struct et_softc *sc)
1928 {
1929 	struct ifnet *ifp;
1930 	struct et_rxstatus_data *rxsd;
1931 	struct et_rxstat_ring *rxst_ring;
1932 	uint32_t rxs_stat_ring, rxst_info2;
1933 	int rxst_wrap, rxst_index;
1934 
1935 	ET_LOCK_ASSERT(sc);
1936 	ifp = sc->ifp;
1937 	rxsd = &sc->sc_rx_status;
1938 	rxst_ring = &sc->sc_rxstat_ring;
1939 
1940 	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
1941 		return;
1942 
1943 	bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap,
1944 			BUS_DMASYNC_POSTREAD);
1945 	bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap,
1946 			BUS_DMASYNC_POSTREAD);
1947 
1948 	rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring);
1949 	rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0;
1950 	rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >>
1951 	    ET_RXS_STATRING_INDEX_SHIFT;
1952 
1953 	while (rxst_index != rxst_ring->rsr_index ||
1954 	       rxst_wrap != rxst_ring->rsr_wrap) {
1955 		struct et_rxbuf_data *rbd;
1956 		struct et_rxdesc_ring *rx_ring;
1957 		struct et_rxstat *st;
1958 		struct mbuf *m;
1959 		int buflen, buf_idx, ring_idx;
1960 		uint32_t rxstat_pos, rxring_pos;
1961 
1962 		MPASS(rxst_ring->rsr_index < ET_RX_NSTAT);
1963 		st = &rxst_ring->rsr_stat[rxst_ring->rsr_index];
1964 		rxst_info2 = le32toh(st->rxst_info2);
1965 		buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >>
1966 		    ET_RXST_INFO2_LEN_SHIFT;
1967 		buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >>
1968 		    ET_RXST_INFO2_BUFIDX_SHIFT;
1969 		ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >>
1970 		    ET_RXST_INFO2_RINGIDX_SHIFT;
1971 
1972 		if (++rxst_ring->rsr_index == ET_RX_NSTAT) {
1973 			rxst_ring->rsr_index = 0;
1974 			rxst_ring->rsr_wrap ^= 1;
1975 		}
1976 		rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK;
1977 		if (rxst_ring->rsr_wrap)
1978 			rxstat_pos |= ET_RXSTAT_POS_WRAP;
1979 		CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos);
1980 
1981 		if (ring_idx >= ET_RX_NRING) {
1982 			ifp->if_ierrors++;
1983 			if_printf(ifp, "invalid ring index %d\n", ring_idx);
1984 			continue;
1985 		}
1986 		if (buf_idx >= ET_RX_NDESC) {
1987 			ifp->if_ierrors++;
1988 			if_printf(ifp, "invalid buf index %d\n", buf_idx);
1989 			continue;
1990 		}
1991 
1992 		rbd = &sc->sc_rx_data[ring_idx];
1993 		m = rbd->rbd_buf[buf_idx].rb_mbuf;
1994 
1995 		if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) {
1996 			if (buflen < ETHER_CRC_LEN) {
1997 				m_freem(m);
1998 				m = NULL;
1999 				ifp->if_ierrors++;
2000 			} else {
2001 				m->m_pkthdr.len = m->m_len =
2002 				    buflen - ETHER_CRC_LEN;
2003 				m->m_pkthdr.rcvif = ifp;
2004 				ifp->if_ipackets++;
2005 				ET_UNLOCK(sc);
2006 				ifp->if_input(ifp, m);
2007 				ET_LOCK(sc);
2008 			}
2009 		} else {
2010 			ifp->if_ierrors++;
2011 		}
2012 		m = NULL;	/* Catch invalid reference */
2013 
2014 		rx_ring = &sc->sc_rx_ring[ring_idx];
2015 
2016 		if (buf_idx != rx_ring->rr_index) {
2017 			if_printf(ifp, "WARNING!! ring %d, "
2018 				  "buf_idx %d, rr_idx %d\n",
2019 				  ring_idx, buf_idx, rx_ring->rr_index);
2020 		}
2021 
2022 		MPASS(rx_ring->rr_index < ET_RX_NDESC);
2023 		if (++rx_ring->rr_index == ET_RX_NDESC) {
2024 			rx_ring->rr_index = 0;
2025 			rx_ring->rr_wrap ^= 1;
2026 		}
2027 		rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK;
2028 		if (rx_ring->rr_wrap)
2029 			rxring_pos |= ET_RX_RING_POS_WRAP;
2030 		CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos);
2031 	}
2032 }
2033 
2034 static int
2035 et_encap(struct et_softc *sc, struct mbuf **m0)
2036 {
2037 	struct mbuf *m = *m0;
2038 	bus_dma_segment_t segs[ET_NSEG_MAX];
2039 	struct et_dmamap_ctx ctx;
2040 	struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
2041 	struct et_txbuf_data *tbd = &sc->sc_tx_data;
2042 	struct et_txdesc *td;
2043 	bus_dmamap_t map;
2044 	int error, maxsegs, first_idx, last_idx, i;
2045 	uint32_t csum_flags, tx_ready_pos, last_td_ctrl2;
2046 
2047 	maxsegs = ET_TX_NDESC - tbd->tbd_used;
2048 	if (maxsegs > ET_NSEG_MAX)
2049 		maxsegs = ET_NSEG_MAX;
2050 	KASSERT(maxsegs >= ET_NSEG_SPARE,
2051 		("not enough spare TX desc (%d)\n", maxsegs));
2052 
2053 	MPASS(tx_ring->tr_ready_index < ET_TX_NDESC);
2054 	first_idx = tx_ring->tr_ready_index;
2055 	map = tbd->tbd_buf[first_idx].tb_dmap;
2056 
2057 	ctx.nsegs = maxsegs;
2058 	ctx.segs = segs;
2059 	error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m,
2060 				     et_dma_buf_addr, &ctx, BUS_DMA_NOWAIT);
2061 	if (!error && ctx.nsegs == 0) {
2062 		bus_dmamap_unload(sc->sc_mbuf_dtag, map);
2063 		error = EFBIG;
2064 	}
2065 	if (error && error != EFBIG) {
2066 		if_printf(sc->ifp, "can't load TX mbuf, error %d\n",
2067 			  error);
2068 		goto back;
2069 	}
2070 	if (error) {	/* error == EFBIG */
2071 		struct mbuf *m_new;
2072 
2073 		m_new = m_defrag(m, M_DONTWAIT);
2074 		if (m_new == NULL) {
2075 			if_printf(sc->ifp, "can't defrag TX mbuf\n");
2076 			error = ENOBUFS;
2077 			goto back;
2078 		} else {
2079 			*m0 = m = m_new;
2080 		}
2081 
2082 		ctx.nsegs = maxsegs;
2083 		ctx.segs = segs;
2084 		error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m,
2085 					     et_dma_buf_addr, &ctx,
2086 					     BUS_DMA_NOWAIT);
2087 		if (error || ctx.nsegs == 0) {
2088 			if (ctx.nsegs == 0) {
2089 				bus_dmamap_unload(sc->sc_mbuf_dtag, map);
2090 				error = EFBIG;
2091 			}
2092 			if_printf(sc->ifp,
2093 				  "can't load defraged TX mbuf\n");
2094 			goto back;
2095 		}
2096 	}
2097 
2098 	bus_dmamap_sync(sc->sc_mbuf_dtag, map, BUS_DMASYNC_PREWRITE);
2099 
2100 	last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG;
2101 	sc->sc_tx += ctx.nsegs;
2102 	if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) {
2103 		sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs;
2104 		last_td_ctrl2 |= ET_TDCTRL2_INTR;
2105 	}
2106 
2107 	csum_flags = 0;
2108 	if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) {
2109 		if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
2110 			csum_flags |= ET_TDCTRL2_CSUM_IP;
2111 		if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2112 			csum_flags |= ET_TDCTRL2_CSUM_UDP;
2113 		else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
2114 			csum_flags |= ET_TDCTRL2_CSUM_TCP;
2115 	}
2116 	last_idx = -1;
2117 	for (i = 0; i < ctx.nsegs; ++i) {
2118 		int idx;
2119 
2120 		idx = (first_idx + i) % ET_TX_NDESC;
2121 		td = &tx_ring->tr_desc[idx];
2122 		td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr));
2123 		td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr));
2124 		td->td_ctrl1 =  htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK);
2125 		if (i == ctx.nsegs - 1) {	/* Last frag */
2126 			td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags);
2127 			last_idx = idx;
2128 		} else
2129 			td->td_ctrl2 = htole32(csum_flags);
2130 
2131 		MPASS(tx_ring->tr_ready_index < ET_TX_NDESC);
2132 		if (++tx_ring->tr_ready_index == ET_TX_NDESC) {
2133 			tx_ring->tr_ready_index = 0;
2134 			tx_ring->tr_ready_wrap ^= 1;
2135 		}
2136 	}
2137 	td = &tx_ring->tr_desc[first_idx];
2138 	td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG);	/* First frag */
2139 
2140 	MPASS(last_idx >= 0);
2141 	tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap;
2142 	tbd->tbd_buf[last_idx].tb_dmap = map;
2143 	tbd->tbd_buf[last_idx].tb_mbuf = m;
2144 
2145 	tbd->tbd_used += ctx.nsegs;
2146 	MPASS(tbd->tbd_used <= ET_TX_NDESC);
2147 
2148 	bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
2149 			BUS_DMASYNC_PREWRITE);
2150 
2151 	tx_ready_pos = tx_ring->tr_ready_index & ET_TX_READY_POS_INDEX_MASK;
2152 	if (tx_ring->tr_ready_wrap)
2153 		tx_ready_pos |= ET_TX_READY_POS_WRAP;
2154 	CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos);
2155 
2156 	error = 0;
2157 back:
2158 	if (error) {
2159 		m_freem(m);
2160 		*m0 = NULL;
2161 	}
2162 	return (error);
2163 }
2164 
2165 static void
2166 et_txeof(struct et_softc *sc)
2167 {
2168 	struct ifnet *ifp;
2169 	struct et_txdesc_ring *tx_ring;
2170 	struct et_txbuf_data *tbd;
2171 	uint32_t tx_done;
2172 	int end, wrap;
2173 
2174 	ET_LOCK_ASSERT(sc);
2175 	ifp = sc->ifp;
2176 	tx_ring = &sc->sc_tx_ring;
2177 	tbd = &sc->sc_tx_data;
2178 
2179 	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
2180 		return;
2181 
2182 	if (tbd->tbd_used == 0)
2183 		return;
2184 
2185 	tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);
2186 	end = tx_done & ET_TX_DONE_POS_INDEX_MASK;
2187 	wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0;
2188 
2189 	while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) {
2190 		struct et_txbuf *tb;
2191 
2192 		MPASS(tbd->tbd_start_index < ET_TX_NDESC);
2193 		tb = &tbd->tbd_buf[tbd->tbd_start_index];
2194 
2195 		bzero(&tx_ring->tr_desc[tbd->tbd_start_index],
2196 		      sizeof(struct et_txdesc));
2197 		bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap,
2198 				BUS_DMASYNC_PREWRITE);
2199 
2200 		if (tb->tb_mbuf != NULL) {
2201 			bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap);
2202 			m_freem(tb->tb_mbuf);
2203 			tb->tb_mbuf = NULL;
2204 			ifp->if_opackets++;
2205 		}
2206 
2207 		if (++tbd->tbd_start_index == ET_TX_NDESC) {
2208 			tbd->tbd_start_index = 0;
2209 			tbd->tbd_start_wrap ^= 1;
2210 		}
2211 
2212 		MPASS(tbd->tbd_used > 0);
2213 		tbd->tbd_used--;
2214 	}
2215 
2216 	if (tbd->tbd_used == 0)
2217 		sc->watchdog_timer = 0;
2218 	if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC)
2219 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2220 
2221 	et_start_locked(ifp);
2222 }
2223 
2224 static void
2225 et_tick(void *xsc)
2226 {
2227 	struct et_softc *sc = xsc;
2228 	struct ifnet *ifp;
2229 	struct mii_data *mii;
2230 
2231 	ET_LOCK_ASSERT(sc);
2232 	ifp = sc->ifp;
2233 	mii = device_get_softc(sc->sc_miibus);
2234 
2235 	mii_tick(mii);
2236 	if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 &&
2237 	    (mii->mii_media_status & IFM_ACTIVE) &&
2238 	    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2239 		if_printf(ifp, "Link up, enable TX/RX\n");
2240 		if (et_enable_txrx(sc, 0) == 0)
2241 			et_start_locked(ifp);
2242 	}
2243 	et_watchdog(sc);
2244 	callout_reset(&sc->sc_tick, hz, et_tick, sc);
2245 }
2246 
2247 static int
2248 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init)
2249 {
2250 	return (et_newbuf(rbd, buf_idx, init, MCLBYTES));
2251 }
2252 
2253 static int
2254 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init)
2255 {
2256 	return (et_newbuf(rbd, buf_idx, init, MHLEN));
2257 }
2258 
2259 static int
2260 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0)
2261 {
2262 	struct et_softc *sc = rbd->rbd_softc;
2263 	struct et_rxbuf *rb;
2264 	struct mbuf *m;
2265 	struct et_dmamap_ctx ctx;
2266 	bus_dma_segment_t seg;
2267 	bus_dmamap_t dmap;
2268 	int error, len;
2269 
2270 	MPASS(buf_idx < ET_RX_NDESC);
2271 	rb = &rbd->rbd_buf[buf_idx];
2272 
2273 	m = m_getl(len0, /* init ? M_WAIT :*/ M_DONTWAIT, MT_DATA, M_PKTHDR, &len);
2274 	if (m == NULL) {
2275 		error = ENOBUFS;
2276 
2277 		if (init) {
2278 			if_printf(sc->ifp,
2279 				  "m_getl failed, size %d\n", len0);
2280 			return (error);
2281 		} else {
2282 			goto back;
2283 		}
2284 	}
2285 	m->m_len = m->m_pkthdr.len = len;
2286 
2287 	/*
2288 	 * Try load RX mbuf into temporary DMA tag
2289 	 */
2290 	ctx.nsegs = 1;
2291 	ctx.segs = &seg;
2292 	error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap, m,
2293 				     et_dma_buf_addr, &ctx,
2294 				     init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2295 	if (error || ctx.nsegs == 0) {
2296 		if (!error) {
2297 			bus_dmamap_unload(sc->sc_mbuf_dtag,
2298 					  sc->sc_mbuf_tmp_dmap);
2299 			error = EFBIG;
2300 			if_printf(sc->ifp, "too many segments?!\n");
2301 		}
2302 		m_freem(m);
2303 		m = NULL;
2304 
2305 		if (init) {
2306 			if_printf(sc->ifp, "can't load RX mbuf\n");
2307 			return (error);
2308 		} else {
2309 			goto back;
2310 		}
2311 	}
2312 
2313 	if (!init) {
2314 		bus_dmamap_sync(sc->sc_mbuf_dtag, rb->rb_dmap,
2315 				BUS_DMASYNC_POSTREAD);
2316 		bus_dmamap_unload(sc->sc_mbuf_dtag, rb->rb_dmap);
2317 	}
2318 	rb->rb_mbuf = m;
2319 	rb->rb_paddr = seg.ds_addr;
2320 
2321 	/*
2322 	 * Swap RX buf's DMA map with the loaded temporary one
2323 	 */
2324 	dmap = rb->rb_dmap;
2325 	rb->rb_dmap = sc->sc_mbuf_tmp_dmap;
2326 	sc->sc_mbuf_tmp_dmap = dmap;
2327 
2328 	error = 0;
2329 back:
2330 	et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr);
2331 	return (error);
2332 }
2333 
2334 /*
2335  * Create sysctl tree
2336  */
2337 static void
2338 et_add_sysctls(struct et_softc * sc)
2339 {
2340 	struct sysctl_ctx_list *ctx;
2341 	struct sysctl_oid_list *children;
2342 
2343 	ctx = device_get_sysctl_ctx(sc->dev);
2344 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
2345 
2346 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts",
2347 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_npkts, "I",
2348 	    "RX IM, # packets per RX interrupt");
2349 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay",
2350 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_delay, "I",
2351 	    "RX IM, RX interrupt delay (x10 usec)");
2352 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs",
2353 	    CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0,
2354 	    "TX IM, # segments per TX interrupt");
2355 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer",
2356 	    CTLFLAG_RW, &sc->sc_timer, 0, "TX timer");
2357 }
2358 
2359 static int
2360 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS)
2361 {
2362 	struct et_softc *sc = arg1;
2363 	struct ifnet *ifp = sc->ifp;
2364 	int error = 0, v;
2365 
2366 	v = sc->sc_rx_intr_npkts;
2367 	error = sysctl_handle_int(oidp, &v, 0, req);
2368 	if (error || req->newptr == NULL)
2369 		goto back;
2370 	if (v <= 0) {
2371 		error = EINVAL;
2372 		goto back;
2373 	}
2374 
2375 	if (sc->sc_rx_intr_npkts != v) {
2376 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2377 			CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v);
2378 		sc->sc_rx_intr_npkts = v;
2379 	}
2380 back:
2381 	return (error);
2382 }
2383 
2384 static int
2385 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS)
2386 {
2387 	struct et_softc *sc = arg1;
2388 	struct ifnet *ifp = sc->ifp;
2389 	int error = 0, v;
2390 
2391 	v = sc->sc_rx_intr_delay;
2392 	error = sysctl_handle_int(oidp, &v, 0, req);
2393 	if (error || req->newptr == NULL)
2394 		goto back;
2395 	if (v <= 0) {
2396 		error = EINVAL;
2397 		goto back;
2398 	}
2399 
2400 	if (sc->sc_rx_intr_delay != v) {
2401 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2402 			CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v);
2403 		sc->sc_rx_intr_delay = v;
2404 	}
2405 back:
2406 	return (error);
2407 }
2408 
2409 static void
2410 et_setmedia(struct et_softc *sc)
2411 {
2412 	struct mii_data *mii = device_get_softc(sc->sc_miibus);
2413 	uint32_t cfg2, ctrl;
2414 
2415 	cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
2416 	cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII |
2417 		  ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM);
2418 	cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC |
2419 	    ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) &
2420 	    ET_MAC_CFG2_PREAMBLE_LEN_MASK);
2421 
2422 	ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
2423 	ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
2424 
2425 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
2426 		cfg2 |= ET_MAC_CFG2_MODE_GMII;
2427 	} else {
2428 		cfg2 |= ET_MAC_CFG2_MODE_MII;
2429 		ctrl |= ET_MAC_CTRL_MODE_MII;
2430 	}
2431 
2432 	if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
2433 		cfg2 |= ET_MAC_CFG2_FDX;
2434 	else
2435 		ctrl |= ET_MAC_CTRL_GHDX;
2436 
2437 	CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
2438 	CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
2439 }
2440 
2441 static void
2442 et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr)
2443 {
2444 	struct et_rxdesc_ring *rx_ring = rbd->rbd_ring;
2445 	struct et_rxdesc *desc;
2446 
2447 	MPASS(buf_idx < ET_RX_NDESC);
2448 	desc = &rx_ring->rr_desc[buf_idx];
2449 
2450 	desc->rd_addr_hi = htole32(ET_ADDR_HI(paddr));
2451 	desc->rd_addr_lo = htole32(ET_ADDR_LO(paddr));
2452 	desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK);
2453 
2454 	bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap,
2455 			BUS_DMASYNC_PREWRITE);
2456 }
2457