1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/malloc.h> 48 #include <sys/mbuf.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/module.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/bpf.h> 62 #include <net/if_arp.h> 63 #include <net/if_media.h> 64 #include <net/if_vlan_var.h> 65 66 #include <machine/bus.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/et/if_etreg.h> 75 #include <dev/et/if_etvar.h> 76 77 #include "miibus_if.h" 78 79 MODULE_DEPEND(et, pci, 1, 1, 1); 80 MODULE_DEPEND(et, ether, 1, 1, 1); 81 MODULE_DEPEND(et, miibus, 1, 1, 1); 82 83 /* Tunables. */ 84 static int msi_disable = 0; 85 TUNABLE_INT("hw.et.msi_disable", &msi_disable); 86 87 #define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 88 89 static int et_probe(device_t); 90 static int et_attach(device_t); 91 static int et_detach(device_t); 92 static int et_shutdown(device_t); 93 static int et_suspend(device_t); 94 static int et_resume(device_t); 95 96 static int et_miibus_readreg(device_t, int, int); 97 static int et_miibus_writereg(device_t, int, int, int); 98 static void et_miibus_statchg(device_t); 99 100 static void et_init_locked(struct et_softc *); 101 static void et_init(void *); 102 static int et_ioctl(struct ifnet *, u_long, caddr_t); 103 static void et_start_locked(struct ifnet *); 104 static void et_start(struct ifnet *); 105 static int et_watchdog(struct et_softc *); 106 static int et_ifmedia_upd_locked(struct ifnet *); 107 static int et_ifmedia_upd(struct ifnet *); 108 static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 static uint64_t et_get_counter(struct ifnet *, ift_counter); 110 111 static void et_add_sysctls(struct et_softc *); 112 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 113 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 114 115 static void et_intr(void *); 116 static void et_rxeof(struct et_softc *); 117 static void et_txeof(struct et_softc *); 118 119 static int et_dma_alloc(struct et_softc *); 120 static void et_dma_free(struct et_softc *); 121 static void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 122 static int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 123 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 124 const char *); 125 static void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 126 bus_dmamap_t, bus_addr_t *); 127 static void et_init_tx_ring(struct et_softc *); 128 static int et_init_rx_ring(struct et_softc *); 129 static void et_free_tx_ring(struct et_softc *); 130 static void et_free_rx_ring(struct et_softc *); 131 static int et_encap(struct et_softc *, struct mbuf **); 132 static int et_newbuf_cluster(struct et_rxbuf_data *, int); 133 static int et_newbuf_hdr(struct et_rxbuf_data *, int); 134 static void et_rxbuf_discard(struct et_rxbuf_data *, int); 135 136 static void et_stop(struct et_softc *); 137 static int et_chip_init(struct et_softc *); 138 static void et_chip_attach(struct et_softc *); 139 static void et_init_mac(struct et_softc *); 140 static void et_init_rxmac(struct et_softc *); 141 static void et_init_txmac(struct et_softc *); 142 static int et_init_rxdma(struct et_softc *); 143 static int et_init_txdma(struct et_softc *); 144 static int et_start_rxdma(struct et_softc *); 145 static int et_start_txdma(struct et_softc *); 146 static int et_stop_rxdma(struct et_softc *); 147 static int et_stop_txdma(struct et_softc *); 148 static void et_reset(struct et_softc *); 149 static int et_bus_config(struct et_softc *); 150 static void et_get_eaddr(device_t, uint8_t[]); 151 static void et_setmulti(struct et_softc *); 152 static void et_tick(void *); 153 static void et_stats_update(struct et_softc *); 154 155 static const struct et_dev { 156 uint16_t vid; 157 uint16_t did; 158 const char *desc; 159 } et_devices[] = { 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 161 "Agere ET1310 Gigabit Ethernet" }, 162 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 163 "Agere ET1310 Fast Ethernet" }, 164 { 0, 0, NULL } 165 }; 166 167 static device_method_t et_methods[] = { 168 DEVMETHOD(device_probe, et_probe), 169 DEVMETHOD(device_attach, et_attach), 170 DEVMETHOD(device_detach, et_detach), 171 DEVMETHOD(device_shutdown, et_shutdown), 172 DEVMETHOD(device_suspend, et_suspend), 173 DEVMETHOD(device_resume, et_resume), 174 175 DEVMETHOD(miibus_readreg, et_miibus_readreg), 176 DEVMETHOD(miibus_writereg, et_miibus_writereg), 177 DEVMETHOD(miibus_statchg, et_miibus_statchg), 178 179 DEVMETHOD_END 180 }; 181 182 static driver_t et_driver = { 183 "et", 184 et_methods, 185 sizeof(struct et_softc) 186 }; 187 188 static devclass_t et_devclass; 189 190 DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0); 191 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, et, et_devices, 192 nitems(et_devices) - 1); 193 DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0); 194 195 static int et_rx_intr_npkts = 32; 196 static int et_rx_intr_delay = 20; /* x10 usec */ 197 static int et_tx_intr_nsegs = 126; 198 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 199 200 TUNABLE_INT("hw.et.timer", &et_timer); 201 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 202 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 203 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 204 205 static int 206 et_probe(device_t dev) 207 { 208 const struct et_dev *d; 209 uint16_t did, vid; 210 211 vid = pci_get_vendor(dev); 212 did = pci_get_device(dev); 213 214 for (d = et_devices; d->desc != NULL; ++d) { 215 if (vid == d->vid && did == d->did) { 216 device_set_desc(dev, d->desc); 217 return (BUS_PROBE_DEFAULT); 218 } 219 } 220 return (ENXIO); 221 } 222 223 static int 224 et_attach(device_t dev) 225 { 226 struct et_softc *sc; 227 struct ifnet *ifp; 228 uint8_t eaddr[ETHER_ADDR_LEN]; 229 uint32_t pmcfg; 230 int cap, error, msic; 231 232 sc = device_get_softc(dev); 233 sc->dev = dev; 234 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 235 MTX_DEF); 236 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 237 238 ifp = sc->ifp = if_alloc(IFT_ETHER); 239 if (ifp == NULL) { 240 device_printf(dev, "can not if_alloc()\n"); 241 error = ENOSPC; 242 goto fail; 243 } 244 245 /* 246 * Initialize tunables 247 */ 248 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 249 sc->sc_rx_intr_delay = et_rx_intr_delay; 250 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 251 sc->sc_timer = et_timer; 252 253 /* Enable bus mastering */ 254 pci_enable_busmaster(dev); 255 256 /* 257 * Allocate IO memory 258 */ 259 sc->sc_mem_rid = PCIR_BAR(0); 260 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 261 &sc->sc_mem_rid, RF_ACTIVE); 262 if (sc->sc_mem_res == NULL) { 263 device_printf(dev, "can't allocate IO memory\n"); 264 return (ENXIO); 265 } 266 267 msic = 0; 268 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 269 sc->sc_expcap = cap; 270 sc->sc_flags |= ET_FLAG_PCIE; 271 msic = pci_msi_count(dev); 272 if (bootverbose) 273 device_printf(dev, "MSI count: %d\n", msic); 274 } 275 if (msic > 0 && msi_disable == 0) { 276 msic = 1; 277 if (pci_alloc_msi(dev, &msic) == 0) { 278 if (msic == 1) { 279 device_printf(dev, "Using %d MSI message\n", 280 msic); 281 sc->sc_flags |= ET_FLAG_MSI; 282 } else 283 pci_release_msi(dev); 284 } 285 } 286 287 /* 288 * Allocate IRQ 289 */ 290 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 291 sc->sc_irq_rid = 0; 292 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 293 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 294 } else { 295 sc->sc_irq_rid = 1; 296 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 297 &sc->sc_irq_rid, RF_ACTIVE); 298 } 299 if (sc->sc_irq_res == NULL) { 300 device_printf(dev, "can't allocate irq\n"); 301 error = ENXIO; 302 goto fail; 303 } 304 305 if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST) 306 sc->sc_flags |= ET_FLAG_FASTETHER; 307 308 error = et_bus_config(sc); 309 if (error) 310 goto fail; 311 312 et_get_eaddr(dev, eaddr); 313 314 /* Take PHY out of COMA and enable clocks. */ 315 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 316 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 317 pmcfg |= EM_PM_GIGEPHY_ENB; 318 CSR_WRITE_4(sc, ET_PM, pmcfg); 319 320 et_reset(sc); 321 322 error = et_dma_alloc(sc); 323 if (error) 324 goto fail; 325 326 ifp->if_softc = sc; 327 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 328 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 329 ifp->if_init = et_init; 330 ifp->if_ioctl = et_ioctl; 331 ifp->if_start = et_start; 332 ifp->if_get_counter = et_get_counter; 333 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU; 334 ifp->if_capenable = ifp->if_capabilities; 335 ifp->if_snd.ifq_drv_maxlen = ET_TX_NDESC - 1; 336 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC - 1); 337 IFQ_SET_READY(&ifp->if_snd); 338 339 et_chip_attach(sc); 340 341 error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 342 et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 343 MIIF_DOPAUSE); 344 if (error) { 345 device_printf(dev, "attaching PHYs failed\n"); 346 goto fail; 347 } 348 349 ether_ifattach(ifp, eaddr); 350 351 /* Tell the upper layer(s) we support long frames. */ 352 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 353 354 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 355 NULL, et_intr, sc, &sc->sc_irq_handle); 356 if (error) { 357 ether_ifdetach(ifp); 358 device_printf(dev, "can't setup intr\n"); 359 goto fail; 360 } 361 362 et_add_sysctls(sc); 363 364 return (0); 365 fail: 366 et_detach(dev); 367 return (error); 368 } 369 370 static int 371 et_detach(device_t dev) 372 { 373 struct et_softc *sc; 374 375 sc = device_get_softc(dev); 376 if (device_is_attached(dev)) { 377 ether_ifdetach(sc->ifp); 378 ET_LOCK(sc); 379 et_stop(sc); 380 ET_UNLOCK(sc); 381 callout_drain(&sc->sc_tick); 382 } 383 384 if (sc->sc_miibus != NULL) 385 device_delete_child(dev, sc->sc_miibus); 386 bus_generic_detach(dev); 387 388 if (sc->sc_irq_handle != NULL) 389 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 390 if (sc->sc_irq_res != NULL) 391 bus_release_resource(dev, SYS_RES_IRQ, 392 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 393 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 394 pci_release_msi(dev); 395 if (sc->sc_mem_res != NULL) 396 bus_release_resource(dev, SYS_RES_MEMORY, 397 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 398 399 if (sc->ifp != NULL) 400 if_free(sc->ifp); 401 402 et_dma_free(sc); 403 404 mtx_destroy(&sc->sc_mtx); 405 406 return (0); 407 } 408 409 static int 410 et_shutdown(device_t dev) 411 { 412 struct et_softc *sc; 413 414 sc = device_get_softc(dev); 415 ET_LOCK(sc); 416 et_stop(sc); 417 ET_UNLOCK(sc); 418 return (0); 419 } 420 421 static int 422 et_miibus_readreg(device_t dev, int phy, int reg) 423 { 424 struct et_softc *sc; 425 uint32_t val; 426 int i, ret; 427 428 sc = device_get_softc(dev); 429 /* Stop any pending operations */ 430 CSR_WRITE_4(sc, ET_MII_CMD, 0); 431 432 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 433 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 434 CSR_WRITE_4(sc, ET_MII_ADDR, val); 435 436 /* Start reading */ 437 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 438 439 #define NRETRY 50 440 441 for (i = 0; i < NRETRY; ++i) { 442 val = CSR_READ_4(sc, ET_MII_IND); 443 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 444 break; 445 DELAY(50); 446 } 447 if (i == NRETRY) { 448 if_printf(sc->ifp, 449 "read phy %d, reg %d timed out\n", phy, reg); 450 ret = 0; 451 goto back; 452 } 453 454 #undef NRETRY 455 456 val = CSR_READ_4(sc, ET_MII_STAT); 457 ret = val & ET_MII_STAT_VALUE_MASK; 458 459 back: 460 /* Make sure that the current operation is stopped */ 461 CSR_WRITE_4(sc, ET_MII_CMD, 0); 462 return (ret); 463 } 464 465 static int 466 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 467 { 468 struct et_softc *sc; 469 uint32_t val; 470 int i; 471 472 sc = device_get_softc(dev); 473 /* Stop any pending operations */ 474 CSR_WRITE_4(sc, ET_MII_CMD, 0); 475 476 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 477 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 478 CSR_WRITE_4(sc, ET_MII_ADDR, val); 479 480 /* Start writing */ 481 CSR_WRITE_4(sc, ET_MII_CTRL, 482 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 483 484 #define NRETRY 100 485 486 for (i = 0; i < NRETRY; ++i) { 487 val = CSR_READ_4(sc, ET_MII_IND); 488 if ((val & ET_MII_IND_BUSY) == 0) 489 break; 490 DELAY(50); 491 } 492 if (i == NRETRY) { 493 if_printf(sc->ifp, 494 "write phy %d, reg %d timed out\n", phy, reg); 495 et_miibus_readreg(dev, phy, reg); 496 } 497 498 #undef NRETRY 499 500 /* Make sure that the current operation is stopped */ 501 CSR_WRITE_4(sc, ET_MII_CMD, 0); 502 return (0); 503 } 504 505 static void 506 et_miibus_statchg(device_t dev) 507 { 508 struct et_softc *sc; 509 struct mii_data *mii; 510 struct ifnet *ifp; 511 uint32_t cfg1, cfg2, ctrl; 512 int i; 513 514 sc = device_get_softc(dev); 515 516 mii = device_get_softc(sc->sc_miibus); 517 ifp = sc->ifp; 518 if (mii == NULL || ifp == NULL || 519 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 520 return; 521 522 sc->sc_flags &= ~ET_FLAG_LINK; 523 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 524 (IFM_ACTIVE | IFM_AVALID)) { 525 switch (IFM_SUBTYPE(mii->mii_media_active)) { 526 case IFM_10_T: 527 case IFM_100_TX: 528 sc->sc_flags |= ET_FLAG_LINK; 529 break; 530 case IFM_1000_T: 531 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 532 sc->sc_flags |= ET_FLAG_LINK; 533 break; 534 } 535 } 536 537 /* XXX Stop TX/RX MAC? */ 538 if ((sc->sc_flags & ET_FLAG_LINK) == 0) 539 return; 540 541 /* Program MACs with resolved speed/duplex/flow-control. */ 542 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 543 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 544 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 545 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 546 ET_MAC_CFG1_LOOPBACK); 547 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 548 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 549 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 550 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 551 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 552 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 553 554 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 555 cfg2 |= ET_MAC_CFG2_MODE_GMII; 556 else { 557 cfg2 |= ET_MAC_CFG2_MODE_MII; 558 ctrl |= ET_MAC_CTRL_MODE_MII; 559 } 560 561 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 562 cfg2 |= ET_MAC_CFG2_FDX; 563 /* 564 * Controller lacks automatic TX pause frame 565 * generation so it should be handled by driver. 566 * Even though driver can send pause frame with 567 * arbitrary pause time, controller does not 568 * provide a way that tells how many free RX 569 * buffers are available in controller. This 570 * limitation makes it hard to generate XON frame 571 * in time on driver side so don't enable TX flow 572 * control. 573 */ 574 #ifdef notyet 575 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 576 cfg1 |= ET_MAC_CFG1_TXFLOW; 577 #endif 578 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 579 cfg1 |= ET_MAC_CFG1_RXFLOW; 580 } else 581 ctrl |= ET_MAC_CTRL_GHDX; 582 583 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 584 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 585 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 586 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); 587 588 #define NRETRY 50 589 590 for (i = 0; i < NRETRY; ++i) { 591 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 592 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 593 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 594 break; 595 DELAY(100); 596 } 597 if (i == NRETRY) 598 if_printf(ifp, "can't enable RX/TX\n"); 599 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 600 601 #undef NRETRY 602 } 603 604 static int 605 et_ifmedia_upd_locked(struct ifnet *ifp) 606 { 607 struct et_softc *sc; 608 struct mii_data *mii; 609 struct mii_softc *miisc; 610 611 sc = ifp->if_softc; 612 mii = device_get_softc(sc->sc_miibus); 613 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 614 PHY_RESET(miisc); 615 return (mii_mediachg(mii)); 616 } 617 618 static int 619 et_ifmedia_upd(struct ifnet *ifp) 620 { 621 struct et_softc *sc; 622 int res; 623 624 sc = ifp->if_softc; 625 ET_LOCK(sc); 626 res = et_ifmedia_upd_locked(ifp); 627 ET_UNLOCK(sc); 628 629 return (res); 630 } 631 632 static void 633 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 634 { 635 struct et_softc *sc; 636 struct mii_data *mii; 637 638 sc = ifp->if_softc; 639 ET_LOCK(sc); 640 if ((ifp->if_flags & IFF_UP) == 0) { 641 ET_UNLOCK(sc); 642 return; 643 } 644 645 mii = device_get_softc(sc->sc_miibus); 646 mii_pollstat(mii); 647 ifmr->ifm_active = mii->mii_media_active; 648 ifmr->ifm_status = mii->mii_media_status; 649 ET_UNLOCK(sc); 650 } 651 652 static void 653 et_stop(struct et_softc *sc) 654 { 655 struct ifnet *ifp; 656 657 ET_LOCK_ASSERT(sc); 658 659 ifp = sc->ifp; 660 callout_stop(&sc->sc_tick); 661 /* Disable interrupts. */ 662 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 663 664 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( 665 ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN)); 666 DELAY(100); 667 668 et_stop_rxdma(sc); 669 et_stop_txdma(sc); 670 et_stats_update(sc); 671 672 et_free_tx_ring(sc); 673 et_free_rx_ring(sc); 674 675 sc->sc_tx = 0; 676 sc->sc_tx_intr = 0; 677 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 678 679 sc->watchdog_timer = 0; 680 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 681 } 682 683 static int 684 et_bus_config(struct et_softc *sc) 685 { 686 uint32_t val, max_plsz; 687 uint16_t ack_latency, replay_timer; 688 689 /* 690 * Test whether EEPROM is valid 691 * NOTE: Read twice to get the correct value 692 */ 693 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 694 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 695 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 696 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 697 return (ENXIO); 698 } 699 700 /* TODO: LED */ 701 702 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 703 return (0); 704 705 /* 706 * Configure ACK latency and replay timer according to 707 * max playload size 708 */ 709 val = pci_read_config(sc->dev, 710 sc->sc_expcap + PCIER_DEVICE_CAP, 4); 711 max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; 712 713 switch (max_plsz) { 714 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 715 ack_latency = ET_PCIV_ACK_LATENCY_128; 716 replay_timer = ET_PCIV_REPLAY_TIMER_128; 717 break; 718 719 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 720 ack_latency = ET_PCIV_ACK_LATENCY_256; 721 replay_timer = ET_PCIV_REPLAY_TIMER_256; 722 break; 723 724 default: 725 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 726 replay_timer = pci_read_config(sc->dev, 727 ET_PCIR_REPLAY_TIMER, 2); 728 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 729 ack_latency, replay_timer); 730 break; 731 } 732 if (ack_latency != 0) { 733 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 734 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 735 2); 736 } 737 738 /* 739 * Set L0s and L1 latency timer to 2us 740 */ 741 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 742 val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); 743 /* L0s exit latency : 2us */ 744 val |= 0x00005000; 745 /* L1 exit latency : 2us */ 746 val |= 0x00028000; 747 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 748 749 /* 750 * Set max read request size to 2048 bytes 751 */ 752 pci_set_max_read_req(sc->dev, 2048); 753 754 return (0); 755 } 756 757 static void 758 et_get_eaddr(device_t dev, uint8_t eaddr[]) 759 { 760 uint32_t val; 761 int i; 762 763 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 764 for (i = 0; i < 4; ++i) 765 eaddr[i] = (val >> (8 * i)) & 0xff; 766 767 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 768 for (; i < ETHER_ADDR_LEN; ++i) 769 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 770 } 771 772 static void 773 et_reset(struct et_softc *sc) 774 { 775 776 CSR_WRITE_4(sc, ET_MAC_CFG1, 777 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 778 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 779 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 780 781 CSR_WRITE_4(sc, ET_SWRST, 782 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 783 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 784 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 785 786 CSR_WRITE_4(sc, ET_MAC_CFG1, 787 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 788 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 789 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 790 /* Disable interrupts. */ 791 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 792 } 793 794 struct et_dmamap_arg { 795 bus_addr_t et_busaddr; 796 }; 797 798 static void 799 et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 800 { 801 struct et_dmamap_arg *ctx; 802 803 if (error) 804 return; 805 806 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 807 808 ctx = arg; 809 ctx->et_busaddr = segs->ds_addr; 810 } 811 812 static int 813 et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 814 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 815 const char *msg) 816 { 817 struct et_dmamap_arg ctx; 818 int error; 819 820 error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 821 BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 822 tag); 823 if (error != 0) { 824 device_printf(sc->dev, "could not create %s dma tag\n", msg); 825 return (error); 826 } 827 /* Allocate DMA'able memory for ring. */ 828 error = bus_dmamem_alloc(*tag, (void **)ring, 829 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 830 if (error != 0) { 831 device_printf(sc->dev, 832 "could not allocate DMA'able memory for %s\n", msg); 833 return (error); 834 } 835 /* Load the address of the ring. */ 836 ctx.et_busaddr = 0; 837 error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 838 &ctx, BUS_DMA_NOWAIT); 839 if (error != 0) { 840 device_printf(sc->dev, 841 "could not load DMA'able memory for %s\n", msg); 842 return (error); 843 } 844 *paddr = ctx.et_busaddr; 845 return (0); 846 } 847 848 static void 849 et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 850 bus_dmamap_t map, bus_addr_t *paddr) 851 { 852 853 if (*paddr != 0) { 854 bus_dmamap_unload(*tag, map); 855 *paddr = 0; 856 } 857 if (*ring != NULL) { 858 bus_dmamem_free(*tag, *ring, map); 859 *ring = NULL; 860 } 861 if (*tag) { 862 bus_dma_tag_destroy(*tag); 863 *tag = NULL; 864 } 865 } 866 867 static int 868 et_dma_alloc(struct et_softc *sc) 869 { 870 struct et_txdesc_ring *tx_ring; 871 struct et_rxdesc_ring *rx_ring; 872 struct et_rxstat_ring *rxst_ring; 873 struct et_rxstatus_data *rxsd; 874 struct et_rxbuf_data *rbd; 875 struct et_txbuf_data *tbd; 876 struct et_txstatus_data *txsd; 877 int i, error; 878 879 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 880 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 881 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 882 &sc->sc_dtag); 883 if (error != 0) { 884 device_printf(sc->dev, "could not allocate parent dma tag\n"); 885 return (error); 886 } 887 888 /* TX ring. */ 889 tx_ring = &sc->sc_tx_ring; 890 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 891 &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 892 &tx_ring->tr_paddr, "TX ring"); 893 if (error) 894 return (error); 895 896 /* TX status block. */ 897 txsd = &sc->sc_tx_status; 898 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 899 &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 900 &txsd->txsd_paddr, "TX status block"); 901 if (error) 902 return (error); 903 904 /* RX ring 0, used as to recive small sized frames. */ 905 rx_ring = &sc->sc_rx_ring[0]; 906 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 907 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 908 &rx_ring->rr_paddr, "RX ring 0"); 909 rx_ring->rr_posreg = ET_RX_RING0_POS; 910 if (error) 911 return (error); 912 913 /* RX ring 1, used as to store normal sized frames. */ 914 rx_ring = &sc->sc_rx_ring[1]; 915 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 916 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 917 &rx_ring->rr_paddr, "RX ring 1"); 918 rx_ring->rr_posreg = ET_RX_RING1_POS; 919 if (error) 920 return (error); 921 922 /* RX stat ring. */ 923 rxst_ring = &sc->sc_rxstat_ring; 924 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 925 &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 926 &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 927 if (error) 928 return (error); 929 930 /* RX status block. */ 931 rxsd = &sc->sc_rx_status; 932 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 933 sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 934 (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 935 &rxsd->rxsd_paddr, "RX status block"); 936 if (error) 937 return (error); 938 939 /* Create parent DMA tag for mbufs. */ 940 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 941 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 942 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 943 &sc->sc_mbuf_dtag); 944 if (error != 0) { 945 device_printf(sc->dev, 946 "could not allocate parent dma tag for mbuf\n"); 947 return (error); 948 } 949 950 /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 951 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 952 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 953 MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 954 if (error) { 955 device_printf(sc->dev, "could not create mini RX dma tag\n"); 956 return (error); 957 } 958 959 /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 960 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 961 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 962 MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 963 if (error) { 964 device_printf(sc->dev, "could not create RX dma tag\n"); 965 return (error); 966 } 967 968 /* Create DMA tag for TX mbufs. */ 969 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 970 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 971 MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 972 &sc->sc_tx_tag); 973 if (error) { 974 device_printf(sc->dev, "could not create TX dma tag\n"); 975 return (error); 976 } 977 978 /* Initialize RX ring 0. */ 979 rbd = &sc->sc_rx_data[0]; 980 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 981 rbd->rbd_newbuf = et_newbuf_hdr; 982 rbd->rbd_discard = et_rxbuf_discard; 983 rbd->rbd_softc = sc; 984 rbd->rbd_ring = &sc->sc_rx_ring[0]; 985 /* Create DMA maps for mini RX buffers, ring 0. */ 986 for (i = 0; i < ET_RX_NDESC; i++) { 987 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 988 &rbd->rbd_buf[i].rb_dmap); 989 if (error) { 990 device_printf(sc->dev, 991 "could not create DMA map for mini RX mbufs\n"); 992 return (error); 993 } 994 } 995 996 /* Create a spare DMA map for mini RX buffers, ring 0. */ 997 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 998 &sc->sc_rx_mini_sparemap); 999 if (error) { 1000 device_printf(sc->dev, 1001 "could not create spare DMA map for mini RX mbuf\n"); 1002 return (error); 1003 } 1004 1005 /* Initialize RX ring 1. */ 1006 rbd = &sc->sc_rx_data[1]; 1007 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 1008 rbd->rbd_newbuf = et_newbuf_cluster; 1009 rbd->rbd_discard = et_rxbuf_discard; 1010 rbd->rbd_softc = sc; 1011 rbd->rbd_ring = &sc->sc_rx_ring[1]; 1012 /* Create DMA maps for standard RX buffers, ring 1. */ 1013 for (i = 0; i < ET_RX_NDESC; i++) { 1014 error = bus_dmamap_create(sc->sc_rx_tag, 0, 1015 &rbd->rbd_buf[i].rb_dmap); 1016 if (error) { 1017 device_printf(sc->dev, 1018 "could not create DMA map for mini RX mbufs\n"); 1019 return (error); 1020 } 1021 } 1022 1023 /* Create a spare DMA map for standard RX buffers, ring 1. */ 1024 error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 1025 if (error) { 1026 device_printf(sc->dev, 1027 "could not create spare DMA map for RX mbuf\n"); 1028 return (error); 1029 } 1030 1031 /* Create DMA maps for TX buffers. */ 1032 tbd = &sc->sc_tx_data; 1033 for (i = 0; i < ET_TX_NDESC; i++) { 1034 error = bus_dmamap_create(sc->sc_tx_tag, 0, 1035 &tbd->tbd_buf[i].tb_dmap); 1036 if (error) { 1037 device_printf(sc->dev, 1038 "could not create DMA map for TX mbufs\n"); 1039 return (error); 1040 } 1041 } 1042 1043 return (0); 1044 } 1045 1046 static void 1047 et_dma_free(struct et_softc *sc) 1048 { 1049 struct et_txdesc_ring *tx_ring; 1050 struct et_rxdesc_ring *rx_ring; 1051 struct et_txstatus_data *txsd; 1052 struct et_rxstat_ring *rxst_ring; 1053 struct et_rxbuf_data *rbd; 1054 struct et_txbuf_data *tbd; 1055 int i; 1056 1057 /* Destroy DMA maps for mini RX buffers, ring 0. */ 1058 rbd = &sc->sc_rx_data[0]; 1059 for (i = 0; i < ET_RX_NDESC; i++) { 1060 if (rbd->rbd_buf[i].rb_dmap) { 1061 bus_dmamap_destroy(sc->sc_rx_mini_tag, 1062 rbd->rbd_buf[i].rb_dmap); 1063 rbd->rbd_buf[i].rb_dmap = NULL; 1064 } 1065 } 1066 if (sc->sc_rx_mini_sparemap) { 1067 bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 1068 sc->sc_rx_mini_sparemap = NULL; 1069 } 1070 if (sc->sc_rx_mini_tag) { 1071 bus_dma_tag_destroy(sc->sc_rx_mini_tag); 1072 sc->sc_rx_mini_tag = NULL; 1073 } 1074 1075 /* Destroy DMA maps for standard RX buffers, ring 1. */ 1076 rbd = &sc->sc_rx_data[1]; 1077 for (i = 0; i < ET_RX_NDESC; i++) { 1078 if (rbd->rbd_buf[i].rb_dmap) { 1079 bus_dmamap_destroy(sc->sc_rx_tag, 1080 rbd->rbd_buf[i].rb_dmap); 1081 rbd->rbd_buf[i].rb_dmap = NULL; 1082 } 1083 } 1084 if (sc->sc_rx_sparemap) { 1085 bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 1086 sc->sc_rx_sparemap = NULL; 1087 } 1088 if (sc->sc_rx_tag) { 1089 bus_dma_tag_destroy(sc->sc_rx_tag); 1090 sc->sc_rx_tag = NULL; 1091 } 1092 1093 /* Destroy DMA maps for TX buffers. */ 1094 tbd = &sc->sc_tx_data; 1095 for (i = 0; i < ET_TX_NDESC; i++) { 1096 if (tbd->tbd_buf[i].tb_dmap) { 1097 bus_dmamap_destroy(sc->sc_tx_tag, 1098 tbd->tbd_buf[i].tb_dmap); 1099 tbd->tbd_buf[i].tb_dmap = NULL; 1100 } 1101 } 1102 if (sc->sc_tx_tag) { 1103 bus_dma_tag_destroy(sc->sc_tx_tag); 1104 sc->sc_tx_tag = NULL; 1105 } 1106 1107 /* Destroy mini RX ring, ring 0. */ 1108 rx_ring = &sc->sc_rx_ring[0]; 1109 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1110 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1111 /* Destroy standard RX ring, ring 1. */ 1112 rx_ring = &sc->sc_rx_ring[1]; 1113 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1114 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1115 /* Destroy RX stat ring. */ 1116 rxst_ring = &sc->sc_rxstat_ring; 1117 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1118 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1119 /* Destroy RX status block. */ 1120 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1121 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1122 /* Destroy TX ring. */ 1123 tx_ring = &sc->sc_tx_ring; 1124 et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1125 tx_ring->tr_dmap, &tx_ring->tr_paddr); 1126 /* Destroy TX status block. */ 1127 txsd = &sc->sc_tx_status; 1128 et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1129 txsd->txsd_dmap, &txsd->txsd_paddr); 1130 1131 /* Destroy the parent tag. */ 1132 if (sc->sc_dtag) { 1133 bus_dma_tag_destroy(sc->sc_dtag); 1134 sc->sc_dtag = NULL; 1135 } 1136 } 1137 1138 static void 1139 et_chip_attach(struct et_softc *sc) 1140 { 1141 uint32_t val; 1142 1143 /* 1144 * Perform minimal initialization 1145 */ 1146 1147 /* Disable loopback */ 1148 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1149 1150 /* Reset MAC */ 1151 CSR_WRITE_4(sc, ET_MAC_CFG1, 1152 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1153 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1154 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1155 1156 /* 1157 * Setup half duplex mode 1158 */ 1159 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1160 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1161 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1162 ET_MAC_HDX_EXC_DEFER; 1163 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1164 1165 /* Clear MAC control */ 1166 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1167 1168 /* Reset MII */ 1169 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1170 1171 /* Bring MAC out of reset state */ 1172 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1173 1174 /* Enable memory controllers */ 1175 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1176 } 1177 1178 static void 1179 et_intr(void *xsc) 1180 { 1181 struct et_softc *sc; 1182 struct ifnet *ifp; 1183 uint32_t status; 1184 1185 sc = xsc; 1186 ET_LOCK(sc); 1187 ifp = sc->ifp; 1188 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1189 goto done; 1190 1191 status = CSR_READ_4(sc, ET_INTR_STATUS); 1192 if ((status & ET_INTRS) == 0) 1193 goto done; 1194 1195 /* Disable further interrupts. */ 1196 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 1197 1198 if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) { 1199 device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n", 1200 status); 1201 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1202 et_init_locked(sc); 1203 ET_UNLOCK(sc); 1204 return; 1205 } 1206 if (status & ET_INTR_RXDMA) 1207 et_rxeof(sc); 1208 if (status & (ET_INTR_TXDMA | ET_INTR_TIMER)) 1209 et_txeof(sc); 1210 if (status & ET_INTR_TIMER) 1211 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1212 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1213 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1214 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1215 et_start_locked(ifp); 1216 } 1217 done: 1218 ET_UNLOCK(sc); 1219 } 1220 1221 static void 1222 et_init_locked(struct et_softc *sc) 1223 { 1224 struct ifnet *ifp; 1225 int error; 1226 1227 ET_LOCK_ASSERT(sc); 1228 1229 ifp = sc->ifp; 1230 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1231 return; 1232 1233 et_stop(sc); 1234 et_reset(sc); 1235 1236 et_init_tx_ring(sc); 1237 error = et_init_rx_ring(sc); 1238 if (error) 1239 return; 1240 1241 error = et_chip_init(sc); 1242 if (error) 1243 goto fail; 1244 1245 /* 1246 * Start TX/RX DMA engine 1247 */ 1248 error = et_start_rxdma(sc); 1249 if (error) 1250 return; 1251 1252 error = et_start_txdma(sc); 1253 if (error) 1254 return; 1255 1256 /* Enable interrupts. */ 1257 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1258 1259 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1260 1261 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1262 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1263 1264 sc->sc_flags &= ~ET_FLAG_LINK; 1265 et_ifmedia_upd_locked(ifp); 1266 1267 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1268 1269 fail: 1270 if (error) 1271 et_stop(sc); 1272 } 1273 1274 static void 1275 et_init(void *xsc) 1276 { 1277 struct et_softc *sc = xsc; 1278 1279 ET_LOCK(sc); 1280 et_init_locked(sc); 1281 ET_UNLOCK(sc); 1282 } 1283 1284 static int 1285 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1286 { 1287 struct et_softc *sc; 1288 struct mii_data *mii; 1289 struct ifreq *ifr; 1290 int error, mask, max_framelen; 1291 1292 sc = ifp->if_softc; 1293 ifr = (struct ifreq *)data; 1294 error = 0; 1295 1296 /* XXX LOCKSUSED */ 1297 switch (cmd) { 1298 case SIOCSIFFLAGS: 1299 ET_LOCK(sc); 1300 if (ifp->if_flags & IFF_UP) { 1301 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1302 if ((ifp->if_flags ^ sc->sc_if_flags) & 1303 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1304 et_setmulti(sc); 1305 } else { 1306 et_init_locked(sc); 1307 } 1308 } else { 1309 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1310 et_stop(sc); 1311 } 1312 sc->sc_if_flags = ifp->if_flags; 1313 ET_UNLOCK(sc); 1314 break; 1315 1316 case SIOCSIFMEDIA: 1317 case SIOCGIFMEDIA: 1318 mii = device_get_softc(sc->sc_miibus); 1319 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1320 break; 1321 1322 case SIOCADDMULTI: 1323 case SIOCDELMULTI: 1324 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1325 ET_LOCK(sc); 1326 et_setmulti(sc); 1327 ET_UNLOCK(sc); 1328 } 1329 break; 1330 1331 case SIOCSIFMTU: 1332 ET_LOCK(sc); 1333 #if 0 1334 if (sc->sc_flags & ET_FLAG_JUMBO) 1335 max_framelen = ET_JUMBO_FRAMELEN; 1336 else 1337 #endif 1338 max_framelen = MCLBYTES - 1; 1339 1340 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1341 error = EOPNOTSUPP; 1342 ET_UNLOCK(sc); 1343 break; 1344 } 1345 1346 if (ifp->if_mtu != ifr->ifr_mtu) { 1347 ifp->if_mtu = ifr->ifr_mtu; 1348 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1349 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1350 et_init_locked(sc); 1351 } 1352 } 1353 ET_UNLOCK(sc); 1354 break; 1355 1356 case SIOCSIFCAP: 1357 ET_LOCK(sc); 1358 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1359 if ((mask & IFCAP_TXCSUM) != 0 && 1360 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1361 ifp->if_capenable ^= IFCAP_TXCSUM; 1362 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1363 ifp->if_hwassist |= ET_CSUM_FEATURES; 1364 else 1365 ifp->if_hwassist &= ~ET_CSUM_FEATURES; 1366 } 1367 ET_UNLOCK(sc); 1368 break; 1369 1370 default: 1371 error = ether_ioctl(ifp, cmd, data); 1372 break; 1373 } 1374 return (error); 1375 } 1376 1377 static void 1378 et_start_locked(struct ifnet *ifp) 1379 { 1380 struct et_softc *sc; 1381 struct mbuf *m_head = NULL; 1382 struct et_txdesc_ring *tx_ring; 1383 struct et_txbuf_data *tbd; 1384 uint32_t tx_ready_pos; 1385 int enq; 1386 1387 sc = ifp->if_softc; 1388 ET_LOCK_ASSERT(sc); 1389 1390 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1391 IFF_DRV_RUNNING || 1392 (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) != 1393 (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) 1394 return; 1395 1396 /* 1397 * Driver does not request TX completion interrupt for every 1398 * queued frames to prevent generating excessive interrupts. 1399 * This means driver may wait for TX completion interrupt even 1400 * though some frames were successfully transmitted. Reclaiming 1401 * transmitted frames will ensure driver see all available 1402 * descriptors. 1403 */ 1404 tbd = &sc->sc_tx_data; 1405 if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3) 1406 et_txeof(sc); 1407 1408 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1409 if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 1410 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1411 break; 1412 } 1413 1414 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1415 if (m_head == NULL) 1416 break; 1417 1418 if (et_encap(sc, &m_head)) { 1419 if (m_head == NULL) { 1420 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1421 break; 1422 } 1423 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1424 if (tbd->tbd_used > 0) 1425 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1426 break; 1427 } 1428 enq++; 1429 ETHER_BPF_MTAP(ifp, m_head); 1430 } 1431 1432 if (enq > 0) { 1433 tx_ring = &sc->sc_tx_ring; 1434 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1435 BUS_DMASYNC_PREWRITE); 1436 tx_ready_pos = tx_ring->tr_ready_index & 1437 ET_TX_READY_POS_INDEX_MASK; 1438 if (tx_ring->tr_ready_wrap) 1439 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1440 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1441 sc->watchdog_timer = 5; 1442 } 1443 } 1444 1445 static void 1446 et_start(struct ifnet *ifp) 1447 { 1448 struct et_softc *sc; 1449 1450 sc = ifp->if_softc; 1451 ET_LOCK(sc); 1452 et_start_locked(ifp); 1453 ET_UNLOCK(sc); 1454 } 1455 1456 static int 1457 et_watchdog(struct et_softc *sc) 1458 { 1459 uint32_t status; 1460 1461 ET_LOCK_ASSERT(sc); 1462 1463 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1464 return (0); 1465 1466 bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1467 BUS_DMASYNC_POSTREAD); 1468 status = le32toh(*(sc->sc_tx_status.txsd_status)); 1469 if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1470 status); 1471 1472 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 1473 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1474 et_init_locked(sc); 1475 return (EJUSTRETURN); 1476 } 1477 1478 static int 1479 et_stop_rxdma(struct et_softc *sc) 1480 { 1481 1482 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1483 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1484 1485 DELAY(5); 1486 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1487 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1488 return (ETIMEDOUT); 1489 } 1490 return (0); 1491 } 1492 1493 static int 1494 et_stop_txdma(struct et_softc *sc) 1495 { 1496 1497 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1498 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1499 return (0); 1500 } 1501 1502 static void 1503 et_free_tx_ring(struct et_softc *sc) 1504 { 1505 struct et_txbuf_data *tbd; 1506 struct et_txbuf *tb; 1507 int i; 1508 1509 tbd = &sc->sc_tx_data; 1510 for (i = 0; i < ET_TX_NDESC; ++i) { 1511 tb = &tbd->tbd_buf[i]; 1512 if (tb->tb_mbuf != NULL) { 1513 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1514 BUS_DMASYNC_POSTWRITE); 1515 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1516 m_freem(tb->tb_mbuf); 1517 tb->tb_mbuf = NULL; 1518 } 1519 } 1520 } 1521 1522 static void 1523 et_free_rx_ring(struct et_softc *sc) 1524 { 1525 struct et_rxbuf_data *rbd; 1526 struct et_rxdesc_ring *rx_ring; 1527 struct et_rxbuf *rb; 1528 int i; 1529 1530 /* Ring 0 */ 1531 rx_ring = &sc->sc_rx_ring[0]; 1532 rbd = &sc->sc_rx_data[0]; 1533 for (i = 0; i < ET_RX_NDESC; ++i) { 1534 rb = &rbd->rbd_buf[i]; 1535 if (rb->rb_mbuf != NULL) { 1536 bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1537 BUS_DMASYNC_POSTREAD); 1538 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 1539 m_freem(rb->rb_mbuf); 1540 rb->rb_mbuf = NULL; 1541 } 1542 } 1543 1544 /* Ring 1 */ 1545 rx_ring = &sc->sc_rx_ring[1]; 1546 rbd = &sc->sc_rx_data[1]; 1547 for (i = 0; i < ET_RX_NDESC; ++i) { 1548 rb = &rbd->rbd_buf[i]; 1549 if (rb->rb_mbuf != NULL) { 1550 bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1551 BUS_DMASYNC_POSTREAD); 1552 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1553 m_freem(rb->rb_mbuf); 1554 rb->rb_mbuf = NULL; 1555 } 1556 } 1557 } 1558 1559 static u_int 1560 et_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1561 { 1562 uint32_t h, *hp, *hash = arg; 1563 1564 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 1565 h = (h & 0x3f800000) >> 23; 1566 1567 hp = &hash[0]; 1568 if (h >= 32 && h < 64) { 1569 h -= 32; 1570 hp = &hash[1]; 1571 } else if (h >= 64 && h < 96) { 1572 h -= 64; 1573 hp = &hash[2]; 1574 } else if (h >= 96) { 1575 h -= 96; 1576 hp = &hash[3]; 1577 } 1578 *hp |= (1 << h); 1579 1580 return (1); 1581 } 1582 1583 static void 1584 et_setmulti(struct et_softc *sc) 1585 { 1586 struct ifnet *ifp; 1587 uint32_t hash[4] = { 0, 0, 0, 0 }; 1588 uint32_t rxmac_ctrl, pktfilt; 1589 int i, count; 1590 1591 ET_LOCK_ASSERT(sc); 1592 ifp = sc->ifp; 1593 1594 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1595 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1596 1597 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1598 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1599 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1600 goto back; 1601 } 1602 1603 count = if_foreach_llmaddr(ifp, et_hash_maddr, &hash); 1604 1605 for (i = 0; i < 4; ++i) 1606 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1607 1608 if (count > 0) 1609 pktfilt |= ET_PKTFILT_MCAST; 1610 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1611 back: 1612 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1613 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1614 } 1615 1616 static int 1617 et_chip_init(struct et_softc *sc) 1618 { 1619 struct ifnet *ifp; 1620 uint32_t rxq_end; 1621 int error, frame_len, rxmem_size; 1622 1623 ifp = sc->ifp; 1624 /* 1625 * Split 16Kbytes internal memory between TX and RX 1626 * according to frame length. 1627 */ 1628 frame_len = ET_FRAMELEN(ifp->if_mtu); 1629 if (frame_len < 2048) { 1630 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1631 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1632 rxmem_size = ET_MEM_SIZE / 2; 1633 } else { 1634 rxmem_size = ET_MEM_SIZE - 1635 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1636 } 1637 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1638 1639 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1640 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1641 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1642 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1643 1644 /* No loopback */ 1645 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1646 1647 /* Clear MSI configure */ 1648 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1649 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1650 1651 /* Disable timer */ 1652 CSR_WRITE_4(sc, ET_TIMER, 0); 1653 1654 /* Initialize MAC */ 1655 et_init_mac(sc); 1656 1657 /* Enable memory controllers */ 1658 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1659 1660 /* Initialize RX MAC */ 1661 et_init_rxmac(sc); 1662 1663 /* Initialize TX MAC */ 1664 et_init_txmac(sc); 1665 1666 /* Initialize RX DMA engine */ 1667 error = et_init_rxdma(sc); 1668 if (error) 1669 return (error); 1670 1671 /* Initialize TX DMA engine */ 1672 error = et_init_txdma(sc); 1673 if (error) 1674 return (error); 1675 1676 return (0); 1677 } 1678 1679 static void 1680 et_init_tx_ring(struct et_softc *sc) 1681 { 1682 struct et_txdesc_ring *tx_ring; 1683 struct et_txbuf_data *tbd; 1684 struct et_txstatus_data *txsd; 1685 1686 tx_ring = &sc->sc_tx_ring; 1687 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1688 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1689 BUS_DMASYNC_PREWRITE); 1690 1691 tbd = &sc->sc_tx_data; 1692 tbd->tbd_start_index = 0; 1693 tbd->tbd_start_wrap = 0; 1694 tbd->tbd_used = 0; 1695 1696 txsd = &sc->sc_tx_status; 1697 bzero(txsd->txsd_status, sizeof(uint32_t)); 1698 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1699 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1700 } 1701 1702 static int 1703 et_init_rx_ring(struct et_softc *sc) 1704 { 1705 struct et_rxstatus_data *rxsd; 1706 struct et_rxstat_ring *rxst_ring; 1707 struct et_rxbuf_data *rbd; 1708 int i, error, n; 1709 1710 for (n = 0; n < ET_RX_NRING; ++n) { 1711 rbd = &sc->sc_rx_data[n]; 1712 for (i = 0; i < ET_RX_NDESC; ++i) { 1713 error = rbd->rbd_newbuf(rbd, i); 1714 if (error) { 1715 if_printf(sc->ifp, "%d ring %d buf, " 1716 "newbuf failed: %d\n", n, i, error); 1717 return (error); 1718 } 1719 } 1720 } 1721 1722 rxsd = &sc->sc_rx_status; 1723 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1724 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1725 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1726 1727 rxst_ring = &sc->sc_rxstat_ring; 1728 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1729 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1730 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1731 1732 return (0); 1733 } 1734 1735 static int 1736 et_init_rxdma(struct et_softc *sc) 1737 { 1738 struct et_rxstatus_data *rxsd; 1739 struct et_rxstat_ring *rxst_ring; 1740 struct et_rxdesc_ring *rx_ring; 1741 int error; 1742 1743 error = et_stop_rxdma(sc); 1744 if (error) { 1745 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1746 return (error); 1747 } 1748 1749 /* 1750 * Install RX status 1751 */ 1752 rxsd = &sc->sc_rx_status; 1753 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1754 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1755 1756 /* 1757 * Install RX stat ring 1758 */ 1759 rxst_ring = &sc->sc_rxstat_ring; 1760 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1761 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1762 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1763 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1764 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1765 1766 /* Match ET_RXSTAT_POS */ 1767 rxst_ring->rsr_index = 0; 1768 rxst_ring->rsr_wrap = 0; 1769 1770 /* 1771 * Install the 2nd RX descriptor ring 1772 */ 1773 rx_ring = &sc->sc_rx_ring[1]; 1774 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1775 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1776 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1777 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1778 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1779 1780 /* Match ET_RX_RING1_POS */ 1781 rx_ring->rr_index = 0; 1782 rx_ring->rr_wrap = 1; 1783 1784 /* 1785 * Install the 1st RX descriptor ring 1786 */ 1787 rx_ring = &sc->sc_rx_ring[0]; 1788 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1789 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1790 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1791 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1792 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1793 1794 /* Match ET_RX_RING0_POS */ 1795 rx_ring->rr_index = 0; 1796 rx_ring->rr_wrap = 1; 1797 1798 /* 1799 * RX intr moderation 1800 */ 1801 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1802 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1803 1804 return (0); 1805 } 1806 1807 static int 1808 et_init_txdma(struct et_softc *sc) 1809 { 1810 struct et_txdesc_ring *tx_ring; 1811 struct et_txstatus_data *txsd; 1812 int error; 1813 1814 error = et_stop_txdma(sc); 1815 if (error) { 1816 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1817 return (error); 1818 } 1819 1820 /* 1821 * Install TX descriptor ring 1822 */ 1823 tx_ring = &sc->sc_tx_ring; 1824 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1825 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1826 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1827 1828 /* 1829 * Install TX status 1830 */ 1831 txsd = &sc->sc_tx_status; 1832 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1833 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1834 1835 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1836 1837 /* Match ET_TX_READY_POS */ 1838 tx_ring->tr_ready_index = 0; 1839 tx_ring->tr_ready_wrap = 0; 1840 1841 return (0); 1842 } 1843 1844 static void 1845 et_init_mac(struct et_softc *sc) 1846 { 1847 struct ifnet *ifp; 1848 const uint8_t *eaddr; 1849 uint32_t val; 1850 1851 /* Reset MAC */ 1852 CSR_WRITE_4(sc, ET_MAC_CFG1, 1853 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1854 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1855 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1856 1857 /* 1858 * Setup inter packet gap 1859 */ 1860 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1861 (88 << ET_IPG_NONB2B_2_SHIFT) | 1862 (80 << ET_IPG_MINIFG_SHIFT) | 1863 (96 << ET_IPG_B2B_SHIFT); 1864 CSR_WRITE_4(sc, ET_IPG, val); 1865 1866 /* 1867 * Setup half duplex mode 1868 */ 1869 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1870 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1871 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1872 ET_MAC_HDX_EXC_DEFER; 1873 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1874 1875 /* Clear MAC control */ 1876 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1877 1878 /* Reset MII */ 1879 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1880 1881 /* 1882 * Set MAC address 1883 */ 1884 ifp = sc->ifp; 1885 eaddr = IF_LLADDR(ifp); 1886 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1887 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1888 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1889 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1890 1891 /* Set max frame length */ 1892 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 1893 1894 /* Bring MAC out of reset state */ 1895 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1896 } 1897 1898 static void 1899 et_init_rxmac(struct et_softc *sc) 1900 { 1901 struct ifnet *ifp; 1902 const uint8_t *eaddr; 1903 uint32_t val; 1904 int i; 1905 1906 /* Disable RX MAC and WOL */ 1907 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1908 1909 /* 1910 * Clear all WOL related registers 1911 */ 1912 for (i = 0; i < 3; ++i) 1913 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1914 for (i = 0; i < 20; ++i) 1915 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1916 1917 /* 1918 * Set WOL source address. XXX is this necessary? 1919 */ 1920 ifp = sc->ifp; 1921 eaddr = IF_LLADDR(ifp); 1922 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1923 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1924 val = (eaddr[0] << 8) | eaddr[1]; 1925 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1926 1927 /* Clear packet filters */ 1928 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1929 1930 /* No ucast filtering */ 1931 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1932 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1933 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1934 1935 if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 1936 /* 1937 * In order to transmit jumbo packets greater than 1938 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1939 * RX MAC and RX DMA needs to be reduced in size to 1940 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1941 * order to implement this, we must use "cut through" 1942 * mode in the RX MAC, which chops packets down into 1943 * segments. In this case we selected 256 bytes, 1944 * since this is the size of the PCI-Express TLP's 1945 * that the ET1310 uses. 1946 */ 1947 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1948 ET_RXMAC_MC_SEGSZ_ENABLE; 1949 } else { 1950 val = 0; 1951 } 1952 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1953 1954 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1955 1956 /* Initialize RX MAC management register */ 1957 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1958 1959 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1960 1961 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1962 ET_RXMAC_MGT_PASS_ECRC | 1963 ET_RXMAC_MGT_PASS_ELEN | 1964 ET_RXMAC_MGT_PASS_ETRUNC | 1965 ET_RXMAC_MGT_CHECK_PKT); 1966 1967 /* 1968 * Configure runt filtering (may not work on certain chip generation) 1969 */ 1970 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1971 ET_PKTFILT_MINLEN_MASK; 1972 val |= ET_PKTFILT_FRAG; 1973 CSR_WRITE_4(sc, ET_PKTFILT, val); 1974 1975 /* Enable RX MAC but leave WOL disabled */ 1976 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1977 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1978 1979 /* 1980 * Setup multicast hash and allmulti/promisc mode 1981 */ 1982 et_setmulti(sc); 1983 } 1984 1985 static void 1986 et_init_txmac(struct et_softc *sc) 1987 { 1988 1989 /* Disable TX MAC and FC(?) */ 1990 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1991 1992 /* 1993 * Initialize pause time. 1994 * This register should be set before XON/XOFF frame is 1995 * sent by driver. 1996 */ 1997 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT); 1998 1999 /* Enable TX MAC but leave FC(?) diabled */ 2000 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 2001 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 2002 } 2003 2004 static int 2005 et_start_rxdma(struct et_softc *sc) 2006 { 2007 uint32_t val; 2008 2009 val = (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 2010 ET_RXDMA_CTRL_RING0_ENABLE; 2011 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 2012 ET_RXDMA_CTRL_RING1_ENABLE; 2013 2014 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 2015 2016 DELAY(5); 2017 2018 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 2019 if_printf(sc->ifp, "can't start RX DMA engine\n"); 2020 return (ETIMEDOUT); 2021 } 2022 return (0); 2023 } 2024 2025 static int 2026 et_start_txdma(struct et_softc *sc) 2027 { 2028 2029 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 2030 return (0); 2031 } 2032 2033 static void 2034 et_rxeof(struct et_softc *sc) 2035 { 2036 struct et_rxstatus_data *rxsd; 2037 struct et_rxstat_ring *rxst_ring; 2038 struct et_rxbuf_data *rbd; 2039 struct et_rxdesc_ring *rx_ring; 2040 struct et_rxstat *st; 2041 struct ifnet *ifp; 2042 struct mbuf *m; 2043 uint32_t rxstat_pos, rxring_pos; 2044 uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 2045 int buflen, buf_idx, npost[2], ring_idx; 2046 int rxst_index, rxst_wrap; 2047 2048 ET_LOCK_ASSERT(sc); 2049 2050 ifp = sc->ifp; 2051 rxsd = &sc->sc_rx_status; 2052 rxst_ring = &sc->sc_rxstat_ring; 2053 2054 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2055 return; 2056 2057 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2058 BUS_DMASYNC_POSTREAD); 2059 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2060 BUS_DMASYNC_POSTREAD); 2061 2062 npost[0] = npost[1] = 0; 2063 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 2064 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 2065 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 2066 ET_RXS_STATRING_INDEX_SHIFT; 2067 2068 while (rxst_index != rxst_ring->rsr_index || 2069 rxst_wrap != rxst_ring->rsr_wrap) { 2070 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2071 break; 2072 2073 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 2074 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 2075 rxst_info1 = le32toh(st->rxst_info1); 2076 rxst_info2 = le32toh(st->rxst_info2); 2077 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 2078 ET_RXST_INFO2_LEN_SHIFT; 2079 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 2080 ET_RXST_INFO2_BUFIDX_SHIFT; 2081 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 2082 ET_RXST_INFO2_RINGIDX_SHIFT; 2083 2084 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 2085 rxst_ring->rsr_index = 0; 2086 rxst_ring->rsr_wrap ^= 1; 2087 } 2088 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 2089 if (rxst_ring->rsr_wrap) 2090 rxstat_pos |= ET_RXSTAT_POS_WRAP; 2091 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 2092 2093 if (ring_idx >= ET_RX_NRING) { 2094 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2095 if_printf(ifp, "invalid ring index %d\n", ring_idx); 2096 continue; 2097 } 2098 if (buf_idx >= ET_RX_NDESC) { 2099 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2100 if_printf(ifp, "invalid buf index %d\n", buf_idx); 2101 continue; 2102 } 2103 2104 rbd = &sc->sc_rx_data[ring_idx]; 2105 m = rbd->rbd_buf[buf_idx].rb_mbuf; 2106 if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 2107 /* Discard errored frame. */ 2108 rbd->rbd_discard(rbd, buf_idx); 2109 } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 2110 /* No available mbufs, discard it. */ 2111 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2112 rbd->rbd_discard(rbd, buf_idx); 2113 } else { 2114 buflen -= ETHER_CRC_LEN; 2115 if (buflen < ETHER_HDR_LEN) { 2116 m_freem(m); 2117 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2118 } else { 2119 m->m_pkthdr.len = m->m_len = buflen; 2120 m->m_pkthdr.rcvif = ifp; 2121 ET_UNLOCK(sc); 2122 ifp->if_input(ifp, m); 2123 ET_LOCK(sc); 2124 } 2125 } 2126 2127 rx_ring = &sc->sc_rx_ring[ring_idx]; 2128 if (buf_idx != rx_ring->rr_index) { 2129 if_printf(ifp, 2130 "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 2131 ring_idx, buf_idx, rx_ring->rr_index); 2132 } 2133 2134 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2135 if (++rx_ring->rr_index == ET_RX_NDESC) { 2136 rx_ring->rr_index = 0; 2137 rx_ring->rr_wrap ^= 1; 2138 } 2139 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2140 if (rx_ring->rr_wrap) 2141 rxring_pos |= ET_RX_RING_POS_WRAP; 2142 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2143 } 2144 2145 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2146 BUS_DMASYNC_PREREAD); 2147 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2148 BUS_DMASYNC_PREREAD); 2149 } 2150 2151 static int 2152 et_encap(struct et_softc *sc, struct mbuf **m0) 2153 { 2154 struct et_txdesc_ring *tx_ring; 2155 struct et_txbuf_data *tbd; 2156 struct et_txdesc *td; 2157 struct mbuf *m; 2158 bus_dma_segment_t segs[ET_NSEG_MAX]; 2159 bus_dmamap_t map; 2160 uint32_t csum_flags, last_td_ctrl2; 2161 int error, i, idx, first_idx, last_idx, nsegs; 2162 2163 tx_ring = &sc->sc_tx_ring; 2164 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2165 tbd = &sc->sc_tx_data; 2166 first_idx = tx_ring->tr_ready_index; 2167 map = tbd->tbd_buf[first_idx].tb_dmap; 2168 2169 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2170 0); 2171 if (error == EFBIG) { 2172 m = m_collapse(*m0, M_NOWAIT, ET_NSEG_MAX); 2173 if (m == NULL) { 2174 m_freem(*m0); 2175 *m0 = NULL; 2176 return (ENOMEM); 2177 } 2178 *m0 = m; 2179 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2180 &nsegs, 0); 2181 if (error != 0) { 2182 m_freem(*m0); 2183 *m0 = NULL; 2184 return (error); 2185 } 2186 } else if (error != 0) 2187 return (error); 2188 2189 /* Check for descriptor overruns. */ 2190 if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2191 bus_dmamap_unload(sc->sc_tx_tag, map); 2192 return (ENOBUFS); 2193 } 2194 bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2195 2196 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2197 sc->sc_tx += nsegs; 2198 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2199 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2200 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2201 } 2202 2203 m = *m0; 2204 csum_flags = 0; 2205 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2206 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2207 csum_flags |= ET_TDCTRL2_CSUM_IP; 2208 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2209 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2210 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2211 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2212 } 2213 last_idx = -1; 2214 for (i = 0; i < nsegs; ++i) { 2215 idx = (first_idx + i) % ET_TX_NDESC; 2216 td = &tx_ring->tr_desc[idx]; 2217 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2218 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2219 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2220 if (i == nsegs - 1) { 2221 /* Last frag */ 2222 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2223 last_idx = idx; 2224 } else 2225 td->td_ctrl2 = htole32(csum_flags); 2226 2227 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2228 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2229 tx_ring->tr_ready_index = 0; 2230 tx_ring->tr_ready_wrap ^= 1; 2231 } 2232 } 2233 td = &tx_ring->tr_desc[first_idx]; 2234 /* First frag */ 2235 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 2236 2237 MPASS(last_idx >= 0); 2238 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2239 tbd->tbd_buf[last_idx].tb_dmap = map; 2240 tbd->tbd_buf[last_idx].tb_mbuf = m; 2241 2242 tbd->tbd_used += nsegs; 2243 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2244 2245 return (0); 2246 } 2247 2248 static void 2249 et_txeof(struct et_softc *sc) 2250 { 2251 struct et_txdesc_ring *tx_ring; 2252 struct et_txbuf_data *tbd; 2253 struct et_txbuf *tb; 2254 struct ifnet *ifp; 2255 uint32_t tx_done; 2256 int end, wrap; 2257 2258 ET_LOCK_ASSERT(sc); 2259 2260 ifp = sc->ifp; 2261 tx_ring = &sc->sc_tx_ring; 2262 tbd = &sc->sc_tx_data; 2263 2264 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2265 return; 2266 2267 if (tbd->tbd_used == 0) 2268 return; 2269 2270 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2271 BUS_DMASYNC_POSTWRITE); 2272 2273 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2274 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2275 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2276 2277 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2278 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2279 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2280 if (tb->tb_mbuf != NULL) { 2281 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2282 BUS_DMASYNC_POSTWRITE); 2283 bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 2284 m_freem(tb->tb_mbuf); 2285 tb->tb_mbuf = NULL; 2286 } 2287 2288 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2289 tbd->tbd_start_index = 0; 2290 tbd->tbd_start_wrap ^= 1; 2291 } 2292 2293 MPASS(tbd->tbd_used > 0); 2294 tbd->tbd_used--; 2295 } 2296 2297 if (tbd->tbd_used == 0) 2298 sc->watchdog_timer = 0; 2299 if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 2300 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2301 } 2302 2303 static void 2304 et_tick(void *xsc) 2305 { 2306 struct et_softc *sc; 2307 struct mii_data *mii; 2308 2309 sc = xsc; 2310 ET_LOCK_ASSERT(sc); 2311 mii = device_get_softc(sc->sc_miibus); 2312 2313 mii_tick(mii); 2314 et_stats_update(sc); 2315 if (et_watchdog(sc) == EJUSTRETURN) 2316 return; 2317 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2318 } 2319 2320 static int 2321 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 2322 { 2323 struct et_softc *sc; 2324 struct et_rxdesc *desc; 2325 struct et_rxbuf *rb; 2326 struct mbuf *m; 2327 bus_dma_segment_t segs[1]; 2328 bus_dmamap_t dmap; 2329 int nsegs; 2330 2331 MPASS(buf_idx < ET_RX_NDESC); 2332 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2333 if (m == NULL) 2334 return (ENOBUFS); 2335 m->m_len = m->m_pkthdr.len = MCLBYTES; 2336 m_adj(m, ETHER_ALIGN); 2337 2338 sc = rbd->rbd_softc; 2339 rb = &rbd->rbd_buf[buf_idx]; 2340 2341 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2342 segs, &nsegs, 0) != 0) { 2343 m_freem(m); 2344 return (ENOBUFS); 2345 } 2346 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2347 2348 if (rb->rb_mbuf != NULL) { 2349 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 2350 BUS_DMASYNC_POSTREAD); 2351 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 2352 } 2353 dmap = rb->rb_dmap; 2354 rb->rb_dmap = sc->sc_rx_sparemap; 2355 sc->sc_rx_sparemap = dmap; 2356 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2357 2358 rb->rb_mbuf = m; 2359 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2360 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2361 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2362 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2363 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2364 BUS_DMASYNC_PREWRITE); 2365 return (0); 2366 } 2367 2368 static void 2369 et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2370 { 2371 struct et_rxdesc *desc; 2372 2373 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2374 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2375 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2376 BUS_DMASYNC_PREWRITE); 2377 } 2378 2379 static int 2380 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2381 { 2382 struct et_softc *sc; 2383 struct et_rxdesc *desc; 2384 struct et_rxbuf *rb; 2385 struct mbuf *m; 2386 bus_dma_segment_t segs[1]; 2387 bus_dmamap_t dmap; 2388 int nsegs; 2389 2390 MPASS(buf_idx < ET_RX_NDESC); 2391 MGETHDR(m, M_NOWAIT, MT_DATA); 2392 if (m == NULL) 2393 return (ENOBUFS); 2394 m->m_len = m->m_pkthdr.len = MHLEN; 2395 m_adj(m, ETHER_ALIGN); 2396 2397 sc = rbd->rbd_softc; 2398 rb = &rbd->rbd_buf[buf_idx]; 2399 2400 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2401 m, segs, &nsegs, 0) != 0) { 2402 m_freem(m); 2403 return (ENOBUFS); 2404 } 2405 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2406 2407 if (rb->rb_mbuf != NULL) { 2408 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2409 BUS_DMASYNC_POSTREAD); 2410 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2411 } 2412 dmap = rb->rb_dmap; 2413 rb->rb_dmap = sc->sc_rx_mini_sparemap; 2414 sc->sc_rx_mini_sparemap = dmap; 2415 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2416 2417 rb->rb_mbuf = m; 2418 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2419 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2420 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2421 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2422 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2423 BUS_DMASYNC_PREWRITE); 2424 return (0); 2425 } 2426 2427 #define ET_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2428 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2429 #define ET_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2430 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2431 2432 /* 2433 * Create sysctl tree 2434 */ 2435 static void 2436 et_add_sysctls(struct et_softc * sc) 2437 { 2438 struct sysctl_ctx_list *ctx; 2439 struct sysctl_oid_list *children, *parent; 2440 struct sysctl_oid *tree; 2441 struct et_hw_stats *stats; 2442 2443 ctx = device_get_sysctl_ctx(sc->dev); 2444 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2445 2446 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2447 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2448 et_sysctl_rx_intr_npkts, "I", "RX IM, # packets per RX interrupt"); 2449 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2450 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2451 et_sysctl_rx_intr_delay, "I", 2452 "RX IM, RX interrupt delay (x10 usec)"); 2453 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2454 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2455 "TX IM, # segments per TX interrupt"); 2456 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2457 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2458 2459 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 2460 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ET statistics"); 2461 parent = SYSCTL_CHILDREN(tree); 2462 2463 /* TX/RX statistics. */ 2464 stats = &sc->sc_stats; 2465 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64, 2466 "0 to 64 bytes frames"); 2467 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65, 2468 "65 to 127 bytes frames"); 2469 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128, 2470 "128 to 255 bytes frames"); 2471 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256, 2472 "256 to 511 bytes frames"); 2473 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512, 2474 "512 to 1023 bytes frames"); 2475 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024, 2476 "1024 to 1518 bytes frames"); 2477 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519, 2478 "1519 to 1522 bytes frames"); 2479 2480 /* RX statistics. */ 2481 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2482 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 2483 children = SYSCTL_CHILDREN(tree); 2484 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2485 &stats->rx_bytes, "Good bytes"); 2486 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2487 &stats->rx_frames, "Good frames"); 2488 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2489 &stats->rx_crcerrs, "CRC errors"); 2490 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2491 &stats->rx_mcast, "Multicast frames"); 2492 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2493 &stats->rx_bcast, "Broadcast frames"); 2494 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2495 &stats->rx_control, "Control frames"); 2496 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2497 &stats->rx_pause, "Pause frames"); 2498 ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control", 2499 &stats->rx_unknown_control, "Unknown control frames"); 2500 ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs", 2501 &stats->rx_alignerrs, "Alignment errors"); 2502 ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs", 2503 &stats->rx_lenerrs, "Frames with length mismatched"); 2504 ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs", 2505 &stats->rx_codeerrs, "Frames with code error"); 2506 ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs", 2507 &stats->rx_cserrs, "Frames with carrier sense error"); 2508 ET_SYSCTL_STAT_ADD32(ctx, children, "runts", 2509 &stats->rx_runts, "Too short frames"); 2510 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2511 &stats->rx_oversize, "Oversized frames"); 2512 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2513 &stats->rx_fragments, "Fragmented frames"); 2514 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2515 &stats->rx_jabbers, "Frames with jabber error"); 2516 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2517 &stats->rx_drop, "Dropped frames"); 2518 2519 /* TX statistics. */ 2520 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2521 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 2522 children = SYSCTL_CHILDREN(tree); 2523 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2524 &stats->tx_bytes, "Good bytes"); 2525 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2526 &stats->tx_frames, "Good frames"); 2527 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2528 &stats->tx_mcast, "Multicast frames"); 2529 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2530 &stats->tx_bcast, "Broadcast frames"); 2531 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2532 &stats->tx_pause, "Pause frames"); 2533 ET_SYSCTL_STAT_ADD32(ctx, children, "deferred", 2534 &stats->tx_deferred, "Deferred frames"); 2535 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred", 2536 &stats->tx_excess_deferred, "Excessively deferred frames"); 2537 ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls", 2538 &stats->tx_single_colls, "Single collisions"); 2539 ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls", 2540 &stats->tx_multi_colls, "Multiple collisions"); 2541 ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls", 2542 &stats->tx_late_colls, "Late collisions"); 2543 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls", 2544 &stats->tx_excess_colls, "Excess collisions"); 2545 ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls", 2546 &stats->tx_total_colls, "Total collisions"); 2547 ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored", 2548 &stats->tx_pause_honored, "Honored pause frames"); 2549 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2550 &stats->tx_drop, "Dropped frames"); 2551 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2552 &stats->tx_jabbers, "Frames with jabber errors"); 2553 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2554 &stats->tx_crcerrs, "Frames with CRC errors"); 2555 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2556 &stats->tx_control, "Control frames"); 2557 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2558 &stats->tx_oversize, "Oversized frames"); 2559 ET_SYSCTL_STAT_ADD32(ctx, children, "undersize", 2560 &stats->tx_undersize, "Undersized frames"); 2561 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2562 &stats->tx_fragments, "Fragmented frames"); 2563 } 2564 2565 #undef ET_SYSCTL_STAT_ADD32 2566 #undef ET_SYSCTL_STAT_ADD64 2567 2568 static int 2569 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2570 { 2571 struct et_softc *sc; 2572 struct ifnet *ifp; 2573 int error, v; 2574 2575 sc = arg1; 2576 ifp = sc->ifp; 2577 v = sc->sc_rx_intr_npkts; 2578 error = sysctl_handle_int(oidp, &v, 0, req); 2579 if (error || req->newptr == NULL) 2580 goto back; 2581 if (v <= 0) { 2582 error = EINVAL; 2583 goto back; 2584 } 2585 2586 if (sc->sc_rx_intr_npkts != v) { 2587 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2588 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2589 sc->sc_rx_intr_npkts = v; 2590 } 2591 back: 2592 return (error); 2593 } 2594 2595 static int 2596 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2597 { 2598 struct et_softc *sc; 2599 struct ifnet *ifp; 2600 int error, v; 2601 2602 sc = arg1; 2603 ifp = sc->ifp; 2604 v = sc->sc_rx_intr_delay; 2605 error = sysctl_handle_int(oidp, &v, 0, req); 2606 if (error || req->newptr == NULL) 2607 goto back; 2608 if (v <= 0) { 2609 error = EINVAL; 2610 goto back; 2611 } 2612 2613 if (sc->sc_rx_intr_delay != v) { 2614 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2615 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2616 sc->sc_rx_intr_delay = v; 2617 } 2618 back: 2619 return (error); 2620 } 2621 2622 static void 2623 et_stats_update(struct et_softc *sc) 2624 { 2625 struct et_hw_stats *stats; 2626 2627 stats = &sc->sc_stats; 2628 stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64); 2629 stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127); 2630 stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255); 2631 stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511); 2632 stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023); 2633 stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518); 2634 stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522); 2635 2636 stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES); 2637 stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES); 2638 stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR); 2639 stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST); 2640 stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST); 2641 stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL); 2642 stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE); 2643 stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL); 2644 stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR); 2645 stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR); 2646 stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR); 2647 stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR); 2648 stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT); 2649 stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE); 2650 stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG); 2651 stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER); 2652 stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP); 2653 2654 stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES); 2655 stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES); 2656 stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST); 2657 stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST); 2658 stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE); 2659 stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER); 2660 stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER); 2661 stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL); 2662 stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL); 2663 stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL); 2664 stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL); 2665 stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL); 2666 stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR); 2667 stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP); 2668 stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER); 2669 stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR); 2670 stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL); 2671 stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE); 2672 stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE); 2673 stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG); 2674 } 2675 2676 static uint64_t 2677 et_get_counter(struct ifnet *ifp, ift_counter cnt) 2678 { 2679 struct et_softc *sc; 2680 struct et_hw_stats *stats; 2681 2682 sc = if_getsoftc(ifp); 2683 stats = &sc->sc_stats; 2684 2685 switch (cnt) { 2686 case IFCOUNTER_OPACKETS: 2687 return (stats->tx_frames); 2688 case IFCOUNTER_COLLISIONS: 2689 return (stats->tx_total_colls); 2690 case IFCOUNTER_OERRORS: 2691 return (stats->tx_drop + stats->tx_jabbers + 2692 stats->tx_crcerrs + stats->tx_excess_deferred + 2693 stats->tx_late_colls); 2694 case IFCOUNTER_IPACKETS: 2695 return (stats->rx_frames); 2696 case IFCOUNTER_IERRORS: 2697 return (stats->rx_crcerrs + stats->rx_alignerrs + 2698 stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs + 2699 stats->rx_runts + stats->rx_jabbers + stats->rx_drop); 2700 default: 2701 return (if_get_counter_default(ifp, cnt)); 2702 } 2703 } 2704 2705 static int 2706 et_suspend(device_t dev) 2707 { 2708 struct et_softc *sc; 2709 uint32_t pmcfg; 2710 2711 sc = device_get_softc(dev); 2712 ET_LOCK(sc); 2713 if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2714 et_stop(sc); 2715 /* Diable all clocks and put PHY into COMA. */ 2716 pmcfg = CSR_READ_4(sc, ET_PM); 2717 pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | 2718 ET_PM_RXCLK_GATE); 2719 pmcfg |= ET_PM_PHY_SW_COMA; 2720 CSR_WRITE_4(sc, ET_PM, pmcfg); 2721 ET_UNLOCK(sc); 2722 return (0); 2723 } 2724 2725 static int 2726 et_resume(device_t dev) 2727 { 2728 struct et_softc *sc; 2729 uint32_t pmcfg; 2730 2731 sc = device_get_softc(dev); 2732 ET_LOCK(sc); 2733 /* Take PHY out of COMA and enable clocks. */ 2734 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 2735 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 2736 pmcfg |= EM_PM_GIGEPHY_ENB; 2737 CSR_WRITE_4(sc, ET_PM, pmcfg); 2738 if ((sc->ifp->if_flags & IFF_UP) != 0) 2739 et_init_locked(sc); 2740 ET_UNLOCK(sc); 2741 return (0); 2742 } 2743