1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/malloc.h> 48 #include <sys/mbuf.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/module.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/bpf.h> 62 #include <net/if_arp.h> 63 #include <net/if_media.h> 64 #include <net/if_vlan_var.h> 65 66 #include <machine/bus.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/et/if_etreg.h> 75 #include <dev/et/if_etvar.h> 76 77 #include "miibus_if.h" 78 79 MODULE_DEPEND(et, pci, 1, 1, 1); 80 MODULE_DEPEND(et, ether, 1, 1, 1); 81 MODULE_DEPEND(et, miibus, 1, 1, 1); 82 83 /* Tunables. */ 84 static int msi_disable = 0; 85 TUNABLE_INT("hw.et.msi_disable", &msi_disable); 86 87 #define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 88 89 static int et_probe(device_t); 90 static int et_attach(device_t); 91 static int et_detach(device_t); 92 static int et_shutdown(device_t); 93 static int et_suspend(device_t); 94 static int et_resume(device_t); 95 96 static int et_miibus_readreg(device_t, int, int); 97 static int et_miibus_writereg(device_t, int, int, int); 98 static void et_miibus_statchg(device_t); 99 100 static void et_init_locked(struct et_softc *); 101 static void et_init(void *); 102 static int et_ioctl(struct ifnet *, u_long, caddr_t); 103 static void et_start_locked(struct ifnet *); 104 static void et_start(struct ifnet *); 105 static int et_watchdog(struct et_softc *); 106 static int et_ifmedia_upd_locked(struct ifnet *); 107 static int et_ifmedia_upd(struct ifnet *); 108 static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 static uint64_t et_get_counter(struct ifnet *, ift_counter); 110 111 static void et_add_sysctls(struct et_softc *); 112 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 113 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 114 115 static void et_intr(void *); 116 static void et_rxeof(struct et_softc *); 117 static void et_txeof(struct et_softc *); 118 119 static int et_dma_alloc(struct et_softc *); 120 static void et_dma_free(struct et_softc *); 121 static void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 122 static int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 123 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 124 const char *); 125 static void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 126 bus_dmamap_t, bus_addr_t *); 127 static void et_init_tx_ring(struct et_softc *); 128 static int et_init_rx_ring(struct et_softc *); 129 static void et_free_tx_ring(struct et_softc *); 130 static void et_free_rx_ring(struct et_softc *); 131 static int et_encap(struct et_softc *, struct mbuf **); 132 static int et_newbuf_cluster(struct et_rxbuf_data *, int); 133 static int et_newbuf_hdr(struct et_rxbuf_data *, int); 134 static void et_rxbuf_discard(struct et_rxbuf_data *, int); 135 136 static void et_stop(struct et_softc *); 137 static int et_chip_init(struct et_softc *); 138 static void et_chip_attach(struct et_softc *); 139 static void et_init_mac(struct et_softc *); 140 static void et_init_rxmac(struct et_softc *); 141 static void et_init_txmac(struct et_softc *); 142 static int et_init_rxdma(struct et_softc *); 143 static int et_init_txdma(struct et_softc *); 144 static int et_start_rxdma(struct et_softc *); 145 static int et_start_txdma(struct et_softc *); 146 static int et_stop_rxdma(struct et_softc *); 147 static int et_stop_txdma(struct et_softc *); 148 static void et_reset(struct et_softc *); 149 static int et_bus_config(struct et_softc *); 150 static void et_get_eaddr(device_t, uint8_t[]); 151 static void et_setmulti(struct et_softc *); 152 static void et_tick(void *); 153 static void et_stats_update(struct et_softc *); 154 155 static const struct et_dev { 156 uint16_t vid; 157 uint16_t did; 158 const char *desc; 159 } et_devices[] = { 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 161 "Agere ET1310 Gigabit Ethernet" }, 162 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 163 "Agere ET1310 Fast Ethernet" }, 164 { 0, 0, NULL } 165 }; 166 167 static device_method_t et_methods[] = { 168 DEVMETHOD(device_probe, et_probe), 169 DEVMETHOD(device_attach, et_attach), 170 DEVMETHOD(device_detach, et_detach), 171 DEVMETHOD(device_shutdown, et_shutdown), 172 DEVMETHOD(device_suspend, et_suspend), 173 DEVMETHOD(device_resume, et_resume), 174 175 DEVMETHOD(miibus_readreg, et_miibus_readreg), 176 DEVMETHOD(miibus_writereg, et_miibus_writereg), 177 DEVMETHOD(miibus_statchg, et_miibus_statchg), 178 179 DEVMETHOD_END 180 }; 181 182 static driver_t et_driver = { 183 "et", 184 et_methods, 185 sizeof(struct et_softc) 186 }; 187 188 static devclass_t et_devclass; 189 190 DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0); 191 DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0); 192 193 static int et_rx_intr_npkts = 32; 194 static int et_rx_intr_delay = 20; /* x10 usec */ 195 static int et_tx_intr_nsegs = 126; 196 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 197 198 TUNABLE_INT("hw.et.timer", &et_timer); 199 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 200 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 201 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 202 203 static int 204 et_probe(device_t dev) 205 { 206 const struct et_dev *d; 207 uint16_t did, vid; 208 209 vid = pci_get_vendor(dev); 210 did = pci_get_device(dev); 211 212 for (d = et_devices; d->desc != NULL; ++d) { 213 if (vid == d->vid && did == d->did) { 214 device_set_desc(dev, d->desc); 215 return (BUS_PROBE_DEFAULT); 216 } 217 } 218 return (ENXIO); 219 } 220 221 static int 222 et_attach(device_t dev) 223 { 224 struct et_softc *sc; 225 struct ifnet *ifp; 226 uint8_t eaddr[ETHER_ADDR_LEN]; 227 uint32_t pmcfg; 228 int cap, error, msic; 229 230 sc = device_get_softc(dev); 231 sc->dev = dev; 232 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 233 MTX_DEF); 234 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 235 236 ifp = sc->ifp = if_alloc(IFT_ETHER); 237 if (ifp == NULL) { 238 device_printf(dev, "can not if_alloc()\n"); 239 error = ENOSPC; 240 goto fail; 241 } 242 243 /* 244 * Initialize tunables 245 */ 246 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 247 sc->sc_rx_intr_delay = et_rx_intr_delay; 248 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 249 sc->sc_timer = et_timer; 250 251 /* Enable bus mastering */ 252 pci_enable_busmaster(dev); 253 254 /* 255 * Allocate IO memory 256 */ 257 sc->sc_mem_rid = PCIR_BAR(0); 258 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 259 &sc->sc_mem_rid, RF_ACTIVE); 260 if (sc->sc_mem_res == NULL) { 261 device_printf(dev, "can't allocate IO memory\n"); 262 return (ENXIO); 263 } 264 265 msic = 0; 266 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 267 sc->sc_expcap = cap; 268 sc->sc_flags |= ET_FLAG_PCIE; 269 msic = pci_msi_count(dev); 270 if (bootverbose) 271 device_printf(dev, "MSI count: %d\n", msic); 272 } 273 if (msic > 0 && msi_disable == 0) { 274 msic = 1; 275 if (pci_alloc_msi(dev, &msic) == 0) { 276 if (msic == 1) { 277 device_printf(dev, "Using %d MSI message\n", 278 msic); 279 sc->sc_flags |= ET_FLAG_MSI; 280 } else 281 pci_release_msi(dev); 282 } 283 } 284 285 /* 286 * Allocate IRQ 287 */ 288 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 289 sc->sc_irq_rid = 0; 290 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 291 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 292 } else { 293 sc->sc_irq_rid = 1; 294 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 295 &sc->sc_irq_rid, RF_ACTIVE); 296 } 297 if (sc->sc_irq_res == NULL) { 298 device_printf(dev, "can't allocate irq\n"); 299 error = ENXIO; 300 goto fail; 301 } 302 303 if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST) 304 sc->sc_flags |= ET_FLAG_FASTETHER; 305 306 error = et_bus_config(sc); 307 if (error) 308 goto fail; 309 310 et_get_eaddr(dev, eaddr); 311 312 /* Take PHY out of COMA and enable clocks. */ 313 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 314 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 315 pmcfg |= EM_PM_GIGEPHY_ENB; 316 CSR_WRITE_4(sc, ET_PM, pmcfg); 317 318 et_reset(sc); 319 320 error = et_dma_alloc(sc); 321 if (error) 322 goto fail; 323 324 ifp->if_softc = sc; 325 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 326 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 327 ifp->if_init = et_init; 328 ifp->if_ioctl = et_ioctl; 329 ifp->if_start = et_start; 330 ifp->if_get_counter = et_get_counter; 331 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU; 332 ifp->if_capenable = ifp->if_capabilities; 333 ifp->if_snd.ifq_drv_maxlen = ET_TX_NDESC - 1; 334 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC - 1); 335 IFQ_SET_READY(&ifp->if_snd); 336 337 et_chip_attach(sc); 338 339 error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 340 et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 341 MIIF_DOPAUSE); 342 if (error) { 343 device_printf(dev, "attaching PHYs failed\n"); 344 goto fail; 345 } 346 347 ether_ifattach(ifp, eaddr); 348 349 /* Tell the upper layer(s) we support long frames. */ 350 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 351 352 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 353 NULL, et_intr, sc, &sc->sc_irq_handle); 354 if (error) { 355 ether_ifdetach(ifp); 356 device_printf(dev, "can't setup intr\n"); 357 goto fail; 358 } 359 360 et_add_sysctls(sc); 361 362 return (0); 363 fail: 364 et_detach(dev); 365 return (error); 366 } 367 368 static int 369 et_detach(device_t dev) 370 { 371 struct et_softc *sc; 372 373 sc = device_get_softc(dev); 374 if (device_is_attached(dev)) { 375 ether_ifdetach(sc->ifp); 376 ET_LOCK(sc); 377 et_stop(sc); 378 ET_UNLOCK(sc); 379 callout_drain(&sc->sc_tick); 380 } 381 382 if (sc->sc_miibus != NULL) 383 device_delete_child(dev, sc->sc_miibus); 384 bus_generic_detach(dev); 385 386 if (sc->sc_irq_handle != NULL) 387 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 388 if (sc->sc_irq_res != NULL) 389 bus_release_resource(dev, SYS_RES_IRQ, 390 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 391 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 392 pci_release_msi(dev); 393 if (sc->sc_mem_res != NULL) 394 bus_release_resource(dev, SYS_RES_MEMORY, 395 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 396 397 if (sc->ifp != NULL) 398 if_free(sc->ifp); 399 400 et_dma_free(sc); 401 402 mtx_destroy(&sc->sc_mtx); 403 404 return (0); 405 } 406 407 static int 408 et_shutdown(device_t dev) 409 { 410 struct et_softc *sc; 411 412 sc = device_get_softc(dev); 413 ET_LOCK(sc); 414 et_stop(sc); 415 ET_UNLOCK(sc); 416 return (0); 417 } 418 419 static int 420 et_miibus_readreg(device_t dev, int phy, int reg) 421 { 422 struct et_softc *sc; 423 uint32_t val; 424 int i, ret; 425 426 sc = device_get_softc(dev); 427 /* Stop any pending operations */ 428 CSR_WRITE_4(sc, ET_MII_CMD, 0); 429 430 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 431 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 432 CSR_WRITE_4(sc, ET_MII_ADDR, val); 433 434 /* Start reading */ 435 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 436 437 #define NRETRY 50 438 439 for (i = 0; i < NRETRY; ++i) { 440 val = CSR_READ_4(sc, ET_MII_IND); 441 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 442 break; 443 DELAY(50); 444 } 445 if (i == NRETRY) { 446 if_printf(sc->ifp, 447 "read phy %d, reg %d timed out\n", phy, reg); 448 ret = 0; 449 goto back; 450 } 451 452 #undef NRETRY 453 454 val = CSR_READ_4(sc, ET_MII_STAT); 455 ret = val & ET_MII_STAT_VALUE_MASK; 456 457 back: 458 /* Make sure that the current operation is stopped */ 459 CSR_WRITE_4(sc, ET_MII_CMD, 0); 460 return (ret); 461 } 462 463 static int 464 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 465 { 466 struct et_softc *sc; 467 uint32_t val; 468 int i; 469 470 sc = device_get_softc(dev); 471 /* Stop any pending operations */ 472 CSR_WRITE_4(sc, ET_MII_CMD, 0); 473 474 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 475 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 476 CSR_WRITE_4(sc, ET_MII_ADDR, val); 477 478 /* Start writing */ 479 CSR_WRITE_4(sc, ET_MII_CTRL, 480 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 481 482 #define NRETRY 100 483 484 for (i = 0; i < NRETRY; ++i) { 485 val = CSR_READ_4(sc, ET_MII_IND); 486 if ((val & ET_MII_IND_BUSY) == 0) 487 break; 488 DELAY(50); 489 } 490 if (i == NRETRY) { 491 if_printf(sc->ifp, 492 "write phy %d, reg %d timed out\n", phy, reg); 493 et_miibus_readreg(dev, phy, reg); 494 } 495 496 #undef NRETRY 497 498 /* Make sure that the current operation is stopped */ 499 CSR_WRITE_4(sc, ET_MII_CMD, 0); 500 return (0); 501 } 502 503 static void 504 et_miibus_statchg(device_t dev) 505 { 506 struct et_softc *sc; 507 struct mii_data *mii; 508 struct ifnet *ifp; 509 uint32_t cfg1, cfg2, ctrl; 510 int i; 511 512 sc = device_get_softc(dev); 513 514 mii = device_get_softc(sc->sc_miibus); 515 ifp = sc->ifp; 516 if (mii == NULL || ifp == NULL || 517 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 518 return; 519 520 sc->sc_flags &= ~ET_FLAG_LINK; 521 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 522 (IFM_ACTIVE | IFM_AVALID)) { 523 switch (IFM_SUBTYPE(mii->mii_media_active)) { 524 case IFM_10_T: 525 case IFM_100_TX: 526 sc->sc_flags |= ET_FLAG_LINK; 527 break; 528 case IFM_1000_T: 529 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 530 sc->sc_flags |= ET_FLAG_LINK; 531 break; 532 } 533 } 534 535 /* XXX Stop TX/RX MAC? */ 536 if ((sc->sc_flags & ET_FLAG_LINK) == 0) 537 return; 538 539 /* Program MACs with resolved speed/duplex/flow-control. */ 540 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 541 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 542 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 543 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 544 ET_MAC_CFG1_LOOPBACK); 545 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 546 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 547 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 548 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 549 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 550 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 551 552 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 553 cfg2 |= ET_MAC_CFG2_MODE_GMII; 554 else { 555 cfg2 |= ET_MAC_CFG2_MODE_MII; 556 ctrl |= ET_MAC_CTRL_MODE_MII; 557 } 558 559 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 560 cfg2 |= ET_MAC_CFG2_FDX; 561 /* 562 * Controller lacks automatic TX pause frame 563 * generation so it should be handled by driver. 564 * Even though driver can send pause frame with 565 * arbitrary pause time, controller does not 566 * provide a way that tells how many free RX 567 * buffers are available in controller. This 568 * limitation makes it hard to generate XON frame 569 * in time on driver side so don't enable TX flow 570 * control. 571 */ 572 #ifdef notyet 573 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 574 cfg1 |= ET_MAC_CFG1_TXFLOW; 575 #endif 576 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 577 cfg1 |= ET_MAC_CFG1_RXFLOW; 578 } else 579 ctrl |= ET_MAC_CTRL_GHDX; 580 581 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 582 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 583 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 584 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); 585 586 #define NRETRY 50 587 588 for (i = 0; i < NRETRY; ++i) { 589 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 590 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 591 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 592 break; 593 DELAY(100); 594 } 595 if (i == NRETRY) 596 if_printf(ifp, "can't enable RX/TX\n"); 597 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 598 599 #undef NRETRY 600 } 601 602 static int 603 et_ifmedia_upd_locked(struct ifnet *ifp) 604 { 605 struct et_softc *sc; 606 struct mii_data *mii; 607 struct mii_softc *miisc; 608 609 sc = ifp->if_softc; 610 mii = device_get_softc(sc->sc_miibus); 611 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 612 PHY_RESET(miisc); 613 return (mii_mediachg(mii)); 614 } 615 616 static int 617 et_ifmedia_upd(struct ifnet *ifp) 618 { 619 struct et_softc *sc; 620 int res; 621 622 sc = ifp->if_softc; 623 ET_LOCK(sc); 624 res = et_ifmedia_upd_locked(ifp); 625 ET_UNLOCK(sc); 626 627 return (res); 628 } 629 630 static void 631 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 632 { 633 struct et_softc *sc; 634 struct mii_data *mii; 635 636 sc = ifp->if_softc; 637 ET_LOCK(sc); 638 if ((ifp->if_flags & IFF_UP) == 0) { 639 ET_UNLOCK(sc); 640 return; 641 } 642 643 mii = device_get_softc(sc->sc_miibus); 644 mii_pollstat(mii); 645 ifmr->ifm_active = mii->mii_media_active; 646 ifmr->ifm_status = mii->mii_media_status; 647 ET_UNLOCK(sc); 648 } 649 650 static void 651 et_stop(struct et_softc *sc) 652 { 653 struct ifnet *ifp; 654 655 ET_LOCK_ASSERT(sc); 656 657 ifp = sc->ifp; 658 callout_stop(&sc->sc_tick); 659 /* Disable interrupts. */ 660 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 661 662 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( 663 ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN)); 664 DELAY(100); 665 666 et_stop_rxdma(sc); 667 et_stop_txdma(sc); 668 et_stats_update(sc); 669 670 et_free_tx_ring(sc); 671 et_free_rx_ring(sc); 672 673 sc->sc_tx = 0; 674 sc->sc_tx_intr = 0; 675 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 676 677 sc->watchdog_timer = 0; 678 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 679 } 680 681 static int 682 et_bus_config(struct et_softc *sc) 683 { 684 uint32_t val, max_plsz; 685 uint16_t ack_latency, replay_timer; 686 687 /* 688 * Test whether EEPROM is valid 689 * NOTE: Read twice to get the correct value 690 */ 691 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 692 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 693 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 694 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 695 return (ENXIO); 696 } 697 698 /* TODO: LED */ 699 700 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 701 return (0); 702 703 /* 704 * Configure ACK latency and replay timer according to 705 * max playload size 706 */ 707 val = pci_read_config(sc->dev, 708 sc->sc_expcap + PCIER_DEVICE_CAP, 4); 709 max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; 710 711 switch (max_plsz) { 712 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 713 ack_latency = ET_PCIV_ACK_LATENCY_128; 714 replay_timer = ET_PCIV_REPLAY_TIMER_128; 715 break; 716 717 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 718 ack_latency = ET_PCIV_ACK_LATENCY_256; 719 replay_timer = ET_PCIV_REPLAY_TIMER_256; 720 break; 721 722 default: 723 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 724 replay_timer = pci_read_config(sc->dev, 725 ET_PCIR_REPLAY_TIMER, 2); 726 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 727 ack_latency, replay_timer); 728 break; 729 } 730 if (ack_latency != 0) { 731 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 732 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 733 2); 734 } 735 736 /* 737 * Set L0s and L1 latency timer to 2us 738 */ 739 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 740 val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); 741 /* L0s exit latency : 2us */ 742 val |= 0x00005000; 743 /* L1 exit latency : 2us */ 744 val |= 0x00028000; 745 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 746 747 /* 748 * Set max read request size to 2048 bytes 749 */ 750 pci_set_max_read_req(sc->dev, 2048); 751 752 return (0); 753 } 754 755 static void 756 et_get_eaddr(device_t dev, uint8_t eaddr[]) 757 { 758 uint32_t val; 759 int i; 760 761 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 762 for (i = 0; i < 4; ++i) 763 eaddr[i] = (val >> (8 * i)) & 0xff; 764 765 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 766 for (; i < ETHER_ADDR_LEN; ++i) 767 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 768 } 769 770 static void 771 et_reset(struct et_softc *sc) 772 { 773 774 CSR_WRITE_4(sc, ET_MAC_CFG1, 775 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 776 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 777 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 778 779 CSR_WRITE_4(sc, ET_SWRST, 780 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 781 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 782 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 783 784 CSR_WRITE_4(sc, ET_MAC_CFG1, 785 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 786 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 787 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 788 /* Disable interrupts. */ 789 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 790 } 791 792 struct et_dmamap_arg { 793 bus_addr_t et_busaddr; 794 }; 795 796 static void 797 et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 798 { 799 struct et_dmamap_arg *ctx; 800 801 if (error) 802 return; 803 804 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 805 806 ctx = arg; 807 ctx->et_busaddr = segs->ds_addr; 808 } 809 810 static int 811 et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 812 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 813 const char *msg) 814 { 815 struct et_dmamap_arg ctx; 816 int error; 817 818 error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 819 BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 820 tag); 821 if (error != 0) { 822 device_printf(sc->dev, "could not create %s dma tag\n", msg); 823 return (error); 824 } 825 /* Allocate DMA'able memory for ring. */ 826 error = bus_dmamem_alloc(*tag, (void **)ring, 827 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 828 if (error != 0) { 829 device_printf(sc->dev, 830 "could not allocate DMA'able memory for %s\n", msg); 831 return (error); 832 } 833 /* Load the address of the ring. */ 834 ctx.et_busaddr = 0; 835 error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 836 &ctx, BUS_DMA_NOWAIT); 837 if (error != 0) { 838 device_printf(sc->dev, 839 "could not load DMA'able memory for %s\n", msg); 840 return (error); 841 } 842 *paddr = ctx.et_busaddr; 843 return (0); 844 } 845 846 static void 847 et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 848 bus_dmamap_t map, bus_addr_t *paddr) 849 { 850 851 if (*paddr != 0) { 852 bus_dmamap_unload(*tag, map); 853 *paddr = 0; 854 } 855 if (*ring != NULL) { 856 bus_dmamem_free(*tag, *ring, map); 857 *ring = NULL; 858 } 859 if (*tag) { 860 bus_dma_tag_destroy(*tag); 861 *tag = NULL; 862 } 863 } 864 865 static int 866 et_dma_alloc(struct et_softc *sc) 867 { 868 struct et_txdesc_ring *tx_ring; 869 struct et_rxdesc_ring *rx_ring; 870 struct et_rxstat_ring *rxst_ring; 871 struct et_rxstatus_data *rxsd; 872 struct et_rxbuf_data *rbd; 873 struct et_txbuf_data *tbd; 874 struct et_txstatus_data *txsd; 875 int i, error; 876 877 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 878 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 879 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 880 &sc->sc_dtag); 881 if (error != 0) { 882 device_printf(sc->dev, "could not allocate parent dma tag\n"); 883 return (error); 884 } 885 886 /* TX ring. */ 887 tx_ring = &sc->sc_tx_ring; 888 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 889 &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 890 &tx_ring->tr_paddr, "TX ring"); 891 if (error) 892 return (error); 893 894 /* TX status block. */ 895 txsd = &sc->sc_tx_status; 896 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 897 &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 898 &txsd->txsd_paddr, "TX status block"); 899 if (error) 900 return (error); 901 902 /* RX ring 0, used as to recive small sized frames. */ 903 rx_ring = &sc->sc_rx_ring[0]; 904 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 905 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 906 &rx_ring->rr_paddr, "RX ring 0"); 907 rx_ring->rr_posreg = ET_RX_RING0_POS; 908 if (error) 909 return (error); 910 911 /* RX ring 1, used as to store normal sized frames. */ 912 rx_ring = &sc->sc_rx_ring[1]; 913 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 914 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 915 &rx_ring->rr_paddr, "RX ring 1"); 916 rx_ring->rr_posreg = ET_RX_RING1_POS; 917 if (error) 918 return (error); 919 920 /* RX stat ring. */ 921 rxst_ring = &sc->sc_rxstat_ring; 922 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 923 &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 924 &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 925 if (error) 926 return (error); 927 928 /* RX status block. */ 929 rxsd = &sc->sc_rx_status; 930 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 931 sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 932 (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 933 &rxsd->rxsd_paddr, "RX status block"); 934 if (error) 935 return (error); 936 937 /* Create parent DMA tag for mbufs. */ 938 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 939 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 940 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 941 &sc->sc_mbuf_dtag); 942 if (error != 0) { 943 device_printf(sc->dev, 944 "could not allocate parent dma tag for mbuf\n"); 945 return (error); 946 } 947 948 /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 949 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 950 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 951 MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 952 if (error) { 953 device_printf(sc->dev, "could not create mini RX dma tag\n"); 954 return (error); 955 } 956 957 /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 958 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 959 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 960 MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 961 if (error) { 962 device_printf(sc->dev, "could not create RX dma tag\n"); 963 return (error); 964 } 965 966 /* Create DMA tag for TX mbufs. */ 967 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 968 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 969 MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 970 &sc->sc_tx_tag); 971 if (error) { 972 device_printf(sc->dev, "could not create TX dma tag\n"); 973 return (error); 974 } 975 976 /* Initialize RX ring 0. */ 977 rbd = &sc->sc_rx_data[0]; 978 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 979 rbd->rbd_newbuf = et_newbuf_hdr; 980 rbd->rbd_discard = et_rxbuf_discard; 981 rbd->rbd_softc = sc; 982 rbd->rbd_ring = &sc->sc_rx_ring[0]; 983 /* Create DMA maps for mini RX buffers, ring 0. */ 984 for (i = 0; i < ET_RX_NDESC; i++) { 985 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 986 &rbd->rbd_buf[i].rb_dmap); 987 if (error) { 988 device_printf(sc->dev, 989 "could not create DMA map for mini RX mbufs\n"); 990 return (error); 991 } 992 } 993 994 /* Create a spare DMA map for mini RX buffers, ring 0. */ 995 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 996 &sc->sc_rx_mini_sparemap); 997 if (error) { 998 device_printf(sc->dev, 999 "could not create spare DMA map for mini RX mbuf\n"); 1000 return (error); 1001 } 1002 1003 /* Initialize RX ring 1. */ 1004 rbd = &sc->sc_rx_data[1]; 1005 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 1006 rbd->rbd_newbuf = et_newbuf_cluster; 1007 rbd->rbd_discard = et_rxbuf_discard; 1008 rbd->rbd_softc = sc; 1009 rbd->rbd_ring = &sc->sc_rx_ring[1]; 1010 /* Create DMA maps for standard RX buffers, ring 1. */ 1011 for (i = 0; i < ET_RX_NDESC; i++) { 1012 error = bus_dmamap_create(sc->sc_rx_tag, 0, 1013 &rbd->rbd_buf[i].rb_dmap); 1014 if (error) { 1015 device_printf(sc->dev, 1016 "could not create DMA map for mini RX mbufs\n"); 1017 return (error); 1018 } 1019 } 1020 1021 /* Create a spare DMA map for standard RX buffers, ring 1. */ 1022 error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 1023 if (error) { 1024 device_printf(sc->dev, 1025 "could not create spare DMA map for RX mbuf\n"); 1026 return (error); 1027 } 1028 1029 /* Create DMA maps for TX buffers. */ 1030 tbd = &sc->sc_tx_data; 1031 for (i = 0; i < ET_TX_NDESC; i++) { 1032 error = bus_dmamap_create(sc->sc_tx_tag, 0, 1033 &tbd->tbd_buf[i].tb_dmap); 1034 if (error) { 1035 device_printf(sc->dev, 1036 "could not create DMA map for TX mbufs\n"); 1037 return (error); 1038 } 1039 } 1040 1041 return (0); 1042 } 1043 1044 static void 1045 et_dma_free(struct et_softc *sc) 1046 { 1047 struct et_txdesc_ring *tx_ring; 1048 struct et_rxdesc_ring *rx_ring; 1049 struct et_txstatus_data *txsd; 1050 struct et_rxstat_ring *rxst_ring; 1051 struct et_rxstatus_data *rxsd; 1052 struct et_rxbuf_data *rbd; 1053 struct et_txbuf_data *tbd; 1054 int i; 1055 1056 /* Destroy DMA maps for mini RX buffers, ring 0. */ 1057 rbd = &sc->sc_rx_data[0]; 1058 for (i = 0; i < ET_RX_NDESC; i++) { 1059 if (rbd->rbd_buf[i].rb_dmap) { 1060 bus_dmamap_destroy(sc->sc_rx_mini_tag, 1061 rbd->rbd_buf[i].rb_dmap); 1062 rbd->rbd_buf[i].rb_dmap = NULL; 1063 } 1064 } 1065 if (sc->sc_rx_mini_sparemap) { 1066 bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 1067 sc->sc_rx_mini_sparemap = NULL; 1068 } 1069 if (sc->sc_rx_mini_tag) { 1070 bus_dma_tag_destroy(sc->sc_rx_mini_tag); 1071 sc->sc_rx_mini_tag = NULL; 1072 } 1073 1074 /* Destroy DMA maps for standard RX buffers, ring 1. */ 1075 rbd = &sc->sc_rx_data[1]; 1076 for (i = 0; i < ET_RX_NDESC; i++) { 1077 if (rbd->rbd_buf[i].rb_dmap) { 1078 bus_dmamap_destroy(sc->sc_rx_tag, 1079 rbd->rbd_buf[i].rb_dmap); 1080 rbd->rbd_buf[i].rb_dmap = NULL; 1081 } 1082 } 1083 if (sc->sc_rx_sparemap) { 1084 bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 1085 sc->sc_rx_sparemap = NULL; 1086 } 1087 if (sc->sc_rx_tag) { 1088 bus_dma_tag_destroy(sc->sc_rx_tag); 1089 sc->sc_rx_tag = NULL; 1090 } 1091 1092 /* Destroy DMA maps for TX buffers. */ 1093 tbd = &sc->sc_tx_data; 1094 for (i = 0; i < ET_TX_NDESC; i++) { 1095 if (tbd->tbd_buf[i].tb_dmap) { 1096 bus_dmamap_destroy(sc->sc_tx_tag, 1097 tbd->tbd_buf[i].tb_dmap); 1098 tbd->tbd_buf[i].tb_dmap = NULL; 1099 } 1100 } 1101 if (sc->sc_tx_tag) { 1102 bus_dma_tag_destroy(sc->sc_tx_tag); 1103 sc->sc_tx_tag = NULL; 1104 } 1105 1106 /* Destroy mini RX ring, ring 0. */ 1107 rx_ring = &sc->sc_rx_ring[0]; 1108 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1109 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1110 /* Destroy standard RX ring, ring 1. */ 1111 rx_ring = &sc->sc_rx_ring[1]; 1112 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1113 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1114 /* Destroy RX stat ring. */ 1115 rxst_ring = &sc->sc_rxstat_ring; 1116 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1117 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1118 /* Destroy RX status block. */ 1119 rxsd = &sc->sc_rx_status; 1120 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1121 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1122 /* Destroy TX ring. */ 1123 tx_ring = &sc->sc_tx_ring; 1124 et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1125 tx_ring->tr_dmap, &tx_ring->tr_paddr); 1126 /* Destroy TX status block. */ 1127 txsd = &sc->sc_tx_status; 1128 et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1129 txsd->txsd_dmap, &txsd->txsd_paddr); 1130 1131 /* Destroy the parent tag. */ 1132 if (sc->sc_dtag) { 1133 bus_dma_tag_destroy(sc->sc_dtag); 1134 sc->sc_dtag = NULL; 1135 } 1136 } 1137 1138 static void 1139 et_chip_attach(struct et_softc *sc) 1140 { 1141 uint32_t val; 1142 1143 /* 1144 * Perform minimal initialization 1145 */ 1146 1147 /* Disable loopback */ 1148 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1149 1150 /* Reset MAC */ 1151 CSR_WRITE_4(sc, ET_MAC_CFG1, 1152 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1153 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1154 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1155 1156 /* 1157 * Setup half duplex mode 1158 */ 1159 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1160 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1161 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1162 ET_MAC_HDX_EXC_DEFER; 1163 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1164 1165 /* Clear MAC control */ 1166 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1167 1168 /* Reset MII */ 1169 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1170 1171 /* Bring MAC out of reset state */ 1172 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1173 1174 /* Enable memory controllers */ 1175 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1176 } 1177 1178 static void 1179 et_intr(void *xsc) 1180 { 1181 struct et_softc *sc; 1182 struct ifnet *ifp; 1183 uint32_t status; 1184 1185 sc = xsc; 1186 ET_LOCK(sc); 1187 ifp = sc->ifp; 1188 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1189 goto done; 1190 1191 status = CSR_READ_4(sc, ET_INTR_STATUS); 1192 if ((status & ET_INTRS) == 0) 1193 goto done; 1194 1195 /* Disable further interrupts. */ 1196 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 1197 1198 if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) { 1199 device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n", 1200 status); 1201 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1202 et_init_locked(sc); 1203 ET_UNLOCK(sc); 1204 return; 1205 } 1206 if (status & ET_INTR_RXDMA) 1207 et_rxeof(sc); 1208 if (status & (ET_INTR_TXDMA | ET_INTR_TIMER)) 1209 et_txeof(sc); 1210 if (status & ET_INTR_TIMER) 1211 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1212 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1213 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1214 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1215 et_start_locked(ifp); 1216 } 1217 done: 1218 ET_UNLOCK(sc); 1219 } 1220 1221 static void 1222 et_init_locked(struct et_softc *sc) 1223 { 1224 struct ifnet *ifp; 1225 int error; 1226 1227 ET_LOCK_ASSERT(sc); 1228 1229 ifp = sc->ifp; 1230 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1231 return; 1232 1233 et_stop(sc); 1234 et_reset(sc); 1235 1236 et_init_tx_ring(sc); 1237 error = et_init_rx_ring(sc); 1238 if (error) 1239 return; 1240 1241 error = et_chip_init(sc); 1242 if (error) 1243 goto fail; 1244 1245 /* 1246 * Start TX/RX DMA engine 1247 */ 1248 error = et_start_rxdma(sc); 1249 if (error) 1250 return; 1251 1252 error = et_start_txdma(sc); 1253 if (error) 1254 return; 1255 1256 /* Enable interrupts. */ 1257 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1258 1259 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1260 1261 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1262 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1263 1264 sc->sc_flags &= ~ET_FLAG_LINK; 1265 et_ifmedia_upd_locked(ifp); 1266 1267 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1268 1269 fail: 1270 if (error) 1271 et_stop(sc); 1272 } 1273 1274 static void 1275 et_init(void *xsc) 1276 { 1277 struct et_softc *sc = xsc; 1278 1279 ET_LOCK(sc); 1280 et_init_locked(sc); 1281 ET_UNLOCK(sc); 1282 } 1283 1284 static int 1285 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1286 { 1287 struct et_softc *sc; 1288 struct mii_data *mii; 1289 struct ifreq *ifr; 1290 int error, mask, max_framelen; 1291 1292 sc = ifp->if_softc; 1293 ifr = (struct ifreq *)data; 1294 error = 0; 1295 1296 /* XXX LOCKSUSED */ 1297 switch (cmd) { 1298 case SIOCSIFFLAGS: 1299 ET_LOCK(sc); 1300 if (ifp->if_flags & IFF_UP) { 1301 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1302 if ((ifp->if_flags ^ sc->sc_if_flags) & 1303 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1304 et_setmulti(sc); 1305 } else { 1306 et_init_locked(sc); 1307 } 1308 } else { 1309 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1310 et_stop(sc); 1311 } 1312 sc->sc_if_flags = ifp->if_flags; 1313 ET_UNLOCK(sc); 1314 break; 1315 1316 case SIOCSIFMEDIA: 1317 case SIOCGIFMEDIA: 1318 mii = device_get_softc(sc->sc_miibus); 1319 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1320 break; 1321 1322 case SIOCADDMULTI: 1323 case SIOCDELMULTI: 1324 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1325 ET_LOCK(sc); 1326 et_setmulti(sc); 1327 ET_UNLOCK(sc); 1328 } 1329 break; 1330 1331 case SIOCSIFMTU: 1332 ET_LOCK(sc); 1333 #if 0 1334 if (sc->sc_flags & ET_FLAG_JUMBO) 1335 max_framelen = ET_JUMBO_FRAMELEN; 1336 else 1337 #endif 1338 max_framelen = MCLBYTES - 1; 1339 1340 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1341 error = EOPNOTSUPP; 1342 ET_UNLOCK(sc); 1343 break; 1344 } 1345 1346 if (ifp->if_mtu != ifr->ifr_mtu) { 1347 ifp->if_mtu = ifr->ifr_mtu; 1348 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1349 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1350 et_init_locked(sc); 1351 } 1352 } 1353 ET_UNLOCK(sc); 1354 break; 1355 1356 case SIOCSIFCAP: 1357 ET_LOCK(sc); 1358 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1359 if ((mask & IFCAP_TXCSUM) != 0 && 1360 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1361 ifp->if_capenable ^= IFCAP_TXCSUM; 1362 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1363 ifp->if_hwassist |= ET_CSUM_FEATURES; 1364 else 1365 ifp->if_hwassist &= ~ET_CSUM_FEATURES; 1366 } 1367 ET_UNLOCK(sc); 1368 break; 1369 1370 default: 1371 error = ether_ioctl(ifp, cmd, data); 1372 break; 1373 } 1374 return (error); 1375 } 1376 1377 static void 1378 et_start_locked(struct ifnet *ifp) 1379 { 1380 struct et_softc *sc; 1381 struct mbuf *m_head = NULL; 1382 struct et_txdesc_ring *tx_ring; 1383 struct et_txbuf_data *tbd; 1384 uint32_t tx_ready_pos; 1385 int enq; 1386 1387 sc = ifp->if_softc; 1388 ET_LOCK_ASSERT(sc); 1389 1390 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1391 IFF_DRV_RUNNING || 1392 (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) != 1393 (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) 1394 return; 1395 1396 /* 1397 * Driver does not request TX completion interrupt for every 1398 * queued frames to prevent generating excessive interrupts. 1399 * This means driver may wait for TX completion interrupt even 1400 * though some frames were successfully transmitted. Reclaiming 1401 * transmitted frames will ensure driver see all available 1402 * descriptors. 1403 */ 1404 tbd = &sc->sc_tx_data; 1405 if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3) 1406 et_txeof(sc); 1407 1408 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1409 if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 1410 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1411 break; 1412 } 1413 1414 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1415 if (m_head == NULL) 1416 break; 1417 1418 if (et_encap(sc, &m_head)) { 1419 if (m_head == NULL) { 1420 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1421 break; 1422 } 1423 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1424 if (tbd->tbd_used > 0) 1425 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1426 break; 1427 } 1428 enq++; 1429 ETHER_BPF_MTAP(ifp, m_head); 1430 } 1431 1432 if (enq > 0) { 1433 tx_ring = &sc->sc_tx_ring; 1434 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1435 BUS_DMASYNC_PREWRITE); 1436 tx_ready_pos = tx_ring->tr_ready_index & 1437 ET_TX_READY_POS_INDEX_MASK; 1438 if (tx_ring->tr_ready_wrap) 1439 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1440 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1441 sc->watchdog_timer = 5; 1442 } 1443 } 1444 1445 static void 1446 et_start(struct ifnet *ifp) 1447 { 1448 struct et_softc *sc; 1449 1450 sc = ifp->if_softc; 1451 ET_LOCK(sc); 1452 et_start_locked(ifp); 1453 ET_UNLOCK(sc); 1454 } 1455 1456 static int 1457 et_watchdog(struct et_softc *sc) 1458 { 1459 uint32_t status; 1460 1461 ET_LOCK_ASSERT(sc); 1462 1463 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1464 return (0); 1465 1466 bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1467 BUS_DMASYNC_POSTREAD); 1468 status = le32toh(*(sc->sc_tx_status.txsd_status)); 1469 if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1470 status); 1471 1472 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 1473 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1474 et_init_locked(sc); 1475 return (EJUSTRETURN); 1476 } 1477 1478 static int 1479 et_stop_rxdma(struct et_softc *sc) 1480 { 1481 1482 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1483 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1484 1485 DELAY(5); 1486 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1487 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1488 return (ETIMEDOUT); 1489 } 1490 return (0); 1491 } 1492 1493 static int 1494 et_stop_txdma(struct et_softc *sc) 1495 { 1496 1497 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1498 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1499 return (0); 1500 } 1501 1502 static void 1503 et_free_tx_ring(struct et_softc *sc) 1504 { 1505 struct et_txdesc_ring *tx_ring; 1506 struct et_txbuf_data *tbd; 1507 struct et_txbuf *tb; 1508 int i; 1509 1510 tbd = &sc->sc_tx_data; 1511 tx_ring = &sc->sc_tx_ring; 1512 for (i = 0; i < ET_TX_NDESC; ++i) { 1513 tb = &tbd->tbd_buf[i]; 1514 if (tb->tb_mbuf != NULL) { 1515 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1516 BUS_DMASYNC_POSTWRITE); 1517 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1518 m_freem(tb->tb_mbuf); 1519 tb->tb_mbuf = NULL; 1520 } 1521 } 1522 } 1523 1524 static void 1525 et_free_rx_ring(struct et_softc *sc) 1526 { 1527 struct et_rxbuf_data *rbd; 1528 struct et_rxdesc_ring *rx_ring; 1529 struct et_rxbuf *rb; 1530 int i; 1531 1532 /* Ring 0 */ 1533 rx_ring = &sc->sc_rx_ring[0]; 1534 rbd = &sc->sc_rx_data[0]; 1535 for (i = 0; i < ET_RX_NDESC; ++i) { 1536 rb = &rbd->rbd_buf[i]; 1537 if (rb->rb_mbuf != NULL) { 1538 bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1539 BUS_DMASYNC_POSTREAD); 1540 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 1541 m_freem(rb->rb_mbuf); 1542 rb->rb_mbuf = NULL; 1543 } 1544 } 1545 1546 /* Ring 1 */ 1547 rx_ring = &sc->sc_rx_ring[1]; 1548 rbd = &sc->sc_rx_data[1]; 1549 for (i = 0; i < ET_RX_NDESC; ++i) { 1550 rb = &rbd->rbd_buf[i]; 1551 if (rb->rb_mbuf != NULL) { 1552 bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1553 BUS_DMASYNC_POSTREAD); 1554 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1555 m_freem(rb->rb_mbuf); 1556 rb->rb_mbuf = NULL; 1557 } 1558 } 1559 } 1560 1561 static void 1562 et_setmulti(struct et_softc *sc) 1563 { 1564 struct ifnet *ifp; 1565 uint32_t hash[4] = { 0, 0, 0, 0 }; 1566 uint32_t rxmac_ctrl, pktfilt; 1567 struct ifmultiaddr *ifma; 1568 int i, count; 1569 1570 ET_LOCK_ASSERT(sc); 1571 ifp = sc->ifp; 1572 1573 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1574 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1575 1576 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1577 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1578 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1579 goto back; 1580 } 1581 1582 count = 0; 1583 if_maddr_rlock(ifp); 1584 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1585 uint32_t *hp, h; 1586 1587 if (ifma->ifma_addr->sa_family != AF_LINK) 1588 continue; 1589 1590 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 1591 ifma->ifma_addr), ETHER_ADDR_LEN); 1592 h = (h & 0x3f800000) >> 23; 1593 1594 hp = &hash[0]; 1595 if (h >= 32 && h < 64) { 1596 h -= 32; 1597 hp = &hash[1]; 1598 } else if (h >= 64 && h < 96) { 1599 h -= 64; 1600 hp = &hash[2]; 1601 } else if (h >= 96) { 1602 h -= 96; 1603 hp = &hash[3]; 1604 } 1605 *hp |= (1 << h); 1606 1607 ++count; 1608 } 1609 if_maddr_runlock(ifp); 1610 1611 for (i = 0; i < 4; ++i) 1612 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1613 1614 if (count > 0) 1615 pktfilt |= ET_PKTFILT_MCAST; 1616 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1617 back: 1618 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1619 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1620 } 1621 1622 static int 1623 et_chip_init(struct et_softc *sc) 1624 { 1625 struct ifnet *ifp; 1626 uint32_t rxq_end; 1627 int error, frame_len, rxmem_size; 1628 1629 ifp = sc->ifp; 1630 /* 1631 * Split 16Kbytes internal memory between TX and RX 1632 * according to frame length. 1633 */ 1634 frame_len = ET_FRAMELEN(ifp->if_mtu); 1635 if (frame_len < 2048) { 1636 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1637 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1638 rxmem_size = ET_MEM_SIZE / 2; 1639 } else { 1640 rxmem_size = ET_MEM_SIZE - 1641 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1642 } 1643 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1644 1645 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1646 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1647 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1648 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1649 1650 /* No loopback */ 1651 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1652 1653 /* Clear MSI configure */ 1654 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1655 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1656 1657 /* Disable timer */ 1658 CSR_WRITE_4(sc, ET_TIMER, 0); 1659 1660 /* Initialize MAC */ 1661 et_init_mac(sc); 1662 1663 /* Enable memory controllers */ 1664 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1665 1666 /* Initialize RX MAC */ 1667 et_init_rxmac(sc); 1668 1669 /* Initialize TX MAC */ 1670 et_init_txmac(sc); 1671 1672 /* Initialize RX DMA engine */ 1673 error = et_init_rxdma(sc); 1674 if (error) 1675 return (error); 1676 1677 /* Initialize TX DMA engine */ 1678 error = et_init_txdma(sc); 1679 if (error) 1680 return (error); 1681 1682 return (0); 1683 } 1684 1685 static void 1686 et_init_tx_ring(struct et_softc *sc) 1687 { 1688 struct et_txdesc_ring *tx_ring; 1689 struct et_txbuf_data *tbd; 1690 struct et_txstatus_data *txsd; 1691 1692 tx_ring = &sc->sc_tx_ring; 1693 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1694 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1695 BUS_DMASYNC_PREWRITE); 1696 1697 tbd = &sc->sc_tx_data; 1698 tbd->tbd_start_index = 0; 1699 tbd->tbd_start_wrap = 0; 1700 tbd->tbd_used = 0; 1701 1702 txsd = &sc->sc_tx_status; 1703 bzero(txsd->txsd_status, sizeof(uint32_t)); 1704 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1705 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1706 } 1707 1708 static int 1709 et_init_rx_ring(struct et_softc *sc) 1710 { 1711 struct et_rxstatus_data *rxsd; 1712 struct et_rxstat_ring *rxst_ring; 1713 struct et_rxbuf_data *rbd; 1714 int i, error, n; 1715 1716 for (n = 0; n < ET_RX_NRING; ++n) { 1717 rbd = &sc->sc_rx_data[n]; 1718 for (i = 0; i < ET_RX_NDESC; ++i) { 1719 error = rbd->rbd_newbuf(rbd, i); 1720 if (error) { 1721 if_printf(sc->ifp, "%d ring %d buf, " 1722 "newbuf failed: %d\n", n, i, error); 1723 return (error); 1724 } 1725 } 1726 } 1727 1728 rxsd = &sc->sc_rx_status; 1729 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1730 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1732 1733 rxst_ring = &sc->sc_rxstat_ring; 1734 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1735 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1736 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1737 1738 return (0); 1739 } 1740 1741 static int 1742 et_init_rxdma(struct et_softc *sc) 1743 { 1744 struct et_rxstatus_data *rxsd; 1745 struct et_rxstat_ring *rxst_ring; 1746 struct et_rxdesc_ring *rx_ring; 1747 int error; 1748 1749 error = et_stop_rxdma(sc); 1750 if (error) { 1751 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1752 return (error); 1753 } 1754 1755 /* 1756 * Install RX status 1757 */ 1758 rxsd = &sc->sc_rx_status; 1759 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1760 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1761 1762 /* 1763 * Install RX stat ring 1764 */ 1765 rxst_ring = &sc->sc_rxstat_ring; 1766 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1767 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1768 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1769 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1770 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1771 1772 /* Match ET_RXSTAT_POS */ 1773 rxst_ring->rsr_index = 0; 1774 rxst_ring->rsr_wrap = 0; 1775 1776 /* 1777 * Install the 2nd RX descriptor ring 1778 */ 1779 rx_ring = &sc->sc_rx_ring[1]; 1780 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1781 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1782 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1783 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1784 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1785 1786 /* Match ET_RX_RING1_POS */ 1787 rx_ring->rr_index = 0; 1788 rx_ring->rr_wrap = 1; 1789 1790 /* 1791 * Install the 1st RX descriptor ring 1792 */ 1793 rx_ring = &sc->sc_rx_ring[0]; 1794 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1795 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1796 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1797 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1798 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1799 1800 /* Match ET_RX_RING0_POS */ 1801 rx_ring->rr_index = 0; 1802 rx_ring->rr_wrap = 1; 1803 1804 /* 1805 * RX intr moderation 1806 */ 1807 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1808 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1809 1810 return (0); 1811 } 1812 1813 static int 1814 et_init_txdma(struct et_softc *sc) 1815 { 1816 struct et_txdesc_ring *tx_ring; 1817 struct et_txstatus_data *txsd; 1818 int error; 1819 1820 error = et_stop_txdma(sc); 1821 if (error) { 1822 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1823 return (error); 1824 } 1825 1826 /* 1827 * Install TX descriptor ring 1828 */ 1829 tx_ring = &sc->sc_tx_ring; 1830 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1831 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1832 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1833 1834 /* 1835 * Install TX status 1836 */ 1837 txsd = &sc->sc_tx_status; 1838 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1839 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1840 1841 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1842 1843 /* Match ET_TX_READY_POS */ 1844 tx_ring->tr_ready_index = 0; 1845 tx_ring->tr_ready_wrap = 0; 1846 1847 return (0); 1848 } 1849 1850 static void 1851 et_init_mac(struct et_softc *sc) 1852 { 1853 struct ifnet *ifp; 1854 const uint8_t *eaddr; 1855 uint32_t val; 1856 1857 /* Reset MAC */ 1858 CSR_WRITE_4(sc, ET_MAC_CFG1, 1859 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1860 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1861 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1862 1863 /* 1864 * Setup inter packet gap 1865 */ 1866 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1867 (88 << ET_IPG_NONB2B_2_SHIFT) | 1868 (80 << ET_IPG_MINIFG_SHIFT) | 1869 (96 << ET_IPG_B2B_SHIFT); 1870 CSR_WRITE_4(sc, ET_IPG, val); 1871 1872 /* 1873 * Setup half duplex mode 1874 */ 1875 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1876 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1877 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1878 ET_MAC_HDX_EXC_DEFER; 1879 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1880 1881 /* Clear MAC control */ 1882 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1883 1884 /* Reset MII */ 1885 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1886 1887 /* 1888 * Set MAC address 1889 */ 1890 ifp = sc->ifp; 1891 eaddr = IF_LLADDR(ifp); 1892 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1893 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1894 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1895 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1896 1897 /* Set max frame length */ 1898 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 1899 1900 /* Bring MAC out of reset state */ 1901 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1902 } 1903 1904 static void 1905 et_init_rxmac(struct et_softc *sc) 1906 { 1907 struct ifnet *ifp; 1908 const uint8_t *eaddr; 1909 uint32_t val; 1910 int i; 1911 1912 /* Disable RX MAC and WOL */ 1913 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1914 1915 /* 1916 * Clear all WOL related registers 1917 */ 1918 for (i = 0; i < 3; ++i) 1919 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1920 for (i = 0; i < 20; ++i) 1921 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1922 1923 /* 1924 * Set WOL source address. XXX is this necessary? 1925 */ 1926 ifp = sc->ifp; 1927 eaddr = IF_LLADDR(ifp); 1928 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1929 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1930 val = (eaddr[0] << 8) | eaddr[1]; 1931 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1932 1933 /* Clear packet filters */ 1934 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1935 1936 /* No ucast filtering */ 1937 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1938 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1939 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1940 1941 if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 1942 /* 1943 * In order to transmit jumbo packets greater than 1944 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1945 * RX MAC and RX DMA needs to be reduced in size to 1946 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1947 * order to implement this, we must use "cut through" 1948 * mode in the RX MAC, which chops packets down into 1949 * segments. In this case we selected 256 bytes, 1950 * since this is the size of the PCI-Express TLP's 1951 * that the ET1310 uses. 1952 */ 1953 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1954 ET_RXMAC_MC_SEGSZ_ENABLE; 1955 } else { 1956 val = 0; 1957 } 1958 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1959 1960 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1961 1962 /* Initialize RX MAC management register */ 1963 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1964 1965 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1966 1967 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1968 ET_RXMAC_MGT_PASS_ECRC | 1969 ET_RXMAC_MGT_PASS_ELEN | 1970 ET_RXMAC_MGT_PASS_ETRUNC | 1971 ET_RXMAC_MGT_CHECK_PKT); 1972 1973 /* 1974 * Configure runt filtering (may not work on certain chip generation) 1975 */ 1976 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1977 ET_PKTFILT_MINLEN_MASK; 1978 val |= ET_PKTFILT_FRAG; 1979 CSR_WRITE_4(sc, ET_PKTFILT, val); 1980 1981 /* Enable RX MAC but leave WOL disabled */ 1982 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1983 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1984 1985 /* 1986 * Setup multicast hash and allmulti/promisc mode 1987 */ 1988 et_setmulti(sc); 1989 } 1990 1991 static void 1992 et_init_txmac(struct et_softc *sc) 1993 { 1994 1995 /* Disable TX MAC and FC(?) */ 1996 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1997 1998 /* 1999 * Initialize pause time. 2000 * This register should be set before XON/XOFF frame is 2001 * sent by driver. 2002 */ 2003 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT); 2004 2005 /* Enable TX MAC but leave FC(?) diabled */ 2006 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 2007 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 2008 } 2009 2010 static int 2011 et_start_rxdma(struct et_softc *sc) 2012 { 2013 uint32_t val; 2014 2015 val = (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 2016 ET_RXDMA_CTRL_RING0_ENABLE; 2017 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 2018 ET_RXDMA_CTRL_RING1_ENABLE; 2019 2020 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 2021 2022 DELAY(5); 2023 2024 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 2025 if_printf(sc->ifp, "can't start RX DMA engine\n"); 2026 return (ETIMEDOUT); 2027 } 2028 return (0); 2029 } 2030 2031 static int 2032 et_start_txdma(struct et_softc *sc) 2033 { 2034 2035 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 2036 return (0); 2037 } 2038 2039 static void 2040 et_rxeof(struct et_softc *sc) 2041 { 2042 struct et_rxstatus_data *rxsd; 2043 struct et_rxstat_ring *rxst_ring; 2044 struct et_rxbuf_data *rbd; 2045 struct et_rxdesc_ring *rx_ring; 2046 struct et_rxstat *st; 2047 struct ifnet *ifp; 2048 struct mbuf *m; 2049 uint32_t rxstat_pos, rxring_pos; 2050 uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 2051 int buflen, buf_idx, npost[2], ring_idx; 2052 int rxst_index, rxst_wrap; 2053 2054 ET_LOCK_ASSERT(sc); 2055 2056 ifp = sc->ifp; 2057 rxsd = &sc->sc_rx_status; 2058 rxst_ring = &sc->sc_rxstat_ring; 2059 2060 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2061 return; 2062 2063 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2064 BUS_DMASYNC_POSTREAD); 2065 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2066 BUS_DMASYNC_POSTREAD); 2067 2068 npost[0] = npost[1] = 0; 2069 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 2070 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 2071 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 2072 ET_RXS_STATRING_INDEX_SHIFT; 2073 2074 while (rxst_index != rxst_ring->rsr_index || 2075 rxst_wrap != rxst_ring->rsr_wrap) { 2076 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2077 break; 2078 2079 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 2080 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 2081 rxst_info1 = le32toh(st->rxst_info1); 2082 rxst_info2 = le32toh(st->rxst_info2); 2083 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 2084 ET_RXST_INFO2_LEN_SHIFT; 2085 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 2086 ET_RXST_INFO2_BUFIDX_SHIFT; 2087 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 2088 ET_RXST_INFO2_RINGIDX_SHIFT; 2089 2090 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 2091 rxst_ring->rsr_index = 0; 2092 rxst_ring->rsr_wrap ^= 1; 2093 } 2094 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 2095 if (rxst_ring->rsr_wrap) 2096 rxstat_pos |= ET_RXSTAT_POS_WRAP; 2097 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 2098 2099 if (ring_idx >= ET_RX_NRING) { 2100 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2101 if_printf(ifp, "invalid ring index %d\n", ring_idx); 2102 continue; 2103 } 2104 if (buf_idx >= ET_RX_NDESC) { 2105 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2106 if_printf(ifp, "invalid buf index %d\n", buf_idx); 2107 continue; 2108 } 2109 2110 rbd = &sc->sc_rx_data[ring_idx]; 2111 m = rbd->rbd_buf[buf_idx].rb_mbuf; 2112 if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 2113 /* Discard errored frame. */ 2114 rbd->rbd_discard(rbd, buf_idx); 2115 } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 2116 /* No available mbufs, discard it. */ 2117 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2118 rbd->rbd_discard(rbd, buf_idx); 2119 } else { 2120 buflen -= ETHER_CRC_LEN; 2121 if (buflen < ETHER_HDR_LEN) { 2122 m_freem(m); 2123 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2124 } else { 2125 m->m_pkthdr.len = m->m_len = buflen; 2126 m->m_pkthdr.rcvif = ifp; 2127 ET_UNLOCK(sc); 2128 ifp->if_input(ifp, m); 2129 ET_LOCK(sc); 2130 } 2131 } 2132 2133 rx_ring = &sc->sc_rx_ring[ring_idx]; 2134 if (buf_idx != rx_ring->rr_index) { 2135 if_printf(ifp, 2136 "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 2137 ring_idx, buf_idx, rx_ring->rr_index); 2138 } 2139 2140 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2141 if (++rx_ring->rr_index == ET_RX_NDESC) { 2142 rx_ring->rr_index = 0; 2143 rx_ring->rr_wrap ^= 1; 2144 } 2145 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2146 if (rx_ring->rr_wrap) 2147 rxring_pos |= ET_RX_RING_POS_WRAP; 2148 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2149 } 2150 2151 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2152 BUS_DMASYNC_PREREAD); 2153 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2154 BUS_DMASYNC_PREREAD); 2155 } 2156 2157 static int 2158 et_encap(struct et_softc *sc, struct mbuf **m0) 2159 { 2160 struct et_txdesc_ring *tx_ring; 2161 struct et_txbuf_data *tbd; 2162 struct et_txdesc *td; 2163 struct mbuf *m; 2164 bus_dma_segment_t segs[ET_NSEG_MAX]; 2165 bus_dmamap_t map; 2166 uint32_t csum_flags, last_td_ctrl2; 2167 int error, i, idx, first_idx, last_idx, nsegs; 2168 2169 tx_ring = &sc->sc_tx_ring; 2170 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2171 tbd = &sc->sc_tx_data; 2172 first_idx = tx_ring->tr_ready_index; 2173 map = tbd->tbd_buf[first_idx].tb_dmap; 2174 2175 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2176 0); 2177 if (error == EFBIG) { 2178 m = m_collapse(*m0, M_NOWAIT, ET_NSEG_MAX); 2179 if (m == NULL) { 2180 m_freem(*m0); 2181 *m0 = NULL; 2182 return (ENOMEM); 2183 } 2184 *m0 = m; 2185 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2186 &nsegs, 0); 2187 if (error != 0) { 2188 m_freem(*m0); 2189 *m0 = NULL; 2190 return (error); 2191 } 2192 } else if (error != 0) 2193 return (error); 2194 2195 /* Check for descriptor overruns. */ 2196 if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2197 bus_dmamap_unload(sc->sc_tx_tag, map); 2198 return (ENOBUFS); 2199 } 2200 bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2201 2202 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2203 sc->sc_tx += nsegs; 2204 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2205 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2206 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2207 } 2208 2209 m = *m0; 2210 csum_flags = 0; 2211 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2212 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2213 csum_flags |= ET_TDCTRL2_CSUM_IP; 2214 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2215 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2216 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2217 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2218 } 2219 last_idx = -1; 2220 for (i = 0; i < nsegs; ++i) { 2221 idx = (first_idx + i) % ET_TX_NDESC; 2222 td = &tx_ring->tr_desc[idx]; 2223 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2224 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2225 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2226 if (i == nsegs - 1) { 2227 /* Last frag */ 2228 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2229 last_idx = idx; 2230 } else 2231 td->td_ctrl2 = htole32(csum_flags); 2232 2233 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2234 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2235 tx_ring->tr_ready_index = 0; 2236 tx_ring->tr_ready_wrap ^= 1; 2237 } 2238 } 2239 td = &tx_ring->tr_desc[first_idx]; 2240 /* First frag */ 2241 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 2242 2243 MPASS(last_idx >= 0); 2244 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2245 tbd->tbd_buf[last_idx].tb_dmap = map; 2246 tbd->tbd_buf[last_idx].tb_mbuf = m; 2247 2248 tbd->tbd_used += nsegs; 2249 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2250 2251 return (0); 2252 } 2253 2254 static void 2255 et_txeof(struct et_softc *sc) 2256 { 2257 struct et_txdesc_ring *tx_ring; 2258 struct et_txbuf_data *tbd; 2259 struct et_txbuf *tb; 2260 struct ifnet *ifp; 2261 uint32_t tx_done; 2262 int end, wrap; 2263 2264 ET_LOCK_ASSERT(sc); 2265 2266 ifp = sc->ifp; 2267 tx_ring = &sc->sc_tx_ring; 2268 tbd = &sc->sc_tx_data; 2269 2270 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2271 return; 2272 2273 if (tbd->tbd_used == 0) 2274 return; 2275 2276 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2277 BUS_DMASYNC_POSTWRITE); 2278 2279 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2280 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2281 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2282 2283 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2284 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2285 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2286 if (tb->tb_mbuf != NULL) { 2287 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2288 BUS_DMASYNC_POSTWRITE); 2289 bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 2290 m_freem(tb->tb_mbuf); 2291 tb->tb_mbuf = NULL; 2292 } 2293 2294 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2295 tbd->tbd_start_index = 0; 2296 tbd->tbd_start_wrap ^= 1; 2297 } 2298 2299 MPASS(tbd->tbd_used > 0); 2300 tbd->tbd_used--; 2301 } 2302 2303 if (tbd->tbd_used == 0) 2304 sc->watchdog_timer = 0; 2305 if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 2306 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2307 } 2308 2309 static void 2310 et_tick(void *xsc) 2311 { 2312 struct et_softc *sc; 2313 struct ifnet *ifp; 2314 struct mii_data *mii; 2315 2316 sc = xsc; 2317 ET_LOCK_ASSERT(sc); 2318 ifp = sc->ifp; 2319 mii = device_get_softc(sc->sc_miibus); 2320 2321 mii_tick(mii); 2322 et_stats_update(sc); 2323 if (et_watchdog(sc) == EJUSTRETURN) 2324 return; 2325 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2326 } 2327 2328 static int 2329 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 2330 { 2331 struct et_softc *sc; 2332 struct et_rxdesc *desc; 2333 struct et_rxbuf *rb; 2334 struct mbuf *m; 2335 bus_dma_segment_t segs[1]; 2336 bus_dmamap_t dmap; 2337 int nsegs; 2338 2339 MPASS(buf_idx < ET_RX_NDESC); 2340 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2341 if (m == NULL) 2342 return (ENOBUFS); 2343 m->m_len = m->m_pkthdr.len = MCLBYTES; 2344 m_adj(m, ETHER_ALIGN); 2345 2346 sc = rbd->rbd_softc; 2347 rb = &rbd->rbd_buf[buf_idx]; 2348 2349 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2350 segs, &nsegs, 0) != 0) { 2351 m_freem(m); 2352 return (ENOBUFS); 2353 } 2354 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2355 2356 if (rb->rb_mbuf != NULL) { 2357 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 2358 BUS_DMASYNC_POSTREAD); 2359 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 2360 } 2361 dmap = rb->rb_dmap; 2362 rb->rb_dmap = sc->sc_rx_sparemap; 2363 sc->sc_rx_sparemap = dmap; 2364 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2365 2366 rb->rb_mbuf = m; 2367 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2368 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2369 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2370 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2371 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2372 BUS_DMASYNC_PREWRITE); 2373 return (0); 2374 } 2375 2376 static void 2377 et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2378 { 2379 struct et_rxdesc *desc; 2380 2381 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2382 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2383 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2384 BUS_DMASYNC_PREWRITE); 2385 } 2386 2387 static int 2388 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2389 { 2390 struct et_softc *sc; 2391 struct et_rxdesc *desc; 2392 struct et_rxbuf *rb; 2393 struct mbuf *m; 2394 bus_dma_segment_t segs[1]; 2395 bus_dmamap_t dmap; 2396 int nsegs; 2397 2398 MPASS(buf_idx < ET_RX_NDESC); 2399 MGETHDR(m, M_NOWAIT, MT_DATA); 2400 if (m == NULL) 2401 return (ENOBUFS); 2402 m->m_len = m->m_pkthdr.len = MHLEN; 2403 m_adj(m, ETHER_ALIGN); 2404 2405 sc = rbd->rbd_softc; 2406 rb = &rbd->rbd_buf[buf_idx]; 2407 2408 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2409 m, segs, &nsegs, 0) != 0) { 2410 m_freem(m); 2411 return (ENOBUFS); 2412 } 2413 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2414 2415 if (rb->rb_mbuf != NULL) { 2416 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2417 BUS_DMASYNC_POSTREAD); 2418 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2419 } 2420 dmap = rb->rb_dmap; 2421 rb->rb_dmap = sc->sc_rx_mini_sparemap; 2422 sc->sc_rx_mini_sparemap = dmap; 2423 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2424 2425 rb->rb_mbuf = m; 2426 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2427 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2428 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2429 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2430 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2431 BUS_DMASYNC_PREWRITE); 2432 return (0); 2433 } 2434 2435 #define ET_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2436 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2437 #define ET_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2438 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2439 2440 /* 2441 * Create sysctl tree 2442 */ 2443 static void 2444 et_add_sysctls(struct et_softc * sc) 2445 { 2446 struct sysctl_ctx_list *ctx; 2447 struct sysctl_oid_list *children, *parent; 2448 struct sysctl_oid *tree; 2449 struct et_hw_stats *stats; 2450 2451 ctx = device_get_sysctl_ctx(sc->dev); 2452 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2453 2454 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2455 CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_npkts, "I", 2456 "RX IM, # packets per RX interrupt"); 2457 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2458 CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_delay, "I", 2459 "RX IM, RX interrupt delay (x10 usec)"); 2460 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2461 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2462 "TX IM, # segments per TX interrupt"); 2463 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2464 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2465 2466 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 2467 NULL, "ET statistics"); 2468 parent = SYSCTL_CHILDREN(tree); 2469 2470 /* TX/RX statistics. */ 2471 stats = &sc->sc_stats; 2472 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64, 2473 "0 to 64 bytes frames"); 2474 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65, 2475 "65 to 127 bytes frames"); 2476 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128, 2477 "128 to 255 bytes frames"); 2478 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256, 2479 "256 to 511 bytes frames"); 2480 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512, 2481 "512 to 1023 bytes frames"); 2482 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024, 2483 "1024 to 1518 bytes frames"); 2484 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519, 2485 "1519 to 1522 bytes frames"); 2486 2487 /* RX statistics. */ 2488 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2489 NULL, "RX MAC statistics"); 2490 children = SYSCTL_CHILDREN(tree); 2491 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2492 &stats->rx_bytes, "Good bytes"); 2493 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2494 &stats->rx_frames, "Good frames"); 2495 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2496 &stats->rx_crcerrs, "CRC errors"); 2497 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2498 &stats->rx_mcast, "Multicast frames"); 2499 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2500 &stats->rx_bcast, "Broadcast frames"); 2501 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2502 &stats->rx_control, "Control frames"); 2503 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2504 &stats->rx_pause, "Pause frames"); 2505 ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control", 2506 &stats->rx_unknown_control, "Unknown control frames"); 2507 ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs", 2508 &stats->rx_alignerrs, "Alignment errors"); 2509 ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs", 2510 &stats->rx_lenerrs, "Frames with length mismatched"); 2511 ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs", 2512 &stats->rx_codeerrs, "Frames with code error"); 2513 ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs", 2514 &stats->rx_cserrs, "Frames with carrier sense error"); 2515 ET_SYSCTL_STAT_ADD32(ctx, children, "runts", 2516 &stats->rx_runts, "Too short frames"); 2517 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2518 &stats->rx_oversize, "Oversized frames"); 2519 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2520 &stats->rx_fragments, "Fragmented frames"); 2521 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2522 &stats->rx_jabbers, "Frames with jabber error"); 2523 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2524 &stats->rx_drop, "Dropped frames"); 2525 2526 /* TX statistics. */ 2527 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2528 NULL, "TX MAC statistics"); 2529 children = SYSCTL_CHILDREN(tree); 2530 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2531 &stats->tx_bytes, "Good bytes"); 2532 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2533 &stats->tx_frames, "Good frames"); 2534 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2535 &stats->tx_mcast, "Multicast frames"); 2536 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2537 &stats->tx_bcast, "Broadcast frames"); 2538 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2539 &stats->tx_pause, "Pause frames"); 2540 ET_SYSCTL_STAT_ADD32(ctx, children, "deferred", 2541 &stats->tx_deferred, "Deferred frames"); 2542 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred", 2543 &stats->tx_excess_deferred, "Excessively deferred frames"); 2544 ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls", 2545 &stats->tx_single_colls, "Single collisions"); 2546 ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls", 2547 &stats->tx_multi_colls, "Multiple collisions"); 2548 ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls", 2549 &stats->tx_late_colls, "Late collisions"); 2550 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls", 2551 &stats->tx_excess_colls, "Excess collisions"); 2552 ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls", 2553 &stats->tx_total_colls, "Total collisions"); 2554 ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored", 2555 &stats->tx_pause_honored, "Honored pause frames"); 2556 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2557 &stats->tx_drop, "Dropped frames"); 2558 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2559 &stats->tx_jabbers, "Frames with jabber errors"); 2560 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2561 &stats->tx_crcerrs, "Frames with CRC errors"); 2562 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2563 &stats->tx_control, "Control frames"); 2564 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2565 &stats->tx_oversize, "Oversized frames"); 2566 ET_SYSCTL_STAT_ADD32(ctx, children, "undersize", 2567 &stats->tx_undersize, "Undersized frames"); 2568 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2569 &stats->tx_fragments, "Fragmented frames"); 2570 } 2571 2572 #undef ET_SYSCTL_STAT_ADD32 2573 #undef ET_SYSCTL_STAT_ADD64 2574 2575 static int 2576 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2577 { 2578 struct et_softc *sc; 2579 struct ifnet *ifp; 2580 int error, v; 2581 2582 sc = arg1; 2583 ifp = sc->ifp; 2584 v = sc->sc_rx_intr_npkts; 2585 error = sysctl_handle_int(oidp, &v, 0, req); 2586 if (error || req->newptr == NULL) 2587 goto back; 2588 if (v <= 0) { 2589 error = EINVAL; 2590 goto back; 2591 } 2592 2593 if (sc->sc_rx_intr_npkts != v) { 2594 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2595 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2596 sc->sc_rx_intr_npkts = v; 2597 } 2598 back: 2599 return (error); 2600 } 2601 2602 static int 2603 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2604 { 2605 struct et_softc *sc; 2606 struct ifnet *ifp; 2607 int error, v; 2608 2609 sc = arg1; 2610 ifp = sc->ifp; 2611 v = sc->sc_rx_intr_delay; 2612 error = sysctl_handle_int(oidp, &v, 0, req); 2613 if (error || req->newptr == NULL) 2614 goto back; 2615 if (v <= 0) { 2616 error = EINVAL; 2617 goto back; 2618 } 2619 2620 if (sc->sc_rx_intr_delay != v) { 2621 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2622 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2623 sc->sc_rx_intr_delay = v; 2624 } 2625 back: 2626 return (error); 2627 } 2628 2629 static void 2630 et_stats_update(struct et_softc *sc) 2631 { 2632 struct et_hw_stats *stats; 2633 2634 stats = &sc->sc_stats; 2635 stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64); 2636 stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127); 2637 stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255); 2638 stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511); 2639 stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023); 2640 stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518); 2641 stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522); 2642 2643 stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES); 2644 stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES); 2645 stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR); 2646 stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST); 2647 stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST); 2648 stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL); 2649 stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE); 2650 stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL); 2651 stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR); 2652 stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR); 2653 stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR); 2654 stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR); 2655 stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT); 2656 stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE); 2657 stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG); 2658 stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER); 2659 stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP); 2660 2661 stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES); 2662 stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES); 2663 stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST); 2664 stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST); 2665 stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE); 2666 stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER); 2667 stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER); 2668 stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL); 2669 stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL); 2670 stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL); 2671 stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL); 2672 stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL); 2673 stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR); 2674 stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP); 2675 stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER); 2676 stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR); 2677 stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL); 2678 stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE); 2679 stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE); 2680 stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG); 2681 } 2682 2683 static uint64_t 2684 et_get_counter(struct ifnet *ifp, ift_counter cnt) 2685 { 2686 struct et_softc *sc; 2687 struct et_hw_stats *stats; 2688 2689 sc = if_getsoftc(ifp); 2690 stats = &sc->sc_stats; 2691 2692 switch (cnt) { 2693 case IFCOUNTER_OPACKETS: 2694 return (stats->tx_frames); 2695 case IFCOUNTER_COLLISIONS: 2696 return (stats->tx_total_colls); 2697 case IFCOUNTER_OERRORS: 2698 return (stats->tx_drop + stats->tx_jabbers + 2699 stats->tx_crcerrs + stats->tx_excess_deferred + 2700 stats->tx_late_colls); 2701 case IFCOUNTER_IPACKETS: 2702 return (stats->rx_frames); 2703 case IFCOUNTER_IERRORS: 2704 return (stats->rx_crcerrs + stats->rx_alignerrs + 2705 stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs + 2706 stats->rx_runts + stats->rx_jabbers + stats->rx_drop); 2707 default: 2708 return (if_get_counter_default(ifp, cnt)); 2709 } 2710 } 2711 2712 static int 2713 et_suspend(device_t dev) 2714 { 2715 struct et_softc *sc; 2716 uint32_t pmcfg; 2717 2718 sc = device_get_softc(dev); 2719 ET_LOCK(sc); 2720 if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2721 et_stop(sc); 2722 /* Diable all clocks and put PHY into COMA. */ 2723 pmcfg = CSR_READ_4(sc, ET_PM); 2724 pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | 2725 ET_PM_RXCLK_GATE); 2726 pmcfg |= ET_PM_PHY_SW_COMA; 2727 CSR_WRITE_4(sc, ET_PM, pmcfg); 2728 ET_UNLOCK(sc); 2729 return (0); 2730 } 2731 2732 static int 2733 et_resume(device_t dev) 2734 { 2735 struct et_softc *sc; 2736 uint32_t pmcfg; 2737 2738 sc = device_get_softc(dev); 2739 ET_LOCK(sc); 2740 /* Take PHY out of COMA and enable clocks. */ 2741 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 2742 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 2743 pmcfg |= EM_PM_GIGEPHY_ENB; 2744 CSR_WRITE_4(sc, ET_PM, pmcfg); 2745 if ((sc->ifp->if_flags & IFF_UP) != 0) 2746 et_init_locked(sc); 2747 ET_UNLOCK(sc); 2748 return (0); 2749 } 2750