1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/endian.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/malloc.h> 45 #include <sys/mbuf.h> 46 #include <sys/proc.h> 47 #include <sys/rman.h> 48 #include <sys/module.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/sysctl.h> 52 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_dl.h> 57 #include <net/if_types.h> 58 #include <net/bpf.h> 59 #include <net/if_arp.h> 60 #include <net/if_media.h> 61 #include <net/if_vlan_var.h> 62 63 #include <machine/bus.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <dev/et/if_etreg.h> 72 #include <dev/et/if_etvar.h> 73 74 #include "miibus_if.h" 75 76 MODULE_DEPEND(et, pci, 1, 1, 1); 77 MODULE_DEPEND(et, ether, 1, 1, 1); 78 MODULE_DEPEND(et, miibus, 1, 1, 1); 79 80 /* Tunables. */ 81 static int msi_disable = 0; 82 TUNABLE_INT("hw.et.msi_disable", &msi_disable); 83 84 #define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85 86 static int et_probe(device_t); 87 static int et_attach(device_t); 88 static int et_detach(device_t); 89 static int et_shutdown(device_t); 90 static int et_suspend(device_t); 91 static int et_resume(device_t); 92 93 static int et_miibus_readreg(device_t, int, int); 94 static int et_miibus_writereg(device_t, int, int, int); 95 static void et_miibus_statchg(device_t); 96 97 static void et_init_locked(struct et_softc *); 98 static void et_init(void *); 99 static int et_ioctl(if_t, u_long, caddr_t); 100 static void et_start_locked(if_t); 101 static void et_start(if_t); 102 static int et_watchdog(struct et_softc *); 103 static int et_ifmedia_upd_locked(if_t); 104 static int et_ifmedia_upd(if_t); 105 static void et_ifmedia_sts(if_t, struct ifmediareq *); 106 static uint64_t et_get_counter(if_t, ift_counter); 107 108 static void et_add_sysctls(struct et_softc *); 109 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 110 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 111 112 static void et_intr(void *); 113 static void et_rxeof(struct et_softc *); 114 static void et_txeof(struct et_softc *); 115 116 static int et_dma_alloc(struct et_softc *); 117 static void et_dma_free(struct et_softc *); 118 static void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 119 static int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 120 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 121 const char *); 122 static void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 123 bus_dmamap_t, bus_addr_t *); 124 static void et_init_tx_ring(struct et_softc *); 125 static int et_init_rx_ring(struct et_softc *); 126 static void et_free_tx_ring(struct et_softc *); 127 static void et_free_rx_ring(struct et_softc *); 128 static int et_encap(struct et_softc *, struct mbuf **); 129 static int et_newbuf_cluster(struct et_rxbuf_data *, int); 130 static int et_newbuf_hdr(struct et_rxbuf_data *, int); 131 static void et_rxbuf_discard(struct et_rxbuf_data *, int); 132 133 static void et_stop(struct et_softc *); 134 static int et_chip_init(struct et_softc *); 135 static void et_chip_attach(struct et_softc *); 136 static void et_init_mac(struct et_softc *); 137 static void et_init_rxmac(struct et_softc *); 138 static void et_init_txmac(struct et_softc *); 139 static int et_init_rxdma(struct et_softc *); 140 static int et_init_txdma(struct et_softc *); 141 static int et_start_rxdma(struct et_softc *); 142 static int et_start_txdma(struct et_softc *); 143 static int et_stop_rxdma(struct et_softc *); 144 static int et_stop_txdma(struct et_softc *); 145 static void et_reset(struct et_softc *); 146 static int et_bus_config(struct et_softc *); 147 static void et_get_eaddr(device_t, uint8_t[]); 148 static void et_setmulti(struct et_softc *); 149 static void et_tick(void *); 150 static void et_stats_update(struct et_softc *); 151 152 static const struct et_dev { 153 uint16_t vid; 154 uint16_t did; 155 const char *desc; 156 } et_devices[] = { 157 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 158 "Agere ET1310 Gigabit Ethernet" }, 159 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 160 "Agere ET1310 Fast Ethernet" }, 161 { 0, 0, NULL } 162 }; 163 164 static device_method_t et_methods[] = { 165 DEVMETHOD(device_probe, et_probe), 166 DEVMETHOD(device_attach, et_attach), 167 DEVMETHOD(device_detach, et_detach), 168 DEVMETHOD(device_shutdown, et_shutdown), 169 DEVMETHOD(device_suspend, et_suspend), 170 DEVMETHOD(device_resume, et_resume), 171 172 DEVMETHOD(miibus_readreg, et_miibus_readreg), 173 DEVMETHOD(miibus_writereg, et_miibus_writereg), 174 DEVMETHOD(miibus_statchg, et_miibus_statchg), 175 176 DEVMETHOD_END 177 }; 178 179 static driver_t et_driver = { 180 "et", 181 et_methods, 182 sizeof(struct et_softc) 183 }; 184 185 DRIVER_MODULE(et, pci, et_driver, 0, 0); 186 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, et, et_devices, 187 nitems(et_devices) - 1); 188 DRIVER_MODULE(miibus, et, miibus_driver, 0, 0); 189 190 static int et_rx_intr_npkts = 32; 191 static int et_rx_intr_delay = 20; /* x10 usec */ 192 static int et_tx_intr_nsegs = 126; 193 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 194 195 TUNABLE_INT("hw.et.timer", &et_timer); 196 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 197 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 198 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 199 200 static int 201 et_probe(device_t dev) 202 { 203 const struct et_dev *d; 204 uint16_t did, vid; 205 206 vid = pci_get_vendor(dev); 207 did = pci_get_device(dev); 208 209 for (d = et_devices; d->desc != NULL; ++d) { 210 if (vid == d->vid && did == d->did) { 211 device_set_desc(dev, d->desc); 212 return (BUS_PROBE_DEFAULT); 213 } 214 } 215 return (ENXIO); 216 } 217 218 static int 219 et_attach(device_t dev) 220 { 221 struct et_softc *sc; 222 if_t ifp; 223 uint8_t eaddr[ETHER_ADDR_LEN]; 224 uint32_t pmcfg; 225 int cap, error, msic; 226 227 sc = device_get_softc(dev); 228 sc->dev = dev; 229 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 230 MTX_DEF); 231 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 232 233 ifp = sc->ifp = if_alloc(IFT_ETHER); 234 if (ifp == NULL) { 235 device_printf(dev, "can not if_alloc()\n"); 236 error = ENOSPC; 237 goto fail; 238 } 239 240 /* 241 * Initialize tunables 242 */ 243 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 244 sc->sc_rx_intr_delay = et_rx_intr_delay; 245 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 246 sc->sc_timer = et_timer; 247 248 /* Enable bus mastering */ 249 pci_enable_busmaster(dev); 250 251 /* 252 * Allocate IO memory 253 */ 254 sc->sc_mem_rid = PCIR_BAR(0); 255 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 256 &sc->sc_mem_rid, RF_ACTIVE); 257 if (sc->sc_mem_res == NULL) { 258 device_printf(dev, "can't allocate IO memory\n"); 259 return (ENXIO); 260 } 261 262 msic = 0; 263 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 264 sc->sc_expcap = cap; 265 sc->sc_flags |= ET_FLAG_PCIE; 266 msic = pci_msi_count(dev); 267 if (bootverbose) 268 device_printf(dev, "MSI count: %d\n", msic); 269 } 270 if (msic > 0 && msi_disable == 0) { 271 msic = 1; 272 if (pci_alloc_msi(dev, &msic) == 0) { 273 if (msic == 1) { 274 device_printf(dev, "Using %d MSI message\n", 275 msic); 276 sc->sc_flags |= ET_FLAG_MSI; 277 } else 278 pci_release_msi(dev); 279 } 280 } 281 282 /* 283 * Allocate IRQ 284 */ 285 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 286 sc->sc_irq_rid = 0; 287 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 288 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 289 } else { 290 sc->sc_irq_rid = 1; 291 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 292 &sc->sc_irq_rid, RF_ACTIVE); 293 } 294 if (sc->sc_irq_res == NULL) { 295 device_printf(dev, "can't allocate irq\n"); 296 error = ENXIO; 297 goto fail; 298 } 299 300 if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST) 301 sc->sc_flags |= ET_FLAG_FASTETHER; 302 303 error = et_bus_config(sc); 304 if (error) 305 goto fail; 306 307 et_get_eaddr(dev, eaddr); 308 309 /* Take PHY out of COMA and enable clocks. */ 310 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 311 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 312 pmcfg |= EM_PM_GIGEPHY_ENB; 313 CSR_WRITE_4(sc, ET_PM, pmcfg); 314 315 et_reset(sc); 316 317 error = et_dma_alloc(sc); 318 if (error) 319 goto fail; 320 321 if_setsoftc(ifp, sc); 322 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 323 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 324 if_setinitfn(ifp, et_init); 325 if_setioctlfn(ifp, et_ioctl); 326 if_setstartfn(ifp, et_start); 327 if_setgetcounterfn(ifp, et_get_counter); 328 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_VLAN_MTU); 329 if_setcapenable(ifp, if_getcapabilities(ifp)); 330 if_setsendqlen(ifp, ET_TX_NDESC - 1); 331 if_setsendqready(ifp); 332 333 et_chip_attach(sc); 334 335 error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 336 et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 337 MIIF_DOPAUSE); 338 if (error) { 339 device_printf(dev, "attaching PHYs failed\n"); 340 goto fail; 341 } 342 343 ether_ifattach(ifp, eaddr); 344 345 /* Tell the upper layer(s) we support long frames. */ 346 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 347 348 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 349 NULL, et_intr, sc, &sc->sc_irq_handle); 350 if (error) { 351 ether_ifdetach(ifp); 352 device_printf(dev, "can't setup intr\n"); 353 goto fail; 354 } 355 356 et_add_sysctls(sc); 357 358 return (0); 359 fail: 360 et_detach(dev); 361 return (error); 362 } 363 364 static int 365 et_detach(device_t dev) 366 { 367 struct et_softc *sc; 368 369 sc = device_get_softc(dev); 370 if (device_is_attached(dev)) { 371 ether_ifdetach(sc->ifp); 372 ET_LOCK(sc); 373 et_stop(sc); 374 ET_UNLOCK(sc); 375 callout_drain(&sc->sc_tick); 376 } 377 378 if (sc->sc_miibus != NULL) 379 device_delete_child(dev, sc->sc_miibus); 380 bus_generic_detach(dev); 381 382 if (sc->sc_irq_handle != NULL) 383 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 384 if (sc->sc_irq_res != NULL) 385 bus_release_resource(dev, SYS_RES_IRQ, 386 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 387 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 388 pci_release_msi(dev); 389 if (sc->sc_mem_res != NULL) 390 bus_release_resource(dev, SYS_RES_MEMORY, 391 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 392 393 if (sc->ifp != NULL) 394 if_free(sc->ifp); 395 396 et_dma_free(sc); 397 398 mtx_destroy(&sc->sc_mtx); 399 400 return (0); 401 } 402 403 static int 404 et_shutdown(device_t dev) 405 { 406 struct et_softc *sc; 407 408 sc = device_get_softc(dev); 409 ET_LOCK(sc); 410 et_stop(sc); 411 ET_UNLOCK(sc); 412 return (0); 413 } 414 415 static int 416 et_miibus_readreg(device_t dev, int phy, int reg) 417 { 418 struct et_softc *sc; 419 uint32_t val; 420 int i, ret; 421 422 sc = device_get_softc(dev); 423 /* Stop any pending operations */ 424 CSR_WRITE_4(sc, ET_MII_CMD, 0); 425 426 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 427 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 428 CSR_WRITE_4(sc, ET_MII_ADDR, val); 429 430 /* Start reading */ 431 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 432 433 #define NRETRY 50 434 435 for (i = 0; i < NRETRY; ++i) { 436 val = CSR_READ_4(sc, ET_MII_IND); 437 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 438 break; 439 DELAY(50); 440 } 441 if (i == NRETRY) { 442 if_printf(sc->ifp, 443 "read phy %d, reg %d timed out\n", phy, reg); 444 ret = 0; 445 goto back; 446 } 447 448 #undef NRETRY 449 450 val = CSR_READ_4(sc, ET_MII_STAT); 451 ret = val & ET_MII_STAT_VALUE_MASK; 452 453 back: 454 /* Make sure that the current operation is stopped */ 455 CSR_WRITE_4(sc, ET_MII_CMD, 0); 456 return (ret); 457 } 458 459 static int 460 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 461 { 462 struct et_softc *sc; 463 uint32_t val; 464 int i; 465 466 sc = device_get_softc(dev); 467 /* Stop any pending operations */ 468 CSR_WRITE_4(sc, ET_MII_CMD, 0); 469 470 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 471 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 472 CSR_WRITE_4(sc, ET_MII_ADDR, val); 473 474 /* Start writing */ 475 CSR_WRITE_4(sc, ET_MII_CTRL, 476 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 477 478 #define NRETRY 100 479 480 for (i = 0; i < NRETRY; ++i) { 481 val = CSR_READ_4(sc, ET_MII_IND); 482 if ((val & ET_MII_IND_BUSY) == 0) 483 break; 484 DELAY(50); 485 } 486 if (i == NRETRY) { 487 if_printf(sc->ifp, 488 "write phy %d, reg %d timed out\n", phy, reg); 489 et_miibus_readreg(dev, phy, reg); 490 } 491 492 #undef NRETRY 493 494 /* Make sure that the current operation is stopped */ 495 CSR_WRITE_4(sc, ET_MII_CMD, 0); 496 return (0); 497 } 498 499 static void 500 et_miibus_statchg(device_t dev) 501 { 502 struct et_softc *sc; 503 struct mii_data *mii; 504 if_t ifp; 505 uint32_t cfg1, cfg2, ctrl; 506 int i; 507 508 sc = device_get_softc(dev); 509 510 mii = device_get_softc(sc->sc_miibus); 511 ifp = sc->ifp; 512 if (mii == NULL || ifp == NULL || 513 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 514 return; 515 516 sc->sc_flags &= ~ET_FLAG_LINK; 517 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 518 (IFM_ACTIVE | IFM_AVALID)) { 519 switch (IFM_SUBTYPE(mii->mii_media_active)) { 520 case IFM_10_T: 521 case IFM_100_TX: 522 sc->sc_flags |= ET_FLAG_LINK; 523 break; 524 case IFM_1000_T: 525 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 526 sc->sc_flags |= ET_FLAG_LINK; 527 break; 528 } 529 } 530 531 /* XXX Stop TX/RX MAC? */ 532 if ((sc->sc_flags & ET_FLAG_LINK) == 0) 533 return; 534 535 /* Program MACs with resolved speed/duplex/flow-control. */ 536 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 537 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 538 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 539 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 540 ET_MAC_CFG1_LOOPBACK); 541 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 542 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 543 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 544 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 545 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 546 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 547 548 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 549 cfg2 |= ET_MAC_CFG2_MODE_GMII; 550 else { 551 cfg2 |= ET_MAC_CFG2_MODE_MII; 552 ctrl |= ET_MAC_CTRL_MODE_MII; 553 } 554 555 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 556 cfg2 |= ET_MAC_CFG2_FDX; 557 /* 558 * Controller lacks automatic TX pause frame 559 * generation so it should be handled by driver. 560 * Even though driver can send pause frame with 561 * arbitrary pause time, controller does not 562 * provide a way that tells how many free RX 563 * buffers are available in controller. This 564 * limitation makes it hard to generate XON frame 565 * in time on driver side so don't enable TX flow 566 * control. 567 */ 568 #ifdef notyet 569 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 570 cfg1 |= ET_MAC_CFG1_TXFLOW; 571 #endif 572 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 573 cfg1 |= ET_MAC_CFG1_RXFLOW; 574 } else 575 ctrl |= ET_MAC_CTRL_GHDX; 576 577 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 578 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 579 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 580 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); 581 582 #define NRETRY 50 583 584 for (i = 0; i < NRETRY; ++i) { 585 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 586 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 587 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 588 break; 589 DELAY(100); 590 } 591 if (i == NRETRY) 592 if_printf(ifp, "can't enable RX/TX\n"); 593 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 594 595 #undef NRETRY 596 } 597 598 static int 599 et_ifmedia_upd_locked(if_t ifp) 600 { 601 struct et_softc *sc; 602 struct mii_data *mii; 603 struct mii_softc *miisc; 604 605 sc = if_getsoftc(ifp); 606 mii = device_get_softc(sc->sc_miibus); 607 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 608 PHY_RESET(miisc); 609 return (mii_mediachg(mii)); 610 } 611 612 static int 613 et_ifmedia_upd(if_t ifp) 614 { 615 struct et_softc *sc; 616 int res; 617 618 sc = if_getsoftc(ifp); 619 ET_LOCK(sc); 620 res = et_ifmedia_upd_locked(ifp); 621 ET_UNLOCK(sc); 622 623 return (res); 624 } 625 626 static void 627 et_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 628 { 629 struct et_softc *sc; 630 struct mii_data *mii; 631 632 sc = if_getsoftc(ifp); 633 ET_LOCK(sc); 634 if ((if_getflags(ifp) & IFF_UP) == 0) { 635 ET_UNLOCK(sc); 636 return; 637 } 638 639 mii = device_get_softc(sc->sc_miibus); 640 mii_pollstat(mii); 641 ifmr->ifm_active = mii->mii_media_active; 642 ifmr->ifm_status = mii->mii_media_status; 643 ET_UNLOCK(sc); 644 } 645 646 static void 647 et_stop(struct et_softc *sc) 648 { 649 if_t ifp; 650 651 ET_LOCK_ASSERT(sc); 652 653 ifp = sc->ifp; 654 callout_stop(&sc->sc_tick); 655 /* Disable interrupts. */ 656 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 657 658 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( 659 ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN)); 660 DELAY(100); 661 662 et_stop_rxdma(sc); 663 et_stop_txdma(sc); 664 et_stats_update(sc); 665 666 et_free_tx_ring(sc); 667 et_free_rx_ring(sc); 668 669 sc->sc_tx = 0; 670 sc->sc_tx_intr = 0; 671 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 672 673 sc->watchdog_timer = 0; 674 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 675 } 676 677 static int 678 et_bus_config(struct et_softc *sc) 679 { 680 uint32_t val, max_plsz; 681 uint16_t ack_latency, replay_timer; 682 683 /* 684 * Test whether EEPROM is valid 685 * NOTE: Read twice to get the correct value 686 */ 687 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 688 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 689 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 690 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 691 return (ENXIO); 692 } 693 694 /* TODO: LED */ 695 696 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 697 return (0); 698 699 /* 700 * Configure ACK latency and replay timer according to 701 * max playload size 702 */ 703 val = pci_read_config(sc->dev, 704 sc->sc_expcap + PCIER_DEVICE_CAP, 4); 705 max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; 706 707 switch (max_plsz) { 708 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 709 ack_latency = ET_PCIV_ACK_LATENCY_128; 710 replay_timer = ET_PCIV_REPLAY_TIMER_128; 711 break; 712 713 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 714 ack_latency = ET_PCIV_ACK_LATENCY_256; 715 replay_timer = ET_PCIV_REPLAY_TIMER_256; 716 break; 717 718 default: 719 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 720 replay_timer = pci_read_config(sc->dev, 721 ET_PCIR_REPLAY_TIMER, 2); 722 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 723 ack_latency, replay_timer); 724 break; 725 } 726 if (ack_latency != 0) { 727 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 728 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 729 2); 730 } 731 732 /* 733 * Set L0s and L1 latency timer to 2us 734 */ 735 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 736 val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); 737 /* L0s exit latency : 2us */ 738 val |= 0x00005000; 739 /* L1 exit latency : 2us */ 740 val |= 0x00028000; 741 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 742 743 /* 744 * Set max read request size to 2048 bytes 745 */ 746 pci_set_max_read_req(sc->dev, 2048); 747 748 return (0); 749 } 750 751 static void 752 et_get_eaddr(device_t dev, uint8_t eaddr[]) 753 { 754 uint32_t val; 755 int i; 756 757 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 758 for (i = 0; i < 4; ++i) 759 eaddr[i] = (val >> (8 * i)) & 0xff; 760 761 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 762 for (; i < ETHER_ADDR_LEN; ++i) 763 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 764 } 765 766 static void 767 et_reset(struct et_softc *sc) 768 { 769 770 CSR_WRITE_4(sc, ET_MAC_CFG1, 771 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 772 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 773 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 774 775 CSR_WRITE_4(sc, ET_SWRST, 776 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 777 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 778 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 779 780 CSR_WRITE_4(sc, ET_MAC_CFG1, 781 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 782 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 783 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 784 /* Disable interrupts. */ 785 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 786 } 787 788 struct et_dmamap_arg { 789 bus_addr_t et_busaddr; 790 }; 791 792 static void 793 et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 794 { 795 struct et_dmamap_arg *ctx; 796 797 if (error) 798 return; 799 800 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 801 802 ctx = arg; 803 ctx->et_busaddr = segs->ds_addr; 804 } 805 806 static int 807 et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 808 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 809 const char *msg) 810 { 811 struct et_dmamap_arg ctx; 812 int error; 813 814 error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 815 BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 816 tag); 817 if (error != 0) { 818 device_printf(sc->dev, "could not create %s dma tag\n", msg); 819 return (error); 820 } 821 /* Allocate DMA'able memory for ring. */ 822 error = bus_dmamem_alloc(*tag, (void **)ring, 823 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 824 if (error != 0) { 825 device_printf(sc->dev, 826 "could not allocate DMA'able memory for %s\n", msg); 827 return (error); 828 } 829 /* Load the address of the ring. */ 830 ctx.et_busaddr = 0; 831 error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 832 &ctx, BUS_DMA_NOWAIT); 833 if (error != 0) { 834 device_printf(sc->dev, 835 "could not load DMA'able memory for %s\n", msg); 836 return (error); 837 } 838 *paddr = ctx.et_busaddr; 839 return (0); 840 } 841 842 static void 843 et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 844 bus_dmamap_t map, bus_addr_t *paddr) 845 { 846 847 if (*paddr != 0) { 848 bus_dmamap_unload(*tag, map); 849 *paddr = 0; 850 } 851 if (*ring != NULL) { 852 bus_dmamem_free(*tag, *ring, map); 853 *ring = NULL; 854 } 855 if (*tag) { 856 bus_dma_tag_destroy(*tag); 857 *tag = NULL; 858 } 859 } 860 861 static int 862 et_dma_alloc(struct et_softc *sc) 863 { 864 struct et_txdesc_ring *tx_ring; 865 struct et_rxdesc_ring *rx_ring; 866 struct et_rxstat_ring *rxst_ring; 867 struct et_rxstatus_data *rxsd; 868 struct et_rxbuf_data *rbd; 869 struct et_txbuf_data *tbd; 870 struct et_txstatus_data *txsd; 871 int i, error; 872 873 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 874 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 875 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 876 &sc->sc_dtag); 877 if (error != 0) { 878 device_printf(sc->dev, "could not allocate parent dma tag\n"); 879 return (error); 880 } 881 882 /* TX ring. */ 883 tx_ring = &sc->sc_tx_ring; 884 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 885 &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 886 &tx_ring->tr_paddr, "TX ring"); 887 if (error) 888 return (error); 889 890 /* TX status block. */ 891 txsd = &sc->sc_tx_status; 892 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 893 &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 894 &txsd->txsd_paddr, "TX status block"); 895 if (error) 896 return (error); 897 898 /* RX ring 0, used as to recive small sized frames. */ 899 rx_ring = &sc->sc_rx_ring[0]; 900 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 901 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 902 &rx_ring->rr_paddr, "RX ring 0"); 903 rx_ring->rr_posreg = ET_RX_RING0_POS; 904 if (error) 905 return (error); 906 907 /* RX ring 1, used as to store normal sized frames. */ 908 rx_ring = &sc->sc_rx_ring[1]; 909 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 910 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 911 &rx_ring->rr_paddr, "RX ring 1"); 912 rx_ring->rr_posreg = ET_RX_RING1_POS; 913 if (error) 914 return (error); 915 916 /* RX stat ring. */ 917 rxst_ring = &sc->sc_rxstat_ring; 918 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 919 &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 920 &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 921 if (error) 922 return (error); 923 924 /* RX status block. */ 925 rxsd = &sc->sc_rx_status; 926 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 927 sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 928 (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 929 &rxsd->rxsd_paddr, "RX status block"); 930 if (error) 931 return (error); 932 933 /* Create parent DMA tag for mbufs. */ 934 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 935 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 936 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 937 &sc->sc_mbuf_dtag); 938 if (error != 0) { 939 device_printf(sc->dev, 940 "could not allocate parent dma tag for mbuf\n"); 941 return (error); 942 } 943 944 /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 945 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 946 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 947 MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 948 if (error) { 949 device_printf(sc->dev, "could not create mini RX dma tag\n"); 950 return (error); 951 } 952 953 /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 954 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 955 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 956 MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 957 if (error) { 958 device_printf(sc->dev, "could not create RX dma tag\n"); 959 return (error); 960 } 961 962 /* Create DMA tag for TX mbufs. */ 963 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 964 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 965 MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 966 &sc->sc_tx_tag); 967 if (error) { 968 device_printf(sc->dev, "could not create TX dma tag\n"); 969 return (error); 970 } 971 972 /* Initialize RX ring 0. */ 973 rbd = &sc->sc_rx_data[0]; 974 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 975 rbd->rbd_newbuf = et_newbuf_hdr; 976 rbd->rbd_discard = et_rxbuf_discard; 977 rbd->rbd_softc = sc; 978 rbd->rbd_ring = &sc->sc_rx_ring[0]; 979 /* Create DMA maps for mini RX buffers, ring 0. */ 980 for (i = 0; i < ET_RX_NDESC; i++) { 981 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 982 &rbd->rbd_buf[i].rb_dmap); 983 if (error) { 984 device_printf(sc->dev, 985 "could not create DMA map for mini RX mbufs\n"); 986 return (error); 987 } 988 } 989 990 /* Create a spare DMA map for mini RX buffers, ring 0. */ 991 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 992 &sc->sc_rx_mini_sparemap); 993 if (error) { 994 device_printf(sc->dev, 995 "could not create spare DMA map for mini RX mbuf\n"); 996 return (error); 997 } 998 999 /* Initialize RX ring 1. */ 1000 rbd = &sc->sc_rx_data[1]; 1001 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 1002 rbd->rbd_newbuf = et_newbuf_cluster; 1003 rbd->rbd_discard = et_rxbuf_discard; 1004 rbd->rbd_softc = sc; 1005 rbd->rbd_ring = &sc->sc_rx_ring[1]; 1006 /* Create DMA maps for standard RX buffers, ring 1. */ 1007 for (i = 0; i < ET_RX_NDESC; i++) { 1008 error = bus_dmamap_create(sc->sc_rx_tag, 0, 1009 &rbd->rbd_buf[i].rb_dmap); 1010 if (error) { 1011 device_printf(sc->dev, 1012 "could not create DMA map for mini RX mbufs\n"); 1013 return (error); 1014 } 1015 } 1016 1017 /* Create a spare DMA map for standard RX buffers, ring 1. */ 1018 error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 1019 if (error) { 1020 device_printf(sc->dev, 1021 "could not create spare DMA map for RX mbuf\n"); 1022 return (error); 1023 } 1024 1025 /* Create DMA maps for TX buffers. */ 1026 tbd = &sc->sc_tx_data; 1027 for (i = 0; i < ET_TX_NDESC; i++) { 1028 error = bus_dmamap_create(sc->sc_tx_tag, 0, 1029 &tbd->tbd_buf[i].tb_dmap); 1030 if (error) { 1031 device_printf(sc->dev, 1032 "could not create DMA map for TX mbufs\n"); 1033 return (error); 1034 } 1035 } 1036 1037 return (0); 1038 } 1039 1040 static void 1041 et_dma_free(struct et_softc *sc) 1042 { 1043 struct et_txdesc_ring *tx_ring; 1044 struct et_rxdesc_ring *rx_ring; 1045 struct et_txstatus_data *txsd; 1046 struct et_rxstat_ring *rxst_ring; 1047 struct et_rxbuf_data *rbd; 1048 struct et_txbuf_data *tbd; 1049 int i; 1050 1051 /* Destroy DMA maps for mini RX buffers, ring 0. */ 1052 rbd = &sc->sc_rx_data[0]; 1053 for (i = 0; i < ET_RX_NDESC; i++) { 1054 if (rbd->rbd_buf[i].rb_dmap) { 1055 bus_dmamap_destroy(sc->sc_rx_mini_tag, 1056 rbd->rbd_buf[i].rb_dmap); 1057 rbd->rbd_buf[i].rb_dmap = NULL; 1058 } 1059 } 1060 if (sc->sc_rx_mini_sparemap) { 1061 bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 1062 sc->sc_rx_mini_sparemap = NULL; 1063 } 1064 if (sc->sc_rx_mini_tag) { 1065 bus_dma_tag_destroy(sc->sc_rx_mini_tag); 1066 sc->sc_rx_mini_tag = NULL; 1067 } 1068 1069 /* Destroy DMA maps for standard RX buffers, ring 1. */ 1070 rbd = &sc->sc_rx_data[1]; 1071 for (i = 0; i < ET_RX_NDESC; i++) { 1072 if (rbd->rbd_buf[i].rb_dmap) { 1073 bus_dmamap_destroy(sc->sc_rx_tag, 1074 rbd->rbd_buf[i].rb_dmap); 1075 rbd->rbd_buf[i].rb_dmap = NULL; 1076 } 1077 } 1078 if (sc->sc_rx_sparemap) { 1079 bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 1080 sc->sc_rx_sparemap = NULL; 1081 } 1082 if (sc->sc_rx_tag) { 1083 bus_dma_tag_destroy(sc->sc_rx_tag); 1084 sc->sc_rx_tag = NULL; 1085 } 1086 1087 /* Destroy DMA maps for TX buffers. */ 1088 tbd = &sc->sc_tx_data; 1089 for (i = 0; i < ET_TX_NDESC; i++) { 1090 if (tbd->tbd_buf[i].tb_dmap) { 1091 bus_dmamap_destroy(sc->sc_tx_tag, 1092 tbd->tbd_buf[i].tb_dmap); 1093 tbd->tbd_buf[i].tb_dmap = NULL; 1094 } 1095 } 1096 if (sc->sc_tx_tag) { 1097 bus_dma_tag_destroy(sc->sc_tx_tag); 1098 sc->sc_tx_tag = NULL; 1099 } 1100 1101 /* Destroy mini RX ring, ring 0. */ 1102 rx_ring = &sc->sc_rx_ring[0]; 1103 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1104 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1105 /* Destroy standard RX ring, ring 1. */ 1106 rx_ring = &sc->sc_rx_ring[1]; 1107 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1108 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1109 /* Destroy RX stat ring. */ 1110 rxst_ring = &sc->sc_rxstat_ring; 1111 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1112 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1113 /* Destroy RX status block. */ 1114 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1115 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1116 /* Destroy TX ring. */ 1117 tx_ring = &sc->sc_tx_ring; 1118 et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1119 tx_ring->tr_dmap, &tx_ring->tr_paddr); 1120 /* Destroy TX status block. */ 1121 txsd = &sc->sc_tx_status; 1122 et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1123 txsd->txsd_dmap, &txsd->txsd_paddr); 1124 1125 /* Destroy the parent tag. */ 1126 if (sc->sc_dtag) { 1127 bus_dma_tag_destroy(sc->sc_dtag); 1128 sc->sc_dtag = NULL; 1129 } 1130 } 1131 1132 static void 1133 et_chip_attach(struct et_softc *sc) 1134 { 1135 uint32_t val; 1136 1137 /* 1138 * Perform minimal initialization 1139 */ 1140 1141 /* Disable loopback */ 1142 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1143 1144 /* Reset MAC */ 1145 CSR_WRITE_4(sc, ET_MAC_CFG1, 1146 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1147 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1148 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1149 1150 /* 1151 * Setup half duplex mode 1152 */ 1153 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1154 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1155 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1156 ET_MAC_HDX_EXC_DEFER; 1157 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1158 1159 /* Clear MAC control */ 1160 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1161 1162 /* Reset MII */ 1163 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1164 1165 /* Bring MAC out of reset state */ 1166 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1167 1168 /* Enable memory controllers */ 1169 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1170 } 1171 1172 static void 1173 et_intr(void *xsc) 1174 { 1175 struct et_softc *sc; 1176 if_t ifp; 1177 uint32_t status; 1178 1179 sc = xsc; 1180 ET_LOCK(sc); 1181 ifp = sc->ifp; 1182 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1183 goto done; 1184 1185 status = CSR_READ_4(sc, ET_INTR_STATUS); 1186 if ((status & ET_INTRS) == 0) 1187 goto done; 1188 1189 /* Disable further interrupts. */ 1190 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 1191 1192 if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) { 1193 device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n", 1194 status); 1195 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1196 et_init_locked(sc); 1197 ET_UNLOCK(sc); 1198 return; 1199 } 1200 if (status & ET_INTR_RXDMA) 1201 et_rxeof(sc); 1202 if (status & (ET_INTR_TXDMA | ET_INTR_TIMER)) 1203 et_txeof(sc); 1204 if (status & ET_INTR_TIMER) 1205 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1206 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1207 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1208 if (!if_sendq_empty(ifp)) 1209 et_start_locked(ifp); 1210 } 1211 done: 1212 ET_UNLOCK(sc); 1213 } 1214 1215 static void 1216 et_init_locked(struct et_softc *sc) 1217 { 1218 if_t ifp; 1219 int error; 1220 1221 ET_LOCK_ASSERT(sc); 1222 1223 ifp = sc->ifp; 1224 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1225 return; 1226 1227 et_stop(sc); 1228 et_reset(sc); 1229 1230 et_init_tx_ring(sc); 1231 error = et_init_rx_ring(sc); 1232 if (error) 1233 return; 1234 1235 error = et_chip_init(sc); 1236 if (error) 1237 goto fail; 1238 1239 /* 1240 * Start TX/RX DMA engine 1241 */ 1242 error = et_start_rxdma(sc); 1243 if (error) 1244 return; 1245 1246 error = et_start_txdma(sc); 1247 if (error) 1248 return; 1249 1250 /* Enable interrupts. */ 1251 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1252 1253 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1254 1255 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1256 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1257 1258 sc->sc_flags &= ~ET_FLAG_LINK; 1259 et_ifmedia_upd_locked(ifp); 1260 1261 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1262 1263 fail: 1264 if (error) 1265 et_stop(sc); 1266 } 1267 1268 static void 1269 et_init(void *xsc) 1270 { 1271 struct et_softc *sc = xsc; 1272 1273 ET_LOCK(sc); 1274 et_init_locked(sc); 1275 ET_UNLOCK(sc); 1276 } 1277 1278 static int 1279 et_ioctl(if_t ifp, u_long cmd, caddr_t data) 1280 { 1281 struct et_softc *sc; 1282 struct mii_data *mii; 1283 struct ifreq *ifr; 1284 int error, mask, max_framelen; 1285 1286 sc = if_getsoftc(ifp); 1287 ifr = (struct ifreq *)data; 1288 error = 0; 1289 1290 /* XXX LOCKSUSED */ 1291 switch (cmd) { 1292 case SIOCSIFFLAGS: 1293 ET_LOCK(sc); 1294 if (if_getflags(ifp) & IFF_UP) { 1295 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1296 if ((if_getflags(ifp) ^ sc->sc_if_flags) & 1297 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1298 et_setmulti(sc); 1299 } else { 1300 et_init_locked(sc); 1301 } 1302 } else { 1303 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1304 et_stop(sc); 1305 } 1306 sc->sc_if_flags = if_getflags(ifp); 1307 ET_UNLOCK(sc); 1308 break; 1309 1310 case SIOCSIFMEDIA: 1311 case SIOCGIFMEDIA: 1312 mii = device_get_softc(sc->sc_miibus); 1313 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1314 break; 1315 1316 case SIOCADDMULTI: 1317 case SIOCDELMULTI: 1318 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1319 ET_LOCK(sc); 1320 et_setmulti(sc); 1321 ET_UNLOCK(sc); 1322 } 1323 break; 1324 1325 case SIOCSIFMTU: 1326 ET_LOCK(sc); 1327 #if 0 1328 if (sc->sc_flags & ET_FLAG_JUMBO) 1329 max_framelen = ET_JUMBO_FRAMELEN; 1330 else 1331 #endif 1332 max_framelen = MCLBYTES - 1; 1333 1334 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1335 error = EOPNOTSUPP; 1336 ET_UNLOCK(sc); 1337 break; 1338 } 1339 1340 if (if_getmtu(ifp) != ifr->ifr_mtu) { 1341 if_setmtu(ifp, ifr->ifr_mtu); 1342 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1343 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1344 et_init_locked(sc); 1345 } 1346 } 1347 ET_UNLOCK(sc); 1348 break; 1349 1350 case SIOCSIFCAP: 1351 ET_LOCK(sc); 1352 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1353 if ((mask & IFCAP_TXCSUM) != 0 && 1354 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1355 if_togglecapenable(ifp, IFCAP_TXCSUM); 1356 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 1357 if_sethwassistbits(ifp, ET_CSUM_FEATURES, 0); 1358 else 1359 if_sethwassistbits(ifp, 0, ET_CSUM_FEATURES); 1360 } 1361 ET_UNLOCK(sc); 1362 break; 1363 1364 default: 1365 error = ether_ioctl(ifp, cmd, data); 1366 break; 1367 } 1368 return (error); 1369 } 1370 1371 static void 1372 et_start_locked(if_t ifp) 1373 { 1374 struct et_softc *sc; 1375 struct mbuf *m_head = NULL; 1376 struct et_txdesc_ring *tx_ring; 1377 struct et_txbuf_data *tbd; 1378 uint32_t tx_ready_pos; 1379 int enq; 1380 1381 sc = if_getsoftc(ifp); 1382 ET_LOCK_ASSERT(sc); 1383 1384 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1385 IFF_DRV_RUNNING || 1386 (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) != 1387 (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) 1388 return; 1389 1390 /* 1391 * Driver does not request TX completion interrupt for every 1392 * queued frames to prevent generating excessive interrupts. 1393 * This means driver may wait for TX completion interrupt even 1394 * though some frames were successfully transmitted. Reclaiming 1395 * transmitted frames will ensure driver see all available 1396 * descriptors. 1397 */ 1398 tbd = &sc->sc_tx_data; 1399 if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3) 1400 et_txeof(sc); 1401 1402 for (enq = 0; !if_sendq_empty(ifp); ) { 1403 if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 1404 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1405 break; 1406 } 1407 1408 m_head = if_dequeue(ifp); 1409 if (m_head == NULL) 1410 break; 1411 1412 if (et_encap(sc, &m_head)) { 1413 if (m_head == NULL) { 1414 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1415 break; 1416 } 1417 if_sendq_prepend(ifp, m_head); 1418 if (tbd->tbd_used > 0) 1419 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1420 break; 1421 } 1422 enq++; 1423 ETHER_BPF_MTAP(ifp, m_head); 1424 } 1425 1426 if (enq > 0) { 1427 tx_ring = &sc->sc_tx_ring; 1428 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1429 BUS_DMASYNC_PREWRITE); 1430 tx_ready_pos = tx_ring->tr_ready_index & 1431 ET_TX_READY_POS_INDEX_MASK; 1432 if (tx_ring->tr_ready_wrap) 1433 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1434 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1435 sc->watchdog_timer = 5; 1436 } 1437 } 1438 1439 static void 1440 et_start(if_t ifp) 1441 { 1442 struct et_softc *sc; 1443 1444 sc = if_getsoftc(ifp); 1445 ET_LOCK(sc); 1446 et_start_locked(ifp); 1447 ET_UNLOCK(sc); 1448 } 1449 1450 static int 1451 et_watchdog(struct et_softc *sc) 1452 { 1453 uint32_t status; 1454 1455 ET_LOCK_ASSERT(sc); 1456 1457 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1458 return (0); 1459 1460 bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1461 BUS_DMASYNC_POSTREAD); 1462 status = le32toh(*(sc->sc_tx_status.txsd_status)); 1463 if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1464 status); 1465 1466 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 1467 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING); 1468 et_init_locked(sc); 1469 return (EJUSTRETURN); 1470 } 1471 1472 static int 1473 et_stop_rxdma(struct et_softc *sc) 1474 { 1475 1476 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1477 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1478 1479 DELAY(5); 1480 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1481 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1482 return (ETIMEDOUT); 1483 } 1484 return (0); 1485 } 1486 1487 static int 1488 et_stop_txdma(struct et_softc *sc) 1489 { 1490 1491 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1492 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1493 return (0); 1494 } 1495 1496 static void 1497 et_free_tx_ring(struct et_softc *sc) 1498 { 1499 struct et_txbuf_data *tbd; 1500 struct et_txbuf *tb; 1501 int i; 1502 1503 tbd = &sc->sc_tx_data; 1504 for (i = 0; i < ET_TX_NDESC; ++i) { 1505 tb = &tbd->tbd_buf[i]; 1506 if (tb->tb_mbuf != NULL) { 1507 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1508 BUS_DMASYNC_POSTWRITE); 1509 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1510 m_freem(tb->tb_mbuf); 1511 tb->tb_mbuf = NULL; 1512 } 1513 } 1514 } 1515 1516 static void 1517 et_free_rx_ring(struct et_softc *sc) 1518 { 1519 struct et_rxbuf_data *rbd; 1520 struct et_rxdesc_ring *rx_ring; 1521 struct et_rxbuf *rb; 1522 int i; 1523 1524 /* Ring 0 */ 1525 rx_ring = &sc->sc_rx_ring[0]; 1526 rbd = &sc->sc_rx_data[0]; 1527 for (i = 0; i < ET_RX_NDESC; ++i) { 1528 rb = &rbd->rbd_buf[i]; 1529 if (rb->rb_mbuf != NULL) { 1530 bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1531 BUS_DMASYNC_POSTREAD); 1532 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 1533 m_freem(rb->rb_mbuf); 1534 rb->rb_mbuf = NULL; 1535 } 1536 } 1537 1538 /* Ring 1 */ 1539 rx_ring = &sc->sc_rx_ring[1]; 1540 rbd = &sc->sc_rx_data[1]; 1541 for (i = 0; i < ET_RX_NDESC; ++i) { 1542 rb = &rbd->rbd_buf[i]; 1543 if (rb->rb_mbuf != NULL) { 1544 bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1545 BUS_DMASYNC_POSTREAD); 1546 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1547 m_freem(rb->rb_mbuf); 1548 rb->rb_mbuf = NULL; 1549 } 1550 } 1551 } 1552 1553 static u_int 1554 et_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1555 { 1556 uint32_t h, *hp, *hash = arg; 1557 1558 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 1559 h = (h & 0x3f800000) >> 23; 1560 1561 hp = &hash[0]; 1562 if (h >= 32 && h < 64) { 1563 h -= 32; 1564 hp = &hash[1]; 1565 } else if (h >= 64 && h < 96) { 1566 h -= 64; 1567 hp = &hash[2]; 1568 } else if (h >= 96) { 1569 h -= 96; 1570 hp = &hash[3]; 1571 } 1572 *hp |= (1 << h); 1573 1574 return (1); 1575 } 1576 1577 static void 1578 et_setmulti(struct et_softc *sc) 1579 { 1580 if_t ifp; 1581 uint32_t hash[4] = { 0, 0, 0, 0 }; 1582 uint32_t rxmac_ctrl, pktfilt; 1583 int i, count; 1584 1585 ET_LOCK_ASSERT(sc); 1586 ifp = sc->ifp; 1587 1588 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1589 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1590 1591 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1592 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 1593 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1594 goto back; 1595 } 1596 1597 count = if_foreach_llmaddr(ifp, et_hash_maddr, &hash); 1598 1599 for (i = 0; i < 4; ++i) 1600 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1601 1602 if (count > 0) 1603 pktfilt |= ET_PKTFILT_MCAST; 1604 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1605 back: 1606 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1607 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1608 } 1609 1610 static int 1611 et_chip_init(struct et_softc *sc) 1612 { 1613 if_t ifp; 1614 uint32_t rxq_end; 1615 int error, frame_len, rxmem_size; 1616 1617 ifp = sc->ifp; 1618 /* 1619 * Split 16Kbytes internal memory between TX and RX 1620 * according to frame length. 1621 */ 1622 frame_len = ET_FRAMELEN(if_getmtu(ifp)); 1623 if (frame_len < 2048) { 1624 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1625 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1626 rxmem_size = ET_MEM_SIZE / 2; 1627 } else { 1628 rxmem_size = ET_MEM_SIZE - 1629 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1630 } 1631 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1632 1633 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1634 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1635 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1636 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1637 1638 /* No loopback */ 1639 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1640 1641 /* Clear MSI configure */ 1642 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1643 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1644 1645 /* Disable timer */ 1646 CSR_WRITE_4(sc, ET_TIMER, 0); 1647 1648 /* Initialize MAC */ 1649 et_init_mac(sc); 1650 1651 /* Enable memory controllers */ 1652 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1653 1654 /* Initialize RX MAC */ 1655 et_init_rxmac(sc); 1656 1657 /* Initialize TX MAC */ 1658 et_init_txmac(sc); 1659 1660 /* Initialize RX DMA engine */ 1661 error = et_init_rxdma(sc); 1662 if (error) 1663 return (error); 1664 1665 /* Initialize TX DMA engine */ 1666 error = et_init_txdma(sc); 1667 if (error) 1668 return (error); 1669 1670 return (0); 1671 } 1672 1673 static void 1674 et_init_tx_ring(struct et_softc *sc) 1675 { 1676 struct et_txdesc_ring *tx_ring; 1677 struct et_txbuf_data *tbd; 1678 struct et_txstatus_data *txsd; 1679 1680 tx_ring = &sc->sc_tx_ring; 1681 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1682 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1683 BUS_DMASYNC_PREWRITE); 1684 1685 tbd = &sc->sc_tx_data; 1686 tbd->tbd_start_index = 0; 1687 tbd->tbd_start_wrap = 0; 1688 tbd->tbd_used = 0; 1689 1690 txsd = &sc->sc_tx_status; 1691 bzero(txsd->txsd_status, sizeof(uint32_t)); 1692 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1693 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1694 } 1695 1696 static int 1697 et_init_rx_ring(struct et_softc *sc) 1698 { 1699 struct et_rxstatus_data *rxsd; 1700 struct et_rxstat_ring *rxst_ring; 1701 struct et_rxbuf_data *rbd; 1702 int i, error, n; 1703 1704 for (n = 0; n < ET_RX_NRING; ++n) { 1705 rbd = &sc->sc_rx_data[n]; 1706 for (i = 0; i < ET_RX_NDESC; ++i) { 1707 error = rbd->rbd_newbuf(rbd, i); 1708 if (error) { 1709 if_printf(sc->ifp, "%d ring %d buf, " 1710 "newbuf failed: %d\n", n, i, error); 1711 return (error); 1712 } 1713 } 1714 } 1715 1716 rxsd = &sc->sc_rx_status; 1717 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1718 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1719 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1720 1721 rxst_ring = &sc->sc_rxstat_ring; 1722 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1723 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1724 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1725 1726 return (0); 1727 } 1728 1729 static int 1730 et_init_rxdma(struct et_softc *sc) 1731 { 1732 struct et_rxstatus_data *rxsd; 1733 struct et_rxstat_ring *rxst_ring; 1734 struct et_rxdesc_ring *rx_ring; 1735 int error; 1736 1737 error = et_stop_rxdma(sc); 1738 if (error) { 1739 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1740 return (error); 1741 } 1742 1743 /* 1744 * Install RX status 1745 */ 1746 rxsd = &sc->sc_rx_status; 1747 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1748 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1749 1750 /* 1751 * Install RX stat ring 1752 */ 1753 rxst_ring = &sc->sc_rxstat_ring; 1754 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1755 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1756 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1757 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1758 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1759 1760 /* Match ET_RXSTAT_POS */ 1761 rxst_ring->rsr_index = 0; 1762 rxst_ring->rsr_wrap = 0; 1763 1764 /* 1765 * Install the 2nd RX descriptor ring 1766 */ 1767 rx_ring = &sc->sc_rx_ring[1]; 1768 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1769 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1770 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1771 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1772 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1773 1774 /* Match ET_RX_RING1_POS */ 1775 rx_ring->rr_index = 0; 1776 rx_ring->rr_wrap = 1; 1777 1778 /* 1779 * Install the 1st RX descriptor ring 1780 */ 1781 rx_ring = &sc->sc_rx_ring[0]; 1782 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1783 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1784 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1785 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1786 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1787 1788 /* Match ET_RX_RING0_POS */ 1789 rx_ring->rr_index = 0; 1790 rx_ring->rr_wrap = 1; 1791 1792 /* 1793 * RX intr moderation 1794 */ 1795 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1796 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1797 1798 return (0); 1799 } 1800 1801 static int 1802 et_init_txdma(struct et_softc *sc) 1803 { 1804 struct et_txdesc_ring *tx_ring; 1805 struct et_txstatus_data *txsd; 1806 int error; 1807 1808 error = et_stop_txdma(sc); 1809 if (error) { 1810 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1811 return (error); 1812 } 1813 1814 /* 1815 * Install TX descriptor ring 1816 */ 1817 tx_ring = &sc->sc_tx_ring; 1818 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1819 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1820 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1821 1822 /* 1823 * Install TX status 1824 */ 1825 txsd = &sc->sc_tx_status; 1826 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1827 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1828 1829 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1830 1831 /* Match ET_TX_READY_POS */ 1832 tx_ring->tr_ready_index = 0; 1833 tx_ring->tr_ready_wrap = 0; 1834 1835 return (0); 1836 } 1837 1838 static void 1839 et_init_mac(struct et_softc *sc) 1840 { 1841 if_t ifp; 1842 const uint8_t *eaddr; 1843 uint32_t val; 1844 1845 /* Reset MAC */ 1846 CSR_WRITE_4(sc, ET_MAC_CFG1, 1847 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1848 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1849 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1850 1851 /* 1852 * Setup inter packet gap 1853 */ 1854 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1855 (88 << ET_IPG_NONB2B_2_SHIFT) | 1856 (80 << ET_IPG_MINIFG_SHIFT) | 1857 (96 << ET_IPG_B2B_SHIFT); 1858 CSR_WRITE_4(sc, ET_IPG, val); 1859 1860 /* 1861 * Setup half duplex mode 1862 */ 1863 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1864 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1865 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1866 ET_MAC_HDX_EXC_DEFER; 1867 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1868 1869 /* Clear MAC control */ 1870 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1871 1872 /* Reset MII */ 1873 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1874 1875 /* 1876 * Set MAC address 1877 */ 1878 ifp = sc->ifp; 1879 eaddr = if_getlladdr(ifp); 1880 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1881 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1882 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1883 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1884 1885 /* Set max frame length */ 1886 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(if_getmtu(ifp))); 1887 1888 /* Bring MAC out of reset state */ 1889 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1890 } 1891 1892 static void 1893 et_init_rxmac(struct et_softc *sc) 1894 { 1895 if_t ifp; 1896 const uint8_t *eaddr; 1897 uint32_t val; 1898 int i; 1899 1900 /* Disable RX MAC and WOL */ 1901 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1902 1903 /* 1904 * Clear all WOL related registers 1905 */ 1906 for (i = 0; i < 3; ++i) 1907 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1908 for (i = 0; i < 20; ++i) 1909 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1910 1911 /* 1912 * Set WOL source address. XXX is this necessary? 1913 */ 1914 ifp = sc->ifp; 1915 eaddr = if_getlladdr(ifp); 1916 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1917 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1918 val = (eaddr[0] << 8) | eaddr[1]; 1919 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1920 1921 /* Clear packet filters */ 1922 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1923 1924 /* No ucast filtering */ 1925 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1926 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1927 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1928 1929 if (ET_FRAMELEN(if_getmtu(ifp)) > ET_RXMAC_CUT_THRU_FRMLEN) { 1930 /* 1931 * In order to transmit jumbo packets greater than 1932 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1933 * RX MAC and RX DMA needs to be reduced in size to 1934 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1935 * order to implement this, we must use "cut through" 1936 * mode in the RX MAC, which chops packets down into 1937 * segments. In this case we selected 256 bytes, 1938 * since this is the size of the PCI-Express TLP's 1939 * that the ET1310 uses. 1940 */ 1941 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1942 ET_RXMAC_MC_SEGSZ_ENABLE; 1943 } else { 1944 val = 0; 1945 } 1946 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1947 1948 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1949 1950 /* Initialize RX MAC management register */ 1951 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1952 1953 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1954 1955 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1956 ET_RXMAC_MGT_PASS_ECRC | 1957 ET_RXMAC_MGT_PASS_ELEN | 1958 ET_RXMAC_MGT_PASS_ETRUNC | 1959 ET_RXMAC_MGT_CHECK_PKT); 1960 1961 /* 1962 * Configure runt filtering (may not work on certain chip generation) 1963 */ 1964 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1965 ET_PKTFILT_MINLEN_MASK; 1966 val |= ET_PKTFILT_FRAG; 1967 CSR_WRITE_4(sc, ET_PKTFILT, val); 1968 1969 /* Enable RX MAC but leave WOL disabled */ 1970 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1971 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1972 1973 /* 1974 * Setup multicast hash and allmulti/promisc mode 1975 */ 1976 et_setmulti(sc); 1977 } 1978 1979 static void 1980 et_init_txmac(struct et_softc *sc) 1981 { 1982 1983 /* Disable TX MAC and FC(?) */ 1984 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1985 1986 /* 1987 * Initialize pause time. 1988 * This register should be set before XON/XOFF frame is 1989 * sent by driver. 1990 */ 1991 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT); 1992 1993 /* Enable TX MAC but leave FC(?) disabled */ 1994 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1995 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1996 } 1997 1998 static int 1999 et_start_rxdma(struct et_softc *sc) 2000 { 2001 uint32_t val; 2002 2003 val = (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 2004 ET_RXDMA_CTRL_RING0_ENABLE; 2005 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 2006 ET_RXDMA_CTRL_RING1_ENABLE; 2007 2008 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 2009 2010 DELAY(5); 2011 2012 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 2013 if_printf(sc->ifp, "can't start RX DMA engine\n"); 2014 return (ETIMEDOUT); 2015 } 2016 return (0); 2017 } 2018 2019 static int 2020 et_start_txdma(struct et_softc *sc) 2021 { 2022 2023 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 2024 return (0); 2025 } 2026 2027 static void 2028 et_rxeof(struct et_softc *sc) 2029 { 2030 struct et_rxstatus_data *rxsd; 2031 struct et_rxstat_ring *rxst_ring; 2032 struct et_rxbuf_data *rbd; 2033 struct et_rxdesc_ring *rx_ring; 2034 struct et_rxstat *st; 2035 if_t ifp; 2036 struct mbuf *m; 2037 uint32_t rxstat_pos, rxring_pos; 2038 uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 2039 int buflen, buf_idx, npost[2], ring_idx; 2040 int rxst_index, rxst_wrap; 2041 2042 ET_LOCK_ASSERT(sc); 2043 2044 ifp = sc->ifp; 2045 rxsd = &sc->sc_rx_status; 2046 rxst_ring = &sc->sc_rxstat_ring; 2047 2048 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2049 return; 2050 2051 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2052 BUS_DMASYNC_POSTREAD); 2053 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2054 BUS_DMASYNC_POSTREAD); 2055 2056 npost[0] = npost[1] = 0; 2057 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 2058 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 2059 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 2060 ET_RXS_STATRING_INDEX_SHIFT; 2061 2062 while (rxst_index != rxst_ring->rsr_index || 2063 rxst_wrap != rxst_ring->rsr_wrap) { 2064 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2065 break; 2066 2067 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 2068 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 2069 rxst_info1 = le32toh(st->rxst_info1); 2070 rxst_info2 = le32toh(st->rxst_info2); 2071 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 2072 ET_RXST_INFO2_LEN_SHIFT; 2073 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 2074 ET_RXST_INFO2_BUFIDX_SHIFT; 2075 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 2076 ET_RXST_INFO2_RINGIDX_SHIFT; 2077 2078 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 2079 rxst_ring->rsr_index = 0; 2080 rxst_ring->rsr_wrap ^= 1; 2081 } 2082 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 2083 if (rxst_ring->rsr_wrap) 2084 rxstat_pos |= ET_RXSTAT_POS_WRAP; 2085 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 2086 2087 if (ring_idx >= ET_RX_NRING) { 2088 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2089 if_printf(ifp, "invalid ring index %d\n", ring_idx); 2090 continue; 2091 } 2092 if (buf_idx >= ET_RX_NDESC) { 2093 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2094 if_printf(ifp, "invalid buf index %d\n", buf_idx); 2095 continue; 2096 } 2097 2098 rbd = &sc->sc_rx_data[ring_idx]; 2099 m = rbd->rbd_buf[buf_idx].rb_mbuf; 2100 if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 2101 /* Discard errored frame. */ 2102 rbd->rbd_discard(rbd, buf_idx); 2103 } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 2104 /* No available mbufs, discard it. */ 2105 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2106 rbd->rbd_discard(rbd, buf_idx); 2107 } else { 2108 buflen -= ETHER_CRC_LEN; 2109 if (buflen < ETHER_HDR_LEN) { 2110 m_freem(m); 2111 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2112 } else { 2113 m->m_pkthdr.len = m->m_len = buflen; 2114 m->m_pkthdr.rcvif = ifp; 2115 ET_UNLOCK(sc); 2116 if_input(ifp, m); 2117 ET_LOCK(sc); 2118 } 2119 } 2120 2121 rx_ring = &sc->sc_rx_ring[ring_idx]; 2122 if (buf_idx != rx_ring->rr_index) { 2123 if_printf(ifp, 2124 "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 2125 ring_idx, buf_idx, rx_ring->rr_index); 2126 } 2127 2128 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2129 if (++rx_ring->rr_index == ET_RX_NDESC) { 2130 rx_ring->rr_index = 0; 2131 rx_ring->rr_wrap ^= 1; 2132 } 2133 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2134 if (rx_ring->rr_wrap) 2135 rxring_pos |= ET_RX_RING_POS_WRAP; 2136 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2137 } 2138 2139 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2140 BUS_DMASYNC_PREREAD); 2141 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2142 BUS_DMASYNC_PREREAD); 2143 } 2144 2145 static int 2146 et_encap(struct et_softc *sc, struct mbuf **m0) 2147 { 2148 struct et_txdesc_ring *tx_ring; 2149 struct et_txbuf_data *tbd; 2150 struct et_txdesc *td; 2151 struct mbuf *m; 2152 bus_dma_segment_t segs[ET_NSEG_MAX]; 2153 bus_dmamap_t map; 2154 uint32_t csum_flags, last_td_ctrl2; 2155 int error, i, idx, first_idx, last_idx, nsegs; 2156 2157 tx_ring = &sc->sc_tx_ring; 2158 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2159 tbd = &sc->sc_tx_data; 2160 first_idx = tx_ring->tr_ready_index; 2161 map = tbd->tbd_buf[first_idx].tb_dmap; 2162 2163 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2164 0); 2165 if (error == EFBIG) { 2166 m = m_collapse(*m0, M_NOWAIT, ET_NSEG_MAX); 2167 if (m == NULL) { 2168 m_freem(*m0); 2169 *m0 = NULL; 2170 return (ENOMEM); 2171 } 2172 *m0 = m; 2173 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2174 &nsegs, 0); 2175 if (error != 0) { 2176 m_freem(*m0); 2177 *m0 = NULL; 2178 return (error); 2179 } 2180 } else if (error != 0) 2181 return (error); 2182 2183 /* Check for descriptor overruns. */ 2184 if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2185 bus_dmamap_unload(sc->sc_tx_tag, map); 2186 return (ENOBUFS); 2187 } 2188 bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2189 2190 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2191 sc->sc_tx += nsegs; 2192 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2193 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2194 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2195 } 2196 2197 m = *m0; 2198 csum_flags = 0; 2199 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2200 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2201 csum_flags |= ET_TDCTRL2_CSUM_IP; 2202 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2203 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2204 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2205 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2206 } 2207 last_idx = -1; 2208 for (i = 0; i < nsegs; ++i) { 2209 idx = (first_idx + i) % ET_TX_NDESC; 2210 td = &tx_ring->tr_desc[idx]; 2211 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2212 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2213 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2214 if (i == nsegs - 1) { 2215 /* Last frag */ 2216 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2217 last_idx = idx; 2218 } else 2219 td->td_ctrl2 = htole32(csum_flags); 2220 2221 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2222 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2223 tx_ring->tr_ready_index = 0; 2224 tx_ring->tr_ready_wrap ^= 1; 2225 } 2226 } 2227 td = &tx_ring->tr_desc[first_idx]; 2228 /* First frag */ 2229 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 2230 2231 MPASS(last_idx >= 0); 2232 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2233 tbd->tbd_buf[last_idx].tb_dmap = map; 2234 tbd->tbd_buf[last_idx].tb_mbuf = m; 2235 2236 tbd->tbd_used += nsegs; 2237 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2238 2239 return (0); 2240 } 2241 2242 static void 2243 et_txeof(struct et_softc *sc) 2244 { 2245 struct et_txdesc_ring *tx_ring; 2246 struct et_txbuf_data *tbd; 2247 struct et_txbuf *tb; 2248 if_t ifp; 2249 uint32_t tx_done; 2250 int end, wrap; 2251 2252 ET_LOCK_ASSERT(sc); 2253 2254 ifp = sc->ifp; 2255 tx_ring = &sc->sc_tx_ring; 2256 tbd = &sc->sc_tx_data; 2257 2258 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2259 return; 2260 2261 if (tbd->tbd_used == 0) 2262 return; 2263 2264 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2265 BUS_DMASYNC_POSTWRITE); 2266 2267 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2268 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2269 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2270 2271 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2272 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2273 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2274 if (tb->tb_mbuf != NULL) { 2275 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2276 BUS_DMASYNC_POSTWRITE); 2277 bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 2278 m_freem(tb->tb_mbuf); 2279 tb->tb_mbuf = NULL; 2280 } 2281 2282 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2283 tbd->tbd_start_index = 0; 2284 tbd->tbd_start_wrap ^= 1; 2285 } 2286 2287 MPASS(tbd->tbd_used > 0); 2288 tbd->tbd_used--; 2289 } 2290 2291 if (tbd->tbd_used == 0) 2292 sc->watchdog_timer = 0; 2293 if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 2294 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2295 } 2296 2297 static void 2298 et_tick(void *xsc) 2299 { 2300 struct et_softc *sc; 2301 struct mii_data *mii; 2302 2303 sc = xsc; 2304 ET_LOCK_ASSERT(sc); 2305 mii = device_get_softc(sc->sc_miibus); 2306 2307 mii_tick(mii); 2308 et_stats_update(sc); 2309 if (et_watchdog(sc) == EJUSTRETURN) 2310 return; 2311 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2312 } 2313 2314 static int 2315 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 2316 { 2317 struct et_softc *sc; 2318 struct et_rxdesc *desc; 2319 struct et_rxbuf *rb; 2320 struct mbuf *m; 2321 bus_dma_segment_t segs[1]; 2322 bus_dmamap_t dmap; 2323 int nsegs; 2324 2325 MPASS(buf_idx < ET_RX_NDESC); 2326 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2327 if (m == NULL) 2328 return (ENOBUFS); 2329 m->m_len = m->m_pkthdr.len = MCLBYTES; 2330 m_adj(m, ETHER_ALIGN); 2331 2332 sc = rbd->rbd_softc; 2333 rb = &rbd->rbd_buf[buf_idx]; 2334 2335 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2336 segs, &nsegs, 0) != 0) { 2337 m_freem(m); 2338 return (ENOBUFS); 2339 } 2340 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2341 2342 if (rb->rb_mbuf != NULL) { 2343 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 2344 BUS_DMASYNC_POSTREAD); 2345 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 2346 } 2347 dmap = rb->rb_dmap; 2348 rb->rb_dmap = sc->sc_rx_sparemap; 2349 sc->sc_rx_sparemap = dmap; 2350 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2351 2352 rb->rb_mbuf = m; 2353 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2354 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2355 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2356 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2357 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2358 BUS_DMASYNC_PREWRITE); 2359 return (0); 2360 } 2361 2362 static void 2363 et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2364 { 2365 struct et_rxdesc *desc; 2366 2367 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2368 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2369 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2370 BUS_DMASYNC_PREWRITE); 2371 } 2372 2373 static int 2374 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2375 { 2376 struct et_softc *sc; 2377 struct et_rxdesc *desc; 2378 struct et_rxbuf *rb; 2379 struct mbuf *m; 2380 bus_dma_segment_t segs[1]; 2381 bus_dmamap_t dmap; 2382 int nsegs; 2383 2384 MPASS(buf_idx < ET_RX_NDESC); 2385 MGETHDR(m, M_NOWAIT, MT_DATA); 2386 if (m == NULL) 2387 return (ENOBUFS); 2388 m->m_len = m->m_pkthdr.len = MHLEN; 2389 m_adj(m, ETHER_ALIGN); 2390 2391 sc = rbd->rbd_softc; 2392 rb = &rbd->rbd_buf[buf_idx]; 2393 2394 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2395 m, segs, &nsegs, 0) != 0) { 2396 m_freem(m); 2397 return (ENOBUFS); 2398 } 2399 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2400 2401 if (rb->rb_mbuf != NULL) { 2402 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2403 BUS_DMASYNC_POSTREAD); 2404 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2405 } 2406 dmap = rb->rb_dmap; 2407 rb->rb_dmap = sc->sc_rx_mini_sparemap; 2408 sc->sc_rx_mini_sparemap = dmap; 2409 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2410 2411 rb->rb_mbuf = m; 2412 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2413 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2414 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2415 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2416 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2417 BUS_DMASYNC_PREWRITE); 2418 return (0); 2419 } 2420 2421 #define ET_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2422 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2423 #define ET_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2424 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2425 2426 /* 2427 * Create sysctl tree 2428 */ 2429 static void 2430 et_add_sysctls(struct et_softc * sc) 2431 { 2432 struct sysctl_ctx_list *ctx; 2433 struct sysctl_oid_list *children, *parent; 2434 struct sysctl_oid *tree; 2435 struct et_hw_stats *stats; 2436 2437 ctx = device_get_sysctl_ctx(sc->dev); 2438 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2439 2440 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2441 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2442 et_sysctl_rx_intr_npkts, "I", "RX IM, # packets per RX interrupt"); 2443 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2444 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2445 et_sysctl_rx_intr_delay, "I", 2446 "RX IM, RX interrupt delay (x10 usec)"); 2447 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2448 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2449 "TX IM, # segments per TX interrupt"); 2450 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2451 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2452 2453 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 2454 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ET statistics"); 2455 parent = SYSCTL_CHILDREN(tree); 2456 2457 /* TX/RX statistics. */ 2458 stats = &sc->sc_stats; 2459 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64, 2460 "0 to 64 bytes frames"); 2461 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65, 2462 "65 to 127 bytes frames"); 2463 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128, 2464 "128 to 255 bytes frames"); 2465 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256, 2466 "256 to 511 bytes frames"); 2467 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512, 2468 "512 to 1023 bytes frames"); 2469 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024, 2470 "1024 to 1518 bytes frames"); 2471 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519, 2472 "1519 to 1522 bytes frames"); 2473 2474 /* RX statistics. */ 2475 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2476 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 2477 children = SYSCTL_CHILDREN(tree); 2478 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2479 &stats->rx_bytes, "Good bytes"); 2480 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2481 &stats->rx_frames, "Good frames"); 2482 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2483 &stats->rx_crcerrs, "CRC errors"); 2484 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2485 &stats->rx_mcast, "Multicast frames"); 2486 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2487 &stats->rx_bcast, "Broadcast frames"); 2488 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2489 &stats->rx_control, "Control frames"); 2490 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2491 &stats->rx_pause, "Pause frames"); 2492 ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control", 2493 &stats->rx_unknown_control, "Unknown control frames"); 2494 ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs", 2495 &stats->rx_alignerrs, "Alignment errors"); 2496 ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs", 2497 &stats->rx_lenerrs, "Frames with length mismatched"); 2498 ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs", 2499 &stats->rx_codeerrs, "Frames with code error"); 2500 ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs", 2501 &stats->rx_cserrs, "Frames with carrier sense error"); 2502 ET_SYSCTL_STAT_ADD32(ctx, children, "runts", 2503 &stats->rx_runts, "Too short frames"); 2504 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2505 &stats->rx_oversize, "Oversized frames"); 2506 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2507 &stats->rx_fragments, "Fragmented frames"); 2508 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2509 &stats->rx_jabbers, "Frames with jabber error"); 2510 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2511 &stats->rx_drop, "Dropped frames"); 2512 2513 /* TX statistics. */ 2514 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2515 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 2516 children = SYSCTL_CHILDREN(tree); 2517 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2518 &stats->tx_bytes, "Good bytes"); 2519 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2520 &stats->tx_frames, "Good frames"); 2521 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2522 &stats->tx_mcast, "Multicast frames"); 2523 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2524 &stats->tx_bcast, "Broadcast frames"); 2525 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2526 &stats->tx_pause, "Pause frames"); 2527 ET_SYSCTL_STAT_ADD32(ctx, children, "deferred", 2528 &stats->tx_deferred, "Deferred frames"); 2529 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred", 2530 &stats->tx_excess_deferred, "Excessively deferred frames"); 2531 ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls", 2532 &stats->tx_single_colls, "Single collisions"); 2533 ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls", 2534 &stats->tx_multi_colls, "Multiple collisions"); 2535 ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls", 2536 &stats->tx_late_colls, "Late collisions"); 2537 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls", 2538 &stats->tx_excess_colls, "Excess collisions"); 2539 ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls", 2540 &stats->tx_total_colls, "Total collisions"); 2541 ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored", 2542 &stats->tx_pause_honored, "Honored pause frames"); 2543 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2544 &stats->tx_drop, "Dropped frames"); 2545 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2546 &stats->tx_jabbers, "Frames with jabber errors"); 2547 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2548 &stats->tx_crcerrs, "Frames with CRC errors"); 2549 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2550 &stats->tx_control, "Control frames"); 2551 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2552 &stats->tx_oversize, "Oversized frames"); 2553 ET_SYSCTL_STAT_ADD32(ctx, children, "undersize", 2554 &stats->tx_undersize, "Undersized frames"); 2555 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2556 &stats->tx_fragments, "Fragmented frames"); 2557 } 2558 2559 #undef ET_SYSCTL_STAT_ADD32 2560 #undef ET_SYSCTL_STAT_ADD64 2561 2562 static int 2563 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2564 { 2565 struct et_softc *sc; 2566 if_t ifp; 2567 int error, v; 2568 2569 sc = arg1; 2570 ifp = sc->ifp; 2571 v = sc->sc_rx_intr_npkts; 2572 error = sysctl_handle_int(oidp, &v, 0, req); 2573 if (error || req->newptr == NULL) 2574 goto back; 2575 if (v <= 0) { 2576 error = EINVAL; 2577 goto back; 2578 } 2579 2580 if (sc->sc_rx_intr_npkts != v) { 2581 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2582 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2583 sc->sc_rx_intr_npkts = v; 2584 } 2585 back: 2586 return (error); 2587 } 2588 2589 static int 2590 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2591 { 2592 struct et_softc *sc; 2593 if_t ifp; 2594 int error, v; 2595 2596 sc = arg1; 2597 ifp = sc->ifp; 2598 v = sc->sc_rx_intr_delay; 2599 error = sysctl_handle_int(oidp, &v, 0, req); 2600 if (error || req->newptr == NULL) 2601 goto back; 2602 if (v <= 0) { 2603 error = EINVAL; 2604 goto back; 2605 } 2606 2607 if (sc->sc_rx_intr_delay != v) { 2608 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2609 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2610 sc->sc_rx_intr_delay = v; 2611 } 2612 back: 2613 return (error); 2614 } 2615 2616 static void 2617 et_stats_update(struct et_softc *sc) 2618 { 2619 struct et_hw_stats *stats; 2620 2621 stats = &sc->sc_stats; 2622 stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64); 2623 stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127); 2624 stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255); 2625 stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511); 2626 stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023); 2627 stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518); 2628 stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522); 2629 2630 stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES); 2631 stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES); 2632 stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR); 2633 stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST); 2634 stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST); 2635 stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL); 2636 stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE); 2637 stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL); 2638 stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR); 2639 stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR); 2640 stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR); 2641 stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR); 2642 stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT); 2643 stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE); 2644 stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG); 2645 stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER); 2646 stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP); 2647 2648 stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES); 2649 stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES); 2650 stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST); 2651 stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST); 2652 stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE); 2653 stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER); 2654 stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER); 2655 stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL); 2656 stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL); 2657 stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL); 2658 stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL); 2659 stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL); 2660 stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR); 2661 stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP); 2662 stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER); 2663 stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR); 2664 stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL); 2665 stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE); 2666 stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE); 2667 stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG); 2668 } 2669 2670 static uint64_t 2671 et_get_counter(if_t ifp, ift_counter cnt) 2672 { 2673 struct et_softc *sc; 2674 struct et_hw_stats *stats; 2675 2676 sc = if_getsoftc(ifp); 2677 stats = &sc->sc_stats; 2678 2679 switch (cnt) { 2680 case IFCOUNTER_OPACKETS: 2681 return (stats->tx_frames); 2682 case IFCOUNTER_COLLISIONS: 2683 return (stats->tx_total_colls); 2684 case IFCOUNTER_OERRORS: 2685 return (stats->tx_drop + stats->tx_jabbers + 2686 stats->tx_crcerrs + stats->tx_excess_deferred + 2687 stats->tx_late_colls); 2688 case IFCOUNTER_IPACKETS: 2689 return (stats->rx_frames); 2690 case IFCOUNTER_IERRORS: 2691 return (stats->rx_crcerrs + stats->rx_alignerrs + 2692 stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs + 2693 stats->rx_runts + stats->rx_jabbers + stats->rx_drop); 2694 default: 2695 return (if_get_counter_default(ifp, cnt)); 2696 } 2697 } 2698 2699 static int 2700 et_suspend(device_t dev) 2701 { 2702 struct et_softc *sc; 2703 uint32_t pmcfg; 2704 2705 sc = device_get_softc(dev); 2706 ET_LOCK(sc); 2707 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != 0) 2708 et_stop(sc); 2709 /* Diable all clocks and put PHY into COMA. */ 2710 pmcfg = CSR_READ_4(sc, ET_PM); 2711 pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | 2712 ET_PM_RXCLK_GATE); 2713 pmcfg |= ET_PM_PHY_SW_COMA; 2714 CSR_WRITE_4(sc, ET_PM, pmcfg); 2715 ET_UNLOCK(sc); 2716 return (0); 2717 } 2718 2719 static int 2720 et_resume(device_t dev) 2721 { 2722 struct et_softc *sc; 2723 uint32_t pmcfg; 2724 2725 sc = device_get_softc(dev); 2726 ET_LOCK(sc); 2727 /* Take PHY out of COMA and enable clocks. */ 2728 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 2729 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 2730 pmcfg |= EM_PM_GIGEPHY_ENB; 2731 CSR_WRITE_4(sc, ET_PM, pmcfg); 2732 if ((if_getflags(sc->ifp) & IFF_UP) != 0) 2733 et_init_locked(sc); 2734 ET_UNLOCK(sc); 2735 return (0); 2736 } 2737