1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/endian.h> 43 #include <sys/kernel.h> 44 #include <sys/bus.h> 45 #include <sys/malloc.h> 46 #include <sys/mbuf.h> 47 #include <sys/proc.h> 48 #include <sys/rman.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_dl.h> 58 #include <net/if_types.h> 59 #include <net/bpf.h> 60 #include <net/if_arp.h> 61 #include <net/if_media.h> 62 #include <net/if_vlan_var.h> 63 64 #include <machine/bus.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <dev/et/if_etreg.h> 73 #include <dev/et/if_etvar.h> 74 75 #include "miibus_if.h" 76 77 MODULE_DEPEND(et, pci, 1, 1, 1); 78 MODULE_DEPEND(et, ether, 1, 1, 1); 79 MODULE_DEPEND(et, miibus, 1, 1, 1); 80 81 /* Tunables. */ 82 static int msi_disable = 0; 83 TUNABLE_INT("hw.et.msi_disable", &msi_disable); 84 85 #define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 86 87 static int et_probe(device_t); 88 static int et_attach(device_t); 89 static int et_detach(device_t); 90 static int et_shutdown(device_t); 91 static int et_suspend(device_t); 92 static int et_resume(device_t); 93 94 static int et_miibus_readreg(device_t, int, int); 95 static int et_miibus_writereg(device_t, int, int, int); 96 static void et_miibus_statchg(device_t); 97 98 static void et_init_locked(struct et_softc *); 99 static void et_init(void *); 100 static int et_ioctl(if_t, u_long, caddr_t); 101 static void et_start_locked(if_t); 102 static void et_start(if_t); 103 static int et_watchdog(struct et_softc *); 104 static int et_ifmedia_upd_locked(if_t); 105 static int et_ifmedia_upd(if_t); 106 static void et_ifmedia_sts(if_t, struct ifmediareq *); 107 static uint64_t et_get_counter(if_t, ift_counter); 108 109 static void et_add_sysctls(struct et_softc *); 110 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 111 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 112 113 static void et_intr(void *); 114 static void et_rxeof(struct et_softc *); 115 static void et_txeof(struct et_softc *); 116 117 static int et_dma_alloc(struct et_softc *); 118 static void et_dma_free(struct et_softc *); 119 static void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 120 static int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 121 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 122 const char *); 123 static void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 124 bus_dmamap_t, bus_addr_t *); 125 static void et_init_tx_ring(struct et_softc *); 126 static int et_init_rx_ring(struct et_softc *); 127 static void et_free_tx_ring(struct et_softc *); 128 static void et_free_rx_ring(struct et_softc *); 129 static int et_encap(struct et_softc *, struct mbuf **); 130 static int et_newbuf_cluster(struct et_rxbuf_data *, int); 131 static int et_newbuf_hdr(struct et_rxbuf_data *, int); 132 static void et_rxbuf_discard(struct et_rxbuf_data *, int); 133 134 static void et_stop(struct et_softc *); 135 static int et_chip_init(struct et_softc *); 136 static void et_chip_attach(struct et_softc *); 137 static void et_init_mac(struct et_softc *); 138 static void et_init_rxmac(struct et_softc *); 139 static void et_init_txmac(struct et_softc *); 140 static int et_init_rxdma(struct et_softc *); 141 static int et_init_txdma(struct et_softc *); 142 static int et_start_rxdma(struct et_softc *); 143 static int et_start_txdma(struct et_softc *); 144 static int et_stop_rxdma(struct et_softc *); 145 static int et_stop_txdma(struct et_softc *); 146 static void et_reset(struct et_softc *); 147 static int et_bus_config(struct et_softc *); 148 static void et_get_eaddr(device_t, uint8_t[]); 149 static void et_setmulti(struct et_softc *); 150 static void et_tick(void *); 151 static void et_stats_update(struct et_softc *); 152 153 static const struct et_dev { 154 uint16_t vid; 155 uint16_t did; 156 const char *desc; 157 } et_devices[] = { 158 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 159 "Agere ET1310 Gigabit Ethernet" }, 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 161 "Agere ET1310 Fast Ethernet" }, 162 { 0, 0, NULL } 163 }; 164 165 static device_method_t et_methods[] = { 166 DEVMETHOD(device_probe, et_probe), 167 DEVMETHOD(device_attach, et_attach), 168 DEVMETHOD(device_detach, et_detach), 169 DEVMETHOD(device_shutdown, et_shutdown), 170 DEVMETHOD(device_suspend, et_suspend), 171 DEVMETHOD(device_resume, et_resume), 172 173 DEVMETHOD(miibus_readreg, et_miibus_readreg), 174 DEVMETHOD(miibus_writereg, et_miibus_writereg), 175 DEVMETHOD(miibus_statchg, et_miibus_statchg), 176 177 DEVMETHOD_END 178 }; 179 180 static driver_t et_driver = { 181 "et", 182 et_methods, 183 sizeof(struct et_softc) 184 }; 185 186 DRIVER_MODULE(et, pci, et_driver, 0, 0); 187 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, et, et_devices, 188 nitems(et_devices) - 1); 189 DRIVER_MODULE(miibus, et, miibus_driver, 0, 0); 190 191 static int et_rx_intr_npkts = 32; 192 static int et_rx_intr_delay = 20; /* x10 usec */ 193 static int et_tx_intr_nsegs = 126; 194 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 195 196 TUNABLE_INT("hw.et.timer", &et_timer); 197 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 198 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 199 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 200 201 static int 202 et_probe(device_t dev) 203 { 204 const struct et_dev *d; 205 uint16_t did, vid; 206 207 vid = pci_get_vendor(dev); 208 did = pci_get_device(dev); 209 210 for (d = et_devices; d->desc != NULL; ++d) { 211 if (vid == d->vid && did == d->did) { 212 device_set_desc(dev, d->desc); 213 return (BUS_PROBE_DEFAULT); 214 } 215 } 216 return (ENXIO); 217 } 218 219 static int 220 et_attach(device_t dev) 221 { 222 struct et_softc *sc; 223 if_t ifp; 224 uint8_t eaddr[ETHER_ADDR_LEN]; 225 uint32_t pmcfg; 226 int cap, error, msic; 227 228 sc = device_get_softc(dev); 229 sc->dev = dev; 230 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 231 MTX_DEF); 232 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 233 234 ifp = sc->ifp = if_alloc(IFT_ETHER); 235 if (ifp == NULL) { 236 device_printf(dev, "can not if_alloc()\n"); 237 error = ENOSPC; 238 goto fail; 239 } 240 241 /* 242 * Initialize tunables 243 */ 244 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 245 sc->sc_rx_intr_delay = et_rx_intr_delay; 246 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 247 sc->sc_timer = et_timer; 248 249 /* Enable bus mastering */ 250 pci_enable_busmaster(dev); 251 252 /* 253 * Allocate IO memory 254 */ 255 sc->sc_mem_rid = PCIR_BAR(0); 256 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 257 &sc->sc_mem_rid, RF_ACTIVE); 258 if (sc->sc_mem_res == NULL) { 259 device_printf(dev, "can't allocate IO memory\n"); 260 return (ENXIO); 261 } 262 263 msic = 0; 264 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 265 sc->sc_expcap = cap; 266 sc->sc_flags |= ET_FLAG_PCIE; 267 msic = pci_msi_count(dev); 268 if (bootverbose) 269 device_printf(dev, "MSI count: %d\n", msic); 270 } 271 if (msic > 0 && msi_disable == 0) { 272 msic = 1; 273 if (pci_alloc_msi(dev, &msic) == 0) { 274 if (msic == 1) { 275 device_printf(dev, "Using %d MSI message\n", 276 msic); 277 sc->sc_flags |= ET_FLAG_MSI; 278 } else 279 pci_release_msi(dev); 280 } 281 } 282 283 /* 284 * Allocate IRQ 285 */ 286 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 287 sc->sc_irq_rid = 0; 288 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 289 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 290 } else { 291 sc->sc_irq_rid = 1; 292 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 293 &sc->sc_irq_rid, RF_ACTIVE); 294 } 295 if (sc->sc_irq_res == NULL) { 296 device_printf(dev, "can't allocate irq\n"); 297 error = ENXIO; 298 goto fail; 299 } 300 301 if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST) 302 sc->sc_flags |= ET_FLAG_FASTETHER; 303 304 error = et_bus_config(sc); 305 if (error) 306 goto fail; 307 308 et_get_eaddr(dev, eaddr); 309 310 /* Take PHY out of COMA and enable clocks. */ 311 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 312 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 313 pmcfg |= EM_PM_GIGEPHY_ENB; 314 CSR_WRITE_4(sc, ET_PM, pmcfg); 315 316 et_reset(sc); 317 318 error = et_dma_alloc(sc); 319 if (error) 320 goto fail; 321 322 if_setsoftc(ifp, sc); 323 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 324 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 325 if_setinitfn(ifp, et_init); 326 if_setioctlfn(ifp, et_ioctl); 327 if_setstartfn(ifp, et_start); 328 if_setgetcounterfn(ifp, et_get_counter); 329 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_VLAN_MTU); 330 if_setcapenable(ifp, if_getcapabilities(ifp)); 331 if_setsendqlen(ifp, ET_TX_NDESC - 1); 332 if_setsendqready(ifp); 333 334 et_chip_attach(sc); 335 336 error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 337 et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 338 MIIF_DOPAUSE); 339 if (error) { 340 device_printf(dev, "attaching PHYs failed\n"); 341 goto fail; 342 } 343 344 ether_ifattach(ifp, eaddr); 345 346 /* Tell the upper layer(s) we support long frames. */ 347 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 348 349 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 350 NULL, et_intr, sc, &sc->sc_irq_handle); 351 if (error) { 352 ether_ifdetach(ifp); 353 device_printf(dev, "can't setup intr\n"); 354 goto fail; 355 } 356 357 et_add_sysctls(sc); 358 359 return (0); 360 fail: 361 et_detach(dev); 362 return (error); 363 } 364 365 static int 366 et_detach(device_t dev) 367 { 368 struct et_softc *sc; 369 370 sc = device_get_softc(dev); 371 if (device_is_attached(dev)) { 372 ether_ifdetach(sc->ifp); 373 ET_LOCK(sc); 374 et_stop(sc); 375 ET_UNLOCK(sc); 376 callout_drain(&sc->sc_tick); 377 } 378 379 if (sc->sc_miibus != NULL) 380 device_delete_child(dev, sc->sc_miibus); 381 bus_generic_detach(dev); 382 383 if (sc->sc_irq_handle != NULL) 384 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 385 if (sc->sc_irq_res != NULL) 386 bus_release_resource(dev, SYS_RES_IRQ, 387 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 388 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 389 pci_release_msi(dev); 390 if (sc->sc_mem_res != NULL) 391 bus_release_resource(dev, SYS_RES_MEMORY, 392 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 393 394 if (sc->ifp != NULL) 395 if_free(sc->ifp); 396 397 et_dma_free(sc); 398 399 mtx_destroy(&sc->sc_mtx); 400 401 return (0); 402 } 403 404 static int 405 et_shutdown(device_t dev) 406 { 407 struct et_softc *sc; 408 409 sc = device_get_softc(dev); 410 ET_LOCK(sc); 411 et_stop(sc); 412 ET_UNLOCK(sc); 413 return (0); 414 } 415 416 static int 417 et_miibus_readreg(device_t dev, int phy, int reg) 418 { 419 struct et_softc *sc; 420 uint32_t val; 421 int i, ret; 422 423 sc = device_get_softc(dev); 424 /* Stop any pending operations */ 425 CSR_WRITE_4(sc, ET_MII_CMD, 0); 426 427 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 428 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 429 CSR_WRITE_4(sc, ET_MII_ADDR, val); 430 431 /* Start reading */ 432 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 433 434 #define NRETRY 50 435 436 for (i = 0; i < NRETRY; ++i) { 437 val = CSR_READ_4(sc, ET_MII_IND); 438 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 439 break; 440 DELAY(50); 441 } 442 if (i == NRETRY) { 443 if_printf(sc->ifp, 444 "read phy %d, reg %d timed out\n", phy, reg); 445 ret = 0; 446 goto back; 447 } 448 449 #undef NRETRY 450 451 val = CSR_READ_4(sc, ET_MII_STAT); 452 ret = val & ET_MII_STAT_VALUE_MASK; 453 454 back: 455 /* Make sure that the current operation is stopped */ 456 CSR_WRITE_4(sc, ET_MII_CMD, 0); 457 return (ret); 458 } 459 460 static int 461 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 462 { 463 struct et_softc *sc; 464 uint32_t val; 465 int i; 466 467 sc = device_get_softc(dev); 468 /* Stop any pending operations */ 469 CSR_WRITE_4(sc, ET_MII_CMD, 0); 470 471 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 472 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 473 CSR_WRITE_4(sc, ET_MII_ADDR, val); 474 475 /* Start writing */ 476 CSR_WRITE_4(sc, ET_MII_CTRL, 477 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 478 479 #define NRETRY 100 480 481 for (i = 0; i < NRETRY; ++i) { 482 val = CSR_READ_4(sc, ET_MII_IND); 483 if ((val & ET_MII_IND_BUSY) == 0) 484 break; 485 DELAY(50); 486 } 487 if (i == NRETRY) { 488 if_printf(sc->ifp, 489 "write phy %d, reg %d timed out\n", phy, reg); 490 et_miibus_readreg(dev, phy, reg); 491 } 492 493 #undef NRETRY 494 495 /* Make sure that the current operation is stopped */ 496 CSR_WRITE_4(sc, ET_MII_CMD, 0); 497 return (0); 498 } 499 500 static void 501 et_miibus_statchg(device_t dev) 502 { 503 struct et_softc *sc; 504 struct mii_data *mii; 505 if_t ifp; 506 uint32_t cfg1, cfg2, ctrl; 507 int i; 508 509 sc = device_get_softc(dev); 510 511 mii = device_get_softc(sc->sc_miibus); 512 ifp = sc->ifp; 513 if (mii == NULL || ifp == NULL || 514 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 515 return; 516 517 sc->sc_flags &= ~ET_FLAG_LINK; 518 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 519 (IFM_ACTIVE | IFM_AVALID)) { 520 switch (IFM_SUBTYPE(mii->mii_media_active)) { 521 case IFM_10_T: 522 case IFM_100_TX: 523 sc->sc_flags |= ET_FLAG_LINK; 524 break; 525 case IFM_1000_T: 526 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 527 sc->sc_flags |= ET_FLAG_LINK; 528 break; 529 } 530 } 531 532 /* XXX Stop TX/RX MAC? */ 533 if ((sc->sc_flags & ET_FLAG_LINK) == 0) 534 return; 535 536 /* Program MACs with resolved speed/duplex/flow-control. */ 537 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 538 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 539 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 540 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 541 ET_MAC_CFG1_LOOPBACK); 542 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 543 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 544 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 545 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 546 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 547 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 548 549 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 550 cfg2 |= ET_MAC_CFG2_MODE_GMII; 551 else { 552 cfg2 |= ET_MAC_CFG2_MODE_MII; 553 ctrl |= ET_MAC_CTRL_MODE_MII; 554 } 555 556 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 557 cfg2 |= ET_MAC_CFG2_FDX; 558 /* 559 * Controller lacks automatic TX pause frame 560 * generation so it should be handled by driver. 561 * Even though driver can send pause frame with 562 * arbitrary pause time, controller does not 563 * provide a way that tells how many free RX 564 * buffers are available in controller. This 565 * limitation makes it hard to generate XON frame 566 * in time on driver side so don't enable TX flow 567 * control. 568 */ 569 #ifdef notyet 570 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 571 cfg1 |= ET_MAC_CFG1_TXFLOW; 572 #endif 573 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 574 cfg1 |= ET_MAC_CFG1_RXFLOW; 575 } else 576 ctrl |= ET_MAC_CTRL_GHDX; 577 578 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 579 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 580 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 581 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); 582 583 #define NRETRY 50 584 585 for (i = 0; i < NRETRY; ++i) { 586 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 587 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 588 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 589 break; 590 DELAY(100); 591 } 592 if (i == NRETRY) 593 if_printf(ifp, "can't enable RX/TX\n"); 594 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 595 596 #undef NRETRY 597 } 598 599 static int 600 et_ifmedia_upd_locked(if_t ifp) 601 { 602 struct et_softc *sc; 603 struct mii_data *mii; 604 struct mii_softc *miisc; 605 606 sc = if_getsoftc(ifp); 607 mii = device_get_softc(sc->sc_miibus); 608 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 609 PHY_RESET(miisc); 610 return (mii_mediachg(mii)); 611 } 612 613 static int 614 et_ifmedia_upd(if_t ifp) 615 { 616 struct et_softc *sc; 617 int res; 618 619 sc = if_getsoftc(ifp); 620 ET_LOCK(sc); 621 res = et_ifmedia_upd_locked(ifp); 622 ET_UNLOCK(sc); 623 624 return (res); 625 } 626 627 static void 628 et_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 629 { 630 struct et_softc *sc; 631 struct mii_data *mii; 632 633 sc = if_getsoftc(ifp); 634 ET_LOCK(sc); 635 if ((if_getflags(ifp) & IFF_UP) == 0) { 636 ET_UNLOCK(sc); 637 return; 638 } 639 640 mii = device_get_softc(sc->sc_miibus); 641 mii_pollstat(mii); 642 ifmr->ifm_active = mii->mii_media_active; 643 ifmr->ifm_status = mii->mii_media_status; 644 ET_UNLOCK(sc); 645 } 646 647 static void 648 et_stop(struct et_softc *sc) 649 { 650 if_t ifp; 651 652 ET_LOCK_ASSERT(sc); 653 654 ifp = sc->ifp; 655 callout_stop(&sc->sc_tick); 656 /* Disable interrupts. */ 657 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 658 659 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( 660 ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN)); 661 DELAY(100); 662 663 et_stop_rxdma(sc); 664 et_stop_txdma(sc); 665 et_stats_update(sc); 666 667 et_free_tx_ring(sc); 668 et_free_rx_ring(sc); 669 670 sc->sc_tx = 0; 671 sc->sc_tx_intr = 0; 672 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 673 674 sc->watchdog_timer = 0; 675 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 676 } 677 678 static int 679 et_bus_config(struct et_softc *sc) 680 { 681 uint32_t val, max_plsz; 682 uint16_t ack_latency, replay_timer; 683 684 /* 685 * Test whether EEPROM is valid 686 * NOTE: Read twice to get the correct value 687 */ 688 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 689 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 690 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 691 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 692 return (ENXIO); 693 } 694 695 /* TODO: LED */ 696 697 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 698 return (0); 699 700 /* 701 * Configure ACK latency and replay timer according to 702 * max playload size 703 */ 704 val = pci_read_config(sc->dev, 705 sc->sc_expcap + PCIER_DEVICE_CAP, 4); 706 max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; 707 708 switch (max_plsz) { 709 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 710 ack_latency = ET_PCIV_ACK_LATENCY_128; 711 replay_timer = ET_PCIV_REPLAY_TIMER_128; 712 break; 713 714 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 715 ack_latency = ET_PCIV_ACK_LATENCY_256; 716 replay_timer = ET_PCIV_REPLAY_TIMER_256; 717 break; 718 719 default: 720 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 721 replay_timer = pci_read_config(sc->dev, 722 ET_PCIR_REPLAY_TIMER, 2); 723 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 724 ack_latency, replay_timer); 725 break; 726 } 727 if (ack_latency != 0) { 728 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 729 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 730 2); 731 } 732 733 /* 734 * Set L0s and L1 latency timer to 2us 735 */ 736 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 737 val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); 738 /* L0s exit latency : 2us */ 739 val |= 0x00005000; 740 /* L1 exit latency : 2us */ 741 val |= 0x00028000; 742 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 743 744 /* 745 * Set max read request size to 2048 bytes 746 */ 747 pci_set_max_read_req(sc->dev, 2048); 748 749 return (0); 750 } 751 752 static void 753 et_get_eaddr(device_t dev, uint8_t eaddr[]) 754 { 755 uint32_t val; 756 int i; 757 758 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 759 for (i = 0; i < 4; ++i) 760 eaddr[i] = (val >> (8 * i)) & 0xff; 761 762 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 763 for (; i < ETHER_ADDR_LEN; ++i) 764 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 765 } 766 767 static void 768 et_reset(struct et_softc *sc) 769 { 770 771 CSR_WRITE_4(sc, ET_MAC_CFG1, 772 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 773 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 774 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 775 776 CSR_WRITE_4(sc, ET_SWRST, 777 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 778 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 779 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 780 781 CSR_WRITE_4(sc, ET_MAC_CFG1, 782 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 783 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 784 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 785 /* Disable interrupts. */ 786 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 787 } 788 789 struct et_dmamap_arg { 790 bus_addr_t et_busaddr; 791 }; 792 793 static void 794 et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 795 { 796 struct et_dmamap_arg *ctx; 797 798 if (error) 799 return; 800 801 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 802 803 ctx = arg; 804 ctx->et_busaddr = segs->ds_addr; 805 } 806 807 static int 808 et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 809 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 810 const char *msg) 811 { 812 struct et_dmamap_arg ctx; 813 int error; 814 815 error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 816 BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 817 tag); 818 if (error != 0) { 819 device_printf(sc->dev, "could not create %s dma tag\n", msg); 820 return (error); 821 } 822 /* Allocate DMA'able memory for ring. */ 823 error = bus_dmamem_alloc(*tag, (void **)ring, 824 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 825 if (error != 0) { 826 device_printf(sc->dev, 827 "could not allocate DMA'able memory for %s\n", msg); 828 return (error); 829 } 830 /* Load the address of the ring. */ 831 ctx.et_busaddr = 0; 832 error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 833 &ctx, BUS_DMA_NOWAIT); 834 if (error != 0) { 835 device_printf(sc->dev, 836 "could not load DMA'able memory for %s\n", msg); 837 return (error); 838 } 839 *paddr = ctx.et_busaddr; 840 return (0); 841 } 842 843 static void 844 et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 845 bus_dmamap_t map, bus_addr_t *paddr) 846 { 847 848 if (*paddr != 0) { 849 bus_dmamap_unload(*tag, map); 850 *paddr = 0; 851 } 852 if (*ring != NULL) { 853 bus_dmamem_free(*tag, *ring, map); 854 *ring = NULL; 855 } 856 if (*tag) { 857 bus_dma_tag_destroy(*tag); 858 *tag = NULL; 859 } 860 } 861 862 static int 863 et_dma_alloc(struct et_softc *sc) 864 { 865 struct et_txdesc_ring *tx_ring; 866 struct et_rxdesc_ring *rx_ring; 867 struct et_rxstat_ring *rxst_ring; 868 struct et_rxstatus_data *rxsd; 869 struct et_rxbuf_data *rbd; 870 struct et_txbuf_data *tbd; 871 struct et_txstatus_data *txsd; 872 int i, error; 873 874 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 875 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 876 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 877 &sc->sc_dtag); 878 if (error != 0) { 879 device_printf(sc->dev, "could not allocate parent dma tag\n"); 880 return (error); 881 } 882 883 /* TX ring. */ 884 tx_ring = &sc->sc_tx_ring; 885 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 886 &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 887 &tx_ring->tr_paddr, "TX ring"); 888 if (error) 889 return (error); 890 891 /* TX status block. */ 892 txsd = &sc->sc_tx_status; 893 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 894 &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 895 &txsd->txsd_paddr, "TX status block"); 896 if (error) 897 return (error); 898 899 /* RX ring 0, used as to recive small sized frames. */ 900 rx_ring = &sc->sc_rx_ring[0]; 901 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 902 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 903 &rx_ring->rr_paddr, "RX ring 0"); 904 rx_ring->rr_posreg = ET_RX_RING0_POS; 905 if (error) 906 return (error); 907 908 /* RX ring 1, used as to store normal sized frames. */ 909 rx_ring = &sc->sc_rx_ring[1]; 910 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 911 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 912 &rx_ring->rr_paddr, "RX ring 1"); 913 rx_ring->rr_posreg = ET_RX_RING1_POS; 914 if (error) 915 return (error); 916 917 /* RX stat ring. */ 918 rxst_ring = &sc->sc_rxstat_ring; 919 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 920 &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 921 &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 922 if (error) 923 return (error); 924 925 /* RX status block. */ 926 rxsd = &sc->sc_rx_status; 927 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 928 sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 929 (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 930 &rxsd->rxsd_paddr, "RX status block"); 931 if (error) 932 return (error); 933 934 /* Create parent DMA tag for mbufs. */ 935 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 936 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 937 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 938 &sc->sc_mbuf_dtag); 939 if (error != 0) { 940 device_printf(sc->dev, 941 "could not allocate parent dma tag for mbuf\n"); 942 return (error); 943 } 944 945 /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 946 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 947 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 948 MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 949 if (error) { 950 device_printf(sc->dev, "could not create mini RX dma tag\n"); 951 return (error); 952 } 953 954 /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 955 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 956 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 957 MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 958 if (error) { 959 device_printf(sc->dev, "could not create RX dma tag\n"); 960 return (error); 961 } 962 963 /* Create DMA tag for TX mbufs. */ 964 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 965 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 966 MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 967 &sc->sc_tx_tag); 968 if (error) { 969 device_printf(sc->dev, "could not create TX dma tag\n"); 970 return (error); 971 } 972 973 /* Initialize RX ring 0. */ 974 rbd = &sc->sc_rx_data[0]; 975 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 976 rbd->rbd_newbuf = et_newbuf_hdr; 977 rbd->rbd_discard = et_rxbuf_discard; 978 rbd->rbd_softc = sc; 979 rbd->rbd_ring = &sc->sc_rx_ring[0]; 980 /* Create DMA maps for mini RX buffers, ring 0. */ 981 for (i = 0; i < ET_RX_NDESC; i++) { 982 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 983 &rbd->rbd_buf[i].rb_dmap); 984 if (error) { 985 device_printf(sc->dev, 986 "could not create DMA map for mini RX mbufs\n"); 987 return (error); 988 } 989 } 990 991 /* Create a spare DMA map for mini RX buffers, ring 0. */ 992 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 993 &sc->sc_rx_mini_sparemap); 994 if (error) { 995 device_printf(sc->dev, 996 "could not create spare DMA map for mini RX mbuf\n"); 997 return (error); 998 } 999 1000 /* Initialize RX ring 1. */ 1001 rbd = &sc->sc_rx_data[1]; 1002 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 1003 rbd->rbd_newbuf = et_newbuf_cluster; 1004 rbd->rbd_discard = et_rxbuf_discard; 1005 rbd->rbd_softc = sc; 1006 rbd->rbd_ring = &sc->sc_rx_ring[1]; 1007 /* Create DMA maps for standard RX buffers, ring 1. */ 1008 for (i = 0; i < ET_RX_NDESC; i++) { 1009 error = bus_dmamap_create(sc->sc_rx_tag, 0, 1010 &rbd->rbd_buf[i].rb_dmap); 1011 if (error) { 1012 device_printf(sc->dev, 1013 "could not create DMA map for mini RX mbufs\n"); 1014 return (error); 1015 } 1016 } 1017 1018 /* Create a spare DMA map for standard RX buffers, ring 1. */ 1019 error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 1020 if (error) { 1021 device_printf(sc->dev, 1022 "could not create spare DMA map for RX mbuf\n"); 1023 return (error); 1024 } 1025 1026 /* Create DMA maps for TX buffers. */ 1027 tbd = &sc->sc_tx_data; 1028 for (i = 0; i < ET_TX_NDESC; i++) { 1029 error = bus_dmamap_create(sc->sc_tx_tag, 0, 1030 &tbd->tbd_buf[i].tb_dmap); 1031 if (error) { 1032 device_printf(sc->dev, 1033 "could not create DMA map for TX mbufs\n"); 1034 return (error); 1035 } 1036 } 1037 1038 return (0); 1039 } 1040 1041 static void 1042 et_dma_free(struct et_softc *sc) 1043 { 1044 struct et_txdesc_ring *tx_ring; 1045 struct et_rxdesc_ring *rx_ring; 1046 struct et_txstatus_data *txsd; 1047 struct et_rxstat_ring *rxst_ring; 1048 struct et_rxbuf_data *rbd; 1049 struct et_txbuf_data *tbd; 1050 int i; 1051 1052 /* Destroy DMA maps for mini RX buffers, ring 0. */ 1053 rbd = &sc->sc_rx_data[0]; 1054 for (i = 0; i < ET_RX_NDESC; i++) { 1055 if (rbd->rbd_buf[i].rb_dmap) { 1056 bus_dmamap_destroy(sc->sc_rx_mini_tag, 1057 rbd->rbd_buf[i].rb_dmap); 1058 rbd->rbd_buf[i].rb_dmap = NULL; 1059 } 1060 } 1061 if (sc->sc_rx_mini_sparemap) { 1062 bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 1063 sc->sc_rx_mini_sparemap = NULL; 1064 } 1065 if (sc->sc_rx_mini_tag) { 1066 bus_dma_tag_destroy(sc->sc_rx_mini_tag); 1067 sc->sc_rx_mini_tag = NULL; 1068 } 1069 1070 /* Destroy DMA maps for standard RX buffers, ring 1. */ 1071 rbd = &sc->sc_rx_data[1]; 1072 for (i = 0; i < ET_RX_NDESC; i++) { 1073 if (rbd->rbd_buf[i].rb_dmap) { 1074 bus_dmamap_destroy(sc->sc_rx_tag, 1075 rbd->rbd_buf[i].rb_dmap); 1076 rbd->rbd_buf[i].rb_dmap = NULL; 1077 } 1078 } 1079 if (sc->sc_rx_sparemap) { 1080 bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 1081 sc->sc_rx_sparemap = NULL; 1082 } 1083 if (sc->sc_rx_tag) { 1084 bus_dma_tag_destroy(sc->sc_rx_tag); 1085 sc->sc_rx_tag = NULL; 1086 } 1087 1088 /* Destroy DMA maps for TX buffers. */ 1089 tbd = &sc->sc_tx_data; 1090 for (i = 0; i < ET_TX_NDESC; i++) { 1091 if (tbd->tbd_buf[i].tb_dmap) { 1092 bus_dmamap_destroy(sc->sc_tx_tag, 1093 tbd->tbd_buf[i].tb_dmap); 1094 tbd->tbd_buf[i].tb_dmap = NULL; 1095 } 1096 } 1097 if (sc->sc_tx_tag) { 1098 bus_dma_tag_destroy(sc->sc_tx_tag); 1099 sc->sc_tx_tag = NULL; 1100 } 1101 1102 /* Destroy mini RX ring, ring 0. */ 1103 rx_ring = &sc->sc_rx_ring[0]; 1104 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1105 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1106 /* Destroy standard RX ring, ring 1. */ 1107 rx_ring = &sc->sc_rx_ring[1]; 1108 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1109 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1110 /* Destroy RX stat ring. */ 1111 rxst_ring = &sc->sc_rxstat_ring; 1112 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1113 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1114 /* Destroy RX status block. */ 1115 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1116 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1117 /* Destroy TX ring. */ 1118 tx_ring = &sc->sc_tx_ring; 1119 et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1120 tx_ring->tr_dmap, &tx_ring->tr_paddr); 1121 /* Destroy TX status block. */ 1122 txsd = &sc->sc_tx_status; 1123 et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1124 txsd->txsd_dmap, &txsd->txsd_paddr); 1125 1126 /* Destroy the parent tag. */ 1127 if (sc->sc_dtag) { 1128 bus_dma_tag_destroy(sc->sc_dtag); 1129 sc->sc_dtag = NULL; 1130 } 1131 } 1132 1133 static void 1134 et_chip_attach(struct et_softc *sc) 1135 { 1136 uint32_t val; 1137 1138 /* 1139 * Perform minimal initialization 1140 */ 1141 1142 /* Disable loopback */ 1143 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1144 1145 /* Reset MAC */ 1146 CSR_WRITE_4(sc, ET_MAC_CFG1, 1147 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1148 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1149 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1150 1151 /* 1152 * Setup half duplex mode 1153 */ 1154 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1155 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1156 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1157 ET_MAC_HDX_EXC_DEFER; 1158 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1159 1160 /* Clear MAC control */ 1161 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1162 1163 /* Reset MII */ 1164 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1165 1166 /* Bring MAC out of reset state */ 1167 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1168 1169 /* Enable memory controllers */ 1170 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1171 } 1172 1173 static void 1174 et_intr(void *xsc) 1175 { 1176 struct et_softc *sc; 1177 if_t ifp; 1178 uint32_t status; 1179 1180 sc = xsc; 1181 ET_LOCK(sc); 1182 ifp = sc->ifp; 1183 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1184 goto done; 1185 1186 status = CSR_READ_4(sc, ET_INTR_STATUS); 1187 if ((status & ET_INTRS) == 0) 1188 goto done; 1189 1190 /* Disable further interrupts. */ 1191 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 1192 1193 if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) { 1194 device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n", 1195 status); 1196 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1197 et_init_locked(sc); 1198 ET_UNLOCK(sc); 1199 return; 1200 } 1201 if (status & ET_INTR_RXDMA) 1202 et_rxeof(sc); 1203 if (status & (ET_INTR_TXDMA | ET_INTR_TIMER)) 1204 et_txeof(sc); 1205 if (status & ET_INTR_TIMER) 1206 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1207 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1208 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1209 if (!if_sendq_empty(ifp)) 1210 et_start_locked(ifp); 1211 } 1212 done: 1213 ET_UNLOCK(sc); 1214 } 1215 1216 static void 1217 et_init_locked(struct et_softc *sc) 1218 { 1219 if_t ifp; 1220 int error; 1221 1222 ET_LOCK_ASSERT(sc); 1223 1224 ifp = sc->ifp; 1225 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1226 return; 1227 1228 et_stop(sc); 1229 et_reset(sc); 1230 1231 et_init_tx_ring(sc); 1232 error = et_init_rx_ring(sc); 1233 if (error) 1234 return; 1235 1236 error = et_chip_init(sc); 1237 if (error) 1238 goto fail; 1239 1240 /* 1241 * Start TX/RX DMA engine 1242 */ 1243 error = et_start_rxdma(sc); 1244 if (error) 1245 return; 1246 1247 error = et_start_txdma(sc); 1248 if (error) 1249 return; 1250 1251 /* Enable interrupts. */ 1252 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1253 1254 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1255 1256 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1257 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1258 1259 sc->sc_flags &= ~ET_FLAG_LINK; 1260 et_ifmedia_upd_locked(ifp); 1261 1262 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1263 1264 fail: 1265 if (error) 1266 et_stop(sc); 1267 } 1268 1269 static void 1270 et_init(void *xsc) 1271 { 1272 struct et_softc *sc = xsc; 1273 1274 ET_LOCK(sc); 1275 et_init_locked(sc); 1276 ET_UNLOCK(sc); 1277 } 1278 1279 static int 1280 et_ioctl(if_t ifp, u_long cmd, caddr_t data) 1281 { 1282 struct et_softc *sc; 1283 struct mii_data *mii; 1284 struct ifreq *ifr; 1285 int error, mask, max_framelen; 1286 1287 sc = if_getsoftc(ifp); 1288 ifr = (struct ifreq *)data; 1289 error = 0; 1290 1291 /* XXX LOCKSUSED */ 1292 switch (cmd) { 1293 case SIOCSIFFLAGS: 1294 ET_LOCK(sc); 1295 if (if_getflags(ifp) & IFF_UP) { 1296 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1297 if ((if_getflags(ifp) ^ sc->sc_if_flags) & 1298 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1299 et_setmulti(sc); 1300 } else { 1301 et_init_locked(sc); 1302 } 1303 } else { 1304 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1305 et_stop(sc); 1306 } 1307 sc->sc_if_flags = if_getflags(ifp); 1308 ET_UNLOCK(sc); 1309 break; 1310 1311 case SIOCSIFMEDIA: 1312 case SIOCGIFMEDIA: 1313 mii = device_get_softc(sc->sc_miibus); 1314 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1315 break; 1316 1317 case SIOCADDMULTI: 1318 case SIOCDELMULTI: 1319 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1320 ET_LOCK(sc); 1321 et_setmulti(sc); 1322 ET_UNLOCK(sc); 1323 } 1324 break; 1325 1326 case SIOCSIFMTU: 1327 ET_LOCK(sc); 1328 #if 0 1329 if (sc->sc_flags & ET_FLAG_JUMBO) 1330 max_framelen = ET_JUMBO_FRAMELEN; 1331 else 1332 #endif 1333 max_framelen = MCLBYTES - 1; 1334 1335 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1336 error = EOPNOTSUPP; 1337 ET_UNLOCK(sc); 1338 break; 1339 } 1340 1341 if (if_getmtu(ifp) != ifr->ifr_mtu) { 1342 if_setmtu(ifp, ifr->ifr_mtu); 1343 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1344 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1345 et_init_locked(sc); 1346 } 1347 } 1348 ET_UNLOCK(sc); 1349 break; 1350 1351 case SIOCSIFCAP: 1352 ET_LOCK(sc); 1353 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1354 if ((mask & IFCAP_TXCSUM) != 0 && 1355 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1356 if_togglecapenable(ifp, IFCAP_TXCSUM); 1357 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 1358 if_sethwassistbits(ifp, ET_CSUM_FEATURES, 0); 1359 else 1360 if_sethwassistbits(ifp, 0, ET_CSUM_FEATURES); 1361 } 1362 ET_UNLOCK(sc); 1363 break; 1364 1365 default: 1366 error = ether_ioctl(ifp, cmd, data); 1367 break; 1368 } 1369 return (error); 1370 } 1371 1372 static void 1373 et_start_locked(if_t ifp) 1374 { 1375 struct et_softc *sc; 1376 struct mbuf *m_head = NULL; 1377 struct et_txdesc_ring *tx_ring; 1378 struct et_txbuf_data *tbd; 1379 uint32_t tx_ready_pos; 1380 int enq; 1381 1382 sc = if_getsoftc(ifp); 1383 ET_LOCK_ASSERT(sc); 1384 1385 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1386 IFF_DRV_RUNNING || 1387 (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) != 1388 (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) 1389 return; 1390 1391 /* 1392 * Driver does not request TX completion interrupt for every 1393 * queued frames to prevent generating excessive interrupts. 1394 * This means driver may wait for TX completion interrupt even 1395 * though some frames were successfully transmitted. Reclaiming 1396 * transmitted frames will ensure driver see all available 1397 * descriptors. 1398 */ 1399 tbd = &sc->sc_tx_data; 1400 if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3) 1401 et_txeof(sc); 1402 1403 for (enq = 0; !if_sendq_empty(ifp); ) { 1404 if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 1405 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1406 break; 1407 } 1408 1409 m_head = if_dequeue(ifp); 1410 if (m_head == NULL) 1411 break; 1412 1413 if (et_encap(sc, &m_head)) { 1414 if (m_head == NULL) { 1415 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1416 break; 1417 } 1418 if_sendq_prepend(ifp, m_head); 1419 if (tbd->tbd_used > 0) 1420 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1421 break; 1422 } 1423 enq++; 1424 ETHER_BPF_MTAP(ifp, m_head); 1425 } 1426 1427 if (enq > 0) { 1428 tx_ring = &sc->sc_tx_ring; 1429 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1430 BUS_DMASYNC_PREWRITE); 1431 tx_ready_pos = tx_ring->tr_ready_index & 1432 ET_TX_READY_POS_INDEX_MASK; 1433 if (tx_ring->tr_ready_wrap) 1434 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1435 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1436 sc->watchdog_timer = 5; 1437 } 1438 } 1439 1440 static void 1441 et_start(if_t ifp) 1442 { 1443 struct et_softc *sc; 1444 1445 sc = if_getsoftc(ifp); 1446 ET_LOCK(sc); 1447 et_start_locked(ifp); 1448 ET_UNLOCK(sc); 1449 } 1450 1451 static int 1452 et_watchdog(struct et_softc *sc) 1453 { 1454 uint32_t status; 1455 1456 ET_LOCK_ASSERT(sc); 1457 1458 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1459 return (0); 1460 1461 bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1462 BUS_DMASYNC_POSTREAD); 1463 status = le32toh(*(sc->sc_tx_status.txsd_status)); 1464 if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1465 status); 1466 1467 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 1468 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING); 1469 et_init_locked(sc); 1470 return (EJUSTRETURN); 1471 } 1472 1473 static int 1474 et_stop_rxdma(struct et_softc *sc) 1475 { 1476 1477 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1478 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1479 1480 DELAY(5); 1481 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1482 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1483 return (ETIMEDOUT); 1484 } 1485 return (0); 1486 } 1487 1488 static int 1489 et_stop_txdma(struct et_softc *sc) 1490 { 1491 1492 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1493 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1494 return (0); 1495 } 1496 1497 static void 1498 et_free_tx_ring(struct et_softc *sc) 1499 { 1500 struct et_txbuf_data *tbd; 1501 struct et_txbuf *tb; 1502 int i; 1503 1504 tbd = &sc->sc_tx_data; 1505 for (i = 0; i < ET_TX_NDESC; ++i) { 1506 tb = &tbd->tbd_buf[i]; 1507 if (tb->tb_mbuf != NULL) { 1508 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1509 BUS_DMASYNC_POSTWRITE); 1510 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1511 m_freem(tb->tb_mbuf); 1512 tb->tb_mbuf = NULL; 1513 } 1514 } 1515 } 1516 1517 static void 1518 et_free_rx_ring(struct et_softc *sc) 1519 { 1520 struct et_rxbuf_data *rbd; 1521 struct et_rxdesc_ring *rx_ring; 1522 struct et_rxbuf *rb; 1523 int i; 1524 1525 /* Ring 0 */ 1526 rx_ring = &sc->sc_rx_ring[0]; 1527 rbd = &sc->sc_rx_data[0]; 1528 for (i = 0; i < ET_RX_NDESC; ++i) { 1529 rb = &rbd->rbd_buf[i]; 1530 if (rb->rb_mbuf != NULL) { 1531 bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1532 BUS_DMASYNC_POSTREAD); 1533 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 1534 m_freem(rb->rb_mbuf); 1535 rb->rb_mbuf = NULL; 1536 } 1537 } 1538 1539 /* Ring 1 */ 1540 rx_ring = &sc->sc_rx_ring[1]; 1541 rbd = &sc->sc_rx_data[1]; 1542 for (i = 0; i < ET_RX_NDESC; ++i) { 1543 rb = &rbd->rbd_buf[i]; 1544 if (rb->rb_mbuf != NULL) { 1545 bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1546 BUS_DMASYNC_POSTREAD); 1547 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1548 m_freem(rb->rb_mbuf); 1549 rb->rb_mbuf = NULL; 1550 } 1551 } 1552 } 1553 1554 static u_int 1555 et_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1556 { 1557 uint32_t h, *hp, *hash = arg; 1558 1559 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 1560 h = (h & 0x3f800000) >> 23; 1561 1562 hp = &hash[0]; 1563 if (h >= 32 && h < 64) { 1564 h -= 32; 1565 hp = &hash[1]; 1566 } else if (h >= 64 && h < 96) { 1567 h -= 64; 1568 hp = &hash[2]; 1569 } else if (h >= 96) { 1570 h -= 96; 1571 hp = &hash[3]; 1572 } 1573 *hp |= (1 << h); 1574 1575 return (1); 1576 } 1577 1578 static void 1579 et_setmulti(struct et_softc *sc) 1580 { 1581 if_t ifp; 1582 uint32_t hash[4] = { 0, 0, 0, 0 }; 1583 uint32_t rxmac_ctrl, pktfilt; 1584 int i, count; 1585 1586 ET_LOCK_ASSERT(sc); 1587 ifp = sc->ifp; 1588 1589 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1590 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1591 1592 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1593 if (if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) { 1594 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1595 goto back; 1596 } 1597 1598 count = if_foreach_llmaddr(ifp, et_hash_maddr, &hash); 1599 1600 for (i = 0; i < 4; ++i) 1601 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1602 1603 if (count > 0) 1604 pktfilt |= ET_PKTFILT_MCAST; 1605 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1606 back: 1607 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1608 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1609 } 1610 1611 static int 1612 et_chip_init(struct et_softc *sc) 1613 { 1614 if_t ifp; 1615 uint32_t rxq_end; 1616 int error, frame_len, rxmem_size; 1617 1618 ifp = sc->ifp; 1619 /* 1620 * Split 16Kbytes internal memory between TX and RX 1621 * according to frame length. 1622 */ 1623 frame_len = ET_FRAMELEN(if_getmtu(ifp)); 1624 if (frame_len < 2048) { 1625 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1626 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1627 rxmem_size = ET_MEM_SIZE / 2; 1628 } else { 1629 rxmem_size = ET_MEM_SIZE - 1630 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1631 } 1632 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1633 1634 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1635 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1636 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1637 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1638 1639 /* No loopback */ 1640 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1641 1642 /* Clear MSI configure */ 1643 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1644 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1645 1646 /* Disable timer */ 1647 CSR_WRITE_4(sc, ET_TIMER, 0); 1648 1649 /* Initialize MAC */ 1650 et_init_mac(sc); 1651 1652 /* Enable memory controllers */ 1653 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1654 1655 /* Initialize RX MAC */ 1656 et_init_rxmac(sc); 1657 1658 /* Initialize TX MAC */ 1659 et_init_txmac(sc); 1660 1661 /* Initialize RX DMA engine */ 1662 error = et_init_rxdma(sc); 1663 if (error) 1664 return (error); 1665 1666 /* Initialize TX DMA engine */ 1667 error = et_init_txdma(sc); 1668 if (error) 1669 return (error); 1670 1671 return (0); 1672 } 1673 1674 static void 1675 et_init_tx_ring(struct et_softc *sc) 1676 { 1677 struct et_txdesc_ring *tx_ring; 1678 struct et_txbuf_data *tbd; 1679 struct et_txstatus_data *txsd; 1680 1681 tx_ring = &sc->sc_tx_ring; 1682 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1683 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1684 BUS_DMASYNC_PREWRITE); 1685 1686 tbd = &sc->sc_tx_data; 1687 tbd->tbd_start_index = 0; 1688 tbd->tbd_start_wrap = 0; 1689 tbd->tbd_used = 0; 1690 1691 txsd = &sc->sc_tx_status; 1692 bzero(txsd->txsd_status, sizeof(uint32_t)); 1693 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1694 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1695 } 1696 1697 static int 1698 et_init_rx_ring(struct et_softc *sc) 1699 { 1700 struct et_rxstatus_data *rxsd; 1701 struct et_rxstat_ring *rxst_ring; 1702 struct et_rxbuf_data *rbd; 1703 int i, error, n; 1704 1705 for (n = 0; n < ET_RX_NRING; ++n) { 1706 rbd = &sc->sc_rx_data[n]; 1707 for (i = 0; i < ET_RX_NDESC; ++i) { 1708 error = rbd->rbd_newbuf(rbd, i); 1709 if (error) { 1710 if_printf(sc->ifp, "%d ring %d buf, " 1711 "newbuf failed: %d\n", n, i, error); 1712 return (error); 1713 } 1714 } 1715 } 1716 1717 rxsd = &sc->sc_rx_status; 1718 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1719 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1720 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1721 1722 rxst_ring = &sc->sc_rxstat_ring; 1723 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1724 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1725 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1726 1727 return (0); 1728 } 1729 1730 static int 1731 et_init_rxdma(struct et_softc *sc) 1732 { 1733 struct et_rxstatus_data *rxsd; 1734 struct et_rxstat_ring *rxst_ring; 1735 struct et_rxdesc_ring *rx_ring; 1736 int error; 1737 1738 error = et_stop_rxdma(sc); 1739 if (error) { 1740 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1741 return (error); 1742 } 1743 1744 /* 1745 * Install RX status 1746 */ 1747 rxsd = &sc->sc_rx_status; 1748 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1749 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1750 1751 /* 1752 * Install RX stat ring 1753 */ 1754 rxst_ring = &sc->sc_rxstat_ring; 1755 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1756 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1757 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1758 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1759 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1760 1761 /* Match ET_RXSTAT_POS */ 1762 rxst_ring->rsr_index = 0; 1763 rxst_ring->rsr_wrap = 0; 1764 1765 /* 1766 * Install the 2nd RX descriptor ring 1767 */ 1768 rx_ring = &sc->sc_rx_ring[1]; 1769 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1770 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1771 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1772 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1773 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1774 1775 /* Match ET_RX_RING1_POS */ 1776 rx_ring->rr_index = 0; 1777 rx_ring->rr_wrap = 1; 1778 1779 /* 1780 * Install the 1st RX descriptor ring 1781 */ 1782 rx_ring = &sc->sc_rx_ring[0]; 1783 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1784 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1785 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1786 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1787 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1788 1789 /* Match ET_RX_RING0_POS */ 1790 rx_ring->rr_index = 0; 1791 rx_ring->rr_wrap = 1; 1792 1793 /* 1794 * RX intr moderation 1795 */ 1796 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1797 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1798 1799 return (0); 1800 } 1801 1802 static int 1803 et_init_txdma(struct et_softc *sc) 1804 { 1805 struct et_txdesc_ring *tx_ring; 1806 struct et_txstatus_data *txsd; 1807 int error; 1808 1809 error = et_stop_txdma(sc); 1810 if (error) { 1811 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1812 return (error); 1813 } 1814 1815 /* 1816 * Install TX descriptor ring 1817 */ 1818 tx_ring = &sc->sc_tx_ring; 1819 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1820 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1821 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1822 1823 /* 1824 * Install TX status 1825 */ 1826 txsd = &sc->sc_tx_status; 1827 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1828 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1829 1830 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1831 1832 /* Match ET_TX_READY_POS */ 1833 tx_ring->tr_ready_index = 0; 1834 tx_ring->tr_ready_wrap = 0; 1835 1836 return (0); 1837 } 1838 1839 static void 1840 et_init_mac(struct et_softc *sc) 1841 { 1842 if_t ifp; 1843 const uint8_t *eaddr; 1844 uint32_t val; 1845 1846 /* Reset MAC */ 1847 CSR_WRITE_4(sc, ET_MAC_CFG1, 1848 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1849 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1850 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1851 1852 /* 1853 * Setup inter packet gap 1854 */ 1855 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1856 (88 << ET_IPG_NONB2B_2_SHIFT) | 1857 (80 << ET_IPG_MINIFG_SHIFT) | 1858 (96 << ET_IPG_B2B_SHIFT); 1859 CSR_WRITE_4(sc, ET_IPG, val); 1860 1861 /* 1862 * Setup half duplex mode 1863 */ 1864 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1865 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1866 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1867 ET_MAC_HDX_EXC_DEFER; 1868 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1869 1870 /* Clear MAC control */ 1871 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1872 1873 /* Reset MII */ 1874 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1875 1876 /* 1877 * Set MAC address 1878 */ 1879 ifp = sc->ifp; 1880 eaddr = if_getlladdr(ifp); 1881 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1882 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1883 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1884 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1885 1886 /* Set max frame length */ 1887 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(if_getmtu(ifp))); 1888 1889 /* Bring MAC out of reset state */ 1890 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1891 } 1892 1893 static void 1894 et_init_rxmac(struct et_softc *sc) 1895 { 1896 if_t ifp; 1897 const uint8_t *eaddr; 1898 uint32_t val; 1899 int i; 1900 1901 /* Disable RX MAC and WOL */ 1902 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1903 1904 /* 1905 * Clear all WOL related registers 1906 */ 1907 for (i = 0; i < 3; ++i) 1908 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1909 for (i = 0; i < 20; ++i) 1910 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1911 1912 /* 1913 * Set WOL source address. XXX is this necessary? 1914 */ 1915 ifp = sc->ifp; 1916 eaddr = if_getlladdr(ifp); 1917 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1918 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1919 val = (eaddr[0] << 8) | eaddr[1]; 1920 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1921 1922 /* Clear packet filters */ 1923 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1924 1925 /* No ucast filtering */ 1926 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1927 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1928 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1929 1930 if (ET_FRAMELEN(if_getmtu(ifp)) > ET_RXMAC_CUT_THRU_FRMLEN) { 1931 /* 1932 * In order to transmit jumbo packets greater than 1933 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1934 * RX MAC and RX DMA needs to be reduced in size to 1935 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1936 * order to implement this, we must use "cut through" 1937 * mode in the RX MAC, which chops packets down into 1938 * segments. In this case we selected 256 bytes, 1939 * since this is the size of the PCI-Express TLP's 1940 * that the ET1310 uses. 1941 */ 1942 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1943 ET_RXMAC_MC_SEGSZ_ENABLE; 1944 } else { 1945 val = 0; 1946 } 1947 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1948 1949 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1950 1951 /* Initialize RX MAC management register */ 1952 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1953 1954 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1955 1956 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1957 ET_RXMAC_MGT_PASS_ECRC | 1958 ET_RXMAC_MGT_PASS_ELEN | 1959 ET_RXMAC_MGT_PASS_ETRUNC | 1960 ET_RXMAC_MGT_CHECK_PKT); 1961 1962 /* 1963 * Configure runt filtering (may not work on certain chip generation) 1964 */ 1965 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1966 ET_PKTFILT_MINLEN_MASK; 1967 val |= ET_PKTFILT_FRAG; 1968 CSR_WRITE_4(sc, ET_PKTFILT, val); 1969 1970 /* Enable RX MAC but leave WOL disabled */ 1971 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1972 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1973 1974 /* 1975 * Setup multicast hash and allmulti/promisc mode 1976 */ 1977 et_setmulti(sc); 1978 } 1979 1980 static void 1981 et_init_txmac(struct et_softc *sc) 1982 { 1983 1984 /* Disable TX MAC and FC(?) */ 1985 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1986 1987 /* 1988 * Initialize pause time. 1989 * This register should be set before XON/XOFF frame is 1990 * sent by driver. 1991 */ 1992 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT); 1993 1994 /* Enable TX MAC but leave FC(?) disabled */ 1995 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 1996 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 1997 } 1998 1999 static int 2000 et_start_rxdma(struct et_softc *sc) 2001 { 2002 uint32_t val; 2003 2004 val = (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 2005 ET_RXDMA_CTRL_RING0_ENABLE; 2006 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 2007 ET_RXDMA_CTRL_RING1_ENABLE; 2008 2009 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 2010 2011 DELAY(5); 2012 2013 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 2014 if_printf(sc->ifp, "can't start RX DMA engine\n"); 2015 return (ETIMEDOUT); 2016 } 2017 return (0); 2018 } 2019 2020 static int 2021 et_start_txdma(struct et_softc *sc) 2022 { 2023 2024 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 2025 return (0); 2026 } 2027 2028 static void 2029 et_rxeof(struct et_softc *sc) 2030 { 2031 struct et_rxstatus_data *rxsd; 2032 struct et_rxstat_ring *rxst_ring; 2033 struct et_rxbuf_data *rbd; 2034 struct et_rxdesc_ring *rx_ring; 2035 struct et_rxstat *st; 2036 if_t ifp; 2037 struct mbuf *m; 2038 uint32_t rxstat_pos, rxring_pos; 2039 uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 2040 int buflen, buf_idx, npost[2], ring_idx; 2041 int rxst_index, rxst_wrap; 2042 2043 ET_LOCK_ASSERT(sc); 2044 2045 ifp = sc->ifp; 2046 rxsd = &sc->sc_rx_status; 2047 rxst_ring = &sc->sc_rxstat_ring; 2048 2049 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2050 return; 2051 2052 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2053 BUS_DMASYNC_POSTREAD); 2054 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2055 BUS_DMASYNC_POSTREAD); 2056 2057 npost[0] = npost[1] = 0; 2058 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 2059 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 2060 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 2061 ET_RXS_STATRING_INDEX_SHIFT; 2062 2063 while (rxst_index != rxst_ring->rsr_index || 2064 rxst_wrap != rxst_ring->rsr_wrap) { 2065 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2066 break; 2067 2068 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 2069 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 2070 rxst_info1 = le32toh(st->rxst_info1); 2071 rxst_info2 = le32toh(st->rxst_info2); 2072 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 2073 ET_RXST_INFO2_LEN_SHIFT; 2074 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 2075 ET_RXST_INFO2_BUFIDX_SHIFT; 2076 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 2077 ET_RXST_INFO2_RINGIDX_SHIFT; 2078 2079 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 2080 rxst_ring->rsr_index = 0; 2081 rxst_ring->rsr_wrap ^= 1; 2082 } 2083 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 2084 if (rxst_ring->rsr_wrap) 2085 rxstat_pos |= ET_RXSTAT_POS_WRAP; 2086 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 2087 2088 if (ring_idx >= ET_RX_NRING) { 2089 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2090 if_printf(ifp, "invalid ring index %d\n", ring_idx); 2091 continue; 2092 } 2093 if (buf_idx >= ET_RX_NDESC) { 2094 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2095 if_printf(ifp, "invalid buf index %d\n", buf_idx); 2096 continue; 2097 } 2098 2099 rbd = &sc->sc_rx_data[ring_idx]; 2100 m = rbd->rbd_buf[buf_idx].rb_mbuf; 2101 if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 2102 /* Discard errored frame. */ 2103 rbd->rbd_discard(rbd, buf_idx); 2104 } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 2105 /* No available mbufs, discard it. */ 2106 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2107 rbd->rbd_discard(rbd, buf_idx); 2108 } else { 2109 buflen -= ETHER_CRC_LEN; 2110 if (buflen < ETHER_HDR_LEN) { 2111 m_freem(m); 2112 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2113 } else { 2114 m->m_pkthdr.len = m->m_len = buflen; 2115 m->m_pkthdr.rcvif = ifp; 2116 ET_UNLOCK(sc); 2117 if_input(ifp, m); 2118 ET_LOCK(sc); 2119 } 2120 } 2121 2122 rx_ring = &sc->sc_rx_ring[ring_idx]; 2123 if (buf_idx != rx_ring->rr_index) { 2124 if_printf(ifp, 2125 "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 2126 ring_idx, buf_idx, rx_ring->rr_index); 2127 } 2128 2129 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2130 if (++rx_ring->rr_index == ET_RX_NDESC) { 2131 rx_ring->rr_index = 0; 2132 rx_ring->rr_wrap ^= 1; 2133 } 2134 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2135 if (rx_ring->rr_wrap) 2136 rxring_pos |= ET_RX_RING_POS_WRAP; 2137 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2138 } 2139 2140 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2141 BUS_DMASYNC_PREREAD); 2142 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2143 BUS_DMASYNC_PREREAD); 2144 } 2145 2146 static int 2147 et_encap(struct et_softc *sc, struct mbuf **m0) 2148 { 2149 struct et_txdesc_ring *tx_ring; 2150 struct et_txbuf_data *tbd; 2151 struct et_txdesc *td; 2152 struct mbuf *m; 2153 bus_dma_segment_t segs[ET_NSEG_MAX]; 2154 bus_dmamap_t map; 2155 uint32_t csum_flags, last_td_ctrl2; 2156 int error, i, idx, first_idx, last_idx, nsegs; 2157 2158 tx_ring = &sc->sc_tx_ring; 2159 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2160 tbd = &sc->sc_tx_data; 2161 first_idx = tx_ring->tr_ready_index; 2162 map = tbd->tbd_buf[first_idx].tb_dmap; 2163 2164 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2165 0); 2166 if (error == EFBIG) { 2167 m = m_collapse(*m0, M_NOWAIT, ET_NSEG_MAX); 2168 if (m == NULL) { 2169 m_freem(*m0); 2170 *m0 = NULL; 2171 return (ENOMEM); 2172 } 2173 *m0 = m; 2174 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2175 &nsegs, 0); 2176 if (error != 0) { 2177 m_freem(*m0); 2178 *m0 = NULL; 2179 return (error); 2180 } 2181 } else if (error != 0) 2182 return (error); 2183 2184 /* Check for descriptor overruns. */ 2185 if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2186 bus_dmamap_unload(sc->sc_tx_tag, map); 2187 return (ENOBUFS); 2188 } 2189 bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2190 2191 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2192 sc->sc_tx += nsegs; 2193 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2194 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2195 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2196 } 2197 2198 m = *m0; 2199 csum_flags = 0; 2200 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2201 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2202 csum_flags |= ET_TDCTRL2_CSUM_IP; 2203 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2204 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2205 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2206 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2207 } 2208 last_idx = -1; 2209 for (i = 0; i < nsegs; ++i) { 2210 idx = (first_idx + i) % ET_TX_NDESC; 2211 td = &tx_ring->tr_desc[idx]; 2212 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2213 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2214 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2215 if (i == nsegs - 1) { 2216 /* Last frag */ 2217 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2218 last_idx = idx; 2219 } else 2220 td->td_ctrl2 = htole32(csum_flags); 2221 2222 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2223 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2224 tx_ring->tr_ready_index = 0; 2225 tx_ring->tr_ready_wrap ^= 1; 2226 } 2227 } 2228 td = &tx_ring->tr_desc[first_idx]; 2229 /* First frag */ 2230 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 2231 2232 MPASS(last_idx >= 0); 2233 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2234 tbd->tbd_buf[last_idx].tb_dmap = map; 2235 tbd->tbd_buf[last_idx].tb_mbuf = m; 2236 2237 tbd->tbd_used += nsegs; 2238 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2239 2240 return (0); 2241 } 2242 2243 static void 2244 et_txeof(struct et_softc *sc) 2245 { 2246 struct et_txdesc_ring *tx_ring; 2247 struct et_txbuf_data *tbd; 2248 struct et_txbuf *tb; 2249 if_t ifp; 2250 uint32_t tx_done; 2251 int end, wrap; 2252 2253 ET_LOCK_ASSERT(sc); 2254 2255 ifp = sc->ifp; 2256 tx_ring = &sc->sc_tx_ring; 2257 tbd = &sc->sc_tx_data; 2258 2259 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2260 return; 2261 2262 if (tbd->tbd_used == 0) 2263 return; 2264 2265 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2266 BUS_DMASYNC_POSTWRITE); 2267 2268 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2269 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2270 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2271 2272 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2273 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2274 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2275 if (tb->tb_mbuf != NULL) { 2276 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2277 BUS_DMASYNC_POSTWRITE); 2278 bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 2279 m_freem(tb->tb_mbuf); 2280 tb->tb_mbuf = NULL; 2281 } 2282 2283 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2284 tbd->tbd_start_index = 0; 2285 tbd->tbd_start_wrap ^= 1; 2286 } 2287 2288 MPASS(tbd->tbd_used > 0); 2289 tbd->tbd_used--; 2290 } 2291 2292 if (tbd->tbd_used == 0) 2293 sc->watchdog_timer = 0; 2294 if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 2295 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2296 } 2297 2298 static void 2299 et_tick(void *xsc) 2300 { 2301 struct et_softc *sc; 2302 struct mii_data *mii; 2303 2304 sc = xsc; 2305 ET_LOCK_ASSERT(sc); 2306 mii = device_get_softc(sc->sc_miibus); 2307 2308 mii_tick(mii); 2309 et_stats_update(sc); 2310 if (et_watchdog(sc) == EJUSTRETURN) 2311 return; 2312 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2313 } 2314 2315 static int 2316 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 2317 { 2318 struct et_softc *sc; 2319 struct et_rxdesc *desc; 2320 struct et_rxbuf *rb; 2321 struct mbuf *m; 2322 bus_dma_segment_t segs[1]; 2323 bus_dmamap_t dmap; 2324 int nsegs; 2325 2326 MPASS(buf_idx < ET_RX_NDESC); 2327 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2328 if (m == NULL) 2329 return (ENOBUFS); 2330 m->m_len = m->m_pkthdr.len = MCLBYTES; 2331 m_adj(m, ETHER_ALIGN); 2332 2333 sc = rbd->rbd_softc; 2334 rb = &rbd->rbd_buf[buf_idx]; 2335 2336 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2337 segs, &nsegs, 0) != 0) { 2338 m_freem(m); 2339 return (ENOBUFS); 2340 } 2341 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2342 2343 if (rb->rb_mbuf != NULL) { 2344 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 2345 BUS_DMASYNC_POSTREAD); 2346 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 2347 } 2348 dmap = rb->rb_dmap; 2349 rb->rb_dmap = sc->sc_rx_sparemap; 2350 sc->sc_rx_sparemap = dmap; 2351 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2352 2353 rb->rb_mbuf = m; 2354 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2355 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2356 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2357 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2358 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2359 BUS_DMASYNC_PREWRITE); 2360 return (0); 2361 } 2362 2363 static void 2364 et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2365 { 2366 struct et_rxdesc *desc; 2367 2368 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2369 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2370 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2371 BUS_DMASYNC_PREWRITE); 2372 } 2373 2374 static int 2375 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2376 { 2377 struct et_softc *sc; 2378 struct et_rxdesc *desc; 2379 struct et_rxbuf *rb; 2380 struct mbuf *m; 2381 bus_dma_segment_t segs[1]; 2382 bus_dmamap_t dmap; 2383 int nsegs; 2384 2385 MPASS(buf_idx < ET_RX_NDESC); 2386 MGETHDR(m, M_NOWAIT, MT_DATA); 2387 if (m == NULL) 2388 return (ENOBUFS); 2389 m->m_len = m->m_pkthdr.len = MHLEN; 2390 m_adj(m, ETHER_ALIGN); 2391 2392 sc = rbd->rbd_softc; 2393 rb = &rbd->rbd_buf[buf_idx]; 2394 2395 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2396 m, segs, &nsegs, 0) != 0) { 2397 m_freem(m); 2398 return (ENOBUFS); 2399 } 2400 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2401 2402 if (rb->rb_mbuf != NULL) { 2403 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2404 BUS_DMASYNC_POSTREAD); 2405 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2406 } 2407 dmap = rb->rb_dmap; 2408 rb->rb_dmap = sc->sc_rx_mini_sparemap; 2409 sc->sc_rx_mini_sparemap = dmap; 2410 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2411 2412 rb->rb_mbuf = m; 2413 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2414 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2415 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2416 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2417 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2418 BUS_DMASYNC_PREWRITE); 2419 return (0); 2420 } 2421 2422 #define ET_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2423 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2424 #define ET_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2425 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2426 2427 /* 2428 * Create sysctl tree 2429 */ 2430 static void 2431 et_add_sysctls(struct et_softc * sc) 2432 { 2433 struct sysctl_ctx_list *ctx; 2434 struct sysctl_oid_list *children, *parent; 2435 struct sysctl_oid *tree; 2436 struct et_hw_stats *stats; 2437 2438 ctx = device_get_sysctl_ctx(sc->dev); 2439 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2440 2441 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2442 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2443 et_sysctl_rx_intr_npkts, "I", "RX IM, # packets per RX interrupt"); 2444 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2445 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2446 et_sysctl_rx_intr_delay, "I", 2447 "RX IM, RX interrupt delay (x10 usec)"); 2448 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2449 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2450 "TX IM, # segments per TX interrupt"); 2451 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2452 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2453 2454 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 2455 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ET statistics"); 2456 parent = SYSCTL_CHILDREN(tree); 2457 2458 /* TX/RX statistics. */ 2459 stats = &sc->sc_stats; 2460 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64, 2461 "0 to 64 bytes frames"); 2462 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65, 2463 "65 to 127 bytes frames"); 2464 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128, 2465 "128 to 255 bytes frames"); 2466 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256, 2467 "256 to 511 bytes frames"); 2468 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512, 2469 "512 to 1023 bytes frames"); 2470 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024, 2471 "1024 to 1518 bytes frames"); 2472 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519, 2473 "1519 to 1522 bytes frames"); 2474 2475 /* RX statistics. */ 2476 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2477 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 2478 children = SYSCTL_CHILDREN(tree); 2479 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2480 &stats->rx_bytes, "Good bytes"); 2481 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2482 &stats->rx_frames, "Good frames"); 2483 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2484 &stats->rx_crcerrs, "CRC errors"); 2485 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2486 &stats->rx_mcast, "Multicast frames"); 2487 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2488 &stats->rx_bcast, "Broadcast frames"); 2489 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2490 &stats->rx_control, "Control frames"); 2491 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2492 &stats->rx_pause, "Pause frames"); 2493 ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control", 2494 &stats->rx_unknown_control, "Unknown control frames"); 2495 ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs", 2496 &stats->rx_alignerrs, "Alignment errors"); 2497 ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs", 2498 &stats->rx_lenerrs, "Frames with length mismatched"); 2499 ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs", 2500 &stats->rx_codeerrs, "Frames with code error"); 2501 ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs", 2502 &stats->rx_cserrs, "Frames with carrier sense error"); 2503 ET_SYSCTL_STAT_ADD32(ctx, children, "runts", 2504 &stats->rx_runts, "Too short frames"); 2505 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2506 &stats->rx_oversize, "Oversized frames"); 2507 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2508 &stats->rx_fragments, "Fragmented frames"); 2509 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2510 &stats->rx_jabbers, "Frames with jabber error"); 2511 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2512 &stats->rx_drop, "Dropped frames"); 2513 2514 /* TX statistics. */ 2515 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2516 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 2517 children = SYSCTL_CHILDREN(tree); 2518 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2519 &stats->tx_bytes, "Good bytes"); 2520 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2521 &stats->tx_frames, "Good frames"); 2522 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2523 &stats->tx_mcast, "Multicast frames"); 2524 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2525 &stats->tx_bcast, "Broadcast frames"); 2526 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2527 &stats->tx_pause, "Pause frames"); 2528 ET_SYSCTL_STAT_ADD32(ctx, children, "deferred", 2529 &stats->tx_deferred, "Deferred frames"); 2530 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred", 2531 &stats->tx_excess_deferred, "Excessively deferred frames"); 2532 ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls", 2533 &stats->tx_single_colls, "Single collisions"); 2534 ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls", 2535 &stats->tx_multi_colls, "Multiple collisions"); 2536 ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls", 2537 &stats->tx_late_colls, "Late collisions"); 2538 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls", 2539 &stats->tx_excess_colls, "Excess collisions"); 2540 ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls", 2541 &stats->tx_total_colls, "Total collisions"); 2542 ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored", 2543 &stats->tx_pause_honored, "Honored pause frames"); 2544 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2545 &stats->tx_drop, "Dropped frames"); 2546 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2547 &stats->tx_jabbers, "Frames with jabber errors"); 2548 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2549 &stats->tx_crcerrs, "Frames with CRC errors"); 2550 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2551 &stats->tx_control, "Control frames"); 2552 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2553 &stats->tx_oversize, "Oversized frames"); 2554 ET_SYSCTL_STAT_ADD32(ctx, children, "undersize", 2555 &stats->tx_undersize, "Undersized frames"); 2556 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2557 &stats->tx_fragments, "Fragmented frames"); 2558 } 2559 2560 #undef ET_SYSCTL_STAT_ADD32 2561 #undef ET_SYSCTL_STAT_ADD64 2562 2563 static int 2564 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2565 { 2566 struct et_softc *sc; 2567 if_t ifp; 2568 int error, v; 2569 2570 sc = arg1; 2571 ifp = sc->ifp; 2572 v = sc->sc_rx_intr_npkts; 2573 error = sysctl_handle_int(oidp, &v, 0, req); 2574 if (error || req->newptr == NULL) 2575 goto back; 2576 if (v <= 0) { 2577 error = EINVAL; 2578 goto back; 2579 } 2580 2581 if (sc->sc_rx_intr_npkts != v) { 2582 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2583 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2584 sc->sc_rx_intr_npkts = v; 2585 } 2586 back: 2587 return (error); 2588 } 2589 2590 static int 2591 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2592 { 2593 struct et_softc *sc; 2594 if_t ifp; 2595 int error, v; 2596 2597 sc = arg1; 2598 ifp = sc->ifp; 2599 v = sc->sc_rx_intr_delay; 2600 error = sysctl_handle_int(oidp, &v, 0, req); 2601 if (error || req->newptr == NULL) 2602 goto back; 2603 if (v <= 0) { 2604 error = EINVAL; 2605 goto back; 2606 } 2607 2608 if (sc->sc_rx_intr_delay != v) { 2609 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2610 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2611 sc->sc_rx_intr_delay = v; 2612 } 2613 back: 2614 return (error); 2615 } 2616 2617 static void 2618 et_stats_update(struct et_softc *sc) 2619 { 2620 struct et_hw_stats *stats; 2621 2622 stats = &sc->sc_stats; 2623 stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64); 2624 stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127); 2625 stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255); 2626 stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511); 2627 stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023); 2628 stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518); 2629 stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522); 2630 2631 stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES); 2632 stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES); 2633 stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR); 2634 stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST); 2635 stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST); 2636 stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL); 2637 stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE); 2638 stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL); 2639 stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR); 2640 stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR); 2641 stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR); 2642 stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR); 2643 stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT); 2644 stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE); 2645 stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG); 2646 stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER); 2647 stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP); 2648 2649 stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES); 2650 stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES); 2651 stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST); 2652 stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST); 2653 stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE); 2654 stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER); 2655 stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER); 2656 stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL); 2657 stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL); 2658 stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL); 2659 stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL); 2660 stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL); 2661 stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR); 2662 stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP); 2663 stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER); 2664 stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR); 2665 stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL); 2666 stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE); 2667 stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE); 2668 stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG); 2669 } 2670 2671 static uint64_t 2672 et_get_counter(if_t ifp, ift_counter cnt) 2673 { 2674 struct et_softc *sc; 2675 struct et_hw_stats *stats; 2676 2677 sc = if_getsoftc(ifp); 2678 stats = &sc->sc_stats; 2679 2680 switch (cnt) { 2681 case IFCOUNTER_OPACKETS: 2682 return (stats->tx_frames); 2683 case IFCOUNTER_COLLISIONS: 2684 return (stats->tx_total_colls); 2685 case IFCOUNTER_OERRORS: 2686 return (stats->tx_drop + stats->tx_jabbers + 2687 stats->tx_crcerrs + stats->tx_excess_deferred + 2688 stats->tx_late_colls); 2689 case IFCOUNTER_IPACKETS: 2690 return (stats->rx_frames); 2691 case IFCOUNTER_IERRORS: 2692 return (stats->rx_crcerrs + stats->rx_alignerrs + 2693 stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs + 2694 stats->rx_runts + stats->rx_jabbers + stats->rx_drop); 2695 default: 2696 return (if_get_counter_default(ifp, cnt)); 2697 } 2698 } 2699 2700 static int 2701 et_suspend(device_t dev) 2702 { 2703 struct et_softc *sc; 2704 uint32_t pmcfg; 2705 2706 sc = device_get_softc(dev); 2707 ET_LOCK(sc); 2708 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != 0) 2709 et_stop(sc); 2710 /* Diable all clocks and put PHY into COMA. */ 2711 pmcfg = CSR_READ_4(sc, ET_PM); 2712 pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | 2713 ET_PM_RXCLK_GATE); 2714 pmcfg |= ET_PM_PHY_SW_COMA; 2715 CSR_WRITE_4(sc, ET_PM, pmcfg); 2716 ET_UNLOCK(sc); 2717 return (0); 2718 } 2719 2720 static int 2721 et_resume(device_t dev) 2722 { 2723 struct et_softc *sc; 2724 uint32_t pmcfg; 2725 2726 sc = device_get_softc(dev); 2727 ET_LOCK(sc); 2728 /* Take PHY out of COMA and enable clocks. */ 2729 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 2730 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 2731 pmcfg |= EM_PM_GIGEPHY_ENB; 2732 CSR_WRITE_4(sc, ET_PM, pmcfg); 2733 if ((if_getflags(sc->ifp) & IFF_UP) != 0) 2734 et_init_locked(sc); 2735 ET_UNLOCK(sc); 2736 return (0); 2737 } 2738