14d52a575SXin LI /*- 2e5fdd9deSXin LI * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 34d52a575SXin LI * 44d52a575SXin LI * This code is derived from software contributed to The DragonFly Project 54d52a575SXin LI * by Sepherosa Ziehau <sepherosa@gmail.com> 64d52a575SXin LI * 74d52a575SXin LI * Redistribution and use in source and binary forms, with or without 84d52a575SXin LI * modification, are permitted provided that the following conditions 94d52a575SXin LI * are met: 104d52a575SXin LI * 114d52a575SXin LI * 1. Redistributions of source code must retain the above copyright 124d52a575SXin LI * notice, this list of conditions and the following disclaimer. 134d52a575SXin LI * 2. Redistributions in binary form must reproduce the above copyright 144d52a575SXin LI * notice, this list of conditions and the following disclaimer in 154d52a575SXin LI * the documentation and/or other materials provided with the 164d52a575SXin LI * distribution. 174d52a575SXin LI * 3. Neither the name of The DragonFly Project nor the names of its 184d52a575SXin LI * contributors may be used to endorse or promote products derived 194d52a575SXin LI * from this software without specific, prior written permission. 204d52a575SXin LI * 214d52a575SXin LI * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 224d52a575SXin LI * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 234d52a575SXin LI * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 244d52a575SXin LI * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 254d52a575SXin LI * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 264d52a575SXin LI * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 274d52a575SXin LI * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 284d52a575SXin LI * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 294d52a575SXin LI * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 304d52a575SXin LI * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 314d52a575SXin LI * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 324d52a575SXin LI * SUCH DAMAGE. 334d52a575SXin LI * 344d52a575SXin LI * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 354d52a575SXin LI */ 364d52a575SXin LI 37fe42b04dSPyun YongHyeon #include <sys/cdefs.h> 38fe42b04dSPyun YongHyeon __FBSDID("$FreeBSD$"); 39fe42b04dSPyun YongHyeon 404d52a575SXin LI #include <sys/param.h> 414d52a575SXin LI #include <sys/systm.h> 424d52a575SXin LI #include <sys/endian.h> 434d52a575SXin LI #include <sys/kernel.h> 444d52a575SXin LI #include <sys/bus.h> 454d52a575SXin LI #include <sys/malloc.h> 464d52a575SXin LI #include <sys/mbuf.h> 474d52a575SXin LI #include <sys/proc.h> 484d52a575SXin LI #include <sys/rman.h> 494d52a575SXin LI #include <sys/module.h> 504d52a575SXin LI #include <sys/socket.h> 514d52a575SXin LI #include <sys/sockio.h> 524d52a575SXin LI #include <sys/sysctl.h> 534d52a575SXin LI 544d52a575SXin LI #include <net/ethernet.h> 554d52a575SXin LI #include <net/if.h> 564d52a575SXin LI #include <net/if_dl.h> 574d52a575SXin LI #include <net/if_types.h> 584d52a575SXin LI #include <net/bpf.h> 594d52a575SXin LI #include <net/if_arp.h> 604d52a575SXin LI #include <net/if_dl.h> 614d52a575SXin LI #include <net/if_media.h> 624d52a575SXin LI #include <net/if_vlan_var.h> 634d52a575SXin LI 644d52a575SXin LI #include <machine/bus.h> 654d52a575SXin LI 66*d6c65d27SMarius Strobl #include <dev/mii/mii.h> 674d52a575SXin LI #include <dev/mii/miivar.h> 684d52a575SXin LI 694d52a575SXin LI #include <dev/pci/pcireg.h> 704d52a575SXin LI #include <dev/pci/pcivar.h> 714d52a575SXin LI 724d52a575SXin LI #include <dev/et/if_etreg.h> 734d52a575SXin LI #include <dev/et/if_etvar.h> 744d52a575SXin LI 754d52a575SXin LI #include "miibus_if.h" 764d52a575SXin LI 774d52a575SXin LI MODULE_DEPEND(et, pci, 1, 1, 1); 784d52a575SXin LI MODULE_DEPEND(et, ether, 1, 1, 1); 794d52a575SXin LI MODULE_DEPEND(et, miibus, 1, 1, 1); 804d52a575SXin LI 81cc3c3b4eSPyun YongHyeon /* Tunables. */ 82cc3c3b4eSPyun YongHyeon static int msi_disable = 0; 83accb4fcdSPyun YongHyeon TUNABLE_INT("hw.et.msi_disable", &msi_disable); 84cc3c3b4eSPyun YongHyeon 859955274cSPyun YongHyeon #define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 869955274cSPyun YongHyeon 874d52a575SXin LI static int et_probe(device_t); 884d52a575SXin LI static int et_attach(device_t); 894d52a575SXin LI static int et_detach(device_t); 904d52a575SXin LI static int et_shutdown(device_t); 914d52a575SXin LI 924d52a575SXin LI static int et_miibus_readreg(device_t, int, int); 934d52a575SXin LI static int et_miibus_writereg(device_t, int, int, int); 944d52a575SXin LI static void et_miibus_statchg(device_t); 954d52a575SXin LI 964d52a575SXin LI static void et_init_locked(struct et_softc *); 974d52a575SXin LI static void et_init(void *); 984d52a575SXin LI static int et_ioctl(struct ifnet *, u_long, caddr_t); 994d52a575SXin LI static void et_start_locked(struct ifnet *); 1004d52a575SXin LI static void et_start(struct ifnet *); 1014d52a575SXin LI static void et_watchdog(struct et_softc *); 1024d52a575SXin LI static int et_ifmedia_upd_locked(struct ifnet *); 1034d52a575SXin LI static int et_ifmedia_upd(struct ifnet *); 1044d52a575SXin LI static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 1054d52a575SXin LI 1064d52a575SXin LI static void et_add_sysctls(struct et_softc *); 1074d52a575SXin LI static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 1084d52a575SXin LI static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 1094d52a575SXin LI 1104d52a575SXin LI static void et_intr(void *); 1114d52a575SXin LI static void et_enable_intrs(struct et_softc *, uint32_t); 1124d52a575SXin LI static void et_disable_intrs(struct et_softc *); 1134d52a575SXin LI static void et_rxeof(struct et_softc *); 1144d52a575SXin LI static void et_txeof(struct et_softc *); 1154d52a575SXin LI 1164d52a575SXin LI static int et_dma_alloc(device_t); 1174d52a575SXin LI static void et_dma_free(device_t); 1184d52a575SXin LI static int et_dma_mem_create(device_t, bus_size_t, bus_dma_tag_t *, 1194d52a575SXin LI void **, bus_addr_t *, bus_dmamap_t *); 1204d52a575SXin LI static void et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t); 1214d52a575SXin LI static int et_dma_mbuf_create(device_t); 1224d52a575SXin LI static void et_dma_mbuf_destroy(device_t, int, const int[]); 1234d52a575SXin LI static void et_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 1244d52a575SXin LI static void et_dma_buf_addr(void *, bus_dma_segment_t *, int, 1254d52a575SXin LI bus_size_t, int); 1264d52a575SXin LI static int et_init_tx_ring(struct et_softc *); 1274d52a575SXin LI static int et_init_rx_ring(struct et_softc *); 1284d52a575SXin LI static void et_free_tx_ring(struct et_softc *); 1294d52a575SXin LI static void et_free_rx_ring(struct et_softc *); 1304d52a575SXin LI static int et_encap(struct et_softc *, struct mbuf **); 1314d52a575SXin LI static int et_newbuf(struct et_rxbuf_data *, int, int, int); 1324d52a575SXin LI static int et_newbuf_cluster(struct et_rxbuf_data *, int, int); 1334d52a575SXin LI static int et_newbuf_hdr(struct et_rxbuf_data *, int, int); 1344d52a575SXin LI 1354d52a575SXin LI static void et_stop(struct et_softc *); 1364d52a575SXin LI static int et_chip_init(struct et_softc *); 1374d52a575SXin LI static void et_chip_attach(struct et_softc *); 1384d52a575SXin LI static void et_init_mac(struct et_softc *); 1394d52a575SXin LI static void et_init_rxmac(struct et_softc *); 1404d52a575SXin LI static void et_init_txmac(struct et_softc *); 1414d52a575SXin LI static int et_init_rxdma(struct et_softc *); 1424d52a575SXin LI static int et_init_txdma(struct et_softc *); 1434d52a575SXin LI static int et_start_rxdma(struct et_softc *); 1444d52a575SXin LI static int et_start_txdma(struct et_softc *); 1454d52a575SXin LI static int et_stop_rxdma(struct et_softc *); 1464d52a575SXin LI static int et_stop_txdma(struct et_softc *); 1474d52a575SXin LI static int et_enable_txrx(struct et_softc *, int); 1484d52a575SXin LI static void et_reset(struct et_softc *); 1498b3c6496SPyun YongHyeon static int et_bus_config(struct et_softc *); 1504d52a575SXin LI static void et_get_eaddr(device_t, uint8_t[]); 1514d52a575SXin LI static void et_setmulti(struct et_softc *); 1524d52a575SXin LI static void et_tick(void *); 1534d52a575SXin LI static void et_setmedia(struct et_softc *); 1544d52a575SXin LI static void et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t); 1554d52a575SXin LI 1564d52a575SXin LI static const struct et_dev { 1574d52a575SXin LI uint16_t vid; 1584d52a575SXin LI uint16_t did; 1594d52a575SXin LI const char *desc; 1604d52a575SXin LI } et_devices[] = { 1614d52a575SXin LI { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 1624d52a575SXin LI "Agere ET1310 Gigabit Ethernet" }, 1634d52a575SXin LI { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 1644d52a575SXin LI "Agere ET1310 Fast Ethernet" }, 1654d52a575SXin LI { 0, 0, NULL } 1664d52a575SXin LI }; 1674d52a575SXin LI 1684d52a575SXin LI static device_method_t et_methods[] = { 1694d52a575SXin LI DEVMETHOD(device_probe, et_probe), 1704d52a575SXin LI DEVMETHOD(device_attach, et_attach), 1714d52a575SXin LI DEVMETHOD(device_detach, et_detach), 1724d52a575SXin LI DEVMETHOD(device_shutdown, et_shutdown), 1734d52a575SXin LI 1744d52a575SXin LI DEVMETHOD(bus_print_child, bus_generic_print_child), 1754d52a575SXin LI DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1764d52a575SXin LI 1774d52a575SXin LI DEVMETHOD(miibus_readreg, et_miibus_readreg), 1784d52a575SXin LI DEVMETHOD(miibus_writereg, et_miibus_writereg), 1794d52a575SXin LI DEVMETHOD(miibus_statchg, et_miibus_statchg), 1804d52a575SXin LI 1814d52a575SXin LI { 0, 0 } 1824d52a575SXin LI }; 1834d52a575SXin LI 1844d52a575SXin LI static driver_t et_driver = { 1854d52a575SXin LI "et", 1864d52a575SXin LI et_methods, 1874d52a575SXin LI sizeof(struct et_softc) 1884d52a575SXin LI }; 1894d52a575SXin LI 1904d52a575SXin LI static devclass_t et_devclass; 1914d52a575SXin LI 1924d52a575SXin LI DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0); 1934d52a575SXin LI DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0); 1944d52a575SXin LI 1954d52a575SXin LI static int et_rx_intr_npkts = 32; 1964d52a575SXin LI static int et_rx_intr_delay = 20; /* x10 usec */ 1974d52a575SXin LI static int et_tx_intr_nsegs = 126; 1984d52a575SXin LI static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 1994d52a575SXin LI 2004d52a575SXin LI TUNABLE_INT("hw.et.timer", &et_timer); 2014d52a575SXin LI TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 2024d52a575SXin LI TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 2034d52a575SXin LI TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 2044d52a575SXin LI 2054d52a575SXin LI struct et_bsize { 2064d52a575SXin LI int bufsize; 2074d52a575SXin LI et_newbuf_t newbuf; 2084d52a575SXin LI }; 2094d52a575SXin LI 2104d52a575SXin LI static const struct et_bsize et_bufsize_std[ET_RX_NRING] = { 2114d52a575SXin LI { .bufsize = ET_RXDMA_CTRL_RING0_128, 2124d52a575SXin LI .newbuf = et_newbuf_hdr }, 2134d52a575SXin LI { .bufsize = ET_RXDMA_CTRL_RING1_2048, 2144d52a575SXin LI .newbuf = et_newbuf_cluster }, 2154d52a575SXin LI }; 2164d52a575SXin LI 2174d52a575SXin LI static int 2184d52a575SXin LI et_probe(device_t dev) 2194d52a575SXin LI { 2204d52a575SXin LI const struct et_dev *d; 2214d52a575SXin LI uint16_t did, vid; 2224d52a575SXin LI 2234d52a575SXin LI vid = pci_get_vendor(dev); 2244d52a575SXin LI did = pci_get_device(dev); 2254d52a575SXin LI 2264d52a575SXin LI for (d = et_devices; d->desc != NULL; ++d) { 2274d52a575SXin LI if (vid == d->vid && did == d->did) { 2284d52a575SXin LI device_set_desc(dev, d->desc); 229398f1b65SPyun YongHyeon return (0); 2304d52a575SXin LI } 2314d52a575SXin LI } 232398f1b65SPyun YongHyeon return (ENXIO); 2334d52a575SXin LI } 2344d52a575SXin LI 2354d52a575SXin LI static int 2364d52a575SXin LI et_attach(device_t dev) 2374d52a575SXin LI { 2384d52a575SXin LI struct et_softc *sc; 2394d52a575SXin LI struct ifnet *ifp; 2404d52a575SXin LI uint8_t eaddr[ETHER_ADDR_LEN]; 241cc3c3b4eSPyun YongHyeon int cap, error, msic; 2424d52a575SXin LI 2434d52a575SXin LI sc = device_get_softc(dev); 2444d52a575SXin LI sc->dev = dev; 2454d52a575SXin LI mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2464d52a575SXin LI MTX_DEF); 2474d52a575SXin LI 2484d52a575SXin LI ifp = sc->ifp = if_alloc(IFT_ETHER); 2494d52a575SXin LI if (ifp == NULL) { 2504d52a575SXin LI device_printf(dev, "can not if_alloc()\n"); 2514d52a575SXin LI error = ENOSPC; 2524d52a575SXin LI goto fail; 2534d52a575SXin LI } 2544d52a575SXin LI 2554d52a575SXin LI /* 2564d52a575SXin LI * Initialize tunables 2574d52a575SXin LI */ 2584d52a575SXin LI sc->sc_rx_intr_npkts = et_rx_intr_npkts; 2594d52a575SXin LI sc->sc_rx_intr_delay = et_rx_intr_delay; 2604d52a575SXin LI sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 2614d52a575SXin LI sc->sc_timer = et_timer; 2624d52a575SXin LI 2634d52a575SXin LI /* Enable bus mastering */ 2644d52a575SXin LI pci_enable_busmaster(dev); 2654d52a575SXin LI 2664d52a575SXin LI /* 2674d52a575SXin LI * Allocate IO memory 2684d52a575SXin LI */ 2694d52a575SXin LI sc->sc_mem_rid = ET_PCIR_BAR; 2704d52a575SXin LI sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2714d52a575SXin LI &sc->sc_mem_rid, RF_ACTIVE); 2724d52a575SXin LI if (sc->sc_mem_res == NULL) { 2734d52a575SXin LI device_printf(dev, "can't allocate IO memory\n"); 274398f1b65SPyun YongHyeon return (ENXIO); 2754d52a575SXin LI } 2764d52a575SXin LI 277cc3c3b4eSPyun YongHyeon msic = 0; 278cc3c3b4eSPyun YongHyeon if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) { 279cc3c3b4eSPyun YongHyeon sc->sc_expcap = cap; 280cc3c3b4eSPyun YongHyeon sc->sc_flags |= ET_FLAG_PCIE; 281cc3c3b4eSPyun YongHyeon msic = pci_msi_count(dev); 282cc3c3b4eSPyun YongHyeon if (bootverbose) 283cc3c3b4eSPyun YongHyeon device_printf(dev, "MSI count: %d\n", msic); 284cc3c3b4eSPyun YongHyeon } 285cc3c3b4eSPyun YongHyeon if (msic > 0 && msi_disable == 0) { 286cc3c3b4eSPyun YongHyeon msic = 1; 287cc3c3b4eSPyun YongHyeon if (pci_alloc_msi(dev, &msic) == 0) { 288cc3c3b4eSPyun YongHyeon if (msic == 1) { 289cc3c3b4eSPyun YongHyeon device_printf(dev, "Using %d MSI message\n", 290cc3c3b4eSPyun YongHyeon msic); 291cc3c3b4eSPyun YongHyeon sc->sc_flags |= ET_FLAG_MSI; 292cc3c3b4eSPyun YongHyeon } else 293cc3c3b4eSPyun YongHyeon pci_release_msi(dev); 294cc3c3b4eSPyun YongHyeon } 295cc3c3b4eSPyun YongHyeon } 296cc3c3b4eSPyun YongHyeon 2974d52a575SXin LI /* 2984d52a575SXin LI * Allocate IRQ 2994d52a575SXin LI */ 300cc3c3b4eSPyun YongHyeon if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 3014d52a575SXin LI sc->sc_irq_rid = 0; 3024d52a575SXin LI sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 303cc3c3b4eSPyun YongHyeon &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 304cc3c3b4eSPyun YongHyeon } else { 305cc3c3b4eSPyun YongHyeon sc->sc_irq_rid = 1; 306cc3c3b4eSPyun YongHyeon sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 307cc3c3b4eSPyun YongHyeon &sc->sc_irq_rid, RF_ACTIVE); 308cc3c3b4eSPyun YongHyeon } 3094d52a575SXin LI if (sc->sc_irq_res == NULL) { 3104d52a575SXin LI device_printf(dev, "can't allocate irq\n"); 3114d52a575SXin LI error = ENXIO; 3124d52a575SXin LI goto fail; 3134d52a575SXin LI } 3144d52a575SXin LI 3158b3c6496SPyun YongHyeon error = et_bus_config(sc); 3164d52a575SXin LI if (error) 3174d52a575SXin LI goto fail; 3184d52a575SXin LI 3194d52a575SXin LI et_get_eaddr(dev, eaddr); 3204d52a575SXin LI 3214d52a575SXin LI CSR_WRITE_4(sc, ET_PM, 3224d52a575SXin LI ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 3234d52a575SXin LI 3244d52a575SXin LI et_reset(sc); 3254d52a575SXin LI 3264d52a575SXin LI et_disable_intrs(sc); 3274d52a575SXin LI 3284d52a575SXin LI error = et_dma_alloc(dev); 3294d52a575SXin LI if (error) 3304d52a575SXin LI goto fail; 3314d52a575SXin LI 3324d52a575SXin LI ifp->if_softc = sc; 3334d52a575SXin LI if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3344d52a575SXin LI ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3354d52a575SXin LI ifp->if_init = et_init; 3364d52a575SXin LI ifp->if_ioctl = et_ioctl; 3374d52a575SXin LI ifp->if_start = et_start; 3384d52a575SXin LI ifp->if_mtu = ETHERMTU; 339ed848e3aSPyun YongHyeon ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU; 3404d52a575SXin LI ifp->if_capenable = ifp->if_capabilities; 3414d52a575SXin LI IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC); 3424d52a575SXin LI IFQ_SET_READY(&ifp->if_snd); 3434d52a575SXin LI 3444d52a575SXin LI et_chip_attach(sc); 3454d52a575SXin LI 346*d6c65d27SMarius Strobl error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 347*d6c65d27SMarius Strobl et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 3484d52a575SXin LI if (error) { 349*d6c65d27SMarius Strobl device_printf(dev, "attaching PHYs failed\n"); 3504d52a575SXin LI goto fail; 3514d52a575SXin LI } 3524d52a575SXin LI 3534d52a575SXin LI ether_ifattach(ifp, eaddr); 3544d52a575SXin LI callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 3554d52a575SXin LI 3564d52a575SXin LI error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 3574d52a575SXin LI NULL, et_intr, sc, &sc->sc_irq_handle); 3584d52a575SXin LI if (error) { 3594d52a575SXin LI ether_ifdetach(ifp); 3604d52a575SXin LI device_printf(dev, "can't setup intr\n"); 3614d52a575SXin LI goto fail; 3624d52a575SXin LI } 3634d52a575SXin LI 3644d52a575SXin LI et_add_sysctls(sc); 3654d52a575SXin LI 366398f1b65SPyun YongHyeon return (0); 3674d52a575SXin LI fail: 3684d52a575SXin LI et_detach(dev); 369398f1b65SPyun YongHyeon return (error); 3704d52a575SXin LI } 3714d52a575SXin LI 3724d52a575SXin LI static int 3734d52a575SXin LI et_detach(device_t dev) 3744d52a575SXin LI { 3754d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 3764d52a575SXin LI 3774d52a575SXin LI if (device_is_attached(dev)) { 3784d52a575SXin LI struct ifnet *ifp = sc->ifp; 3794d52a575SXin LI 3804d52a575SXin LI ET_LOCK(sc); 3814d52a575SXin LI et_stop(sc); 3824d52a575SXin LI bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 3834d52a575SXin LI ET_UNLOCK(sc); 3844d52a575SXin LI 3854d52a575SXin LI ether_ifdetach(ifp); 3864d52a575SXin LI } 3874d52a575SXin LI 3884d52a575SXin LI if (sc->sc_miibus != NULL) 3894d52a575SXin LI device_delete_child(dev, sc->sc_miibus); 3904d52a575SXin LI bus_generic_detach(dev); 3914d52a575SXin LI 3924d52a575SXin LI if (sc->sc_irq_res != NULL) { 3934d52a575SXin LI bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 3944d52a575SXin LI sc->sc_irq_res); 3954d52a575SXin LI } 396cc3c3b4eSPyun YongHyeon if ((sc->sc_flags & ET_FLAG_MSI) != 0) 397cc3c3b4eSPyun YongHyeon pci_release_msi(dev); 3984d52a575SXin LI 3994d52a575SXin LI if (sc->sc_mem_res != NULL) { 4004d52a575SXin LI bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 4014d52a575SXin LI sc->sc_mem_res); 4024d52a575SXin LI } 4034d52a575SXin LI 4044d52a575SXin LI if (sc->ifp != NULL) 4054d52a575SXin LI if_free(sc->ifp); 4064d52a575SXin LI 4074d52a575SXin LI et_dma_free(dev); 4085b8f4900SPyun YongHyeon 4095b8f4900SPyun YongHyeon mtx_destroy(&sc->sc_mtx); 4104d52a575SXin LI 411398f1b65SPyun YongHyeon return (0); 4124d52a575SXin LI } 4134d52a575SXin LI 4144d52a575SXin LI static int 4154d52a575SXin LI et_shutdown(device_t dev) 4164d52a575SXin LI { 4174d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 4184d52a575SXin LI 4194d52a575SXin LI ET_LOCK(sc); 4204d52a575SXin LI et_stop(sc); 4214d52a575SXin LI ET_UNLOCK(sc); 422398f1b65SPyun YongHyeon return (0); 4234d52a575SXin LI } 4244d52a575SXin LI 4254d52a575SXin LI static int 4264d52a575SXin LI et_miibus_readreg(device_t dev, int phy, int reg) 4274d52a575SXin LI { 4284d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 4294d52a575SXin LI uint32_t val; 4304d52a575SXin LI int i, ret; 4314d52a575SXin LI 4324d52a575SXin LI /* Stop any pending operations */ 4334d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, 0); 4344d52a575SXin LI 43523263665SPyun YongHyeon val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 43623263665SPyun YongHyeon val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 4374d52a575SXin LI CSR_WRITE_4(sc, ET_MII_ADDR, val); 4384d52a575SXin LI 4394d52a575SXin LI /* Start reading */ 4404d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 4414d52a575SXin LI 4424d52a575SXin LI #define NRETRY 50 4434d52a575SXin LI 4444d52a575SXin LI for (i = 0; i < NRETRY; ++i) { 4454d52a575SXin LI val = CSR_READ_4(sc, ET_MII_IND); 4464d52a575SXin LI if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 4474d52a575SXin LI break; 4484d52a575SXin LI DELAY(50); 4494d52a575SXin LI } 4504d52a575SXin LI if (i == NRETRY) { 4514d52a575SXin LI if_printf(sc->ifp, 4524d52a575SXin LI "read phy %d, reg %d timed out\n", phy, reg); 4534d52a575SXin LI ret = 0; 4544d52a575SXin LI goto back; 4554d52a575SXin LI } 4564d52a575SXin LI 4574d52a575SXin LI #undef NRETRY 4584d52a575SXin LI 4594d52a575SXin LI val = CSR_READ_4(sc, ET_MII_STAT); 46023263665SPyun YongHyeon ret = val & ET_MII_STAT_VALUE_MASK; 4614d52a575SXin LI 4624d52a575SXin LI back: 4634d52a575SXin LI /* Make sure that the current operation is stopped */ 4644d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, 0); 465398f1b65SPyun YongHyeon return (ret); 4664d52a575SXin LI } 4674d52a575SXin LI 4684d52a575SXin LI static int 4694d52a575SXin LI et_miibus_writereg(device_t dev, int phy, int reg, int val0) 4704d52a575SXin LI { 4714d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 4724d52a575SXin LI uint32_t val; 4734d52a575SXin LI int i; 4744d52a575SXin LI 4754d52a575SXin LI /* Stop any pending operations */ 4764d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, 0); 4774d52a575SXin LI 47823263665SPyun YongHyeon val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 47923263665SPyun YongHyeon val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 4804d52a575SXin LI CSR_WRITE_4(sc, ET_MII_ADDR, val); 4814d52a575SXin LI 4824d52a575SXin LI /* Start writing */ 48323263665SPyun YongHyeon CSR_WRITE_4(sc, ET_MII_CTRL, 48423263665SPyun YongHyeon (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 4854d52a575SXin LI 4864d52a575SXin LI #define NRETRY 100 4874d52a575SXin LI 4884d52a575SXin LI for (i = 0; i < NRETRY; ++i) { 4894d52a575SXin LI val = CSR_READ_4(sc, ET_MII_IND); 4904d52a575SXin LI if ((val & ET_MII_IND_BUSY) == 0) 4914d52a575SXin LI break; 4924d52a575SXin LI DELAY(50); 4934d52a575SXin LI } 4944d52a575SXin LI if (i == NRETRY) { 4954d52a575SXin LI if_printf(sc->ifp, 4964d52a575SXin LI "write phy %d, reg %d timed out\n", phy, reg); 4974d52a575SXin LI et_miibus_readreg(dev, phy, reg); 4984d52a575SXin LI } 4994d52a575SXin LI 5004d52a575SXin LI #undef NRETRY 5014d52a575SXin LI 5024d52a575SXin LI /* Make sure that the current operation is stopped */ 5034d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, 0); 504398f1b65SPyun YongHyeon return (0); 5054d52a575SXin LI } 5064d52a575SXin LI 5074d52a575SXin LI static void 5084d52a575SXin LI et_miibus_statchg(device_t dev) 5094d52a575SXin LI { 5104d52a575SXin LI et_setmedia(device_get_softc(dev)); 5114d52a575SXin LI } 5124d52a575SXin LI 5134d52a575SXin LI static int 5144d52a575SXin LI et_ifmedia_upd_locked(struct ifnet *ifp) 5154d52a575SXin LI { 5164d52a575SXin LI struct et_softc *sc = ifp->if_softc; 5174d52a575SXin LI struct mii_data *mii = device_get_softc(sc->sc_miibus); 5184d52a575SXin LI 5194d52a575SXin LI if (mii->mii_instance != 0) { 5204d52a575SXin LI struct mii_softc *miisc; 5214d52a575SXin LI 5224d52a575SXin LI LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5234d52a575SXin LI mii_phy_reset(miisc); 5244d52a575SXin LI } 5254d52a575SXin LI mii_mediachg(mii); 5264d52a575SXin LI 527398f1b65SPyun YongHyeon return (0); 5284d52a575SXin LI } 5294d52a575SXin LI 5304d52a575SXin LI static int 5314d52a575SXin LI et_ifmedia_upd(struct ifnet *ifp) 5324d52a575SXin LI { 5334d52a575SXin LI struct et_softc *sc = ifp->if_softc; 5344d52a575SXin LI int res; 5354d52a575SXin LI 5364d52a575SXin LI ET_LOCK(sc); 5374d52a575SXin LI res = et_ifmedia_upd_locked(ifp); 5384d52a575SXin LI ET_UNLOCK(sc); 5394d52a575SXin LI 540398f1b65SPyun YongHyeon return (res); 5414d52a575SXin LI } 5424d52a575SXin LI 5434d52a575SXin LI static void 5444d52a575SXin LI et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5454d52a575SXin LI { 5464d52a575SXin LI struct et_softc *sc = ifp->if_softc; 5474d52a575SXin LI struct mii_data *mii = device_get_softc(sc->sc_miibus); 5484d52a575SXin LI 5494d52a575SXin LI mii_pollstat(mii); 5504d52a575SXin LI ifmr->ifm_active = mii->mii_media_active; 5514d52a575SXin LI ifmr->ifm_status = mii->mii_media_status; 5524d52a575SXin LI } 5534d52a575SXin LI 5544d52a575SXin LI static void 5554d52a575SXin LI et_stop(struct et_softc *sc) 5564d52a575SXin LI { 5574d52a575SXin LI struct ifnet *ifp = sc->ifp; 5584d52a575SXin LI 5594d52a575SXin LI ET_LOCK_ASSERT(sc); 5604d52a575SXin LI 5614d52a575SXin LI callout_stop(&sc->sc_tick); 5624d52a575SXin LI 5634d52a575SXin LI et_stop_rxdma(sc); 5644d52a575SXin LI et_stop_txdma(sc); 5654d52a575SXin LI 5664d52a575SXin LI et_disable_intrs(sc); 5674d52a575SXin LI 5684d52a575SXin LI et_free_tx_ring(sc); 5694d52a575SXin LI et_free_rx_ring(sc); 5704d52a575SXin LI 5714d52a575SXin LI et_reset(sc); 5724d52a575SXin LI 5734d52a575SXin LI sc->sc_tx = 0; 5744d52a575SXin LI sc->sc_tx_intr = 0; 5754d52a575SXin LI sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 5764d52a575SXin LI 5774d52a575SXin LI sc->watchdog_timer = 0; 5784d52a575SXin LI ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 5794d52a575SXin LI } 5804d52a575SXin LI 5814d52a575SXin LI static int 5828b3c6496SPyun YongHyeon et_bus_config(struct et_softc *sc) 5834d52a575SXin LI { 5844d52a575SXin LI uint32_t val, max_plsz; 5854d52a575SXin LI uint16_t ack_latency, replay_timer; 5864d52a575SXin LI 5874d52a575SXin LI /* 5884d52a575SXin LI * Test whether EEPROM is valid 5894d52a575SXin LI * NOTE: Read twice to get the correct value 5904d52a575SXin LI */ 5918b3c6496SPyun YongHyeon pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 5928b3c6496SPyun YongHyeon val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 5934d52a575SXin LI if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 5948b3c6496SPyun YongHyeon device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 595398f1b65SPyun YongHyeon return (ENXIO); 5964d52a575SXin LI } 5974d52a575SXin LI 5984d52a575SXin LI /* TODO: LED */ 5994d52a575SXin LI 6008b3c6496SPyun YongHyeon if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 6018b3c6496SPyun YongHyeon return (0); 6028b3c6496SPyun YongHyeon 6034d52a575SXin LI /* 6044d52a575SXin LI * Configure ACK latency and replay timer according to 6054d52a575SXin LI * max playload size 6064d52a575SXin LI */ 6078b3c6496SPyun YongHyeon val = pci_read_config(sc->dev, 6088b3c6496SPyun YongHyeon sc->sc_expcap + PCIR_EXPRESS_DEVICE_CAP, 4); 6098b3c6496SPyun YongHyeon max_plsz = val & PCIM_EXP_CAP_MAX_PAYLOAD; 6104d52a575SXin LI 6114d52a575SXin LI switch (max_plsz) { 6124d52a575SXin LI case ET_PCIV_DEVICE_CAPS_PLSZ_128: 6134d52a575SXin LI ack_latency = ET_PCIV_ACK_LATENCY_128; 6144d52a575SXin LI replay_timer = ET_PCIV_REPLAY_TIMER_128; 6154d52a575SXin LI break; 6164d52a575SXin LI 6174d52a575SXin LI case ET_PCIV_DEVICE_CAPS_PLSZ_256: 6184d52a575SXin LI ack_latency = ET_PCIV_ACK_LATENCY_256; 6194d52a575SXin LI replay_timer = ET_PCIV_REPLAY_TIMER_256; 6204d52a575SXin LI break; 6214d52a575SXin LI 6224d52a575SXin LI default: 6238b3c6496SPyun YongHyeon ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 6248b3c6496SPyun YongHyeon replay_timer = pci_read_config(sc->dev, 6258b3c6496SPyun YongHyeon ET_PCIR_REPLAY_TIMER, 2); 6268b3c6496SPyun YongHyeon device_printf(sc->dev, "ack latency %u, replay timer %u\n", 6274d52a575SXin LI ack_latency, replay_timer); 6284d52a575SXin LI break; 6294d52a575SXin LI } 6304d52a575SXin LI if (ack_latency != 0) { 6318b3c6496SPyun YongHyeon pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 6328b3c6496SPyun YongHyeon pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 6338b3c6496SPyun YongHyeon 2); 6344d52a575SXin LI } 6354d52a575SXin LI 6364d52a575SXin LI /* 6374d52a575SXin LI * Set L0s and L1 latency timer to 2us 6384d52a575SXin LI */ 6398b3c6496SPyun YongHyeon val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 64023263665SPyun YongHyeon val &= ~(PCIM_LINK_CAP_L0S_EXIT | PCIM_LINK_CAP_L1_EXIT); 64123263665SPyun YongHyeon /* L0s exit latency : 2us */ 64223263665SPyun YongHyeon val |= 0x00005000; 64323263665SPyun YongHyeon /* L1 exit latency : 2us */ 64423263665SPyun YongHyeon val |= 0x00028000; 6458b3c6496SPyun YongHyeon pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 6464d52a575SXin LI 6474d52a575SXin LI /* 6484d52a575SXin LI * Set max read request size to 2048 bytes 6494d52a575SXin LI */ 6508b3c6496SPyun YongHyeon val = pci_read_config(sc->dev, 6518b3c6496SPyun YongHyeon sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 6528b3c6496SPyun YongHyeon val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; 6534d52a575SXin LI val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 6548b3c6496SPyun YongHyeon pci_write_config(sc->dev, 6558b3c6496SPyun YongHyeon sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, val, 2); 6564d52a575SXin LI 657398f1b65SPyun YongHyeon return (0); 6584d52a575SXin LI } 6594d52a575SXin LI 6604d52a575SXin LI static void 6614d52a575SXin LI et_get_eaddr(device_t dev, uint8_t eaddr[]) 6624d52a575SXin LI { 6634d52a575SXin LI uint32_t val; 6644d52a575SXin LI int i; 6654d52a575SXin LI 6664d52a575SXin LI val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 6674d52a575SXin LI for (i = 0; i < 4; ++i) 6684d52a575SXin LI eaddr[i] = (val >> (8 * i)) & 0xff; 6694d52a575SXin LI 6704d52a575SXin LI val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 6714d52a575SXin LI for (; i < ETHER_ADDR_LEN; ++i) 6724d52a575SXin LI eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 6734d52a575SXin LI } 6744d52a575SXin LI 6754d52a575SXin LI static void 6764d52a575SXin LI et_reset(struct et_softc *sc) 6774d52a575SXin LI { 6784d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 6794d52a575SXin LI ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 6804d52a575SXin LI ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 6814d52a575SXin LI ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 6824d52a575SXin LI 6834d52a575SXin LI CSR_WRITE_4(sc, ET_SWRST, 6844d52a575SXin LI ET_SWRST_TXDMA | ET_SWRST_RXDMA | 6854d52a575SXin LI ET_SWRST_TXMAC | ET_SWRST_RXMAC | 6864d52a575SXin LI ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 6874d52a575SXin LI 6884d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 6894d52a575SXin LI ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 6904d52a575SXin LI ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 6914d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 6924d52a575SXin LI } 6934d52a575SXin LI 6944d52a575SXin LI static void 6954d52a575SXin LI et_disable_intrs(struct et_softc *sc) 6964d52a575SXin LI { 6974d52a575SXin LI CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 6984d52a575SXin LI } 6994d52a575SXin LI 7004d52a575SXin LI static void 7014d52a575SXin LI et_enable_intrs(struct et_softc *sc, uint32_t intrs) 7024d52a575SXin LI { 7034d52a575SXin LI CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 7044d52a575SXin LI } 7054d52a575SXin LI 7064d52a575SXin LI static int 7074d52a575SXin LI et_dma_alloc(device_t dev) 7084d52a575SXin LI { 7094d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 7104d52a575SXin LI struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 7114d52a575SXin LI struct et_txstatus_data *txsd = &sc->sc_tx_status; 7124d52a575SXin LI struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 7134d52a575SXin LI struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 7144d52a575SXin LI int i, error; 7154d52a575SXin LI 7164d52a575SXin LI /* 7174d52a575SXin LI * Create top level DMA tag 7184d52a575SXin LI */ 7194d52a575SXin LI error = bus_dma_tag_create(NULL, 1, 0, 7204d52a575SXin LI BUS_SPACE_MAXADDR_32BIT, 7214d52a575SXin LI BUS_SPACE_MAXADDR, 7224d52a575SXin LI NULL, NULL, 7234d52a575SXin LI MAXBSIZE, 7244d52a575SXin LI BUS_SPACE_UNRESTRICTED, 7254d52a575SXin LI BUS_SPACE_MAXSIZE_32BIT, 7264d52a575SXin LI 0, NULL, NULL, &sc->sc_dtag); 7274d52a575SXin LI if (error) { 7284d52a575SXin LI device_printf(dev, "can't create DMA tag\n"); 729398f1b65SPyun YongHyeon return (error); 7304d52a575SXin LI } 7314d52a575SXin LI 7324d52a575SXin LI /* 7334d52a575SXin LI * Create TX ring DMA stuffs 7344d52a575SXin LI */ 7354d52a575SXin LI error = et_dma_mem_create(dev, ET_TX_RING_SIZE, &tx_ring->tr_dtag, 7364d52a575SXin LI (void **)&tx_ring->tr_desc, 7374d52a575SXin LI &tx_ring->tr_paddr, &tx_ring->tr_dmap); 7384d52a575SXin LI if (error) { 7394d52a575SXin LI device_printf(dev, "can't create TX ring DMA stuffs\n"); 740398f1b65SPyun YongHyeon return (error); 7414d52a575SXin LI } 7424d52a575SXin LI 7434d52a575SXin LI /* 7444d52a575SXin LI * Create TX status DMA stuffs 7454d52a575SXin LI */ 7464d52a575SXin LI error = et_dma_mem_create(dev, sizeof(uint32_t), &txsd->txsd_dtag, 7474d52a575SXin LI (void **)&txsd->txsd_status, 7484d52a575SXin LI &txsd->txsd_paddr, &txsd->txsd_dmap); 7494d52a575SXin LI if (error) { 7504d52a575SXin LI device_printf(dev, "can't create TX status DMA stuffs\n"); 751398f1b65SPyun YongHyeon return (error); 7524d52a575SXin LI } 7534d52a575SXin LI 7544d52a575SXin LI /* 7554d52a575SXin LI * Create DMA stuffs for RX rings 7564d52a575SXin LI */ 7574d52a575SXin LI for (i = 0; i < ET_RX_NRING; ++i) { 7584d52a575SXin LI static const uint32_t rx_ring_posreg[ET_RX_NRING] = 7594d52a575SXin LI { ET_RX_RING0_POS, ET_RX_RING1_POS }; 7604d52a575SXin LI 7614d52a575SXin LI struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 7624d52a575SXin LI 7634d52a575SXin LI error = et_dma_mem_create(dev, ET_RX_RING_SIZE, 7644d52a575SXin LI &rx_ring->rr_dtag, 7654d52a575SXin LI (void **)&rx_ring->rr_desc, 7664d52a575SXin LI &rx_ring->rr_paddr, 7674d52a575SXin LI &rx_ring->rr_dmap); 7684d52a575SXin LI if (error) { 7694d52a575SXin LI device_printf(dev, "can't create DMA stuffs for " 7704d52a575SXin LI "the %d RX ring\n", i); 771398f1b65SPyun YongHyeon return (error); 7724d52a575SXin LI } 7734d52a575SXin LI rx_ring->rr_posreg = rx_ring_posreg[i]; 7744d52a575SXin LI } 7754d52a575SXin LI 7764d52a575SXin LI /* 7774d52a575SXin LI * Create RX stat ring DMA stuffs 7784d52a575SXin LI */ 7794d52a575SXin LI error = et_dma_mem_create(dev, ET_RXSTAT_RING_SIZE, 7804d52a575SXin LI &rxst_ring->rsr_dtag, 7814d52a575SXin LI (void **)&rxst_ring->rsr_stat, 7824d52a575SXin LI &rxst_ring->rsr_paddr, &rxst_ring->rsr_dmap); 7834d52a575SXin LI if (error) { 7844d52a575SXin LI device_printf(dev, "can't create RX stat ring DMA stuffs\n"); 785398f1b65SPyun YongHyeon return (error); 7864d52a575SXin LI } 7874d52a575SXin LI 7884d52a575SXin LI /* 7894d52a575SXin LI * Create RX status DMA stuffs 7904d52a575SXin LI */ 7914d52a575SXin LI error = et_dma_mem_create(dev, sizeof(struct et_rxstatus), 7924d52a575SXin LI &rxsd->rxsd_dtag, 7934d52a575SXin LI (void **)&rxsd->rxsd_status, 7944d52a575SXin LI &rxsd->rxsd_paddr, &rxsd->rxsd_dmap); 7954d52a575SXin LI if (error) { 7964d52a575SXin LI device_printf(dev, "can't create RX status DMA stuffs\n"); 797398f1b65SPyun YongHyeon return (error); 7984d52a575SXin LI } 7994d52a575SXin LI 8004d52a575SXin LI /* 8014d52a575SXin LI * Create mbuf DMA stuffs 8024d52a575SXin LI */ 8034d52a575SXin LI error = et_dma_mbuf_create(dev); 8044d52a575SXin LI if (error) 805398f1b65SPyun YongHyeon return (error); 8064d52a575SXin LI 807398f1b65SPyun YongHyeon return (0); 8084d52a575SXin LI } 8094d52a575SXin LI 8104d52a575SXin LI static void 8114d52a575SXin LI et_dma_free(device_t dev) 8124d52a575SXin LI { 8134d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 8144d52a575SXin LI struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 8154d52a575SXin LI struct et_txstatus_data *txsd = &sc->sc_tx_status; 8164d52a575SXin LI struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 8174d52a575SXin LI struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 8184d52a575SXin LI int i, rx_done[ET_RX_NRING]; 8194d52a575SXin LI 8204d52a575SXin LI /* 8214d52a575SXin LI * Destroy TX ring DMA stuffs 8224d52a575SXin LI */ 8234d52a575SXin LI et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc, 8244d52a575SXin LI tx_ring->tr_dmap); 8254d52a575SXin LI 8264d52a575SXin LI /* 8274d52a575SXin LI * Destroy TX status DMA stuffs 8284d52a575SXin LI */ 8294d52a575SXin LI et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status, 8304d52a575SXin LI txsd->txsd_dmap); 8314d52a575SXin LI 8324d52a575SXin LI /* 8334d52a575SXin LI * Destroy DMA stuffs for RX rings 8344d52a575SXin LI */ 8354d52a575SXin LI for (i = 0; i < ET_RX_NRING; ++i) { 8364d52a575SXin LI struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i]; 8374d52a575SXin LI 8384d52a575SXin LI et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc, 8394d52a575SXin LI rx_ring->rr_dmap); 8404d52a575SXin LI } 8414d52a575SXin LI 8424d52a575SXin LI /* 8434d52a575SXin LI * Destroy RX stat ring DMA stuffs 8444d52a575SXin LI */ 8454d52a575SXin LI et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat, 8464d52a575SXin LI rxst_ring->rsr_dmap); 8474d52a575SXin LI 8484d52a575SXin LI /* 8494d52a575SXin LI * Destroy RX status DMA stuffs 8504d52a575SXin LI */ 8514d52a575SXin LI et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status, 8524d52a575SXin LI rxsd->rxsd_dmap); 8534d52a575SXin LI 8544d52a575SXin LI /* 8554d52a575SXin LI * Destroy mbuf DMA stuffs 8564d52a575SXin LI */ 8574d52a575SXin LI for (i = 0; i < ET_RX_NRING; ++i) 8584d52a575SXin LI rx_done[i] = ET_RX_NDESC; 8594d52a575SXin LI et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done); 8604d52a575SXin LI 8614d52a575SXin LI /* 8624d52a575SXin LI * Destroy top level DMA tag 8634d52a575SXin LI */ 8644d52a575SXin LI if (sc->sc_dtag != NULL) 8654d52a575SXin LI bus_dma_tag_destroy(sc->sc_dtag); 8664d52a575SXin LI } 8674d52a575SXin LI 8684d52a575SXin LI static int 8694d52a575SXin LI et_dma_mbuf_create(device_t dev) 8704d52a575SXin LI { 8714d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 8724d52a575SXin LI struct et_txbuf_data *tbd = &sc->sc_tx_data; 8734d52a575SXin LI int i, error, rx_done[ET_RX_NRING]; 8744d52a575SXin LI 8754d52a575SXin LI /* 8764d52a575SXin LI * Create mbuf DMA tag 8774d52a575SXin LI */ 8784d52a575SXin LI error = bus_dma_tag_create(sc->sc_dtag, 1, 0, 8794d52a575SXin LI BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 8804d52a575SXin LI NULL, NULL, 8814d52a575SXin LI ET_JUMBO_FRAMELEN, ET_NSEG_MAX, 8824d52a575SXin LI BUS_SPACE_MAXSIZE_32BIT, 8834d52a575SXin LI BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_mbuf_dtag); 8844d52a575SXin LI if (error) { 8854d52a575SXin LI device_printf(dev, "can't create mbuf DMA tag\n"); 886398f1b65SPyun YongHyeon return (error); 8874d52a575SXin LI } 8884d52a575SXin LI 8894d52a575SXin LI /* 8904d52a575SXin LI * Create spare DMA map for RX mbufs 8914d52a575SXin LI */ 8924d52a575SXin LI error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, &sc->sc_mbuf_tmp_dmap); 8934d52a575SXin LI if (error) { 8944d52a575SXin LI device_printf(dev, "can't create spare mbuf DMA map\n"); 8954d52a575SXin LI bus_dma_tag_destroy(sc->sc_mbuf_dtag); 8964d52a575SXin LI sc->sc_mbuf_dtag = NULL; 897398f1b65SPyun YongHyeon return (error); 8984d52a575SXin LI } 8994d52a575SXin LI 9004d52a575SXin LI /* 9014d52a575SXin LI * Create DMA maps for RX mbufs 9024d52a575SXin LI */ 9034d52a575SXin LI bzero(rx_done, sizeof(rx_done)); 9044d52a575SXin LI for (i = 0; i < ET_RX_NRING; ++i) { 9054d52a575SXin LI struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 9064d52a575SXin LI int j; 9074d52a575SXin LI 9084d52a575SXin LI for (j = 0; j < ET_RX_NDESC; ++j) { 9094d52a575SXin LI error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, 9104d52a575SXin LI &rbd->rbd_buf[j].rb_dmap); 9114d52a575SXin LI if (error) { 9124d52a575SXin LI device_printf(dev, "can't create %d RX mbuf " 9134d52a575SXin LI "for %d RX ring\n", j, i); 9144d52a575SXin LI rx_done[i] = j; 9154d52a575SXin LI et_dma_mbuf_destroy(dev, 0, rx_done); 916398f1b65SPyun YongHyeon return (error); 9174d52a575SXin LI } 9184d52a575SXin LI } 9194d52a575SXin LI rx_done[i] = ET_RX_NDESC; 9204d52a575SXin LI 9214d52a575SXin LI rbd->rbd_softc = sc; 9224d52a575SXin LI rbd->rbd_ring = &sc->sc_rx_ring[i]; 9234d52a575SXin LI } 9244d52a575SXin LI 9254d52a575SXin LI /* 9264d52a575SXin LI * Create DMA maps for TX mbufs 9274d52a575SXin LI */ 9284d52a575SXin LI for (i = 0; i < ET_TX_NDESC; ++i) { 9294d52a575SXin LI error = bus_dmamap_create(sc->sc_mbuf_dtag, 0, 9304d52a575SXin LI &tbd->tbd_buf[i].tb_dmap); 9314d52a575SXin LI if (error) { 9324d52a575SXin LI device_printf(dev, "can't create %d TX mbuf " 9334d52a575SXin LI "DMA map\n", i); 9344d52a575SXin LI et_dma_mbuf_destroy(dev, i, rx_done); 935398f1b65SPyun YongHyeon return (error); 9364d52a575SXin LI } 9374d52a575SXin LI } 9384d52a575SXin LI 939398f1b65SPyun YongHyeon return (0); 9404d52a575SXin LI } 9414d52a575SXin LI 9424d52a575SXin LI static void 9434d52a575SXin LI et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[]) 9444d52a575SXin LI { 9454d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 9464d52a575SXin LI struct et_txbuf_data *tbd = &sc->sc_tx_data; 9474d52a575SXin LI int i; 9484d52a575SXin LI 9494d52a575SXin LI if (sc->sc_mbuf_dtag == NULL) 9504d52a575SXin LI return; 9514d52a575SXin LI 9524d52a575SXin LI /* 9534d52a575SXin LI * Destroy DMA maps for RX mbufs 9544d52a575SXin LI */ 9554d52a575SXin LI for (i = 0; i < ET_RX_NRING; ++i) { 9564d52a575SXin LI struct et_rxbuf_data *rbd = &sc->sc_rx_data[i]; 9574d52a575SXin LI int j; 9584d52a575SXin LI 9594d52a575SXin LI for (j = 0; j < rx_done[i]; ++j) { 9604d52a575SXin LI struct et_rxbuf *rb = &rbd->rbd_buf[j]; 9614d52a575SXin LI 9624d52a575SXin LI KASSERT(rb->rb_mbuf == NULL, 9634d52a575SXin LI ("RX mbuf in %d RX ring is not freed yet\n", i)); 9644d52a575SXin LI bus_dmamap_destroy(sc->sc_mbuf_dtag, rb->rb_dmap); 9654d52a575SXin LI } 9664d52a575SXin LI } 9674d52a575SXin LI 9684d52a575SXin LI /* 9694d52a575SXin LI * Destroy DMA maps for TX mbufs 9704d52a575SXin LI */ 9714d52a575SXin LI for (i = 0; i < tx_done; ++i) { 9724d52a575SXin LI struct et_txbuf *tb = &tbd->tbd_buf[i]; 9734d52a575SXin LI 9744d52a575SXin LI KASSERT(tb->tb_mbuf == NULL, ("TX mbuf is not freed yet\n")); 9754d52a575SXin LI bus_dmamap_destroy(sc->sc_mbuf_dtag, tb->tb_dmap); 9764d52a575SXin LI } 9774d52a575SXin LI 9784d52a575SXin LI /* 9794d52a575SXin LI * Destroy spare mbuf DMA map 9804d52a575SXin LI */ 9814d52a575SXin LI bus_dmamap_destroy(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap); 9824d52a575SXin LI 9834d52a575SXin LI /* 9844d52a575SXin LI * Destroy mbuf DMA tag 9854d52a575SXin LI */ 9864d52a575SXin LI bus_dma_tag_destroy(sc->sc_mbuf_dtag); 9874d52a575SXin LI sc->sc_mbuf_dtag = NULL; 9884d52a575SXin LI } 9894d52a575SXin LI 9904d52a575SXin LI static int 9914d52a575SXin LI et_dma_mem_create(device_t dev, bus_size_t size, bus_dma_tag_t *dtag, 9924d52a575SXin LI void **addr, bus_addr_t *paddr, bus_dmamap_t *dmap) 9934d52a575SXin LI { 9944d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 9954d52a575SXin LI int error; 9964d52a575SXin LI 9974d52a575SXin LI error = bus_dma_tag_create(sc->sc_dtag, ET_ALIGN, 0, 9984d52a575SXin LI BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 9994d52a575SXin LI NULL, NULL, 10004d52a575SXin LI size, 1, BUS_SPACE_MAXSIZE_32BIT, 10014d52a575SXin LI 0, NULL, NULL, dtag); 10024d52a575SXin LI if (error) { 10034d52a575SXin LI device_printf(dev, "can't create DMA tag\n"); 1004398f1b65SPyun YongHyeon return (error); 10054d52a575SXin LI } 10064d52a575SXin LI 10074d52a575SXin LI error = bus_dmamem_alloc(*dtag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO, 10084d52a575SXin LI dmap); 10094d52a575SXin LI if (error) { 10104d52a575SXin LI device_printf(dev, "can't allocate DMA mem\n"); 10114d52a575SXin LI bus_dma_tag_destroy(*dtag); 10124d52a575SXin LI *dtag = NULL; 1013398f1b65SPyun YongHyeon return (error); 10144d52a575SXin LI } 10154d52a575SXin LI 10164d52a575SXin LI error = bus_dmamap_load(*dtag, *dmap, *addr, size, 10174d52a575SXin LI et_dma_ring_addr, paddr, BUS_DMA_WAITOK); 10184d52a575SXin LI if (error) { 10194d52a575SXin LI device_printf(dev, "can't load DMA mem\n"); 10204d52a575SXin LI bus_dmamem_free(*dtag, *addr, *dmap); 10214d52a575SXin LI bus_dma_tag_destroy(*dtag); 10224d52a575SXin LI *dtag = NULL; 1023398f1b65SPyun YongHyeon return (error); 10244d52a575SXin LI } 1025398f1b65SPyun YongHyeon return (0); 10264d52a575SXin LI } 10274d52a575SXin LI 10284d52a575SXin LI static void 10294d52a575SXin LI et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap) 10304d52a575SXin LI { 10314d52a575SXin LI if (dtag != NULL) { 10324d52a575SXin LI bus_dmamap_unload(dtag, dmap); 10334d52a575SXin LI bus_dmamem_free(dtag, addr, dmap); 10344d52a575SXin LI bus_dma_tag_destroy(dtag); 10354d52a575SXin LI } 10364d52a575SXin LI } 10374d52a575SXin LI 10384d52a575SXin LI static void 10394d52a575SXin LI et_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 10404d52a575SXin LI { 10414d52a575SXin LI KASSERT(nseg == 1, ("too many segments\n")); 10424d52a575SXin LI *((bus_addr_t *)arg) = seg->ds_addr; 10434d52a575SXin LI } 10444d52a575SXin LI 10454d52a575SXin LI static void 10464d52a575SXin LI et_chip_attach(struct et_softc *sc) 10474d52a575SXin LI { 10484d52a575SXin LI uint32_t val; 10494d52a575SXin LI 10504d52a575SXin LI /* 10514d52a575SXin LI * Perform minimal initialization 10524d52a575SXin LI */ 10534d52a575SXin LI 10544d52a575SXin LI /* Disable loopback */ 10554d52a575SXin LI CSR_WRITE_4(sc, ET_LOOPBACK, 0); 10564d52a575SXin LI 10574d52a575SXin LI /* Reset MAC */ 10584d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 10594d52a575SXin LI ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 10604d52a575SXin LI ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 10614d52a575SXin LI ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 10624d52a575SXin LI 10634d52a575SXin LI /* 10644d52a575SXin LI * Setup half duplex mode 10654d52a575SXin LI */ 106623263665SPyun YongHyeon val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 106723263665SPyun YongHyeon (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 106823263665SPyun YongHyeon (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 10694d52a575SXin LI ET_MAC_HDX_EXC_DEFER; 10704d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_HDX, val); 10714d52a575SXin LI 10724d52a575SXin LI /* Clear MAC control */ 10734d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 10744d52a575SXin LI 10754d52a575SXin LI /* Reset MII */ 10764d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 10774d52a575SXin LI 10784d52a575SXin LI /* Bring MAC out of reset state */ 10794d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 10804d52a575SXin LI 10814d52a575SXin LI /* Enable memory controllers */ 10824d52a575SXin LI CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 10834d52a575SXin LI } 10844d52a575SXin LI 10854d52a575SXin LI static void 10864d52a575SXin LI et_intr(void *xsc) 10874d52a575SXin LI { 10884d52a575SXin LI struct et_softc *sc = xsc; 10894d52a575SXin LI struct ifnet *ifp; 10904d52a575SXin LI uint32_t intrs; 10914d52a575SXin LI 10924d52a575SXin LI ET_LOCK(sc); 10934d52a575SXin LI ifp = sc->ifp; 10944d52a575SXin LI if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 10954d52a575SXin LI ET_UNLOCK(sc); 10964d52a575SXin LI return; 10974d52a575SXin LI } 10984d52a575SXin LI 10994d52a575SXin LI et_disable_intrs(sc); 11004d52a575SXin LI 11014d52a575SXin LI intrs = CSR_READ_4(sc, ET_INTR_STATUS); 11024d52a575SXin LI intrs &= ET_INTRS; 11034d52a575SXin LI if (intrs == 0) /* Not interested */ 11044d52a575SXin LI goto back; 11054d52a575SXin LI 11064d52a575SXin LI if (intrs & ET_INTR_RXEOF) 11074d52a575SXin LI et_rxeof(sc); 11084d52a575SXin LI if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 11094d52a575SXin LI et_txeof(sc); 11104d52a575SXin LI if (intrs & ET_INTR_TIMER) 11114d52a575SXin LI CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 11124d52a575SXin LI back: 11134d52a575SXin LI et_enable_intrs(sc, ET_INTRS); 11144d52a575SXin LI ET_UNLOCK(sc); 11154d52a575SXin LI } 11164d52a575SXin LI 11174d52a575SXin LI static void 11184d52a575SXin LI et_init_locked(struct et_softc *sc) 11194d52a575SXin LI { 11204d52a575SXin LI struct ifnet *ifp = sc->ifp; 11214d52a575SXin LI const struct et_bsize *arr; 11224d52a575SXin LI int error, i; 11234d52a575SXin LI 11244d52a575SXin LI ET_LOCK_ASSERT(sc); 11254d52a575SXin LI 11264d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) 11274d52a575SXin LI return; 11284d52a575SXin LI 11294d52a575SXin LI et_stop(sc); 11304d52a575SXin LI 11314d52a575SXin LI arr = et_bufsize_std; 11324d52a575SXin LI for (i = 0; i < ET_RX_NRING; ++i) { 11334d52a575SXin LI sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize; 11344d52a575SXin LI sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf; 11354d52a575SXin LI } 11364d52a575SXin LI 11374d52a575SXin LI error = et_init_tx_ring(sc); 11384d52a575SXin LI if (error) 11394d52a575SXin LI goto back; 11404d52a575SXin LI 11414d52a575SXin LI error = et_init_rx_ring(sc); 11424d52a575SXin LI if (error) 11434d52a575SXin LI goto back; 11444d52a575SXin LI 11454d52a575SXin LI error = et_chip_init(sc); 11464d52a575SXin LI if (error) 11474d52a575SXin LI goto back; 11484d52a575SXin LI 11494d52a575SXin LI error = et_enable_txrx(sc, 1); 11504d52a575SXin LI if (error) 11514d52a575SXin LI goto back; 11524d52a575SXin LI 11534d52a575SXin LI et_enable_intrs(sc, ET_INTRS); 11544d52a575SXin LI 11554d52a575SXin LI callout_reset(&sc->sc_tick, hz, et_tick, sc); 11564d52a575SXin LI 11574d52a575SXin LI CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 11584d52a575SXin LI 11594d52a575SXin LI ifp->if_drv_flags |= IFF_DRV_RUNNING; 11604d52a575SXin LI ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 11614d52a575SXin LI back: 11624d52a575SXin LI if (error) 11634d52a575SXin LI et_stop(sc); 11644d52a575SXin LI } 11654d52a575SXin LI 11664d52a575SXin LI static void 11674d52a575SXin LI et_init(void *xsc) 11684d52a575SXin LI { 11694d52a575SXin LI struct et_softc *sc = xsc; 11704d52a575SXin LI 11714d52a575SXin LI ET_LOCK(sc); 11724d52a575SXin LI et_init_locked(sc); 11734d52a575SXin LI ET_UNLOCK(sc); 11744d52a575SXin LI } 11754d52a575SXin LI 11764d52a575SXin LI static int 11774d52a575SXin LI et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 11784d52a575SXin LI { 11794d52a575SXin LI struct et_softc *sc = ifp->if_softc; 11804d52a575SXin LI struct mii_data *mii = device_get_softc(sc->sc_miibus); 11814d52a575SXin LI struct ifreq *ifr = (struct ifreq *)data; 11829955274cSPyun YongHyeon int error = 0, mask, max_framelen; 11834d52a575SXin LI 11844d52a575SXin LI /* XXX LOCKSUSED */ 11854d52a575SXin LI switch (cmd) { 11864d52a575SXin LI case SIOCSIFFLAGS: 11874d52a575SXin LI ET_LOCK(sc); 11884d52a575SXin LI if (ifp->if_flags & IFF_UP) { 11894d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 11904d52a575SXin LI if ((ifp->if_flags ^ sc->sc_if_flags) & 11914d52a575SXin LI (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 11924d52a575SXin LI et_setmulti(sc); 11934d52a575SXin LI } else { 11944d52a575SXin LI et_init_locked(sc); 11954d52a575SXin LI } 11964d52a575SXin LI } else { 11974d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) 11984d52a575SXin LI et_stop(sc); 11994d52a575SXin LI } 12004d52a575SXin LI sc->sc_if_flags = ifp->if_flags; 12014d52a575SXin LI ET_UNLOCK(sc); 12024d52a575SXin LI break; 12034d52a575SXin LI 12044d52a575SXin LI case SIOCSIFMEDIA: 12054d52a575SXin LI case SIOCGIFMEDIA: 12064d52a575SXin LI error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 12074d52a575SXin LI break; 12084d52a575SXin LI 12094d52a575SXin LI case SIOCADDMULTI: 12104d52a575SXin LI case SIOCDELMULTI: 12114d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 12124d52a575SXin LI ET_LOCK(sc); 12134d52a575SXin LI et_setmulti(sc); 12144d52a575SXin LI ET_UNLOCK(sc); 12154d52a575SXin LI error = 0; 12164d52a575SXin LI } 12174d52a575SXin LI break; 12184d52a575SXin LI 12194d52a575SXin LI case SIOCSIFMTU: 12204d52a575SXin LI #if 0 12214d52a575SXin LI if (sc->sc_flags & ET_FLAG_JUMBO) 12224d52a575SXin LI max_framelen = ET_JUMBO_FRAMELEN; 12234d52a575SXin LI else 12244d52a575SXin LI #endif 12254d52a575SXin LI max_framelen = MCLBYTES - 1; 12264d52a575SXin LI 12274d52a575SXin LI if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 12284d52a575SXin LI error = EOPNOTSUPP; 12294d52a575SXin LI break; 12304d52a575SXin LI } 12314d52a575SXin LI 12324d52a575SXin LI if (ifp->if_mtu != ifr->ifr_mtu) { 12334d52a575SXin LI ifp->if_mtu = ifr->ifr_mtu; 12344d52a575SXin LI ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 12354d52a575SXin LI et_init(sc); 12364d52a575SXin LI } 12374d52a575SXin LI break; 12384d52a575SXin LI 12399955274cSPyun YongHyeon case SIOCSIFCAP: 12409955274cSPyun YongHyeon ET_LOCK(sc); 12419955274cSPyun YongHyeon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 12429955274cSPyun YongHyeon if ((mask & IFCAP_TXCSUM) != 0 && 12439955274cSPyun YongHyeon (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 12449955274cSPyun YongHyeon ifp->if_capenable ^= IFCAP_TXCSUM; 12459955274cSPyun YongHyeon if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 12469955274cSPyun YongHyeon ifp->if_hwassist |= ET_CSUM_FEATURES; 12479955274cSPyun YongHyeon else 12489955274cSPyun YongHyeon ifp->if_hwassist &= ~ET_CSUM_FEATURES; 12499955274cSPyun YongHyeon } 12509955274cSPyun YongHyeon ET_UNLOCK(sc); 12519955274cSPyun YongHyeon break; 12529955274cSPyun YongHyeon 12534d52a575SXin LI default: 12544d52a575SXin LI error = ether_ioctl(ifp, cmd, data); 12554d52a575SXin LI break; 12564d52a575SXin LI } 1257398f1b65SPyun YongHyeon return (error); 12584d52a575SXin LI } 12594d52a575SXin LI 12604d52a575SXin LI static void 12614d52a575SXin LI et_start_locked(struct ifnet *ifp) 12624d52a575SXin LI { 12634d52a575SXin LI struct et_softc *sc = ifp->if_softc; 12644d52a575SXin LI struct et_txbuf_data *tbd; 12654d52a575SXin LI int trans; 12664d52a575SXin LI 12674d52a575SXin LI ET_LOCK_ASSERT(sc); 12684d52a575SXin LI tbd = &sc->sc_tx_data; 12694d52a575SXin LI 12704d52a575SXin LI if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 12714d52a575SXin LI return; 12724d52a575SXin LI 12734d52a575SXin LI if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) 12744d52a575SXin LI return; 12754d52a575SXin LI 12764d52a575SXin LI trans = 0; 12774d52a575SXin LI for (;;) { 12784d52a575SXin LI struct mbuf *m; 12794d52a575SXin LI 12804d52a575SXin LI if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) { 12814d52a575SXin LI ifp->if_drv_flags |= IFF_DRV_OACTIVE; 12824d52a575SXin LI break; 12834d52a575SXin LI } 12844d52a575SXin LI 12854d52a575SXin LI IFQ_DEQUEUE(&ifp->if_snd, m); 12864d52a575SXin LI if (m == NULL) 12874d52a575SXin LI break; 12884d52a575SXin LI 12894d52a575SXin LI if (et_encap(sc, &m)) { 12904d52a575SXin LI ifp->if_oerrors++; 12914d52a575SXin LI ifp->if_drv_flags |= IFF_DRV_OACTIVE; 12924d52a575SXin LI break; 12934d52a575SXin LI } 12944d52a575SXin LI trans = 1; 12954d52a575SXin LI 12964d52a575SXin LI BPF_MTAP(ifp, m); 12974d52a575SXin LI } 12984d52a575SXin LI 12994d52a575SXin LI if (trans) 13004d52a575SXin LI sc->watchdog_timer = 5; 13014d52a575SXin LI } 13024d52a575SXin LI 13034d52a575SXin LI static void 13044d52a575SXin LI et_start(struct ifnet *ifp) 13054d52a575SXin LI { 13064d52a575SXin LI struct et_softc *sc = ifp->if_softc; 13074d52a575SXin LI 13084d52a575SXin LI ET_LOCK(sc); 13094d52a575SXin LI et_start_locked(ifp); 13104d52a575SXin LI ET_UNLOCK(sc); 13114d52a575SXin LI } 13124d52a575SXin LI 13134d52a575SXin LI static void 13144d52a575SXin LI et_watchdog(struct et_softc *sc) 13154d52a575SXin LI { 13164d52a575SXin LI ET_LOCK_ASSERT(sc); 13174d52a575SXin LI 13184d52a575SXin LI if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 13194d52a575SXin LI return; 13204d52a575SXin LI 13214d52a575SXin LI if_printf(sc->ifp, "watchdog timed out\n"); 13224d52a575SXin LI 1323744ec7f2SPyun YongHyeon sc->ifp->if_oerrors++; 1324744ec7f2SPyun YongHyeon sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 13254d52a575SXin LI et_init_locked(sc); 13264d52a575SXin LI et_start_locked(sc->ifp); 13274d52a575SXin LI } 13284d52a575SXin LI 13294d52a575SXin LI static int 13304d52a575SXin LI et_stop_rxdma(struct et_softc *sc) 13314d52a575SXin LI { 13324d52a575SXin LI CSR_WRITE_4(sc, ET_RXDMA_CTRL, 13334d52a575SXin LI ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 13344d52a575SXin LI 13354d52a575SXin LI DELAY(5); 13364d52a575SXin LI if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 13374d52a575SXin LI if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1338398f1b65SPyun YongHyeon return (ETIMEDOUT); 13394d52a575SXin LI } 1340398f1b65SPyun YongHyeon return (0); 13414d52a575SXin LI } 13424d52a575SXin LI 13434d52a575SXin LI static int 13444d52a575SXin LI et_stop_txdma(struct et_softc *sc) 13454d52a575SXin LI { 13464d52a575SXin LI CSR_WRITE_4(sc, ET_TXDMA_CTRL, 13474d52a575SXin LI ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1348398f1b65SPyun YongHyeon return (0); 13494d52a575SXin LI } 13504d52a575SXin LI 13514d52a575SXin LI static void 13524d52a575SXin LI et_free_tx_ring(struct et_softc *sc) 13534d52a575SXin LI { 13544d52a575SXin LI struct et_txbuf_data *tbd = &sc->sc_tx_data; 13554d52a575SXin LI struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 13564d52a575SXin LI int i; 13574d52a575SXin LI 13584d52a575SXin LI for (i = 0; i < ET_TX_NDESC; ++i) { 13594d52a575SXin LI struct et_txbuf *tb = &tbd->tbd_buf[i]; 13604d52a575SXin LI 13614d52a575SXin LI if (tb->tb_mbuf != NULL) { 13624d52a575SXin LI bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 13634d52a575SXin LI m_freem(tb->tb_mbuf); 13644d52a575SXin LI tb->tb_mbuf = NULL; 13654d52a575SXin LI } 13664d52a575SXin LI } 13674d52a575SXin LI 13684d52a575SXin LI bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 13694d52a575SXin LI bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 13704d52a575SXin LI BUS_DMASYNC_PREWRITE); 13714d52a575SXin LI } 13724d52a575SXin LI 13734d52a575SXin LI static void 13744d52a575SXin LI et_free_rx_ring(struct et_softc *sc) 13754d52a575SXin LI { 13764d52a575SXin LI int n; 13774d52a575SXin LI 13784d52a575SXin LI for (n = 0; n < ET_RX_NRING; ++n) { 13794d52a575SXin LI struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 13804d52a575SXin LI struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n]; 13814d52a575SXin LI int i; 13824d52a575SXin LI 13834d52a575SXin LI for (i = 0; i < ET_RX_NDESC; ++i) { 13844d52a575SXin LI struct et_rxbuf *rb = &rbd->rbd_buf[i]; 13854d52a575SXin LI 13864d52a575SXin LI if (rb->rb_mbuf != NULL) { 1387b4b98624SXin LI bus_dmamap_unload(sc->sc_mbuf_dtag, 1388b4b98624SXin LI rb->rb_dmap); 13894d52a575SXin LI m_freem(rb->rb_mbuf); 13904d52a575SXin LI rb->rb_mbuf = NULL; 13914d52a575SXin LI } 13924d52a575SXin LI } 13934d52a575SXin LI 13944d52a575SXin LI bzero(rx_ring->rr_desc, ET_RX_RING_SIZE); 13954d52a575SXin LI bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap, 13964d52a575SXin LI BUS_DMASYNC_PREWRITE); 13974d52a575SXin LI } 13984d52a575SXin LI } 13994d52a575SXin LI 14004d52a575SXin LI static void 14014d52a575SXin LI et_setmulti(struct et_softc *sc) 14024d52a575SXin LI { 14034d52a575SXin LI struct ifnet *ifp; 14044d52a575SXin LI uint32_t hash[4] = { 0, 0, 0, 0 }; 14054d52a575SXin LI uint32_t rxmac_ctrl, pktfilt; 14064d52a575SXin LI struct ifmultiaddr *ifma; 14074d52a575SXin LI int i, count; 14084d52a575SXin LI 14094d52a575SXin LI ET_LOCK_ASSERT(sc); 14104d52a575SXin LI ifp = sc->ifp; 14114d52a575SXin LI 14124d52a575SXin LI pktfilt = CSR_READ_4(sc, ET_PKTFILT); 14134d52a575SXin LI rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 14144d52a575SXin LI 14154d52a575SXin LI pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 14164d52a575SXin LI if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 14174d52a575SXin LI rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 14184d52a575SXin LI goto back; 14194d52a575SXin LI } 14204d52a575SXin LI 14214d52a575SXin LI count = 0; 1422eb956cd0SRobert Watson if_maddr_rlock(ifp); 14234d52a575SXin LI TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 14244d52a575SXin LI uint32_t *hp, h; 14254d52a575SXin LI 14264d52a575SXin LI if (ifma->ifma_addr->sa_family != AF_LINK) 14274d52a575SXin LI continue; 14284d52a575SXin LI 14294d52a575SXin LI h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 14304d52a575SXin LI ifma->ifma_addr), ETHER_ADDR_LEN); 14314d52a575SXin LI h = (h & 0x3f800000) >> 23; 14324d52a575SXin LI 14334d52a575SXin LI hp = &hash[0]; 14344d52a575SXin LI if (h >= 32 && h < 64) { 14354d52a575SXin LI h -= 32; 14364d52a575SXin LI hp = &hash[1]; 14374d52a575SXin LI } else if (h >= 64 && h < 96) { 14384d52a575SXin LI h -= 64; 14394d52a575SXin LI hp = &hash[2]; 14404d52a575SXin LI } else if (h >= 96) { 14414d52a575SXin LI h -= 96; 14424d52a575SXin LI hp = &hash[3]; 14434d52a575SXin LI } 14444d52a575SXin LI *hp |= (1 << h); 14454d52a575SXin LI 14464d52a575SXin LI ++count; 14474d52a575SXin LI } 1448eb956cd0SRobert Watson if_maddr_runlock(ifp); 14494d52a575SXin LI 14504d52a575SXin LI for (i = 0; i < 4; ++i) 14514d52a575SXin LI CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 14524d52a575SXin LI 14534d52a575SXin LI if (count > 0) 14544d52a575SXin LI pktfilt |= ET_PKTFILT_MCAST; 14554d52a575SXin LI rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 14564d52a575SXin LI back: 14574d52a575SXin LI CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 14584d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 14594d52a575SXin LI } 14604d52a575SXin LI 14614d52a575SXin LI static int 14624d52a575SXin LI et_chip_init(struct et_softc *sc) 14634d52a575SXin LI { 14644d52a575SXin LI struct ifnet *ifp = sc->ifp; 14654d52a575SXin LI uint32_t rxq_end; 14664d52a575SXin LI int error, frame_len, rxmem_size; 14674d52a575SXin LI 14684d52a575SXin LI /* 14694d52a575SXin LI * Split 16Kbytes internal memory between TX and RX 14704d52a575SXin LI * according to frame length. 14714d52a575SXin LI */ 14724d52a575SXin LI frame_len = ET_FRAMELEN(ifp->if_mtu); 14734d52a575SXin LI if (frame_len < 2048) { 14744d52a575SXin LI rxmem_size = ET_MEM_RXSIZE_DEFAULT; 14754d52a575SXin LI } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 14764d52a575SXin LI rxmem_size = ET_MEM_SIZE / 2; 14774d52a575SXin LI } else { 14784d52a575SXin LI rxmem_size = ET_MEM_SIZE - 14794d52a575SXin LI roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 14804d52a575SXin LI } 14814d52a575SXin LI rxq_end = ET_QUEUE_ADDR(rxmem_size); 14824d52a575SXin LI 14834d52a575SXin LI CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 14844d52a575SXin LI CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 14854d52a575SXin LI CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 14864d52a575SXin LI CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 14874d52a575SXin LI 14884d52a575SXin LI /* No loopback */ 14894d52a575SXin LI CSR_WRITE_4(sc, ET_LOOPBACK, 0); 14904d52a575SXin LI 14914d52a575SXin LI /* Clear MSI configure */ 1492cc3c3b4eSPyun YongHyeon if ((sc->sc_flags & ET_FLAG_MSI) == 0) 14934d52a575SXin LI CSR_WRITE_4(sc, ET_MSI_CFG, 0); 14944d52a575SXin LI 14954d52a575SXin LI /* Disable timer */ 14964d52a575SXin LI CSR_WRITE_4(sc, ET_TIMER, 0); 14974d52a575SXin LI 14984d52a575SXin LI /* Initialize MAC */ 14994d52a575SXin LI et_init_mac(sc); 15004d52a575SXin LI 15014d52a575SXin LI /* Enable memory controllers */ 15024d52a575SXin LI CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 15034d52a575SXin LI 15044d52a575SXin LI /* Initialize RX MAC */ 15054d52a575SXin LI et_init_rxmac(sc); 15064d52a575SXin LI 15074d52a575SXin LI /* Initialize TX MAC */ 15084d52a575SXin LI et_init_txmac(sc); 15094d52a575SXin LI 15104d52a575SXin LI /* Initialize RX DMA engine */ 15114d52a575SXin LI error = et_init_rxdma(sc); 15124d52a575SXin LI if (error) 1513398f1b65SPyun YongHyeon return (error); 15144d52a575SXin LI 15154d52a575SXin LI /* Initialize TX DMA engine */ 15164d52a575SXin LI error = et_init_txdma(sc); 15174d52a575SXin LI if (error) 1518398f1b65SPyun YongHyeon return (error); 15194d52a575SXin LI 1520398f1b65SPyun YongHyeon return (0); 15214d52a575SXin LI } 15224d52a575SXin LI 15234d52a575SXin LI static int 15244d52a575SXin LI et_init_tx_ring(struct et_softc *sc) 15254d52a575SXin LI { 15264d52a575SXin LI struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 15274d52a575SXin LI struct et_txstatus_data *txsd = &sc->sc_tx_status; 15284d52a575SXin LI struct et_txbuf_data *tbd = &sc->sc_tx_data; 15294d52a575SXin LI 15304d52a575SXin LI bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 15314d52a575SXin LI bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 15324d52a575SXin LI BUS_DMASYNC_PREWRITE); 15334d52a575SXin LI 15344d52a575SXin LI tbd->tbd_start_index = 0; 15354d52a575SXin LI tbd->tbd_start_wrap = 0; 15364d52a575SXin LI tbd->tbd_used = 0; 15374d52a575SXin LI 15384d52a575SXin LI bzero(txsd->txsd_status, sizeof(uint32_t)); 15394d52a575SXin LI bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 15404d52a575SXin LI BUS_DMASYNC_PREWRITE); 1541398f1b65SPyun YongHyeon return (0); 15424d52a575SXin LI } 15434d52a575SXin LI 15444d52a575SXin LI static int 15454d52a575SXin LI et_init_rx_ring(struct et_softc *sc) 15464d52a575SXin LI { 15474d52a575SXin LI struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 15484d52a575SXin LI struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 15494d52a575SXin LI int n; 15504d52a575SXin LI 15514d52a575SXin LI for (n = 0; n < ET_RX_NRING; ++n) { 15524d52a575SXin LI struct et_rxbuf_data *rbd = &sc->sc_rx_data[n]; 15534d52a575SXin LI int i, error; 15544d52a575SXin LI 15554d52a575SXin LI for (i = 0; i < ET_RX_NDESC; ++i) { 15564d52a575SXin LI error = rbd->rbd_newbuf(rbd, i, 1); 15574d52a575SXin LI if (error) { 15584d52a575SXin LI if_printf(sc->ifp, "%d ring %d buf, " 15594d52a575SXin LI "newbuf failed: %d\n", n, i, error); 1560398f1b65SPyun YongHyeon return (error); 15614d52a575SXin LI } 15624d52a575SXin LI } 15634d52a575SXin LI } 15644d52a575SXin LI 15654d52a575SXin LI bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 15664d52a575SXin LI bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 15674d52a575SXin LI BUS_DMASYNC_PREWRITE); 15684d52a575SXin LI 15694d52a575SXin LI bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 15704d52a575SXin LI bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 15714d52a575SXin LI BUS_DMASYNC_PREWRITE); 15724d52a575SXin LI 1573398f1b65SPyun YongHyeon return (0); 15744d52a575SXin LI } 15754d52a575SXin LI 15764d52a575SXin LI static void 15774d52a575SXin LI et_dma_buf_addr(void *xctx, bus_dma_segment_t *segs, int nsegs, 15784d52a575SXin LI bus_size_t mapsz __unused, int error) 15794d52a575SXin LI { 15804d52a575SXin LI struct et_dmamap_ctx *ctx = xctx; 15814d52a575SXin LI int i; 15824d52a575SXin LI 15834d52a575SXin LI if (error) 15844d52a575SXin LI return; 15854d52a575SXin LI 15864d52a575SXin LI if (nsegs > ctx->nsegs) { 15874d52a575SXin LI ctx->nsegs = 0; 15884d52a575SXin LI return; 15894d52a575SXin LI } 15904d52a575SXin LI 15914d52a575SXin LI ctx->nsegs = nsegs; 15924d52a575SXin LI for (i = 0; i < nsegs; ++i) 15934d52a575SXin LI ctx->segs[i] = segs[i]; 15944d52a575SXin LI } 15954d52a575SXin LI 15964d52a575SXin LI static int 15974d52a575SXin LI et_init_rxdma(struct et_softc *sc) 15984d52a575SXin LI { 15994d52a575SXin LI struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 16004d52a575SXin LI struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 16014d52a575SXin LI struct et_rxdesc_ring *rx_ring; 16024d52a575SXin LI int error; 16034d52a575SXin LI 16044d52a575SXin LI error = et_stop_rxdma(sc); 16054d52a575SXin LI if (error) { 16064d52a575SXin LI if_printf(sc->ifp, "can't init RX DMA engine\n"); 1607398f1b65SPyun YongHyeon return (error); 16084d52a575SXin LI } 16094d52a575SXin LI 16104d52a575SXin LI /* 16114d52a575SXin LI * Install RX status 16124d52a575SXin LI */ 16134d52a575SXin LI CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 16144d52a575SXin LI CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 16154d52a575SXin LI 16164d52a575SXin LI /* 16174d52a575SXin LI * Install RX stat ring 16184d52a575SXin LI */ 16194d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 16204d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 16214d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 16224d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 16234d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 16244d52a575SXin LI 16254d52a575SXin LI /* Match ET_RXSTAT_POS */ 16264d52a575SXin LI rxst_ring->rsr_index = 0; 16274d52a575SXin LI rxst_ring->rsr_wrap = 0; 16284d52a575SXin LI 16294d52a575SXin LI /* 16304d52a575SXin LI * Install the 2nd RX descriptor ring 16314d52a575SXin LI */ 16324d52a575SXin LI rx_ring = &sc->sc_rx_ring[1]; 16334d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 16344d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 16354d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 16364d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 16374d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 16384d52a575SXin LI 16394d52a575SXin LI /* Match ET_RX_RING1_POS */ 16404d52a575SXin LI rx_ring->rr_index = 0; 16414d52a575SXin LI rx_ring->rr_wrap = 1; 16424d52a575SXin LI 16434d52a575SXin LI /* 16444d52a575SXin LI * Install the 1st RX descriptor ring 16454d52a575SXin LI */ 16464d52a575SXin LI rx_ring = &sc->sc_rx_ring[0]; 16474d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 16484d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 16494d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 16504d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 16514d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 16524d52a575SXin LI 16534d52a575SXin LI /* Match ET_RX_RING0_POS */ 16544d52a575SXin LI rx_ring->rr_index = 0; 16554d52a575SXin LI rx_ring->rr_wrap = 1; 16564d52a575SXin LI 16574d52a575SXin LI /* 16584d52a575SXin LI * RX intr moderation 16594d52a575SXin LI */ 16604d52a575SXin LI CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 16614d52a575SXin LI CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 16624d52a575SXin LI 1663398f1b65SPyun YongHyeon return (0); 16644d52a575SXin LI } 16654d52a575SXin LI 16664d52a575SXin LI static int 16674d52a575SXin LI et_init_txdma(struct et_softc *sc) 16684d52a575SXin LI { 16694d52a575SXin LI struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 16704d52a575SXin LI struct et_txstatus_data *txsd = &sc->sc_tx_status; 16714d52a575SXin LI int error; 16724d52a575SXin LI 16734d52a575SXin LI error = et_stop_txdma(sc); 16744d52a575SXin LI if (error) { 16754d52a575SXin LI if_printf(sc->ifp, "can't init TX DMA engine\n"); 1676398f1b65SPyun YongHyeon return (error); 16774d52a575SXin LI } 16784d52a575SXin LI 16794d52a575SXin LI /* 16804d52a575SXin LI * Install TX descriptor ring 16814d52a575SXin LI */ 16824d52a575SXin LI CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 16834d52a575SXin LI CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 16844d52a575SXin LI CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 16854d52a575SXin LI 16864d52a575SXin LI /* 16874d52a575SXin LI * Install TX status 16884d52a575SXin LI */ 16894d52a575SXin LI CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 16904d52a575SXin LI CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 16914d52a575SXin LI 16924d52a575SXin LI CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 16934d52a575SXin LI 16944d52a575SXin LI /* Match ET_TX_READY_POS */ 16954d52a575SXin LI tx_ring->tr_ready_index = 0; 16964d52a575SXin LI tx_ring->tr_ready_wrap = 0; 16974d52a575SXin LI 1698398f1b65SPyun YongHyeon return (0); 16994d52a575SXin LI } 17004d52a575SXin LI 17014d52a575SXin LI static void 17024d52a575SXin LI et_init_mac(struct et_softc *sc) 17034d52a575SXin LI { 17044d52a575SXin LI struct ifnet *ifp = sc->ifp; 17054d52a575SXin LI const uint8_t *eaddr = IF_LLADDR(ifp); 17064d52a575SXin LI uint32_t val; 17074d52a575SXin LI 17084d52a575SXin LI /* Reset MAC */ 17094d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 17104d52a575SXin LI ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 17114d52a575SXin LI ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 17124d52a575SXin LI ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 17134d52a575SXin LI 17144d52a575SXin LI /* 17154d52a575SXin LI * Setup inter packet gap 17164d52a575SXin LI */ 171723263665SPyun YongHyeon val = (56 << ET_IPG_NONB2B_1_SHIFT) | 171823263665SPyun YongHyeon (88 << ET_IPG_NONB2B_2_SHIFT) | 171923263665SPyun YongHyeon (80 << ET_IPG_MINIFG_SHIFT) | 172023263665SPyun YongHyeon (96 << ET_IPG_B2B_SHIFT); 17214d52a575SXin LI CSR_WRITE_4(sc, ET_IPG, val); 17224d52a575SXin LI 17234d52a575SXin LI /* 17244d52a575SXin LI * Setup half duplex mode 17254d52a575SXin LI */ 172623263665SPyun YongHyeon val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 172723263665SPyun YongHyeon (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 172823263665SPyun YongHyeon (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 17294d52a575SXin LI ET_MAC_HDX_EXC_DEFER; 17304d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_HDX, val); 17314d52a575SXin LI 17324d52a575SXin LI /* Clear MAC control */ 17334d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 17344d52a575SXin LI 17354d52a575SXin LI /* Reset MII */ 17364d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 17374d52a575SXin LI 17384d52a575SXin LI /* 17394d52a575SXin LI * Set MAC address 17404d52a575SXin LI */ 17414d52a575SXin LI val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 17424d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 17434d52a575SXin LI val = (eaddr[0] << 16) | (eaddr[1] << 24); 17444d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 17454d52a575SXin LI 17464d52a575SXin LI /* Set max frame length */ 17474d52a575SXin LI CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 17484d52a575SXin LI 17494d52a575SXin LI /* Bring MAC out of reset state */ 17504d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 17514d52a575SXin LI } 17524d52a575SXin LI 17534d52a575SXin LI static void 17544d52a575SXin LI et_init_rxmac(struct et_softc *sc) 17554d52a575SXin LI { 17564d52a575SXin LI struct ifnet *ifp = sc->ifp; 17574d52a575SXin LI const uint8_t *eaddr = IF_LLADDR(ifp); 17584d52a575SXin LI uint32_t val; 17594d52a575SXin LI int i; 17604d52a575SXin LI 17614d52a575SXin LI /* Disable RX MAC and WOL */ 17624d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 17634d52a575SXin LI 17644d52a575SXin LI /* 17654d52a575SXin LI * Clear all WOL related registers 17664d52a575SXin LI */ 17674d52a575SXin LI for (i = 0; i < 3; ++i) 17684d52a575SXin LI CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 17694d52a575SXin LI for (i = 0; i < 20; ++i) 17704d52a575SXin LI CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 17714d52a575SXin LI 17724d52a575SXin LI /* 17734d52a575SXin LI * Set WOL source address. XXX is this necessary? 17744d52a575SXin LI */ 17754d52a575SXin LI val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 17764d52a575SXin LI CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 17774d52a575SXin LI val = (eaddr[0] << 8) | eaddr[1]; 17784d52a575SXin LI CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 17794d52a575SXin LI 17804d52a575SXin LI /* Clear packet filters */ 17814d52a575SXin LI CSR_WRITE_4(sc, ET_PKTFILT, 0); 17824d52a575SXin LI 17834d52a575SXin LI /* No ucast filtering */ 17844d52a575SXin LI CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 17854d52a575SXin LI CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 17864d52a575SXin LI CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 17874d52a575SXin LI 17884d52a575SXin LI if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 17894d52a575SXin LI /* 17904d52a575SXin LI * In order to transmit jumbo packets greater than 17914d52a575SXin LI * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 17924d52a575SXin LI * RX MAC and RX DMA needs to be reduced in size to 17934d52a575SXin LI * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 17944d52a575SXin LI * order to implement this, we must use "cut through" 17954d52a575SXin LI * mode in the RX MAC, which chops packets down into 17964d52a575SXin LI * segments. In this case we selected 256 bytes, 17974d52a575SXin LI * since this is the size of the PCI-Express TLP's 17984d52a575SXin LI * that the ET1310 uses. 17994d52a575SXin LI */ 180023263665SPyun YongHyeon val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 18014d52a575SXin LI ET_RXMAC_MC_SEGSZ_ENABLE; 18024d52a575SXin LI } else { 18034d52a575SXin LI val = 0; 18044d52a575SXin LI } 18054d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 18064d52a575SXin LI 18074d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 18084d52a575SXin LI 18094d52a575SXin LI /* Initialize RX MAC management register */ 18104d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 18114d52a575SXin LI 18124d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 18134d52a575SXin LI 18144d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_MGT, 18154d52a575SXin LI ET_RXMAC_MGT_PASS_ECRC | 18164d52a575SXin LI ET_RXMAC_MGT_PASS_ELEN | 18174d52a575SXin LI ET_RXMAC_MGT_PASS_ETRUNC | 18184d52a575SXin LI ET_RXMAC_MGT_CHECK_PKT); 18194d52a575SXin LI 18204d52a575SXin LI /* 18214d52a575SXin LI * Configure runt filtering (may not work on certain chip generation) 18224d52a575SXin LI */ 182323263665SPyun YongHyeon val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 182423263665SPyun YongHyeon ET_PKTFILT_MINLEN_MASK; 182523263665SPyun YongHyeon val |= ET_PKTFILT_FRAG; 18264d52a575SXin LI CSR_WRITE_4(sc, ET_PKTFILT, val); 18274d52a575SXin LI 18284d52a575SXin LI /* Enable RX MAC but leave WOL disabled */ 18294d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_CTRL, 18304d52a575SXin LI ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 18314d52a575SXin LI 18324d52a575SXin LI /* 18334d52a575SXin LI * Setup multicast hash and allmulti/promisc mode 18344d52a575SXin LI */ 18354d52a575SXin LI et_setmulti(sc); 18364d52a575SXin LI } 18374d52a575SXin LI 18384d52a575SXin LI static void 18394d52a575SXin LI et_init_txmac(struct et_softc *sc) 18404d52a575SXin LI { 18414d52a575SXin LI /* Disable TX MAC and FC(?) */ 18424d52a575SXin LI CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 18434d52a575SXin LI 18444d52a575SXin LI /* No flow control yet */ 18454d52a575SXin LI CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 18464d52a575SXin LI 18474d52a575SXin LI /* Enable TX MAC but leave FC(?) diabled */ 18484d52a575SXin LI CSR_WRITE_4(sc, ET_TXMAC_CTRL, 18494d52a575SXin LI ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 18504d52a575SXin LI } 18514d52a575SXin LI 18524d52a575SXin LI static int 18534d52a575SXin LI et_start_rxdma(struct et_softc *sc) 18544d52a575SXin LI { 18554d52a575SXin LI uint32_t val = 0; 18564d52a575SXin LI 185723263665SPyun YongHyeon val |= (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 18584d52a575SXin LI ET_RXDMA_CTRL_RING0_ENABLE; 185923263665SPyun YongHyeon val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 18604d52a575SXin LI ET_RXDMA_CTRL_RING1_ENABLE; 18614d52a575SXin LI 18624d52a575SXin LI CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 18634d52a575SXin LI 18644d52a575SXin LI DELAY(5); 18654d52a575SXin LI 18664d52a575SXin LI if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 18674d52a575SXin LI if_printf(sc->ifp, "can't start RX DMA engine\n"); 1868398f1b65SPyun YongHyeon return (ETIMEDOUT); 18694d52a575SXin LI } 1870398f1b65SPyun YongHyeon return (0); 18714d52a575SXin LI } 18724d52a575SXin LI 18734d52a575SXin LI static int 18744d52a575SXin LI et_start_txdma(struct et_softc *sc) 18754d52a575SXin LI { 18764d52a575SXin LI CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1877398f1b65SPyun YongHyeon return (0); 18784d52a575SXin LI } 18794d52a575SXin LI 18804d52a575SXin LI static int 18814d52a575SXin LI et_enable_txrx(struct et_softc *sc, int media_upd) 18824d52a575SXin LI { 18834d52a575SXin LI struct ifnet *ifp = sc->ifp; 18844d52a575SXin LI uint32_t val; 18854d52a575SXin LI int i, error; 18864d52a575SXin LI 18874d52a575SXin LI val = CSR_READ_4(sc, ET_MAC_CFG1); 18884d52a575SXin LI val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 18894d52a575SXin LI val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 18904d52a575SXin LI ET_MAC_CFG1_LOOPBACK); 18914d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, val); 18924d52a575SXin LI 18934d52a575SXin LI if (media_upd) 18944d52a575SXin LI et_ifmedia_upd_locked(ifp); 18954d52a575SXin LI else 18964d52a575SXin LI et_setmedia(sc); 18974d52a575SXin LI 18984d52a575SXin LI #define NRETRY 50 18994d52a575SXin LI 19004d52a575SXin LI for (i = 0; i < NRETRY; ++i) { 19014d52a575SXin LI val = CSR_READ_4(sc, ET_MAC_CFG1); 19024d52a575SXin LI if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 19034d52a575SXin LI (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 19044d52a575SXin LI break; 19054d52a575SXin LI 19064d52a575SXin LI DELAY(100); 19074d52a575SXin LI } 19084d52a575SXin LI if (i == NRETRY) { 19094d52a575SXin LI if_printf(ifp, "can't enable RX/TX\n"); 1910398f1b65SPyun YongHyeon return (0); 19114d52a575SXin LI } 19124d52a575SXin LI sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 19134d52a575SXin LI 19144d52a575SXin LI #undef NRETRY 19154d52a575SXin LI 19164d52a575SXin LI /* 19174d52a575SXin LI * Start TX/RX DMA engine 19184d52a575SXin LI */ 19194d52a575SXin LI error = et_start_rxdma(sc); 19204d52a575SXin LI if (error) 1921398f1b65SPyun YongHyeon return (error); 19224d52a575SXin LI 19234d52a575SXin LI error = et_start_txdma(sc); 19244d52a575SXin LI if (error) 1925398f1b65SPyun YongHyeon return (error); 19264d52a575SXin LI 1927398f1b65SPyun YongHyeon return (0); 19284d52a575SXin LI } 19294d52a575SXin LI 19304d52a575SXin LI static void 19314d52a575SXin LI et_rxeof(struct et_softc *sc) 19324d52a575SXin LI { 19334d52a575SXin LI struct ifnet *ifp; 19344d52a575SXin LI struct et_rxstatus_data *rxsd; 19354d52a575SXin LI struct et_rxstat_ring *rxst_ring; 193626e07b50SPyun YongHyeon uint32_t rxs_stat_ring, rxst_info2; 19374d52a575SXin LI int rxst_wrap, rxst_index; 19384d52a575SXin LI 19394d52a575SXin LI ET_LOCK_ASSERT(sc); 19404d52a575SXin LI ifp = sc->ifp; 19414d52a575SXin LI rxsd = &sc->sc_rx_status; 19424d52a575SXin LI rxst_ring = &sc->sc_rxstat_ring; 19434d52a575SXin LI 19444d52a575SXin LI if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 19454d52a575SXin LI return; 19464d52a575SXin LI 19474d52a575SXin LI bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 19484d52a575SXin LI BUS_DMASYNC_POSTREAD); 19494d52a575SXin LI bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 19504d52a575SXin LI BUS_DMASYNC_POSTREAD); 19514d52a575SXin LI 195226e07b50SPyun YongHyeon rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 19534d52a575SXin LI rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 195423263665SPyun YongHyeon rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 195523263665SPyun YongHyeon ET_RXS_STATRING_INDEX_SHIFT; 19564d52a575SXin LI 19574d52a575SXin LI while (rxst_index != rxst_ring->rsr_index || 19584d52a575SXin LI rxst_wrap != rxst_ring->rsr_wrap) { 19594d52a575SXin LI struct et_rxbuf_data *rbd; 19604d52a575SXin LI struct et_rxdesc_ring *rx_ring; 19614d52a575SXin LI struct et_rxstat *st; 19624d52a575SXin LI struct mbuf *m; 19634d52a575SXin LI int buflen, buf_idx, ring_idx; 19644d52a575SXin LI uint32_t rxstat_pos, rxring_pos; 19654d52a575SXin LI 19664d52a575SXin LI MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 19674d52a575SXin LI st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 196826e07b50SPyun YongHyeon rxst_info2 = le32toh(st->rxst_info2); 196926e07b50SPyun YongHyeon buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 197023263665SPyun YongHyeon ET_RXST_INFO2_LEN_SHIFT; 197126e07b50SPyun YongHyeon buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 197223263665SPyun YongHyeon ET_RXST_INFO2_BUFIDX_SHIFT; 197326e07b50SPyun YongHyeon ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 197423263665SPyun YongHyeon ET_RXST_INFO2_RINGIDX_SHIFT; 19754d52a575SXin LI 19764d52a575SXin LI if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 19774d52a575SXin LI rxst_ring->rsr_index = 0; 19784d52a575SXin LI rxst_ring->rsr_wrap ^= 1; 19794d52a575SXin LI } 198023263665SPyun YongHyeon rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 19814d52a575SXin LI if (rxst_ring->rsr_wrap) 19824d52a575SXin LI rxstat_pos |= ET_RXSTAT_POS_WRAP; 19834d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 19844d52a575SXin LI 19854d52a575SXin LI if (ring_idx >= ET_RX_NRING) { 19864d52a575SXin LI ifp->if_ierrors++; 19874d52a575SXin LI if_printf(ifp, "invalid ring index %d\n", ring_idx); 19884d52a575SXin LI continue; 19894d52a575SXin LI } 19904d52a575SXin LI if (buf_idx >= ET_RX_NDESC) { 19914d52a575SXin LI ifp->if_ierrors++; 19924d52a575SXin LI if_printf(ifp, "invalid buf index %d\n", buf_idx); 19934d52a575SXin LI continue; 19944d52a575SXin LI } 19954d52a575SXin LI 19964d52a575SXin LI rbd = &sc->sc_rx_data[ring_idx]; 19974d52a575SXin LI m = rbd->rbd_buf[buf_idx].rb_mbuf; 19984d52a575SXin LI 19994d52a575SXin LI if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) { 20004d52a575SXin LI if (buflen < ETHER_CRC_LEN) { 20014d52a575SXin LI m_freem(m); 20024d52a575SXin LI m = NULL; 20034d52a575SXin LI ifp->if_ierrors++; 20044d52a575SXin LI } else { 2005abd12fc6SPyun YongHyeon m->m_pkthdr.len = m->m_len = 2006abd12fc6SPyun YongHyeon buflen - ETHER_CRC_LEN; 20074d52a575SXin LI m->m_pkthdr.rcvif = ifp; 20084d52a575SXin LI ifp->if_ipackets++; 20094d52a575SXin LI ET_UNLOCK(sc); 20104d52a575SXin LI ifp->if_input(ifp, m); 20114d52a575SXin LI ET_LOCK(sc); 20124d52a575SXin LI } 20134d52a575SXin LI } else { 20144d52a575SXin LI ifp->if_ierrors++; 20154d52a575SXin LI } 20164d52a575SXin LI m = NULL; /* Catch invalid reference */ 20174d52a575SXin LI 20184d52a575SXin LI rx_ring = &sc->sc_rx_ring[ring_idx]; 20194d52a575SXin LI 20204d52a575SXin LI if (buf_idx != rx_ring->rr_index) { 20214d52a575SXin LI if_printf(ifp, "WARNING!! ring %d, " 20224d52a575SXin LI "buf_idx %d, rr_idx %d\n", 20234d52a575SXin LI ring_idx, buf_idx, rx_ring->rr_index); 20244d52a575SXin LI } 20254d52a575SXin LI 20264d52a575SXin LI MPASS(rx_ring->rr_index < ET_RX_NDESC); 20274d52a575SXin LI if (++rx_ring->rr_index == ET_RX_NDESC) { 20284d52a575SXin LI rx_ring->rr_index = 0; 20294d52a575SXin LI rx_ring->rr_wrap ^= 1; 20304d52a575SXin LI } 203123263665SPyun YongHyeon rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 20324d52a575SXin LI if (rx_ring->rr_wrap) 20334d52a575SXin LI rxring_pos |= ET_RX_RING_POS_WRAP; 20344d52a575SXin LI CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 20354d52a575SXin LI } 20364d52a575SXin LI } 20374d52a575SXin LI 20384d52a575SXin LI static int 20394d52a575SXin LI et_encap(struct et_softc *sc, struct mbuf **m0) 20404d52a575SXin LI { 20414d52a575SXin LI struct mbuf *m = *m0; 20424d52a575SXin LI bus_dma_segment_t segs[ET_NSEG_MAX]; 20434d52a575SXin LI struct et_dmamap_ctx ctx; 20444d52a575SXin LI struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 20454d52a575SXin LI struct et_txbuf_data *tbd = &sc->sc_tx_data; 20464d52a575SXin LI struct et_txdesc *td; 20474d52a575SXin LI bus_dmamap_t map; 20484d52a575SXin LI int error, maxsegs, first_idx, last_idx, i; 20499955274cSPyun YongHyeon uint32_t csum_flags, tx_ready_pos, last_td_ctrl2; 20504d52a575SXin LI 20514d52a575SXin LI maxsegs = ET_TX_NDESC - tbd->tbd_used; 20524d52a575SXin LI if (maxsegs > ET_NSEG_MAX) 20534d52a575SXin LI maxsegs = ET_NSEG_MAX; 20544d52a575SXin LI KASSERT(maxsegs >= ET_NSEG_SPARE, 20554d52a575SXin LI ("not enough spare TX desc (%d)\n", maxsegs)); 20564d52a575SXin LI 20574d52a575SXin LI MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 20584d52a575SXin LI first_idx = tx_ring->tr_ready_index; 20594d52a575SXin LI map = tbd->tbd_buf[first_idx].tb_dmap; 20604d52a575SXin LI 20614d52a575SXin LI ctx.nsegs = maxsegs; 20624d52a575SXin LI ctx.segs = segs; 20634d52a575SXin LI error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m, 20644d52a575SXin LI et_dma_buf_addr, &ctx, BUS_DMA_NOWAIT); 20654d52a575SXin LI if (!error && ctx.nsegs == 0) { 20664d52a575SXin LI bus_dmamap_unload(sc->sc_mbuf_dtag, map); 20674d52a575SXin LI error = EFBIG; 20684d52a575SXin LI } 20694d52a575SXin LI if (error && error != EFBIG) { 20704d52a575SXin LI if_printf(sc->ifp, "can't load TX mbuf, error %d\n", 20714d52a575SXin LI error); 20724d52a575SXin LI goto back; 20734d52a575SXin LI } 20744d52a575SXin LI if (error) { /* error == EFBIG */ 20754d52a575SXin LI struct mbuf *m_new; 20764d52a575SXin LI 20774d52a575SXin LI m_new = m_defrag(m, M_DONTWAIT); 20784d52a575SXin LI if (m_new == NULL) { 20794d52a575SXin LI if_printf(sc->ifp, "can't defrag TX mbuf\n"); 20804d52a575SXin LI error = ENOBUFS; 20814d52a575SXin LI goto back; 20824d52a575SXin LI } else { 20834d52a575SXin LI *m0 = m = m_new; 20844d52a575SXin LI } 20854d52a575SXin LI 20864d52a575SXin LI ctx.nsegs = maxsegs; 20874d52a575SXin LI ctx.segs = segs; 20884d52a575SXin LI error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, map, m, 20894d52a575SXin LI et_dma_buf_addr, &ctx, 20904d52a575SXin LI BUS_DMA_NOWAIT); 20914d52a575SXin LI if (error || ctx.nsegs == 0) { 20924d52a575SXin LI if (ctx.nsegs == 0) { 20934d52a575SXin LI bus_dmamap_unload(sc->sc_mbuf_dtag, map); 20944d52a575SXin LI error = EFBIG; 20954d52a575SXin LI } 20964d52a575SXin LI if_printf(sc->ifp, 20974d52a575SXin LI "can't load defraged TX mbuf\n"); 20984d52a575SXin LI goto back; 20994d52a575SXin LI } 21004d52a575SXin LI } 21014d52a575SXin LI 21024d52a575SXin LI bus_dmamap_sync(sc->sc_mbuf_dtag, map, BUS_DMASYNC_PREWRITE); 21034d52a575SXin LI 21044d52a575SXin LI last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 21054d52a575SXin LI sc->sc_tx += ctx.nsegs; 21064d52a575SXin LI if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 21074d52a575SXin LI sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 21084d52a575SXin LI last_td_ctrl2 |= ET_TDCTRL2_INTR; 21094d52a575SXin LI } 21104d52a575SXin LI 21119955274cSPyun YongHyeon csum_flags = 0; 21129955274cSPyun YongHyeon if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 21139955274cSPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 21149955274cSPyun YongHyeon csum_flags |= ET_TDCTRL2_CSUM_IP; 21159955274cSPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 21169955274cSPyun YongHyeon csum_flags |= ET_TDCTRL2_CSUM_UDP; 21179955274cSPyun YongHyeon else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 21189955274cSPyun YongHyeon csum_flags |= ET_TDCTRL2_CSUM_TCP; 21199955274cSPyun YongHyeon } 21204d52a575SXin LI last_idx = -1; 21214d52a575SXin LI for (i = 0; i < ctx.nsegs; ++i) { 21224d52a575SXin LI int idx; 21234d52a575SXin LI 21244d52a575SXin LI idx = (first_idx + i) % ET_TX_NDESC; 21254d52a575SXin LI td = &tx_ring->tr_desc[idx]; 212626e07b50SPyun YongHyeon td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 212726e07b50SPyun YongHyeon td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 212826e07b50SPyun YongHyeon td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 21294d52a575SXin LI if (i == ctx.nsegs - 1) { /* Last frag */ 21309955274cSPyun YongHyeon td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 21314d52a575SXin LI last_idx = idx; 21329955274cSPyun YongHyeon } else 21339955274cSPyun YongHyeon td->td_ctrl2 = htole32(csum_flags); 21344d52a575SXin LI 21354d52a575SXin LI MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 21364d52a575SXin LI if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 21374d52a575SXin LI tx_ring->tr_ready_index = 0; 21384d52a575SXin LI tx_ring->tr_ready_wrap ^= 1; 21394d52a575SXin LI } 21404d52a575SXin LI } 21414d52a575SXin LI td = &tx_ring->tr_desc[first_idx]; 214226e07b50SPyun YongHyeon td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); /* First frag */ 21434d52a575SXin LI 21444d52a575SXin LI MPASS(last_idx >= 0); 21454d52a575SXin LI tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 21464d52a575SXin LI tbd->tbd_buf[last_idx].tb_dmap = map; 21474d52a575SXin LI tbd->tbd_buf[last_idx].tb_mbuf = m; 21484d52a575SXin LI 21494d52a575SXin LI tbd->tbd_used += ctx.nsegs; 21504d52a575SXin LI MPASS(tbd->tbd_used <= ET_TX_NDESC); 21514d52a575SXin LI 21524d52a575SXin LI bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 21534d52a575SXin LI BUS_DMASYNC_PREWRITE); 21544d52a575SXin LI 215523263665SPyun YongHyeon tx_ready_pos = tx_ring->tr_ready_index & ET_TX_READY_POS_INDEX_MASK; 21564d52a575SXin LI if (tx_ring->tr_ready_wrap) 21574d52a575SXin LI tx_ready_pos |= ET_TX_READY_POS_WRAP; 21584d52a575SXin LI CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 21594d52a575SXin LI 21604d52a575SXin LI error = 0; 21614d52a575SXin LI back: 21624d52a575SXin LI if (error) { 21634d52a575SXin LI m_freem(m); 21644d52a575SXin LI *m0 = NULL; 21654d52a575SXin LI } 2166398f1b65SPyun YongHyeon return (error); 21674d52a575SXin LI } 21684d52a575SXin LI 21694d52a575SXin LI static void 21704d52a575SXin LI et_txeof(struct et_softc *sc) 21714d52a575SXin LI { 21724d52a575SXin LI struct ifnet *ifp; 21734d52a575SXin LI struct et_txdesc_ring *tx_ring; 21744d52a575SXin LI struct et_txbuf_data *tbd; 21754d52a575SXin LI uint32_t tx_done; 21764d52a575SXin LI int end, wrap; 21774d52a575SXin LI 21784d52a575SXin LI ET_LOCK_ASSERT(sc); 21794d52a575SXin LI ifp = sc->ifp; 21804d52a575SXin LI tx_ring = &sc->sc_tx_ring; 21814d52a575SXin LI tbd = &sc->sc_tx_data; 21824d52a575SXin LI 21834d52a575SXin LI if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 21844d52a575SXin LI return; 21854d52a575SXin LI 21864d52a575SXin LI if (tbd->tbd_used == 0) 21874d52a575SXin LI return; 21884d52a575SXin LI 21894d52a575SXin LI tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 219023263665SPyun YongHyeon end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 21914d52a575SXin LI wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 21924d52a575SXin LI 21934d52a575SXin LI while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 21944d52a575SXin LI struct et_txbuf *tb; 21954d52a575SXin LI 21964d52a575SXin LI MPASS(tbd->tbd_start_index < ET_TX_NDESC); 21974d52a575SXin LI tb = &tbd->tbd_buf[tbd->tbd_start_index]; 21984d52a575SXin LI 21994d52a575SXin LI bzero(&tx_ring->tr_desc[tbd->tbd_start_index], 22004d52a575SXin LI sizeof(struct et_txdesc)); 22014d52a575SXin LI bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 22024d52a575SXin LI BUS_DMASYNC_PREWRITE); 22034d52a575SXin LI 22044d52a575SXin LI if (tb->tb_mbuf != NULL) { 22054d52a575SXin LI bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 22064d52a575SXin LI m_freem(tb->tb_mbuf); 22074d52a575SXin LI tb->tb_mbuf = NULL; 22084d52a575SXin LI ifp->if_opackets++; 22094d52a575SXin LI } 22104d52a575SXin LI 22114d52a575SXin LI if (++tbd->tbd_start_index == ET_TX_NDESC) { 22124d52a575SXin LI tbd->tbd_start_index = 0; 22134d52a575SXin LI tbd->tbd_start_wrap ^= 1; 22144d52a575SXin LI } 22154d52a575SXin LI 22164d52a575SXin LI MPASS(tbd->tbd_used > 0); 22174d52a575SXin LI tbd->tbd_used--; 22184d52a575SXin LI } 22194d52a575SXin LI 22204d52a575SXin LI if (tbd->tbd_used == 0) 22214d52a575SXin LI sc->watchdog_timer = 0; 22224d52a575SXin LI if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC) 22234d52a575SXin LI ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 22244d52a575SXin LI 22254d52a575SXin LI et_start_locked(ifp); 22264d52a575SXin LI } 22274d52a575SXin LI 22284d52a575SXin LI static void 22294d52a575SXin LI et_tick(void *xsc) 22304d52a575SXin LI { 22314d52a575SXin LI struct et_softc *sc = xsc; 22324d52a575SXin LI struct ifnet *ifp; 22334d52a575SXin LI struct mii_data *mii; 22344d52a575SXin LI 22354d52a575SXin LI ET_LOCK_ASSERT(sc); 22364d52a575SXin LI ifp = sc->ifp; 22374d52a575SXin LI mii = device_get_softc(sc->sc_miibus); 22384d52a575SXin LI 22394d52a575SXin LI mii_tick(mii); 22404d52a575SXin LI if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 && 22414d52a575SXin LI (mii->mii_media_status & IFM_ACTIVE) && 22424d52a575SXin LI IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 22434d52a575SXin LI if_printf(ifp, "Link up, enable TX/RX\n"); 22444d52a575SXin LI if (et_enable_txrx(sc, 0) == 0) 22454d52a575SXin LI et_start_locked(ifp); 22464d52a575SXin LI } 22474d52a575SXin LI et_watchdog(sc); 22484d52a575SXin LI callout_reset(&sc->sc_tick, hz, et_tick, sc); 22494d52a575SXin LI } 22504d52a575SXin LI 22514d52a575SXin LI static int 22524d52a575SXin LI et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init) 22534d52a575SXin LI { 2254398f1b65SPyun YongHyeon return (et_newbuf(rbd, buf_idx, init, MCLBYTES)); 22554d52a575SXin LI } 22564d52a575SXin LI 22574d52a575SXin LI static int 22584d52a575SXin LI et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init) 22594d52a575SXin LI { 2260398f1b65SPyun YongHyeon return (et_newbuf(rbd, buf_idx, init, MHLEN)); 22614d52a575SXin LI } 22624d52a575SXin LI 22634d52a575SXin LI static int 22644d52a575SXin LI et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0) 22654d52a575SXin LI { 22664d52a575SXin LI struct et_softc *sc = rbd->rbd_softc; 22674d52a575SXin LI struct et_rxbuf *rb; 22684d52a575SXin LI struct mbuf *m; 22694d52a575SXin LI struct et_dmamap_ctx ctx; 22704d52a575SXin LI bus_dma_segment_t seg; 22714d52a575SXin LI bus_dmamap_t dmap; 22724d52a575SXin LI int error, len; 22734d52a575SXin LI 22744d52a575SXin LI MPASS(buf_idx < ET_RX_NDESC); 22754d52a575SXin LI rb = &rbd->rbd_buf[buf_idx]; 22764d52a575SXin LI 22774d52a575SXin LI m = m_getl(len0, /* init ? M_WAIT :*/ M_DONTWAIT, MT_DATA, M_PKTHDR, &len); 22784d52a575SXin LI if (m == NULL) { 22794d52a575SXin LI error = ENOBUFS; 22804d52a575SXin LI 22814d52a575SXin LI if (init) { 22824d52a575SXin LI if_printf(sc->ifp, 22834d52a575SXin LI "m_getl failed, size %d\n", len0); 2284398f1b65SPyun YongHyeon return (error); 22854d52a575SXin LI } else { 22864d52a575SXin LI goto back; 22874d52a575SXin LI } 22884d52a575SXin LI } 22894d52a575SXin LI m->m_len = m->m_pkthdr.len = len; 22904d52a575SXin LI 22914d52a575SXin LI /* 22924d52a575SXin LI * Try load RX mbuf into temporary DMA tag 22934d52a575SXin LI */ 22944d52a575SXin LI ctx.nsegs = 1; 22954d52a575SXin LI ctx.segs = &seg; 22964d52a575SXin LI error = bus_dmamap_load_mbuf(sc->sc_mbuf_dtag, sc->sc_mbuf_tmp_dmap, m, 22974d52a575SXin LI et_dma_buf_addr, &ctx, 22984d52a575SXin LI init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT); 22994d52a575SXin LI if (error || ctx.nsegs == 0) { 23004d52a575SXin LI if (!error) { 23014d52a575SXin LI bus_dmamap_unload(sc->sc_mbuf_dtag, 23024d52a575SXin LI sc->sc_mbuf_tmp_dmap); 23034d52a575SXin LI error = EFBIG; 23044d52a575SXin LI if_printf(sc->ifp, "too many segments?!\n"); 23054d52a575SXin LI } 23064d52a575SXin LI m_freem(m); 23074d52a575SXin LI m = NULL; 23084d52a575SXin LI 23094d52a575SXin LI if (init) { 23104d52a575SXin LI if_printf(sc->ifp, "can't load RX mbuf\n"); 2311398f1b65SPyun YongHyeon return (error); 23124d52a575SXin LI } else { 23134d52a575SXin LI goto back; 23144d52a575SXin LI } 23154d52a575SXin LI } 23164d52a575SXin LI 23174d52a575SXin LI if (!init) { 23184d52a575SXin LI bus_dmamap_sync(sc->sc_mbuf_dtag, rb->rb_dmap, 23194d52a575SXin LI BUS_DMASYNC_POSTREAD); 23204d52a575SXin LI bus_dmamap_unload(sc->sc_mbuf_dtag, rb->rb_dmap); 23214d52a575SXin LI } 23224d52a575SXin LI rb->rb_mbuf = m; 23234d52a575SXin LI rb->rb_paddr = seg.ds_addr; 23244d52a575SXin LI 23254d52a575SXin LI /* 23264d52a575SXin LI * Swap RX buf's DMA map with the loaded temporary one 23274d52a575SXin LI */ 23284d52a575SXin LI dmap = rb->rb_dmap; 23294d52a575SXin LI rb->rb_dmap = sc->sc_mbuf_tmp_dmap; 23304d52a575SXin LI sc->sc_mbuf_tmp_dmap = dmap; 23314d52a575SXin LI 23324d52a575SXin LI error = 0; 23334d52a575SXin LI back: 23344d52a575SXin LI et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr); 2335398f1b65SPyun YongHyeon return (error); 23364d52a575SXin LI } 23374d52a575SXin LI 23384d52a575SXin LI /* 23394d52a575SXin LI * Create sysctl tree 23404d52a575SXin LI */ 23414d52a575SXin LI static void 23424d52a575SXin LI et_add_sysctls(struct et_softc * sc) 23434d52a575SXin LI { 23444d52a575SXin LI struct sysctl_ctx_list *ctx; 23454d52a575SXin LI struct sysctl_oid_list *children; 23464d52a575SXin LI 23474d52a575SXin LI ctx = device_get_sysctl_ctx(sc->dev); 23484d52a575SXin LI children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 23494d52a575SXin LI 23504d52a575SXin LI SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 23514d52a575SXin LI CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_npkts, "I", 23524d52a575SXin LI "RX IM, # packets per RX interrupt"); 23534d52a575SXin LI SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 23544d52a575SXin LI CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_delay, "I", 23554d52a575SXin LI "RX IM, RX interrupt delay (x10 usec)"); 23564d52a575SXin LI SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 23574d52a575SXin LI CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 23584d52a575SXin LI "TX IM, # segments per TX interrupt"); 23594d52a575SXin LI SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 23604d52a575SXin LI CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 23614d52a575SXin LI } 23624d52a575SXin LI 23634d52a575SXin LI static int 23644d52a575SXin LI et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 23654d52a575SXin LI { 23664d52a575SXin LI struct et_softc *sc = arg1; 23674d52a575SXin LI struct ifnet *ifp = sc->ifp; 23684d52a575SXin LI int error = 0, v; 23694d52a575SXin LI 23704d52a575SXin LI v = sc->sc_rx_intr_npkts; 23714d52a575SXin LI error = sysctl_handle_int(oidp, &v, 0, req); 23724d52a575SXin LI if (error || req->newptr == NULL) 23734d52a575SXin LI goto back; 23744d52a575SXin LI if (v <= 0) { 23754d52a575SXin LI error = EINVAL; 23764d52a575SXin LI goto back; 23774d52a575SXin LI } 23784d52a575SXin LI 23794d52a575SXin LI if (sc->sc_rx_intr_npkts != v) { 23804d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) 23814d52a575SXin LI CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 23824d52a575SXin LI sc->sc_rx_intr_npkts = v; 23834d52a575SXin LI } 23844d52a575SXin LI back: 2385398f1b65SPyun YongHyeon return (error); 23864d52a575SXin LI } 23874d52a575SXin LI 23884d52a575SXin LI static int 23894d52a575SXin LI et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 23904d52a575SXin LI { 23914d52a575SXin LI struct et_softc *sc = arg1; 23924d52a575SXin LI struct ifnet *ifp = sc->ifp; 23934d52a575SXin LI int error = 0, v; 23944d52a575SXin LI 23954d52a575SXin LI v = sc->sc_rx_intr_delay; 23964d52a575SXin LI error = sysctl_handle_int(oidp, &v, 0, req); 23974d52a575SXin LI if (error || req->newptr == NULL) 23984d52a575SXin LI goto back; 23994d52a575SXin LI if (v <= 0) { 24004d52a575SXin LI error = EINVAL; 24014d52a575SXin LI goto back; 24024d52a575SXin LI } 24034d52a575SXin LI 24044d52a575SXin LI if (sc->sc_rx_intr_delay != v) { 24054d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) 24064d52a575SXin LI CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 24074d52a575SXin LI sc->sc_rx_intr_delay = v; 24084d52a575SXin LI } 24094d52a575SXin LI back: 2410398f1b65SPyun YongHyeon return (error); 24114d52a575SXin LI } 24124d52a575SXin LI 24134d52a575SXin LI static void 24144d52a575SXin LI et_setmedia(struct et_softc *sc) 24154d52a575SXin LI { 24164d52a575SXin LI struct mii_data *mii = device_get_softc(sc->sc_miibus); 24174d52a575SXin LI uint32_t cfg2, ctrl; 24184d52a575SXin LI 24194d52a575SXin LI cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 24204d52a575SXin LI cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 24214d52a575SXin LI ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 24224d52a575SXin LI cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 242323263665SPyun YongHyeon ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 242423263665SPyun YongHyeon ET_MAC_CFG2_PREAMBLE_LEN_MASK); 24254d52a575SXin LI 24264d52a575SXin LI ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 24274d52a575SXin LI ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 24284d52a575SXin LI 24294d52a575SXin LI if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 24304d52a575SXin LI cfg2 |= ET_MAC_CFG2_MODE_GMII; 24314d52a575SXin LI } else { 24324d52a575SXin LI cfg2 |= ET_MAC_CFG2_MODE_MII; 24334d52a575SXin LI ctrl |= ET_MAC_CTRL_MODE_MII; 24344d52a575SXin LI } 24354d52a575SXin LI 24364d52a575SXin LI if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 24374d52a575SXin LI cfg2 |= ET_MAC_CFG2_FDX; 24384d52a575SXin LI else 24394d52a575SXin LI ctrl |= ET_MAC_CTRL_GHDX; 24404d52a575SXin LI 24414d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 24424d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 24434d52a575SXin LI } 24444d52a575SXin LI 24454d52a575SXin LI static void 24464d52a575SXin LI et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr) 24474d52a575SXin LI { 24484d52a575SXin LI struct et_rxdesc_ring *rx_ring = rbd->rbd_ring; 24494d52a575SXin LI struct et_rxdesc *desc; 24504d52a575SXin LI 24514d52a575SXin LI MPASS(buf_idx < ET_RX_NDESC); 24524d52a575SXin LI desc = &rx_ring->rr_desc[buf_idx]; 24534d52a575SXin LI 245426e07b50SPyun YongHyeon desc->rd_addr_hi = htole32(ET_ADDR_HI(paddr)); 245526e07b50SPyun YongHyeon desc->rd_addr_lo = htole32(ET_ADDR_LO(paddr)); 245626e07b50SPyun YongHyeon desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 24574d52a575SXin LI 24584d52a575SXin LI bus_dmamap_sync(rx_ring->rr_dtag, rx_ring->rr_dmap, 24594d52a575SXin LI BUS_DMASYNC_PREWRITE); 24604d52a575SXin LI } 2461