14d52a575SXin LI /*- 2e5fdd9deSXin LI * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 34d52a575SXin LI * 44d52a575SXin LI * This code is derived from software contributed to The DragonFly Project 54d52a575SXin LI * by Sepherosa Ziehau <sepherosa@gmail.com> 64d52a575SXin LI * 74d52a575SXin LI * Redistribution and use in source and binary forms, with or without 84d52a575SXin LI * modification, are permitted provided that the following conditions 94d52a575SXin LI * are met: 104d52a575SXin LI * 114d52a575SXin LI * 1. Redistributions of source code must retain the above copyright 124d52a575SXin LI * notice, this list of conditions and the following disclaimer. 134d52a575SXin LI * 2. Redistributions in binary form must reproduce the above copyright 144d52a575SXin LI * notice, this list of conditions and the following disclaimer in 154d52a575SXin LI * the documentation and/or other materials provided with the 164d52a575SXin LI * distribution. 174d52a575SXin LI * 3. Neither the name of The DragonFly Project nor the names of its 184d52a575SXin LI * contributors may be used to endorse or promote products derived 194d52a575SXin LI * from this software without specific, prior written permission. 204d52a575SXin LI * 214d52a575SXin LI * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 224d52a575SXin LI * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 234d52a575SXin LI * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 244d52a575SXin LI * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 254d52a575SXin LI * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 264d52a575SXin LI * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 274d52a575SXin LI * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 284d52a575SXin LI * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 294d52a575SXin LI * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 304d52a575SXin LI * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 314d52a575SXin LI * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 324d52a575SXin LI * SUCH DAMAGE. 334d52a575SXin LI * 344d52a575SXin LI * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 354d52a575SXin LI */ 364d52a575SXin LI 37fe42b04dSPyun YongHyeon #include <sys/cdefs.h> 38fe42b04dSPyun YongHyeon __FBSDID("$FreeBSD$"); 39fe42b04dSPyun YongHyeon 404d52a575SXin LI #include <sys/param.h> 414d52a575SXin LI #include <sys/systm.h> 424d52a575SXin LI #include <sys/endian.h> 434d52a575SXin LI #include <sys/kernel.h> 444d52a575SXin LI #include <sys/bus.h> 454d52a575SXin LI #include <sys/malloc.h> 464d52a575SXin LI #include <sys/mbuf.h> 474d52a575SXin LI #include <sys/proc.h> 484d52a575SXin LI #include <sys/rman.h> 494d52a575SXin LI #include <sys/module.h> 504d52a575SXin LI #include <sys/socket.h> 514d52a575SXin LI #include <sys/sockio.h> 524d52a575SXin LI #include <sys/sysctl.h> 534d52a575SXin LI 544d52a575SXin LI #include <net/ethernet.h> 554d52a575SXin LI #include <net/if.h> 564d52a575SXin LI #include <net/if_dl.h> 574d52a575SXin LI #include <net/if_types.h> 584d52a575SXin LI #include <net/bpf.h> 594d52a575SXin LI #include <net/if_arp.h> 604d52a575SXin LI #include <net/if_media.h> 614d52a575SXin LI #include <net/if_vlan_var.h> 624d52a575SXin LI 634d52a575SXin LI #include <machine/bus.h> 644d52a575SXin LI 65d6c65d27SMarius Strobl #include <dev/mii/mii.h> 664d52a575SXin LI #include <dev/mii/miivar.h> 674d52a575SXin LI 684d52a575SXin LI #include <dev/pci/pcireg.h> 694d52a575SXin LI #include <dev/pci/pcivar.h> 704d52a575SXin LI 714d52a575SXin LI #include <dev/et/if_etreg.h> 724d52a575SXin LI #include <dev/et/if_etvar.h> 734d52a575SXin LI 744d52a575SXin LI #include "miibus_if.h" 754d52a575SXin LI 764d52a575SXin LI MODULE_DEPEND(et, pci, 1, 1, 1); 774d52a575SXin LI MODULE_DEPEND(et, ether, 1, 1, 1); 784d52a575SXin LI MODULE_DEPEND(et, miibus, 1, 1, 1); 794d52a575SXin LI 80cc3c3b4eSPyun YongHyeon /* Tunables. */ 81cc3c3b4eSPyun YongHyeon static int msi_disable = 0; 82accb4fcdSPyun YongHyeon TUNABLE_INT("hw.et.msi_disable", &msi_disable); 83cc3c3b4eSPyun YongHyeon 849955274cSPyun YongHyeon #define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 859955274cSPyun YongHyeon 864d52a575SXin LI static int et_probe(device_t); 874d52a575SXin LI static int et_attach(device_t); 884d52a575SXin LI static int et_detach(device_t); 894d52a575SXin LI static int et_shutdown(device_t); 900442028aSPyun YongHyeon static int et_suspend(device_t); 910442028aSPyun YongHyeon static int et_resume(device_t); 924d52a575SXin LI 934d52a575SXin LI static int et_miibus_readreg(device_t, int, int); 944d52a575SXin LI static int et_miibus_writereg(device_t, int, int, int); 954d52a575SXin LI static void et_miibus_statchg(device_t); 964d52a575SXin LI 974d52a575SXin LI static void et_init_locked(struct et_softc *); 984d52a575SXin LI static void et_init(void *); 994d52a575SXin LI static int et_ioctl(struct ifnet *, u_long, caddr_t); 1004d52a575SXin LI static void et_start_locked(struct ifnet *); 1014d52a575SXin LI static void et_start(struct ifnet *); 102*05884511SPyun YongHyeon static int et_watchdog(struct et_softc *); 1034d52a575SXin LI static int et_ifmedia_upd_locked(struct ifnet *); 1044d52a575SXin LI static int et_ifmedia_upd(struct ifnet *); 1054d52a575SXin LI static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 1064d52a575SXin LI 1074d52a575SXin LI static void et_add_sysctls(struct et_softc *); 1084d52a575SXin LI static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 1094d52a575SXin LI static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 1104d52a575SXin LI 1114d52a575SXin LI static void et_intr(void *); 1124d52a575SXin LI static void et_enable_intrs(struct et_softc *, uint32_t); 1134d52a575SXin LI static void et_disable_intrs(struct et_softc *); 1144d52a575SXin LI static void et_rxeof(struct et_softc *); 1154d52a575SXin LI static void et_txeof(struct et_softc *); 1164d52a575SXin LI 117*05884511SPyun YongHyeon static int et_dma_alloc(struct et_softc *); 118*05884511SPyun YongHyeon static void et_dma_free(struct et_softc *); 119*05884511SPyun YongHyeon static void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 120*05884511SPyun YongHyeon static int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 121*05884511SPyun YongHyeon bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 122*05884511SPyun YongHyeon const char *); 123*05884511SPyun YongHyeon static void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 124*05884511SPyun YongHyeon bus_dmamap_t *); 125*05884511SPyun YongHyeon static void et_init_tx_ring(struct et_softc *); 1264d52a575SXin LI static int et_init_rx_ring(struct et_softc *); 1274d52a575SXin LI static void et_free_tx_ring(struct et_softc *); 1284d52a575SXin LI static void et_free_rx_ring(struct et_softc *); 1294d52a575SXin LI static int et_encap(struct et_softc *, struct mbuf **); 130*05884511SPyun YongHyeon static int et_newbuf_cluster(struct et_rxbuf_data *, int); 131*05884511SPyun YongHyeon static int et_newbuf_hdr(struct et_rxbuf_data *, int); 132*05884511SPyun YongHyeon static void et_rxbuf_discard(struct et_rxbuf_data *, int); 1334d52a575SXin LI 1344d52a575SXin LI static void et_stop(struct et_softc *); 1354d52a575SXin LI static int et_chip_init(struct et_softc *); 1364d52a575SXin LI static void et_chip_attach(struct et_softc *); 1374d52a575SXin LI static void et_init_mac(struct et_softc *); 1384d52a575SXin LI static void et_init_rxmac(struct et_softc *); 1394d52a575SXin LI static void et_init_txmac(struct et_softc *); 1404d52a575SXin LI static int et_init_rxdma(struct et_softc *); 1414d52a575SXin LI static int et_init_txdma(struct et_softc *); 1424d52a575SXin LI static int et_start_rxdma(struct et_softc *); 1434d52a575SXin LI static int et_start_txdma(struct et_softc *); 1444d52a575SXin LI static int et_stop_rxdma(struct et_softc *); 1454d52a575SXin LI static int et_stop_txdma(struct et_softc *); 1464d52a575SXin LI static int et_enable_txrx(struct et_softc *, int); 1474d52a575SXin LI static void et_reset(struct et_softc *); 1488b3c6496SPyun YongHyeon static int et_bus_config(struct et_softc *); 1494d52a575SXin LI static void et_get_eaddr(device_t, uint8_t[]); 1504d52a575SXin LI static void et_setmulti(struct et_softc *); 1514d52a575SXin LI static void et_tick(void *); 1524d52a575SXin LI static void et_setmedia(struct et_softc *); 1534d52a575SXin LI 1544d52a575SXin LI static const struct et_dev { 1554d52a575SXin LI uint16_t vid; 1564d52a575SXin LI uint16_t did; 1574d52a575SXin LI const char *desc; 1584d52a575SXin LI } et_devices[] = { 1594d52a575SXin LI { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 1604d52a575SXin LI "Agere ET1310 Gigabit Ethernet" }, 1614d52a575SXin LI { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 1624d52a575SXin LI "Agere ET1310 Fast Ethernet" }, 1634d52a575SXin LI { 0, 0, NULL } 1644d52a575SXin LI }; 1654d52a575SXin LI 1664d52a575SXin LI static device_method_t et_methods[] = { 1674d52a575SXin LI DEVMETHOD(device_probe, et_probe), 1684d52a575SXin LI DEVMETHOD(device_attach, et_attach), 1694d52a575SXin LI DEVMETHOD(device_detach, et_detach), 1704d52a575SXin LI DEVMETHOD(device_shutdown, et_shutdown), 1710442028aSPyun YongHyeon DEVMETHOD(device_suspend, et_suspend), 1720442028aSPyun YongHyeon DEVMETHOD(device_resume, et_resume), 1734d52a575SXin LI 1744d52a575SXin LI DEVMETHOD(miibus_readreg, et_miibus_readreg), 1754d52a575SXin LI DEVMETHOD(miibus_writereg, et_miibus_writereg), 1764d52a575SXin LI DEVMETHOD(miibus_statchg, et_miibus_statchg), 1774d52a575SXin LI 1784b7ec270SMarius Strobl DEVMETHOD_END 1794d52a575SXin LI }; 1804d52a575SXin LI 1814d52a575SXin LI static driver_t et_driver = { 1824d52a575SXin LI "et", 1834d52a575SXin LI et_methods, 1844d52a575SXin LI sizeof(struct et_softc) 1854d52a575SXin LI }; 1864d52a575SXin LI 1874d52a575SXin LI static devclass_t et_devclass; 1884d52a575SXin LI 1894d52a575SXin LI DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0); 1904d52a575SXin LI DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0); 1914d52a575SXin LI 1924d52a575SXin LI static int et_rx_intr_npkts = 32; 1934d52a575SXin LI static int et_rx_intr_delay = 20; /* x10 usec */ 1944d52a575SXin LI static int et_tx_intr_nsegs = 126; 1954d52a575SXin LI static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 1964d52a575SXin LI 1974d52a575SXin LI TUNABLE_INT("hw.et.timer", &et_timer); 1984d52a575SXin LI TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 1994d52a575SXin LI TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 2004d52a575SXin LI TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 2014d52a575SXin LI 2024d52a575SXin LI static int 2034d52a575SXin LI et_probe(device_t dev) 2044d52a575SXin LI { 2054d52a575SXin LI const struct et_dev *d; 2064d52a575SXin LI uint16_t did, vid; 2074d52a575SXin LI 2084d52a575SXin LI vid = pci_get_vendor(dev); 2094d52a575SXin LI did = pci_get_device(dev); 2104d52a575SXin LI 2114d52a575SXin LI for (d = et_devices; d->desc != NULL; ++d) { 2124d52a575SXin LI if (vid == d->vid && did == d->did) { 2134d52a575SXin LI device_set_desc(dev, d->desc); 214a64788d1SPyun YongHyeon return (BUS_PROBE_DEFAULT); 2154d52a575SXin LI } 2164d52a575SXin LI } 217398f1b65SPyun YongHyeon return (ENXIO); 2184d52a575SXin LI } 2194d52a575SXin LI 2204d52a575SXin LI static int 2214d52a575SXin LI et_attach(device_t dev) 2224d52a575SXin LI { 2234d52a575SXin LI struct et_softc *sc; 2244d52a575SXin LI struct ifnet *ifp; 2254d52a575SXin LI uint8_t eaddr[ETHER_ADDR_LEN]; 226cc3c3b4eSPyun YongHyeon int cap, error, msic; 2274d52a575SXin LI 2284d52a575SXin LI sc = device_get_softc(dev); 2294d52a575SXin LI sc->dev = dev; 2304d52a575SXin LI mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2314d52a575SXin LI MTX_DEF); 232d2f7028cSPyun YongHyeon callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 2334d52a575SXin LI 2344d52a575SXin LI ifp = sc->ifp = if_alloc(IFT_ETHER); 2354d52a575SXin LI if (ifp == NULL) { 2364d52a575SXin LI device_printf(dev, "can not if_alloc()\n"); 2374d52a575SXin LI error = ENOSPC; 2384d52a575SXin LI goto fail; 2394d52a575SXin LI } 2404d52a575SXin LI 2414d52a575SXin LI /* 2424d52a575SXin LI * Initialize tunables 2434d52a575SXin LI */ 2444d52a575SXin LI sc->sc_rx_intr_npkts = et_rx_intr_npkts; 2454d52a575SXin LI sc->sc_rx_intr_delay = et_rx_intr_delay; 2464d52a575SXin LI sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 2474d52a575SXin LI sc->sc_timer = et_timer; 2484d52a575SXin LI 2494d52a575SXin LI /* Enable bus mastering */ 2504d52a575SXin LI pci_enable_busmaster(dev); 2514d52a575SXin LI 2524d52a575SXin LI /* 2534d52a575SXin LI * Allocate IO memory 2544d52a575SXin LI */ 2554d52a575SXin LI sc->sc_mem_rid = ET_PCIR_BAR; 2564d52a575SXin LI sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2574d52a575SXin LI &sc->sc_mem_rid, RF_ACTIVE); 2584d52a575SXin LI if (sc->sc_mem_res == NULL) { 2594d52a575SXin LI device_printf(dev, "can't allocate IO memory\n"); 260398f1b65SPyun YongHyeon return (ENXIO); 2614d52a575SXin LI } 2624d52a575SXin LI 263cc3c3b4eSPyun YongHyeon msic = 0; 2643b0a4aefSJohn Baldwin if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 265cc3c3b4eSPyun YongHyeon sc->sc_expcap = cap; 266cc3c3b4eSPyun YongHyeon sc->sc_flags |= ET_FLAG_PCIE; 267cc3c3b4eSPyun YongHyeon msic = pci_msi_count(dev); 268cc3c3b4eSPyun YongHyeon if (bootverbose) 269cc3c3b4eSPyun YongHyeon device_printf(dev, "MSI count: %d\n", msic); 270cc3c3b4eSPyun YongHyeon } 271cc3c3b4eSPyun YongHyeon if (msic > 0 && msi_disable == 0) { 272cc3c3b4eSPyun YongHyeon msic = 1; 273cc3c3b4eSPyun YongHyeon if (pci_alloc_msi(dev, &msic) == 0) { 274cc3c3b4eSPyun YongHyeon if (msic == 1) { 275cc3c3b4eSPyun YongHyeon device_printf(dev, "Using %d MSI message\n", 276cc3c3b4eSPyun YongHyeon msic); 277cc3c3b4eSPyun YongHyeon sc->sc_flags |= ET_FLAG_MSI; 278cc3c3b4eSPyun YongHyeon } else 279cc3c3b4eSPyun YongHyeon pci_release_msi(dev); 280cc3c3b4eSPyun YongHyeon } 281cc3c3b4eSPyun YongHyeon } 282cc3c3b4eSPyun YongHyeon 2834d52a575SXin LI /* 2844d52a575SXin LI * Allocate IRQ 2854d52a575SXin LI */ 286cc3c3b4eSPyun YongHyeon if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 2874d52a575SXin LI sc->sc_irq_rid = 0; 2884d52a575SXin LI sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 289cc3c3b4eSPyun YongHyeon &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 290cc3c3b4eSPyun YongHyeon } else { 291cc3c3b4eSPyun YongHyeon sc->sc_irq_rid = 1; 292cc3c3b4eSPyun YongHyeon sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 293cc3c3b4eSPyun YongHyeon &sc->sc_irq_rid, RF_ACTIVE); 294cc3c3b4eSPyun YongHyeon } 2954d52a575SXin LI if (sc->sc_irq_res == NULL) { 2964d52a575SXin LI device_printf(dev, "can't allocate irq\n"); 2974d52a575SXin LI error = ENXIO; 2984d52a575SXin LI goto fail; 2994d52a575SXin LI } 3004d52a575SXin LI 3018b3c6496SPyun YongHyeon error = et_bus_config(sc); 3024d52a575SXin LI if (error) 3034d52a575SXin LI goto fail; 3044d52a575SXin LI 3054d52a575SXin LI et_get_eaddr(dev, eaddr); 3064d52a575SXin LI 3074d52a575SXin LI CSR_WRITE_4(sc, ET_PM, 3084d52a575SXin LI ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE); 3094d52a575SXin LI 3104d52a575SXin LI et_reset(sc); 3114d52a575SXin LI 3124d52a575SXin LI et_disable_intrs(sc); 3134d52a575SXin LI 314*05884511SPyun YongHyeon error = et_dma_alloc(sc); 3154d52a575SXin LI if (error) 3164d52a575SXin LI goto fail; 3174d52a575SXin LI 3184d52a575SXin LI ifp->if_softc = sc; 3194d52a575SXin LI if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3204d52a575SXin LI ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3214d52a575SXin LI ifp->if_init = et_init; 3224d52a575SXin LI ifp->if_ioctl = et_ioctl; 3234d52a575SXin LI ifp->if_start = et_start; 324ed848e3aSPyun YongHyeon ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU; 3254d52a575SXin LI ifp->if_capenable = ifp->if_capabilities; 326c8b727ceSPyun YongHyeon ifp->if_snd.ifq_drv_maxlen = ET_TX_NDESC - 1; 327c8b727ceSPyun YongHyeon IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC - 1); 3284d52a575SXin LI IFQ_SET_READY(&ifp->if_snd); 3294d52a575SXin LI 3304d52a575SXin LI et_chip_attach(sc); 3314d52a575SXin LI 332d6c65d27SMarius Strobl error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 333d6c65d27SMarius Strobl et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 3344d52a575SXin LI if (error) { 335d6c65d27SMarius Strobl device_printf(dev, "attaching PHYs failed\n"); 3364d52a575SXin LI goto fail; 3374d52a575SXin LI } 3384d52a575SXin LI 3394d52a575SXin LI ether_ifattach(ifp, eaddr); 340d2f7028cSPyun YongHyeon 341d2f7028cSPyun YongHyeon /* Tell the upper layer(s) we support long frames. */ 342d2f7028cSPyun YongHyeon ifp->if_hdrlen = sizeof(struct ether_vlan_header); 3434d52a575SXin LI 3444d52a575SXin LI error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 3454d52a575SXin LI NULL, et_intr, sc, &sc->sc_irq_handle); 3464d52a575SXin LI if (error) { 3474d52a575SXin LI ether_ifdetach(ifp); 3484d52a575SXin LI device_printf(dev, "can't setup intr\n"); 3494d52a575SXin LI goto fail; 3504d52a575SXin LI } 3514d52a575SXin LI 3524d52a575SXin LI et_add_sysctls(sc); 3534d52a575SXin LI 354398f1b65SPyun YongHyeon return (0); 3554d52a575SXin LI fail: 3564d52a575SXin LI et_detach(dev); 357398f1b65SPyun YongHyeon return (error); 3584d52a575SXin LI } 3594d52a575SXin LI 3604d52a575SXin LI static int 3614d52a575SXin LI et_detach(device_t dev) 3624d52a575SXin LI { 3634d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 3644d52a575SXin LI 3654d52a575SXin LI if (device_is_attached(dev)) { 366a64788d1SPyun YongHyeon ether_ifdetach(sc->ifp); 3674d52a575SXin LI ET_LOCK(sc); 3684d52a575SXin LI et_stop(sc); 3694d52a575SXin LI ET_UNLOCK(sc); 370a64788d1SPyun YongHyeon callout_drain(&sc->sc_tick); 3714d52a575SXin LI } 3724d52a575SXin LI 3734d52a575SXin LI if (sc->sc_miibus != NULL) 3744d52a575SXin LI device_delete_child(dev, sc->sc_miibus); 3754d52a575SXin LI bus_generic_detach(dev); 3764d52a575SXin LI 377a64788d1SPyun YongHyeon if (sc->sc_irq_handle != NULL) 378a64788d1SPyun YongHyeon bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 379a64788d1SPyun YongHyeon if (sc->sc_irq_res != NULL) 380a64788d1SPyun YongHyeon bus_release_resource(dev, SYS_RES_IRQ, 381a64788d1SPyun YongHyeon rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 382cc3c3b4eSPyun YongHyeon if ((sc->sc_flags & ET_FLAG_MSI) != 0) 383cc3c3b4eSPyun YongHyeon pci_release_msi(dev); 384a64788d1SPyun YongHyeon if (sc->sc_mem_res != NULL) 385a64788d1SPyun YongHyeon bus_release_resource(dev, SYS_RES_MEMORY, 386a64788d1SPyun YongHyeon rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 3874d52a575SXin LI 3884d52a575SXin LI if (sc->ifp != NULL) 3894d52a575SXin LI if_free(sc->ifp); 3904d52a575SXin LI 391*05884511SPyun YongHyeon et_dma_free(sc); 3925b8f4900SPyun YongHyeon 3935b8f4900SPyun YongHyeon mtx_destroy(&sc->sc_mtx); 3944d52a575SXin LI 395398f1b65SPyun YongHyeon return (0); 3964d52a575SXin LI } 3974d52a575SXin LI 3984d52a575SXin LI static int 3994d52a575SXin LI et_shutdown(device_t dev) 4004d52a575SXin LI { 4014d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 4024d52a575SXin LI 4034d52a575SXin LI ET_LOCK(sc); 4044d52a575SXin LI et_stop(sc); 4054d52a575SXin LI ET_UNLOCK(sc); 406398f1b65SPyun YongHyeon return (0); 4074d52a575SXin LI } 4084d52a575SXin LI 4094d52a575SXin LI static int 4104d52a575SXin LI et_miibus_readreg(device_t dev, int phy, int reg) 4114d52a575SXin LI { 4124d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 4134d52a575SXin LI uint32_t val; 4144d52a575SXin LI int i, ret; 4154d52a575SXin LI 4164d52a575SXin LI /* Stop any pending operations */ 4174d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, 0); 4184d52a575SXin LI 41923263665SPyun YongHyeon val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 42023263665SPyun YongHyeon val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 4214d52a575SXin LI CSR_WRITE_4(sc, ET_MII_ADDR, val); 4224d52a575SXin LI 4234d52a575SXin LI /* Start reading */ 4244d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 4254d52a575SXin LI 4264d52a575SXin LI #define NRETRY 50 4274d52a575SXin LI 4284d52a575SXin LI for (i = 0; i < NRETRY; ++i) { 4294d52a575SXin LI val = CSR_READ_4(sc, ET_MII_IND); 4304d52a575SXin LI if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 4314d52a575SXin LI break; 4324d52a575SXin LI DELAY(50); 4334d52a575SXin LI } 4344d52a575SXin LI if (i == NRETRY) { 4354d52a575SXin LI if_printf(sc->ifp, 4364d52a575SXin LI "read phy %d, reg %d timed out\n", phy, reg); 4374d52a575SXin LI ret = 0; 4384d52a575SXin LI goto back; 4394d52a575SXin LI } 4404d52a575SXin LI 4414d52a575SXin LI #undef NRETRY 4424d52a575SXin LI 4434d52a575SXin LI val = CSR_READ_4(sc, ET_MII_STAT); 44423263665SPyun YongHyeon ret = val & ET_MII_STAT_VALUE_MASK; 4454d52a575SXin LI 4464d52a575SXin LI back: 4474d52a575SXin LI /* Make sure that the current operation is stopped */ 4484d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, 0); 449398f1b65SPyun YongHyeon return (ret); 4504d52a575SXin LI } 4514d52a575SXin LI 4524d52a575SXin LI static int 4534d52a575SXin LI et_miibus_writereg(device_t dev, int phy, int reg, int val0) 4544d52a575SXin LI { 4554d52a575SXin LI struct et_softc *sc = device_get_softc(dev); 4564d52a575SXin LI uint32_t val; 4574d52a575SXin LI int i; 4584d52a575SXin LI 4594d52a575SXin LI /* Stop any pending operations */ 4604d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, 0); 4614d52a575SXin LI 46223263665SPyun YongHyeon val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 46323263665SPyun YongHyeon val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 4644d52a575SXin LI CSR_WRITE_4(sc, ET_MII_ADDR, val); 4654d52a575SXin LI 4664d52a575SXin LI /* Start writing */ 46723263665SPyun YongHyeon CSR_WRITE_4(sc, ET_MII_CTRL, 46823263665SPyun YongHyeon (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 4694d52a575SXin LI 4704d52a575SXin LI #define NRETRY 100 4714d52a575SXin LI 4724d52a575SXin LI for (i = 0; i < NRETRY; ++i) { 4734d52a575SXin LI val = CSR_READ_4(sc, ET_MII_IND); 4744d52a575SXin LI if ((val & ET_MII_IND_BUSY) == 0) 4754d52a575SXin LI break; 4764d52a575SXin LI DELAY(50); 4774d52a575SXin LI } 4784d52a575SXin LI if (i == NRETRY) { 4794d52a575SXin LI if_printf(sc->ifp, 4804d52a575SXin LI "write phy %d, reg %d timed out\n", phy, reg); 4814d52a575SXin LI et_miibus_readreg(dev, phy, reg); 4824d52a575SXin LI } 4834d52a575SXin LI 4844d52a575SXin LI #undef NRETRY 4854d52a575SXin LI 4864d52a575SXin LI /* Make sure that the current operation is stopped */ 4874d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CMD, 0); 488398f1b65SPyun YongHyeon return (0); 4894d52a575SXin LI } 4904d52a575SXin LI 4914d52a575SXin LI static void 4924d52a575SXin LI et_miibus_statchg(device_t dev) 4934d52a575SXin LI { 4944d52a575SXin LI et_setmedia(device_get_softc(dev)); 4954d52a575SXin LI } 4964d52a575SXin LI 4974d52a575SXin LI static int 4984d52a575SXin LI et_ifmedia_upd_locked(struct ifnet *ifp) 4994d52a575SXin LI { 5004d52a575SXin LI struct et_softc *sc = ifp->if_softc; 5014d52a575SXin LI struct mii_data *mii = device_get_softc(sc->sc_miibus); 5024d52a575SXin LI struct mii_softc *miisc; 5034d52a575SXin LI 5044d52a575SXin LI LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5053fcb7a53SMarius Strobl PHY_RESET(miisc); 50696570638SPyun YongHyeon return (mii_mediachg(mii)); 5074d52a575SXin LI } 5084d52a575SXin LI 5094d52a575SXin LI static int 5104d52a575SXin LI et_ifmedia_upd(struct ifnet *ifp) 5114d52a575SXin LI { 5124d52a575SXin LI struct et_softc *sc = ifp->if_softc; 5134d52a575SXin LI int res; 5144d52a575SXin LI 5154d52a575SXin LI ET_LOCK(sc); 5164d52a575SXin LI res = et_ifmedia_upd_locked(ifp); 5174d52a575SXin LI ET_UNLOCK(sc); 5184d52a575SXin LI 519398f1b65SPyun YongHyeon return (res); 5204d52a575SXin LI } 5214d52a575SXin LI 5224d52a575SXin LI static void 5234d52a575SXin LI et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5244d52a575SXin LI { 5254d52a575SXin LI struct et_softc *sc = ifp->if_softc; 5264d52a575SXin LI struct mii_data *mii = device_get_softc(sc->sc_miibus); 5274d52a575SXin LI 5280ae9f6a9SPyun YongHyeon ET_LOCK(sc); 5294d52a575SXin LI mii_pollstat(mii); 5304d52a575SXin LI ifmr->ifm_active = mii->mii_media_active; 5314d52a575SXin LI ifmr->ifm_status = mii->mii_media_status; 5320ae9f6a9SPyun YongHyeon ET_UNLOCK(sc); 5334d52a575SXin LI } 5344d52a575SXin LI 5354d52a575SXin LI static void 5364d52a575SXin LI et_stop(struct et_softc *sc) 5374d52a575SXin LI { 5384d52a575SXin LI struct ifnet *ifp = sc->ifp; 5394d52a575SXin LI 5404d52a575SXin LI ET_LOCK_ASSERT(sc); 5414d52a575SXin LI 5424d52a575SXin LI callout_stop(&sc->sc_tick); 5434d52a575SXin LI 5444d52a575SXin LI et_stop_rxdma(sc); 5454d52a575SXin LI et_stop_txdma(sc); 5464d52a575SXin LI 5474d52a575SXin LI et_disable_intrs(sc); 5484d52a575SXin LI 5494d52a575SXin LI et_free_tx_ring(sc); 5504d52a575SXin LI et_free_rx_ring(sc); 5514d52a575SXin LI 5524d52a575SXin LI et_reset(sc); 5534d52a575SXin LI 5544d52a575SXin LI sc->sc_tx = 0; 5554d52a575SXin LI sc->sc_tx_intr = 0; 5564d52a575SXin LI sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 5574d52a575SXin LI 5584d52a575SXin LI sc->watchdog_timer = 0; 5594d52a575SXin LI ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 5604d52a575SXin LI } 5614d52a575SXin LI 5624d52a575SXin LI static int 5638b3c6496SPyun YongHyeon et_bus_config(struct et_softc *sc) 5644d52a575SXin LI { 5654d52a575SXin LI uint32_t val, max_plsz; 5664d52a575SXin LI uint16_t ack_latency, replay_timer; 5674d52a575SXin LI 5684d52a575SXin LI /* 5694d52a575SXin LI * Test whether EEPROM is valid 5704d52a575SXin LI * NOTE: Read twice to get the correct value 5714d52a575SXin LI */ 5728b3c6496SPyun YongHyeon pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 5738b3c6496SPyun YongHyeon val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 5744d52a575SXin LI if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 5758b3c6496SPyun YongHyeon device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 576398f1b65SPyun YongHyeon return (ENXIO); 5774d52a575SXin LI } 5784d52a575SXin LI 5794d52a575SXin LI /* TODO: LED */ 5804d52a575SXin LI 5818b3c6496SPyun YongHyeon if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 5828b3c6496SPyun YongHyeon return (0); 5838b3c6496SPyun YongHyeon 5844d52a575SXin LI /* 5854d52a575SXin LI * Configure ACK latency and replay timer according to 5864d52a575SXin LI * max playload size 5874d52a575SXin LI */ 5888b3c6496SPyun YongHyeon val = pci_read_config(sc->dev, 5898b3c6496SPyun YongHyeon sc->sc_expcap + PCIR_EXPRESS_DEVICE_CAP, 4); 5908b3c6496SPyun YongHyeon max_plsz = val & PCIM_EXP_CAP_MAX_PAYLOAD; 5914d52a575SXin LI 5924d52a575SXin LI switch (max_plsz) { 5934d52a575SXin LI case ET_PCIV_DEVICE_CAPS_PLSZ_128: 5944d52a575SXin LI ack_latency = ET_PCIV_ACK_LATENCY_128; 5954d52a575SXin LI replay_timer = ET_PCIV_REPLAY_TIMER_128; 5964d52a575SXin LI break; 5974d52a575SXin LI 5984d52a575SXin LI case ET_PCIV_DEVICE_CAPS_PLSZ_256: 5994d52a575SXin LI ack_latency = ET_PCIV_ACK_LATENCY_256; 6004d52a575SXin LI replay_timer = ET_PCIV_REPLAY_TIMER_256; 6014d52a575SXin LI break; 6024d52a575SXin LI 6034d52a575SXin LI default: 6048b3c6496SPyun YongHyeon ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 6058b3c6496SPyun YongHyeon replay_timer = pci_read_config(sc->dev, 6068b3c6496SPyun YongHyeon ET_PCIR_REPLAY_TIMER, 2); 6078b3c6496SPyun YongHyeon device_printf(sc->dev, "ack latency %u, replay timer %u\n", 6084d52a575SXin LI ack_latency, replay_timer); 6094d52a575SXin LI break; 6104d52a575SXin LI } 6114d52a575SXin LI if (ack_latency != 0) { 6128b3c6496SPyun YongHyeon pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 6138b3c6496SPyun YongHyeon pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 6148b3c6496SPyun YongHyeon 2); 6154d52a575SXin LI } 6164d52a575SXin LI 6174d52a575SXin LI /* 6184d52a575SXin LI * Set L0s and L1 latency timer to 2us 6194d52a575SXin LI */ 6208b3c6496SPyun YongHyeon val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 62123263665SPyun YongHyeon val &= ~(PCIM_LINK_CAP_L0S_EXIT | PCIM_LINK_CAP_L1_EXIT); 62223263665SPyun YongHyeon /* L0s exit latency : 2us */ 62323263665SPyun YongHyeon val |= 0x00005000; 62423263665SPyun YongHyeon /* L1 exit latency : 2us */ 62523263665SPyun YongHyeon val |= 0x00028000; 6268b3c6496SPyun YongHyeon pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 6274d52a575SXin LI 6284d52a575SXin LI /* 6294d52a575SXin LI * Set max read request size to 2048 bytes 6304d52a575SXin LI */ 6318b3c6496SPyun YongHyeon val = pci_read_config(sc->dev, 6328b3c6496SPyun YongHyeon sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 6338b3c6496SPyun YongHyeon val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; 6344d52a575SXin LI val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K; 6358b3c6496SPyun YongHyeon pci_write_config(sc->dev, 6368b3c6496SPyun YongHyeon sc->sc_expcap + PCIR_EXPRESS_DEVICE_CTL, val, 2); 6374d52a575SXin LI 638398f1b65SPyun YongHyeon return (0); 6394d52a575SXin LI } 6404d52a575SXin LI 6414d52a575SXin LI static void 6424d52a575SXin LI et_get_eaddr(device_t dev, uint8_t eaddr[]) 6434d52a575SXin LI { 6444d52a575SXin LI uint32_t val; 6454d52a575SXin LI int i; 6464d52a575SXin LI 6474d52a575SXin LI val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 6484d52a575SXin LI for (i = 0; i < 4; ++i) 6494d52a575SXin LI eaddr[i] = (val >> (8 * i)) & 0xff; 6504d52a575SXin LI 6514d52a575SXin LI val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 6524d52a575SXin LI for (; i < ETHER_ADDR_LEN; ++i) 6534d52a575SXin LI eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 6544d52a575SXin LI } 6554d52a575SXin LI 6564d52a575SXin LI static void 6574d52a575SXin LI et_reset(struct et_softc *sc) 6584d52a575SXin LI { 6594d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 6604d52a575SXin LI ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 6614d52a575SXin LI ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 6624d52a575SXin LI ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 6634d52a575SXin LI 6644d52a575SXin LI CSR_WRITE_4(sc, ET_SWRST, 6654d52a575SXin LI ET_SWRST_TXDMA | ET_SWRST_RXDMA | 6664d52a575SXin LI ET_SWRST_TXMAC | ET_SWRST_RXMAC | 6674d52a575SXin LI ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 6684d52a575SXin LI 6694d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 6704d52a575SXin LI ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 6714d52a575SXin LI ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 6724d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 6734d52a575SXin LI } 6744d52a575SXin LI 6754d52a575SXin LI static void 6764d52a575SXin LI et_disable_intrs(struct et_softc *sc) 6774d52a575SXin LI { 6784d52a575SXin LI CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 6794d52a575SXin LI } 6804d52a575SXin LI 6814d52a575SXin LI static void 6824d52a575SXin LI et_enable_intrs(struct et_softc *sc, uint32_t intrs) 6834d52a575SXin LI { 6844d52a575SXin LI CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs); 6854d52a575SXin LI } 6864d52a575SXin LI 687*05884511SPyun YongHyeon struct et_dmamap_arg { 688*05884511SPyun YongHyeon bus_addr_t et_busaddr; 689*05884511SPyun YongHyeon }; 690*05884511SPyun YongHyeon 691*05884511SPyun YongHyeon static void 692*05884511SPyun YongHyeon et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 6934d52a575SXin LI { 694*05884511SPyun YongHyeon struct et_dmamap_arg *ctx; 695*05884511SPyun YongHyeon 696*05884511SPyun YongHyeon if (error) 697*05884511SPyun YongHyeon return; 698*05884511SPyun YongHyeon 699*05884511SPyun YongHyeon KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 700*05884511SPyun YongHyeon 701*05884511SPyun YongHyeon ctx = arg; 702*05884511SPyun YongHyeon ctx->et_busaddr = segs->ds_addr; 703*05884511SPyun YongHyeon } 704*05884511SPyun YongHyeon 705*05884511SPyun YongHyeon static int 706*05884511SPyun YongHyeon et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 707*05884511SPyun YongHyeon bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 708*05884511SPyun YongHyeon const char *msg) 709*05884511SPyun YongHyeon { 710*05884511SPyun YongHyeon struct et_dmamap_arg ctx; 711*05884511SPyun YongHyeon int error; 712*05884511SPyun YongHyeon 713*05884511SPyun YongHyeon error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 714*05884511SPyun YongHyeon BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 715*05884511SPyun YongHyeon tag); 716*05884511SPyun YongHyeon if (error != 0) { 717*05884511SPyun YongHyeon device_printf(sc->dev, "could not create %s dma tag\n", msg); 718*05884511SPyun YongHyeon return (error); 719*05884511SPyun YongHyeon } 720*05884511SPyun YongHyeon /* Allocate DMA'able memory for ring. */ 721*05884511SPyun YongHyeon error = bus_dmamem_alloc(*tag, (void **)ring, 722*05884511SPyun YongHyeon BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 723*05884511SPyun YongHyeon if (error != 0) { 724*05884511SPyun YongHyeon device_printf(sc->dev, 725*05884511SPyun YongHyeon "could not allocate DMA'able memory for %s\n", msg); 726*05884511SPyun YongHyeon return (error); 727*05884511SPyun YongHyeon } 728*05884511SPyun YongHyeon /* Load the address of the ring. */ 729*05884511SPyun YongHyeon ctx.et_busaddr = 0; 730*05884511SPyun YongHyeon error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 731*05884511SPyun YongHyeon &ctx, BUS_DMA_NOWAIT); 732*05884511SPyun YongHyeon if (error != 0) { 733*05884511SPyun YongHyeon device_printf(sc->dev, 734*05884511SPyun YongHyeon "could not load DMA'able memory for %s\n", msg); 735*05884511SPyun YongHyeon return (error); 736*05884511SPyun YongHyeon } 737*05884511SPyun YongHyeon *paddr = ctx.et_busaddr; 738*05884511SPyun YongHyeon return (0); 739*05884511SPyun YongHyeon } 740*05884511SPyun YongHyeon 741*05884511SPyun YongHyeon static void 742*05884511SPyun YongHyeon et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 743*05884511SPyun YongHyeon bus_dmamap_t *map) 744*05884511SPyun YongHyeon { 745*05884511SPyun YongHyeon 746*05884511SPyun YongHyeon if (*map != NULL) 747*05884511SPyun YongHyeon bus_dmamap_unload(*tag, *map); 748*05884511SPyun YongHyeon if (*map != NULL && *ring != NULL) { 749*05884511SPyun YongHyeon bus_dmamem_free(*tag, *ring, *map); 750*05884511SPyun YongHyeon *ring = NULL; 751*05884511SPyun YongHyeon *map = NULL; 752*05884511SPyun YongHyeon } 753*05884511SPyun YongHyeon if (*tag) { 754*05884511SPyun YongHyeon bus_dma_tag_destroy(*tag); 755*05884511SPyun YongHyeon *tag = NULL; 756*05884511SPyun YongHyeon } 757*05884511SPyun YongHyeon } 758*05884511SPyun YongHyeon 759*05884511SPyun YongHyeon static int 760*05884511SPyun YongHyeon et_dma_alloc(struct et_softc *sc) 761*05884511SPyun YongHyeon { 762*05884511SPyun YongHyeon struct et_txdesc_ring *tx_ring; 763*05884511SPyun YongHyeon struct et_rxdesc_ring *rx_ring; 764*05884511SPyun YongHyeon struct et_rxstat_ring *rxst_ring; 765*05884511SPyun YongHyeon struct et_rxstatus_data *rxsd; 766*05884511SPyun YongHyeon struct et_rxbuf_data *rbd; 767*05884511SPyun YongHyeon struct et_txbuf_data *tbd; 768*05884511SPyun YongHyeon struct et_txstatus_data *txsd; 7694d52a575SXin LI int i, error; 7704d52a575SXin LI 771*05884511SPyun YongHyeon error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 772*05884511SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 773*05884511SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 774*05884511SPyun YongHyeon &sc->sc_dtag); 775*05884511SPyun YongHyeon if (error != 0) { 776*05884511SPyun YongHyeon device_printf(sc->dev, "could not allocate parent dma tag\n"); 777398f1b65SPyun YongHyeon return (error); 7784d52a575SXin LI } 7794d52a575SXin LI 780*05884511SPyun YongHyeon /* TX ring. */ 781*05884511SPyun YongHyeon tx_ring = &sc->sc_tx_ring; 782*05884511SPyun YongHyeon error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 783*05884511SPyun YongHyeon &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 784*05884511SPyun YongHyeon &tx_ring->tr_paddr, "TX ring"); 7854d52a575SXin LI if (error) 786398f1b65SPyun YongHyeon return (error); 7874d52a575SXin LI 788*05884511SPyun YongHyeon /* TX status block. */ 789*05884511SPyun YongHyeon txsd = &sc->sc_tx_status; 790*05884511SPyun YongHyeon error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 791*05884511SPyun YongHyeon &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 792*05884511SPyun YongHyeon &txsd->txsd_paddr, "TX status block"); 793*05884511SPyun YongHyeon if (error) 794*05884511SPyun YongHyeon return (error); 7954d52a575SXin LI 796*05884511SPyun YongHyeon /* RX ring 0, used as to recive small sized frames. */ 797*05884511SPyun YongHyeon rx_ring = &sc->sc_rx_ring[0]; 798*05884511SPyun YongHyeon error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 799*05884511SPyun YongHyeon &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 800*05884511SPyun YongHyeon &rx_ring->rr_paddr, "RX ring 0"); 801*05884511SPyun YongHyeon rx_ring->rr_posreg = ET_RX_RING0_POS; 802*05884511SPyun YongHyeon if (error) 803*05884511SPyun YongHyeon return (error); 8044d52a575SXin LI 805*05884511SPyun YongHyeon /* RX ring 1, used as to store normal sized frames. */ 806*05884511SPyun YongHyeon rx_ring = &sc->sc_rx_ring[1]; 807*05884511SPyun YongHyeon error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 808*05884511SPyun YongHyeon &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 809*05884511SPyun YongHyeon &rx_ring->rr_paddr, "RX ring 1"); 810*05884511SPyun YongHyeon rx_ring->rr_posreg = ET_RX_RING1_POS; 811*05884511SPyun YongHyeon if (error) 812*05884511SPyun YongHyeon return (error); 8134d52a575SXin LI 814*05884511SPyun YongHyeon /* RX stat ring. */ 815*05884511SPyun YongHyeon rxst_ring = &sc->sc_rxstat_ring; 816*05884511SPyun YongHyeon error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 817*05884511SPyun YongHyeon &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 818*05884511SPyun YongHyeon &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 819*05884511SPyun YongHyeon if (error) 820*05884511SPyun YongHyeon return (error); 8214d52a575SXin LI 822*05884511SPyun YongHyeon /* RX status block. */ 823*05884511SPyun YongHyeon rxsd = &sc->sc_rx_status; 824*05884511SPyun YongHyeon error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 825*05884511SPyun YongHyeon sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 826*05884511SPyun YongHyeon (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 827*05884511SPyun YongHyeon &rxsd->rxsd_paddr, "RX status block"); 828*05884511SPyun YongHyeon if (error) 829*05884511SPyun YongHyeon return (error); 8304d52a575SXin LI 831*05884511SPyun YongHyeon /* Create parent DMA tag for mbufs. */ 832*05884511SPyun YongHyeon error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 833*05884511SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 834*05884511SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 835*05884511SPyun YongHyeon &sc->sc_mbuf_dtag); 836*05884511SPyun YongHyeon if (error != 0) { 837*05884511SPyun YongHyeon device_printf(sc->dev, 838*05884511SPyun YongHyeon "could not allocate parent dma tag for mbuf\n"); 839398f1b65SPyun YongHyeon return (error); 8404d52a575SXin LI } 8414d52a575SXin LI 842*05884511SPyun YongHyeon /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 843*05884511SPyun YongHyeon error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 844*05884511SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 845*05884511SPyun YongHyeon MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 8464d52a575SXin LI if (error) { 847*05884511SPyun YongHyeon device_printf(sc->dev, "could not create mini RX dma tag\n"); 848398f1b65SPyun YongHyeon return (error); 8494d52a575SXin LI } 8504d52a575SXin LI 851*05884511SPyun YongHyeon /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 852*05884511SPyun YongHyeon error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 853*05884511SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 854*05884511SPyun YongHyeon MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 8554d52a575SXin LI if (error) { 856*05884511SPyun YongHyeon device_printf(sc->dev, "could not create RX dma tag\n"); 857398f1b65SPyun YongHyeon return (error); 8584d52a575SXin LI } 8594d52a575SXin LI 860*05884511SPyun YongHyeon /* Create DMA tag for TX mbufs. */ 861*05884511SPyun YongHyeon error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 862*05884511SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 863*05884511SPyun YongHyeon MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 864*05884511SPyun YongHyeon &sc->sc_tx_tag); 865*05884511SPyun YongHyeon if (error) { 866*05884511SPyun YongHyeon device_printf(sc->dev, "could not create TX dma tag\n"); 867*05884511SPyun YongHyeon return (error); 868*05884511SPyun YongHyeon } 869*05884511SPyun YongHyeon 870*05884511SPyun YongHyeon /* Initialize RX ring 0. */ 871*05884511SPyun YongHyeon rbd = &sc->sc_rx_data[0]; 872*05884511SPyun YongHyeon rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 873*05884511SPyun YongHyeon rbd->rbd_newbuf = et_newbuf_hdr; 874*05884511SPyun YongHyeon rbd->rbd_discard = et_rxbuf_discard; 8754d52a575SXin LI rbd->rbd_softc = sc; 876*05884511SPyun YongHyeon rbd->rbd_ring = &sc->sc_rx_ring[0]; 877*05884511SPyun YongHyeon /* Create DMA maps for mini RX buffers, ring 0. */ 878*05884511SPyun YongHyeon for (i = 0; i < ET_RX_NDESC; i++) { 879*05884511SPyun YongHyeon error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 880*05884511SPyun YongHyeon &rbd->rbd_buf[i].rb_dmap); 881*05884511SPyun YongHyeon if (error) { 882*05884511SPyun YongHyeon device_printf(sc->dev, 883*05884511SPyun YongHyeon "could not create DMA map for mini RX mbufs\n"); 884*05884511SPyun YongHyeon return (error); 885*05884511SPyun YongHyeon } 8864d52a575SXin LI } 8874d52a575SXin LI 888*05884511SPyun YongHyeon /* Create a spare DMA map for mini RX buffers, ring 0. */ 889*05884511SPyun YongHyeon error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 890*05884511SPyun YongHyeon &sc->sc_rx_mini_sparemap); 891*05884511SPyun YongHyeon if (error) { 892*05884511SPyun YongHyeon device_printf(sc->dev, 893*05884511SPyun YongHyeon "could not create spare DMA map for mini RX mbuf\n"); 894*05884511SPyun YongHyeon return (error); 895*05884511SPyun YongHyeon } 896*05884511SPyun YongHyeon 897*05884511SPyun YongHyeon /* Initialize RX ring 1. */ 898*05884511SPyun YongHyeon rbd = &sc->sc_rx_data[1]; 899*05884511SPyun YongHyeon rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 900*05884511SPyun YongHyeon rbd->rbd_newbuf = et_newbuf_cluster; 901*05884511SPyun YongHyeon rbd->rbd_discard = et_rxbuf_discard; 902*05884511SPyun YongHyeon rbd->rbd_softc = sc; 903*05884511SPyun YongHyeon rbd->rbd_ring = &sc->sc_rx_ring[1]; 904*05884511SPyun YongHyeon /* Create DMA maps for standard RX buffers, ring 1. */ 905*05884511SPyun YongHyeon for (i = 0; i < ET_RX_NDESC; i++) { 906*05884511SPyun YongHyeon error = bus_dmamap_create(sc->sc_rx_tag, 0, 907*05884511SPyun YongHyeon &rbd->rbd_buf[i].rb_dmap); 908*05884511SPyun YongHyeon if (error) { 909*05884511SPyun YongHyeon device_printf(sc->dev, 910*05884511SPyun YongHyeon "could not create DMA map for mini RX mbufs\n"); 911*05884511SPyun YongHyeon return (error); 912*05884511SPyun YongHyeon } 913*05884511SPyun YongHyeon } 914*05884511SPyun YongHyeon 915*05884511SPyun YongHyeon /* Create a spare DMA map for standard RX buffers, ring 1. */ 916*05884511SPyun YongHyeon error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 917*05884511SPyun YongHyeon if (error) { 918*05884511SPyun YongHyeon device_printf(sc->dev, 919*05884511SPyun YongHyeon "could not create spare DMA map for RX mbuf\n"); 920*05884511SPyun YongHyeon return (error); 921*05884511SPyun YongHyeon } 922*05884511SPyun YongHyeon 923*05884511SPyun YongHyeon /* Create DMA maps for TX buffers. */ 924*05884511SPyun YongHyeon tbd = &sc->sc_tx_data; 925*05884511SPyun YongHyeon for (i = 0; i < ET_TX_NDESC; i++) { 926*05884511SPyun YongHyeon error = bus_dmamap_create(sc->sc_tx_tag, 0, 9274d52a575SXin LI &tbd->tbd_buf[i].tb_dmap); 9284d52a575SXin LI if (error) { 929*05884511SPyun YongHyeon device_printf(sc->dev, 930*05884511SPyun YongHyeon "could not create DMA map for TX mbufs\n"); 931398f1b65SPyun YongHyeon return (error); 9324d52a575SXin LI } 9334d52a575SXin LI } 9344d52a575SXin LI 935398f1b65SPyun YongHyeon return (0); 9364d52a575SXin LI } 9374d52a575SXin LI 9384d52a575SXin LI static void 939*05884511SPyun YongHyeon et_dma_free(struct et_softc *sc) 9404d52a575SXin LI { 941*05884511SPyun YongHyeon struct et_txdesc_ring *tx_ring; 942*05884511SPyun YongHyeon struct et_rxdesc_ring *rx_ring; 943*05884511SPyun YongHyeon struct et_txstatus_data *txsd; 944*05884511SPyun YongHyeon struct et_rxstat_ring *rxst_ring; 945*05884511SPyun YongHyeon struct et_rxstatus_data *rxsd; 946*05884511SPyun YongHyeon struct et_rxbuf_data *rbd; 947*05884511SPyun YongHyeon struct et_txbuf_data *tbd; 9484d52a575SXin LI int i; 9494d52a575SXin LI 950*05884511SPyun YongHyeon /* Destroy DMA maps for mini RX buffers, ring 0. */ 951*05884511SPyun YongHyeon rbd = &sc->sc_rx_data[0]; 952*05884511SPyun YongHyeon for (i = 0; i < ET_RX_NDESC; i++) { 953*05884511SPyun YongHyeon if (rbd->rbd_buf[i].rb_dmap) { 954*05884511SPyun YongHyeon bus_dmamap_destroy(sc->sc_rx_mini_tag, 955*05884511SPyun YongHyeon rbd->rbd_buf[i].rb_dmap); 956*05884511SPyun YongHyeon rbd->rbd_buf[i].rb_dmap = NULL; 9574d52a575SXin LI } 9584d52a575SXin LI } 959*05884511SPyun YongHyeon if (sc->sc_rx_mini_sparemap) { 960*05884511SPyun YongHyeon bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 961*05884511SPyun YongHyeon sc->sc_rx_mini_sparemap = NULL; 962*05884511SPyun YongHyeon } 963*05884511SPyun YongHyeon if (sc->sc_rx_mini_tag) { 964*05884511SPyun YongHyeon bus_dma_tag_destroy(sc->sc_rx_mini_tag); 965*05884511SPyun YongHyeon sc->sc_rx_mini_tag = NULL; 9664d52a575SXin LI } 9674d52a575SXin LI 968*05884511SPyun YongHyeon /* Destroy DMA maps for standard RX buffers, ring 1. */ 969*05884511SPyun YongHyeon rbd = &sc->sc_rx_data[1]; 970*05884511SPyun YongHyeon for (i = 0; i < ET_RX_NDESC; i++) { 971*05884511SPyun YongHyeon if (rbd->rbd_buf[i].rb_dmap) { 972*05884511SPyun YongHyeon bus_dmamap_destroy(sc->sc_rx_tag, 973*05884511SPyun YongHyeon rbd->rbd_buf[i].rb_dmap); 974*05884511SPyun YongHyeon rbd->rbd_buf[i].rb_dmap = NULL; 9754d52a575SXin LI } 9764d52a575SXin LI } 977*05884511SPyun YongHyeon if (sc->sc_rx_sparemap) { 978*05884511SPyun YongHyeon bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 979*05884511SPyun YongHyeon sc->sc_rx_sparemap = NULL; 980*05884511SPyun YongHyeon } 981*05884511SPyun YongHyeon if (sc->sc_rx_tag) { 982*05884511SPyun YongHyeon bus_dma_tag_destroy(sc->sc_rx_tag); 983*05884511SPyun YongHyeon sc->sc_rx_tag = NULL; 984*05884511SPyun YongHyeon } 9854d52a575SXin LI 986*05884511SPyun YongHyeon /* Destroy DMA maps for TX buffers. */ 987*05884511SPyun YongHyeon tbd = &sc->sc_tx_data; 988*05884511SPyun YongHyeon for (i = 0; i < ET_TX_NDESC; i++) { 989*05884511SPyun YongHyeon if (tbd->tbd_buf[i].tb_dmap) { 990*05884511SPyun YongHyeon bus_dmamap_destroy(sc->sc_tx_tag, 991*05884511SPyun YongHyeon tbd->tbd_buf[i].tb_dmap); 992*05884511SPyun YongHyeon tbd->tbd_buf[i].tb_dmap = NULL; 993*05884511SPyun YongHyeon } 994*05884511SPyun YongHyeon } 995*05884511SPyun YongHyeon if (sc->sc_tx_tag) { 996*05884511SPyun YongHyeon bus_dma_tag_destroy(sc->sc_tx_tag); 997*05884511SPyun YongHyeon sc->sc_tx_tag = NULL; 998*05884511SPyun YongHyeon } 999*05884511SPyun YongHyeon 1000*05884511SPyun YongHyeon /* Destroy mini RX ring, ring 0. */ 1001*05884511SPyun YongHyeon rx_ring = &sc->sc_rx_ring[0]; 1002*05884511SPyun YongHyeon et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1003*05884511SPyun YongHyeon &rx_ring->rr_dmap); 1004*05884511SPyun YongHyeon /* Destroy standard RX ring, ring 1. */ 1005*05884511SPyun YongHyeon rx_ring = &sc->sc_rx_ring[1]; 1006*05884511SPyun YongHyeon et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1007*05884511SPyun YongHyeon &rx_ring->rr_dmap); 1008*05884511SPyun YongHyeon /* Destroy RX stat ring. */ 1009*05884511SPyun YongHyeon rxst_ring = &sc->sc_rxstat_ring; 1010*05884511SPyun YongHyeon et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1011*05884511SPyun YongHyeon &rxst_ring->rsr_dmap); 1012*05884511SPyun YongHyeon /* Destroy RX status block. */ 1013*05884511SPyun YongHyeon rxsd = &sc->sc_rx_status; 1014*05884511SPyun YongHyeon et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1015*05884511SPyun YongHyeon &rxst_ring->rsr_dmap); 1016*05884511SPyun YongHyeon /* Destroy TX ring. */ 1017*05884511SPyun YongHyeon tx_ring = &sc->sc_tx_ring; 1018*05884511SPyun YongHyeon et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1019*05884511SPyun YongHyeon &tx_ring->tr_dmap); 1020*05884511SPyun YongHyeon /* Destroy TX status block. */ 1021*05884511SPyun YongHyeon txsd = &sc->sc_tx_status; 1022*05884511SPyun YongHyeon et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1023*05884511SPyun YongHyeon &txsd->txsd_dmap); 1024*05884511SPyun YongHyeon 1025*05884511SPyun YongHyeon /* Destroy the parent tag. */ 1026*05884511SPyun YongHyeon if (sc->sc_dtag) { 1027*05884511SPyun YongHyeon bus_dma_tag_destroy(sc->sc_dtag); 1028*05884511SPyun YongHyeon sc->sc_dtag = NULL; 1029*05884511SPyun YongHyeon } 10304d52a575SXin LI } 10314d52a575SXin LI 10324d52a575SXin LI static void 10334d52a575SXin LI et_chip_attach(struct et_softc *sc) 10344d52a575SXin LI { 10354d52a575SXin LI uint32_t val; 10364d52a575SXin LI 10374d52a575SXin LI /* 10384d52a575SXin LI * Perform minimal initialization 10394d52a575SXin LI */ 10404d52a575SXin LI 10414d52a575SXin LI /* Disable loopback */ 10424d52a575SXin LI CSR_WRITE_4(sc, ET_LOOPBACK, 0); 10434d52a575SXin LI 10444d52a575SXin LI /* Reset MAC */ 10454d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 10464d52a575SXin LI ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 10474d52a575SXin LI ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 10484d52a575SXin LI ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 10494d52a575SXin LI 10504d52a575SXin LI /* 10514d52a575SXin LI * Setup half duplex mode 10524d52a575SXin LI */ 105323263665SPyun YongHyeon val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 105423263665SPyun YongHyeon (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 105523263665SPyun YongHyeon (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 10564d52a575SXin LI ET_MAC_HDX_EXC_DEFER; 10574d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_HDX, val); 10584d52a575SXin LI 10594d52a575SXin LI /* Clear MAC control */ 10604d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 10614d52a575SXin LI 10624d52a575SXin LI /* Reset MII */ 10634d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 10644d52a575SXin LI 10654d52a575SXin LI /* Bring MAC out of reset state */ 10664d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 10674d52a575SXin LI 10684d52a575SXin LI /* Enable memory controllers */ 10694d52a575SXin LI CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 10704d52a575SXin LI } 10714d52a575SXin LI 10724d52a575SXin LI static void 10734d52a575SXin LI et_intr(void *xsc) 10744d52a575SXin LI { 10754d52a575SXin LI struct et_softc *sc = xsc; 10764d52a575SXin LI struct ifnet *ifp; 10774d52a575SXin LI uint32_t intrs; 10784d52a575SXin LI 10794d52a575SXin LI ET_LOCK(sc); 10804d52a575SXin LI ifp = sc->ifp; 10814d52a575SXin LI if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 10824d52a575SXin LI ET_UNLOCK(sc); 10834d52a575SXin LI return; 10844d52a575SXin LI } 10854d52a575SXin LI 10864d52a575SXin LI et_disable_intrs(sc); 10874d52a575SXin LI 10884d52a575SXin LI intrs = CSR_READ_4(sc, ET_INTR_STATUS); 10894d52a575SXin LI intrs &= ET_INTRS; 10904d52a575SXin LI if (intrs == 0) /* Not interested */ 10914d52a575SXin LI goto back; 10924d52a575SXin LI 10934d52a575SXin LI if (intrs & ET_INTR_RXEOF) 10944d52a575SXin LI et_rxeof(sc); 10954d52a575SXin LI if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER)) 10964d52a575SXin LI et_txeof(sc); 10974d52a575SXin LI if (intrs & ET_INTR_TIMER) 10984d52a575SXin LI CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 10994d52a575SXin LI back: 11004d52a575SXin LI et_enable_intrs(sc, ET_INTRS); 11014d52a575SXin LI ET_UNLOCK(sc); 11024d52a575SXin LI } 11034d52a575SXin LI 11044d52a575SXin LI static void 11054d52a575SXin LI et_init_locked(struct et_softc *sc) 11064d52a575SXin LI { 1107*05884511SPyun YongHyeon struct ifnet *ifp; 1108*05884511SPyun YongHyeon int error; 11094d52a575SXin LI 11104d52a575SXin LI ET_LOCK_ASSERT(sc); 11114d52a575SXin LI 1112*05884511SPyun YongHyeon ifp = sc->ifp; 11134d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) 11144d52a575SXin LI return; 11154d52a575SXin LI 11164d52a575SXin LI et_stop(sc); 11174d52a575SXin LI 1118*05884511SPyun YongHyeon et_init_tx_ring(sc); 11194d52a575SXin LI error = et_init_rx_ring(sc); 11204d52a575SXin LI if (error) 1121*05884511SPyun YongHyeon return; 11224d52a575SXin LI 11234d52a575SXin LI error = et_chip_init(sc); 11244d52a575SXin LI if (error) 11254d52a575SXin LI goto back; 11264d52a575SXin LI 11274d52a575SXin LI error = et_enable_txrx(sc, 1); 11284d52a575SXin LI if (error) 11294d52a575SXin LI goto back; 11304d52a575SXin LI 11314d52a575SXin LI et_enable_intrs(sc, ET_INTRS); 11324d52a575SXin LI 11334d52a575SXin LI callout_reset(&sc->sc_tick, hz, et_tick, sc); 11344d52a575SXin LI 11354d52a575SXin LI CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 11364d52a575SXin LI 11374d52a575SXin LI ifp->if_drv_flags |= IFF_DRV_RUNNING; 11384d52a575SXin LI ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 11394d52a575SXin LI back: 11404d52a575SXin LI if (error) 11414d52a575SXin LI et_stop(sc); 11424d52a575SXin LI } 11434d52a575SXin LI 11444d52a575SXin LI static void 11454d52a575SXin LI et_init(void *xsc) 11464d52a575SXin LI { 11474d52a575SXin LI struct et_softc *sc = xsc; 11484d52a575SXin LI 11494d52a575SXin LI ET_LOCK(sc); 11504d52a575SXin LI et_init_locked(sc); 11514d52a575SXin LI ET_UNLOCK(sc); 11524d52a575SXin LI } 11534d52a575SXin LI 11544d52a575SXin LI static int 11554d52a575SXin LI et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 11564d52a575SXin LI { 11574d52a575SXin LI struct et_softc *sc = ifp->if_softc; 11584d52a575SXin LI struct mii_data *mii = device_get_softc(sc->sc_miibus); 11594d52a575SXin LI struct ifreq *ifr = (struct ifreq *)data; 11609955274cSPyun YongHyeon int error = 0, mask, max_framelen; 11614d52a575SXin LI 11624d52a575SXin LI /* XXX LOCKSUSED */ 11634d52a575SXin LI switch (cmd) { 11644d52a575SXin LI case SIOCSIFFLAGS: 11654d52a575SXin LI ET_LOCK(sc); 11664d52a575SXin LI if (ifp->if_flags & IFF_UP) { 11674d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 11684d52a575SXin LI if ((ifp->if_flags ^ sc->sc_if_flags) & 11694d52a575SXin LI (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 11704d52a575SXin LI et_setmulti(sc); 11714d52a575SXin LI } else { 11724d52a575SXin LI et_init_locked(sc); 11734d52a575SXin LI } 11744d52a575SXin LI } else { 11754d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) 11764d52a575SXin LI et_stop(sc); 11774d52a575SXin LI } 11784d52a575SXin LI sc->sc_if_flags = ifp->if_flags; 11794d52a575SXin LI ET_UNLOCK(sc); 11804d52a575SXin LI break; 11814d52a575SXin LI 11824d52a575SXin LI case SIOCSIFMEDIA: 11834d52a575SXin LI case SIOCGIFMEDIA: 11844d52a575SXin LI error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 11854d52a575SXin LI break; 11864d52a575SXin LI 11874d52a575SXin LI case SIOCADDMULTI: 11884d52a575SXin LI case SIOCDELMULTI: 11894d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 11904d52a575SXin LI ET_LOCK(sc); 11914d52a575SXin LI et_setmulti(sc); 11924d52a575SXin LI ET_UNLOCK(sc); 11934d52a575SXin LI error = 0; 11944d52a575SXin LI } 11954d52a575SXin LI break; 11964d52a575SXin LI 11974d52a575SXin LI case SIOCSIFMTU: 11984d52a575SXin LI #if 0 11994d52a575SXin LI if (sc->sc_flags & ET_FLAG_JUMBO) 12004d52a575SXin LI max_framelen = ET_JUMBO_FRAMELEN; 12014d52a575SXin LI else 12024d52a575SXin LI #endif 12034d52a575SXin LI max_framelen = MCLBYTES - 1; 12044d52a575SXin LI 12054d52a575SXin LI if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 12064d52a575SXin LI error = EOPNOTSUPP; 12074d52a575SXin LI break; 12084d52a575SXin LI } 12094d52a575SXin LI 12104d52a575SXin LI if (ifp->if_mtu != ifr->ifr_mtu) { 12114d52a575SXin LI ifp->if_mtu = ifr->ifr_mtu; 12124d52a575SXin LI ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 12134d52a575SXin LI et_init(sc); 12144d52a575SXin LI } 12154d52a575SXin LI break; 12164d52a575SXin LI 12179955274cSPyun YongHyeon case SIOCSIFCAP: 12189955274cSPyun YongHyeon ET_LOCK(sc); 12199955274cSPyun YongHyeon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 12209955274cSPyun YongHyeon if ((mask & IFCAP_TXCSUM) != 0 && 12219955274cSPyun YongHyeon (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 12229955274cSPyun YongHyeon ifp->if_capenable ^= IFCAP_TXCSUM; 12239955274cSPyun YongHyeon if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 12249955274cSPyun YongHyeon ifp->if_hwassist |= ET_CSUM_FEATURES; 12259955274cSPyun YongHyeon else 12269955274cSPyun YongHyeon ifp->if_hwassist &= ~ET_CSUM_FEATURES; 12279955274cSPyun YongHyeon } 12289955274cSPyun YongHyeon ET_UNLOCK(sc); 12299955274cSPyun YongHyeon break; 12309955274cSPyun YongHyeon 12314d52a575SXin LI default: 12324d52a575SXin LI error = ether_ioctl(ifp, cmd, data); 12334d52a575SXin LI break; 12344d52a575SXin LI } 1235398f1b65SPyun YongHyeon return (error); 12364d52a575SXin LI } 12374d52a575SXin LI 12384d52a575SXin LI static void 12394d52a575SXin LI et_start_locked(struct ifnet *ifp) 12404d52a575SXin LI { 1241c8b727ceSPyun YongHyeon struct et_softc *sc; 1242c8b727ceSPyun YongHyeon struct mbuf *m_head = NULL; 12434d52a575SXin LI struct et_txbuf_data *tbd; 1244c8b727ceSPyun YongHyeon int enq; 12454d52a575SXin LI 1246c8b727ceSPyun YongHyeon sc = ifp->if_softc; 12474d52a575SXin LI ET_LOCK_ASSERT(sc); 12484d52a575SXin LI 12494d52a575SXin LI if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 12504d52a575SXin LI return; 12514d52a575SXin LI 12524d52a575SXin LI if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) 12534d52a575SXin LI return; 12544d52a575SXin LI 1255c8b727ceSPyun YongHyeon tbd = &sc->sc_tx_data; 1256c8b727ceSPyun YongHyeon for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1257c8b727ceSPyun YongHyeon if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 12584d52a575SXin LI ifp->if_drv_flags |= IFF_DRV_OACTIVE; 12594d52a575SXin LI break; 12604d52a575SXin LI } 12614d52a575SXin LI 1262c8b727ceSPyun YongHyeon IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1263c8b727ceSPyun YongHyeon if (m_head == NULL) 12644d52a575SXin LI break; 12654d52a575SXin LI 1266c8b727ceSPyun YongHyeon if (et_encap(sc, &m_head)) { 1267c8b727ceSPyun YongHyeon if (m_head == NULL) { 12684d52a575SXin LI ifp->if_oerrors++; 1269c8b727ceSPyun YongHyeon break; 1270c8b727ceSPyun YongHyeon } 1271c8b727ceSPyun YongHyeon IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1272c8b727ceSPyun YongHyeon if (tbd->tbd_used > 0) 12734d52a575SXin LI ifp->if_drv_flags |= IFF_DRV_OACTIVE; 12744d52a575SXin LI break; 12754d52a575SXin LI } 1276c8b727ceSPyun YongHyeon enq++; 1277c8b727ceSPyun YongHyeon ETHER_BPF_MTAP(ifp, m_head); 12784d52a575SXin LI } 12794d52a575SXin LI 1280c8b727ceSPyun YongHyeon if (enq > 0) 12814d52a575SXin LI sc->watchdog_timer = 5; 12824d52a575SXin LI } 12834d52a575SXin LI 12844d52a575SXin LI static void 12854d52a575SXin LI et_start(struct ifnet *ifp) 12864d52a575SXin LI { 12874d52a575SXin LI struct et_softc *sc = ifp->if_softc; 12884d52a575SXin LI 12894d52a575SXin LI ET_LOCK(sc); 12904d52a575SXin LI et_start_locked(ifp); 12914d52a575SXin LI ET_UNLOCK(sc); 12924d52a575SXin LI } 12934d52a575SXin LI 1294*05884511SPyun YongHyeon static int 12954d52a575SXin LI et_watchdog(struct et_softc *sc) 12964d52a575SXin LI { 1297*05884511SPyun YongHyeon uint32_t status; 1298*05884511SPyun YongHyeon 12994d52a575SXin LI ET_LOCK_ASSERT(sc); 13004d52a575SXin LI 13014d52a575SXin LI if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1302*05884511SPyun YongHyeon return (0); 13034d52a575SXin LI 1304*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1305*05884511SPyun YongHyeon BUS_DMASYNC_POSTREAD); 1306*05884511SPyun YongHyeon status = le32toh(*(sc->sc_tx_status.txsd_status)); 1307*05884511SPyun YongHyeon if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1308*05884511SPyun YongHyeon status); 13094d52a575SXin LI 1310744ec7f2SPyun YongHyeon sc->ifp->if_oerrors++; 1311744ec7f2SPyun YongHyeon sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 13124d52a575SXin LI et_init_locked(sc); 1313*05884511SPyun YongHyeon return (EJUSTRETURN); 13144d52a575SXin LI } 13154d52a575SXin LI 13164d52a575SXin LI static int 13174d52a575SXin LI et_stop_rxdma(struct et_softc *sc) 13184d52a575SXin LI { 13194d52a575SXin LI CSR_WRITE_4(sc, ET_RXDMA_CTRL, 13204d52a575SXin LI ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 13214d52a575SXin LI 13224d52a575SXin LI DELAY(5); 13234d52a575SXin LI if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 13244d52a575SXin LI if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1325398f1b65SPyun YongHyeon return (ETIMEDOUT); 13264d52a575SXin LI } 1327398f1b65SPyun YongHyeon return (0); 13284d52a575SXin LI } 13294d52a575SXin LI 13304d52a575SXin LI static int 13314d52a575SXin LI et_stop_txdma(struct et_softc *sc) 13324d52a575SXin LI { 13334d52a575SXin LI CSR_WRITE_4(sc, ET_TXDMA_CTRL, 13344d52a575SXin LI ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1335398f1b65SPyun YongHyeon return (0); 13364d52a575SXin LI } 13374d52a575SXin LI 13384d52a575SXin LI static void 13394d52a575SXin LI et_free_tx_ring(struct et_softc *sc) 13404d52a575SXin LI { 1341*05884511SPyun YongHyeon struct et_txdesc_ring *tx_ring; 1342*05884511SPyun YongHyeon struct et_txbuf_data *tbd; 1343*05884511SPyun YongHyeon struct et_txbuf *tb; 13444d52a575SXin LI int i; 13454d52a575SXin LI 1346*05884511SPyun YongHyeon tbd = &sc->sc_tx_data; 1347*05884511SPyun YongHyeon tx_ring = &sc->sc_tx_ring; 13484d52a575SXin LI for (i = 0; i < ET_TX_NDESC; ++i) { 1349*05884511SPyun YongHyeon tb = &tbd->tbd_buf[i]; 13504d52a575SXin LI if (tb->tb_mbuf != NULL) { 1351*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1352*05884511SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 13534d52a575SXin LI bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 13544d52a575SXin LI m_freem(tb->tb_mbuf); 13554d52a575SXin LI tb->tb_mbuf = NULL; 13564d52a575SXin LI } 13574d52a575SXin LI } 13584d52a575SXin LI } 13594d52a575SXin LI 13604d52a575SXin LI static void 13614d52a575SXin LI et_free_rx_ring(struct et_softc *sc) 13624d52a575SXin LI { 1363*05884511SPyun YongHyeon struct et_rxbuf_data *rbd; 1364*05884511SPyun YongHyeon struct et_rxdesc_ring *rx_ring; 1365*05884511SPyun YongHyeon struct et_rxbuf *rb; 13664d52a575SXin LI int i; 13674d52a575SXin LI 1368*05884511SPyun YongHyeon /* Ring 0 */ 1369*05884511SPyun YongHyeon rx_ring = &sc->sc_rx_ring[0]; 1370*05884511SPyun YongHyeon rbd = &sc->sc_rx_data[0]; 13714d52a575SXin LI for (i = 0; i < ET_RX_NDESC; ++i) { 1372*05884511SPyun YongHyeon rb = &rbd->rbd_buf[i]; 13734d52a575SXin LI if (rb->rb_mbuf != NULL) { 1374*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1375*05884511SPyun YongHyeon BUS_DMASYNC_POSTREAD); 1376*05884511SPyun YongHyeon bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 13774d52a575SXin LI m_freem(rb->rb_mbuf); 13784d52a575SXin LI rb->rb_mbuf = NULL; 13794d52a575SXin LI } 13804d52a575SXin LI } 13814d52a575SXin LI 1382*05884511SPyun YongHyeon /* Ring 1 */ 1383*05884511SPyun YongHyeon rx_ring = &sc->sc_rx_ring[1]; 1384*05884511SPyun YongHyeon rbd = &sc->sc_rx_data[1]; 1385*05884511SPyun YongHyeon for (i = 0; i < ET_RX_NDESC; ++i) { 1386*05884511SPyun YongHyeon rb = &rbd->rbd_buf[i]; 1387*05884511SPyun YongHyeon if (rb->rb_mbuf != NULL) { 1388*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1389*05884511SPyun YongHyeon BUS_DMASYNC_POSTREAD); 1390*05884511SPyun YongHyeon bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1391*05884511SPyun YongHyeon m_freem(rb->rb_mbuf); 1392*05884511SPyun YongHyeon rb->rb_mbuf = NULL; 1393*05884511SPyun YongHyeon } 13944d52a575SXin LI } 13954d52a575SXin LI } 13964d52a575SXin LI 13974d52a575SXin LI static void 13984d52a575SXin LI et_setmulti(struct et_softc *sc) 13994d52a575SXin LI { 14004d52a575SXin LI struct ifnet *ifp; 14014d52a575SXin LI uint32_t hash[4] = { 0, 0, 0, 0 }; 14024d52a575SXin LI uint32_t rxmac_ctrl, pktfilt; 14034d52a575SXin LI struct ifmultiaddr *ifma; 14044d52a575SXin LI int i, count; 14054d52a575SXin LI 14064d52a575SXin LI ET_LOCK_ASSERT(sc); 14074d52a575SXin LI ifp = sc->ifp; 14084d52a575SXin LI 14094d52a575SXin LI pktfilt = CSR_READ_4(sc, ET_PKTFILT); 14104d52a575SXin LI rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 14114d52a575SXin LI 14124d52a575SXin LI pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 14134d52a575SXin LI if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 14144d52a575SXin LI rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 14154d52a575SXin LI goto back; 14164d52a575SXin LI } 14174d52a575SXin LI 14184d52a575SXin LI count = 0; 1419eb956cd0SRobert Watson if_maddr_rlock(ifp); 14204d52a575SXin LI TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 14214d52a575SXin LI uint32_t *hp, h; 14224d52a575SXin LI 14234d52a575SXin LI if (ifma->ifma_addr->sa_family != AF_LINK) 14244d52a575SXin LI continue; 14254d52a575SXin LI 14264d52a575SXin LI h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 14274d52a575SXin LI ifma->ifma_addr), ETHER_ADDR_LEN); 14284d52a575SXin LI h = (h & 0x3f800000) >> 23; 14294d52a575SXin LI 14304d52a575SXin LI hp = &hash[0]; 14314d52a575SXin LI if (h >= 32 && h < 64) { 14324d52a575SXin LI h -= 32; 14334d52a575SXin LI hp = &hash[1]; 14344d52a575SXin LI } else if (h >= 64 && h < 96) { 14354d52a575SXin LI h -= 64; 14364d52a575SXin LI hp = &hash[2]; 14374d52a575SXin LI } else if (h >= 96) { 14384d52a575SXin LI h -= 96; 14394d52a575SXin LI hp = &hash[3]; 14404d52a575SXin LI } 14414d52a575SXin LI *hp |= (1 << h); 14424d52a575SXin LI 14434d52a575SXin LI ++count; 14444d52a575SXin LI } 1445eb956cd0SRobert Watson if_maddr_runlock(ifp); 14464d52a575SXin LI 14474d52a575SXin LI for (i = 0; i < 4; ++i) 14484d52a575SXin LI CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 14494d52a575SXin LI 14504d52a575SXin LI if (count > 0) 14514d52a575SXin LI pktfilt |= ET_PKTFILT_MCAST; 14524d52a575SXin LI rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 14534d52a575SXin LI back: 14544d52a575SXin LI CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 14554d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 14564d52a575SXin LI } 14574d52a575SXin LI 14584d52a575SXin LI static int 14594d52a575SXin LI et_chip_init(struct et_softc *sc) 14604d52a575SXin LI { 14614d52a575SXin LI struct ifnet *ifp = sc->ifp; 14624d52a575SXin LI uint32_t rxq_end; 14634d52a575SXin LI int error, frame_len, rxmem_size; 14644d52a575SXin LI 14654d52a575SXin LI /* 14664d52a575SXin LI * Split 16Kbytes internal memory between TX and RX 14674d52a575SXin LI * according to frame length. 14684d52a575SXin LI */ 14694d52a575SXin LI frame_len = ET_FRAMELEN(ifp->if_mtu); 14704d52a575SXin LI if (frame_len < 2048) { 14714d52a575SXin LI rxmem_size = ET_MEM_RXSIZE_DEFAULT; 14724d52a575SXin LI } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 14734d52a575SXin LI rxmem_size = ET_MEM_SIZE / 2; 14744d52a575SXin LI } else { 14754d52a575SXin LI rxmem_size = ET_MEM_SIZE - 14764d52a575SXin LI roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 14774d52a575SXin LI } 14784d52a575SXin LI rxq_end = ET_QUEUE_ADDR(rxmem_size); 14794d52a575SXin LI 14804d52a575SXin LI CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 14814d52a575SXin LI CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 14824d52a575SXin LI CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 14834d52a575SXin LI CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 14844d52a575SXin LI 14854d52a575SXin LI /* No loopback */ 14864d52a575SXin LI CSR_WRITE_4(sc, ET_LOOPBACK, 0); 14874d52a575SXin LI 14884d52a575SXin LI /* Clear MSI configure */ 1489cc3c3b4eSPyun YongHyeon if ((sc->sc_flags & ET_FLAG_MSI) == 0) 14904d52a575SXin LI CSR_WRITE_4(sc, ET_MSI_CFG, 0); 14914d52a575SXin LI 14924d52a575SXin LI /* Disable timer */ 14934d52a575SXin LI CSR_WRITE_4(sc, ET_TIMER, 0); 14944d52a575SXin LI 14954d52a575SXin LI /* Initialize MAC */ 14964d52a575SXin LI et_init_mac(sc); 14974d52a575SXin LI 14984d52a575SXin LI /* Enable memory controllers */ 14994d52a575SXin LI CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 15004d52a575SXin LI 15014d52a575SXin LI /* Initialize RX MAC */ 15024d52a575SXin LI et_init_rxmac(sc); 15034d52a575SXin LI 15044d52a575SXin LI /* Initialize TX MAC */ 15054d52a575SXin LI et_init_txmac(sc); 15064d52a575SXin LI 15074d52a575SXin LI /* Initialize RX DMA engine */ 15084d52a575SXin LI error = et_init_rxdma(sc); 15094d52a575SXin LI if (error) 1510398f1b65SPyun YongHyeon return (error); 15114d52a575SXin LI 15124d52a575SXin LI /* Initialize TX DMA engine */ 15134d52a575SXin LI error = et_init_txdma(sc); 15144d52a575SXin LI if (error) 1515398f1b65SPyun YongHyeon return (error); 15164d52a575SXin LI 1517398f1b65SPyun YongHyeon return (0); 15184d52a575SXin LI } 15194d52a575SXin LI 1520*05884511SPyun YongHyeon static void 15214d52a575SXin LI et_init_tx_ring(struct et_softc *sc) 15224d52a575SXin LI { 1523*05884511SPyun YongHyeon struct et_txdesc_ring *tx_ring; 1524*05884511SPyun YongHyeon struct et_txbuf_data *tbd; 1525*05884511SPyun YongHyeon struct et_txstatus_data *txsd; 15264d52a575SXin LI 1527*05884511SPyun YongHyeon tx_ring = &sc->sc_tx_ring; 15284d52a575SXin LI bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 15294d52a575SXin LI bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 15304d52a575SXin LI BUS_DMASYNC_PREWRITE); 15314d52a575SXin LI 1532*05884511SPyun YongHyeon tbd = &sc->sc_tx_data; 15334d52a575SXin LI tbd->tbd_start_index = 0; 15344d52a575SXin LI tbd->tbd_start_wrap = 0; 15354d52a575SXin LI tbd->tbd_used = 0; 15364d52a575SXin LI 1537*05884511SPyun YongHyeon txsd = &sc->sc_tx_status; 15384d52a575SXin LI bzero(txsd->txsd_status, sizeof(uint32_t)); 15394d52a575SXin LI bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1540*05884511SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 15414d52a575SXin LI } 15424d52a575SXin LI 15434d52a575SXin LI static int 15444d52a575SXin LI et_init_rx_ring(struct et_softc *sc) 15454d52a575SXin LI { 1546*05884511SPyun YongHyeon struct et_rxstatus_data *rxsd; 1547*05884511SPyun YongHyeon struct et_rxstat_ring *rxst_ring; 1548*05884511SPyun YongHyeon struct et_rxbuf_data *rbd; 1549*05884511SPyun YongHyeon int i, error, n; 15504d52a575SXin LI 15514d52a575SXin LI for (n = 0; n < ET_RX_NRING; ++n) { 1552*05884511SPyun YongHyeon rbd = &sc->sc_rx_data[n]; 15534d52a575SXin LI for (i = 0; i < ET_RX_NDESC; ++i) { 1554*05884511SPyun YongHyeon error = rbd->rbd_newbuf(rbd, i); 15554d52a575SXin LI if (error) { 15564d52a575SXin LI if_printf(sc->ifp, "%d ring %d buf, " 15574d52a575SXin LI "newbuf failed: %d\n", n, i, error); 1558398f1b65SPyun YongHyeon return (error); 15594d52a575SXin LI } 15604d52a575SXin LI } 15614d52a575SXin LI } 15624d52a575SXin LI 1563*05884511SPyun YongHyeon rxsd = &sc->sc_rx_status; 15644d52a575SXin LI bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 15654d52a575SXin LI bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1566*05884511SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 15674d52a575SXin LI 1568*05884511SPyun YongHyeon rxst_ring = &sc->sc_rxstat_ring; 15694d52a575SXin LI bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 15704d52a575SXin LI bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1571*05884511SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 15724d52a575SXin LI 1573398f1b65SPyun YongHyeon return (0); 15744d52a575SXin LI } 15754d52a575SXin LI 15764d52a575SXin LI static int 15774d52a575SXin LI et_init_rxdma(struct et_softc *sc) 15784d52a575SXin LI { 15794d52a575SXin LI struct et_rxstatus_data *rxsd = &sc->sc_rx_status; 15804d52a575SXin LI struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring; 15814d52a575SXin LI struct et_rxdesc_ring *rx_ring; 15824d52a575SXin LI int error; 15834d52a575SXin LI 15844d52a575SXin LI error = et_stop_rxdma(sc); 15854d52a575SXin LI if (error) { 15864d52a575SXin LI if_printf(sc->ifp, "can't init RX DMA engine\n"); 1587398f1b65SPyun YongHyeon return (error); 15884d52a575SXin LI } 15894d52a575SXin LI 15904d52a575SXin LI /* 15914d52a575SXin LI * Install RX status 15924d52a575SXin LI */ 15934d52a575SXin LI CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 15944d52a575SXin LI CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 15954d52a575SXin LI 15964d52a575SXin LI /* 15974d52a575SXin LI * Install RX stat ring 15984d52a575SXin LI */ 15994d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 16004d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 16014d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 16024d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 16034d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 16044d52a575SXin LI 16054d52a575SXin LI /* Match ET_RXSTAT_POS */ 16064d52a575SXin LI rxst_ring->rsr_index = 0; 16074d52a575SXin LI rxst_ring->rsr_wrap = 0; 16084d52a575SXin LI 16094d52a575SXin LI /* 16104d52a575SXin LI * Install the 2nd RX descriptor ring 16114d52a575SXin LI */ 16124d52a575SXin LI rx_ring = &sc->sc_rx_ring[1]; 16134d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 16144d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 16154d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 16164d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 16174d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 16184d52a575SXin LI 16194d52a575SXin LI /* Match ET_RX_RING1_POS */ 16204d52a575SXin LI rx_ring->rr_index = 0; 16214d52a575SXin LI rx_ring->rr_wrap = 1; 16224d52a575SXin LI 16234d52a575SXin LI /* 16244d52a575SXin LI * Install the 1st RX descriptor ring 16254d52a575SXin LI */ 16264d52a575SXin LI rx_ring = &sc->sc_rx_ring[0]; 16274d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 16284d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 16294d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 16304d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 16314d52a575SXin LI CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 16324d52a575SXin LI 16334d52a575SXin LI /* Match ET_RX_RING0_POS */ 16344d52a575SXin LI rx_ring->rr_index = 0; 16354d52a575SXin LI rx_ring->rr_wrap = 1; 16364d52a575SXin LI 16374d52a575SXin LI /* 16384d52a575SXin LI * RX intr moderation 16394d52a575SXin LI */ 16404d52a575SXin LI CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 16414d52a575SXin LI CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 16424d52a575SXin LI 1643398f1b65SPyun YongHyeon return (0); 16444d52a575SXin LI } 16454d52a575SXin LI 16464d52a575SXin LI static int 16474d52a575SXin LI et_init_txdma(struct et_softc *sc) 16484d52a575SXin LI { 16494d52a575SXin LI struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring; 16504d52a575SXin LI struct et_txstatus_data *txsd = &sc->sc_tx_status; 16514d52a575SXin LI int error; 16524d52a575SXin LI 16534d52a575SXin LI error = et_stop_txdma(sc); 16544d52a575SXin LI if (error) { 16554d52a575SXin LI if_printf(sc->ifp, "can't init TX DMA engine\n"); 1656398f1b65SPyun YongHyeon return (error); 16574d52a575SXin LI } 16584d52a575SXin LI 16594d52a575SXin LI /* 16604d52a575SXin LI * Install TX descriptor ring 16614d52a575SXin LI */ 16624d52a575SXin LI CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 16634d52a575SXin LI CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 16644d52a575SXin LI CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 16654d52a575SXin LI 16664d52a575SXin LI /* 16674d52a575SXin LI * Install TX status 16684d52a575SXin LI */ 16694d52a575SXin LI CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 16704d52a575SXin LI CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 16714d52a575SXin LI 16724d52a575SXin LI CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 16734d52a575SXin LI 16744d52a575SXin LI /* Match ET_TX_READY_POS */ 16754d52a575SXin LI tx_ring->tr_ready_index = 0; 16764d52a575SXin LI tx_ring->tr_ready_wrap = 0; 16774d52a575SXin LI 1678398f1b65SPyun YongHyeon return (0); 16794d52a575SXin LI } 16804d52a575SXin LI 16814d52a575SXin LI static void 16824d52a575SXin LI et_init_mac(struct et_softc *sc) 16834d52a575SXin LI { 16844d52a575SXin LI struct ifnet *ifp = sc->ifp; 16854d52a575SXin LI const uint8_t *eaddr = IF_LLADDR(ifp); 16864d52a575SXin LI uint32_t val; 16874d52a575SXin LI 16884d52a575SXin LI /* Reset MAC */ 16894d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 16904d52a575SXin LI ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 16914d52a575SXin LI ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 16924d52a575SXin LI ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 16934d52a575SXin LI 16944d52a575SXin LI /* 16954d52a575SXin LI * Setup inter packet gap 16964d52a575SXin LI */ 169723263665SPyun YongHyeon val = (56 << ET_IPG_NONB2B_1_SHIFT) | 169823263665SPyun YongHyeon (88 << ET_IPG_NONB2B_2_SHIFT) | 169923263665SPyun YongHyeon (80 << ET_IPG_MINIFG_SHIFT) | 170023263665SPyun YongHyeon (96 << ET_IPG_B2B_SHIFT); 17014d52a575SXin LI CSR_WRITE_4(sc, ET_IPG, val); 17024d52a575SXin LI 17034d52a575SXin LI /* 17044d52a575SXin LI * Setup half duplex mode 17054d52a575SXin LI */ 170623263665SPyun YongHyeon val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 170723263665SPyun YongHyeon (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 170823263665SPyun YongHyeon (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 17094d52a575SXin LI ET_MAC_HDX_EXC_DEFER; 17104d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_HDX, val); 17114d52a575SXin LI 17124d52a575SXin LI /* Clear MAC control */ 17134d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 17144d52a575SXin LI 17154d52a575SXin LI /* Reset MII */ 17164d52a575SXin LI CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 17174d52a575SXin LI 17184d52a575SXin LI /* 17194d52a575SXin LI * Set MAC address 17204d52a575SXin LI */ 17214d52a575SXin LI val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 17224d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 17234d52a575SXin LI val = (eaddr[0] << 16) | (eaddr[1] << 24); 17244d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 17254d52a575SXin LI 17264d52a575SXin LI /* Set max frame length */ 17274d52a575SXin LI CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 17284d52a575SXin LI 17294d52a575SXin LI /* Bring MAC out of reset state */ 17304d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 17314d52a575SXin LI } 17324d52a575SXin LI 17334d52a575SXin LI static void 17344d52a575SXin LI et_init_rxmac(struct et_softc *sc) 17354d52a575SXin LI { 17364d52a575SXin LI struct ifnet *ifp = sc->ifp; 17374d52a575SXin LI const uint8_t *eaddr = IF_LLADDR(ifp); 17384d52a575SXin LI uint32_t val; 17394d52a575SXin LI int i; 17404d52a575SXin LI 17414d52a575SXin LI /* Disable RX MAC and WOL */ 17424d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 17434d52a575SXin LI 17444d52a575SXin LI /* 17454d52a575SXin LI * Clear all WOL related registers 17464d52a575SXin LI */ 17474d52a575SXin LI for (i = 0; i < 3; ++i) 17484d52a575SXin LI CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 17494d52a575SXin LI for (i = 0; i < 20; ++i) 17504d52a575SXin LI CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 17514d52a575SXin LI 17524d52a575SXin LI /* 17534d52a575SXin LI * Set WOL source address. XXX is this necessary? 17544d52a575SXin LI */ 17554d52a575SXin LI val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 17564d52a575SXin LI CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 17574d52a575SXin LI val = (eaddr[0] << 8) | eaddr[1]; 17584d52a575SXin LI CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 17594d52a575SXin LI 17604d52a575SXin LI /* Clear packet filters */ 17614d52a575SXin LI CSR_WRITE_4(sc, ET_PKTFILT, 0); 17624d52a575SXin LI 17634d52a575SXin LI /* No ucast filtering */ 17644d52a575SXin LI CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 17654d52a575SXin LI CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 17664d52a575SXin LI CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 17674d52a575SXin LI 17684d52a575SXin LI if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 17694d52a575SXin LI /* 17704d52a575SXin LI * In order to transmit jumbo packets greater than 17714d52a575SXin LI * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 17724d52a575SXin LI * RX MAC and RX DMA needs to be reduced in size to 17734d52a575SXin LI * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 17744d52a575SXin LI * order to implement this, we must use "cut through" 17754d52a575SXin LI * mode in the RX MAC, which chops packets down into 17764d52a575SXin LI * segments. In this case we selected 256 bytes, 17774d52a575SXin LI * since this is the size of the PCI-Express TLP's 17784d52a575SXin LI * that the ET1310 uses. 17794d52a575SXin LI */ 178023263665SPyun YongHyeon val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 17814d52a575SXin LI ET_RXMAC_MC_SEGSZ_ENABLE; 17824d52a575SXin LI } else { 17834d52a575SXin LI val = 0; 17844d52a575SXin LI } 17854d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 17864d52a575SXin LI 17874d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 17884d52a575SXin LI 17894d52a575SXin LI /* Initialize RX MAC management register */ 17904d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 17914d52a575SXin LI 17924d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 17934d52a575SXin LI 17944d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_MGT, 17954d52a575SXin LI ET_RXMAC_MGT_PASS_ECRC | 17964d52a575SXin LI ET_RXMAC_MGT_PASS_ELEN | 17974d52a575SXin LI ET_RXMAC_MGT_PASS_ETRUNC | 17984d52a575SXin LI ET_RXMAC_MGT_CHECK_PKT); 17994d52a575SXin LI 18004d52a575SXin LI /* 18014d52a575SXin LI * Configure runt filtering (may not work on certain chip generation) 18024d52a575SXin LI */ 180323263665SPyun YongHyeon val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 180423263665SPyun YongHyeon ET_PKTFILT_MINLEN_MASK; 180523263665SPyun YongHyeon val |= ET_PKTFILT_FRAG; 18064d52a575SXin LI CSR_WRITE_4(sc, ET_PKTFILT, val); 18074d52a575SXin LI 18084d52a575SXin LI /* Enable RX MAC but leave WOL disabled */ 18094d52a575SXin LI CSR_WRITE_4(sc, ET_RXMAC_CTRL, 18104d52a575SXin LI ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 18114d52a575SXin LI 18124d52a575SXin LI /* 18134d52a575SXin LI * Setup multicast hash and allmulti/promisc mode 18144d52a575SXin LI */ 18154d52a575SXin LI et_setmulti(sc); 18164d52a575SXin LI } 18174d52a575SXin LI 18184d52a575SXin LI static void 18194d52a575SXin LI et_init_txmac(struct et_softc *sc) 18204d52a575SXin LI { 18214d52a575SXin LI /* Disable TX MAC and FC(?) */ 18224d52a575SXin LI CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 18234d52a575SXin LI 18244d52a575SXin LI /* No flow control yet */ 18254d52a575SXin LI CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0); 18264d52a575SXin LI 18274d52a575SXin LI /* Enable TX MAC but leave FC(?) diabled */ 18284d52a575SXin LI CSR_WRITE_4(sc, ET_TXMAC_CTRL, 18294d52a575SXin LI ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 18304d52a575SXin LI } 18314d52a575SXin LI 18324d52a575SXin LI static int 18334d52a575SXin LI et_start_rxdma(struct et_softc *sc) 18344d52a575SXin LI { 18354d52a575SXin LI uint32_t val = 0; 18364d52a575SXin LI 183723263665SPyun YongHyeon val |= (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 18384d52a575SXin LI ET_RXDMA_CTRL_RING0_ENABLE; 183923263665SPyun YongHyeon val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 18404d52a575SXin LI ET_RXDMA_CTRL_RING1_ENABLE; 18414d52a575SXin LI 18424d52a575SXin LI CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 18434d52a575SXin LI 18444d52a575SXin LI DELAY(5); 18454d52a575SXin LI 18464d52a575SXin LI if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 18474d52a575SXin LI if_printf(sc->ifp, "can't start RX DMA engine\n"); 1848398f1b65SPyun YongHyeon return (ETIMEDOUT); 18494d52a575SXin LI } 1850398f1b65SPyun YongHyeon return (0); 18514d52a575SXin LI } 18524d52a575SXin LI 18534d52a575SXin LI static int 18544d52a575SXin LI et_start_txdma(struct et_softc *sc) 18554d52a575SXin LI { 18564d52a575SXin LI CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 1857398f1b65SPyun YongHyeon return (0); 18584d52a575SXin LI } 18594d52a575SXin LI 18604d52a575SXin LI static int 18614d52a575SXin LI et_enable_txrx(struct et_softc *sc, int media_upd) 18624d52a575SXin LI { 18634d52a575SXin LI struct ifnet *ifp = sc->ifp; 18644d52a575SXin LI uint32_t val; 18654d52a575SXin LI int i, error; 18664d52a575SXin LI 18674d52a575SXin LI val = CSR_READ_4(sc, ET_MAC_CFG1); 18684d52a575SXin LI val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 18694d52a575SXin LI val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 18704d52a575SXin LI ET_MAC_CFG1_LOOPBACK); 18714d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG1, val); 18724d52a575SXin LI 18734d52a575SXin LI if (media_upd) 18744d52a575SXin LI et_ifmedia_upd_locked(ifp); 18754d52a575SXin LI else 18764d52a575SXin LI et_setmedia(sc); 18774d52a575SXin LI 18784d52a575SXin LI #define NRETRY 50 18794d52a575SXin LI 18804d52a575SXin LI for (i = 0; i < NRETRY; ++i) { 18814d52a575SXin LI val = CSR_READ_4(sc, ET_MAC_CFG1); 18824d52a575SXin LI if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 18834d52a575SXin LI (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 18844d52a575SXin LI break; 18854d52a575SXin LI 18864d52a575SXin LI DELAY(100); 18874d52a575SXin LI } 18884d52a575SXin LI if (i == NRETRY) { 18894d52a575SXin LI if_printf(ifp, "can't enable RX/TX\n"); 1890398f1b65SPyun YongHyeon return (0); 18914d52a575SXin LI } 18924d52a575SXin LI sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 18934d52a575SXin LI 18944d52a575SXin LI #undef NRETRY 18954d52a575SXin LI 18964d52a575SXin LI /* 18974d52a575SXin LI * Start TX/RX DMA engine 18984d52a575SXin LI */ 18994d52a575SXin LI error = et_start_rxdma(sc); 19004d52a575SXin LI if (error) 1901398f1b65SPyun YongHyeon return (error); 19024d52a575SXin LI 19034d52a575SXin LI error = et_start_txdma(sc); 19044d52a575SXin LI if (error) 1905398f1b65SPyun YongHyeon return (error); 19064d52a575SXin LI 1907398f1b65SPyun YongHyeon return (0); 19084d52a575SXin LI } 19094d52a575SXin LI 19104d52a575SXin LI static void 19114d52a575SXin LI et_rxeof(struct et_softc *sc) 19124d52a575SXin LI { 19134d52a575SXin LI struct et_rxstatus_data *rxsd; 19144d52a575SXin LI struct et_rxstat_ring *rxst_ring; 1915*05884511SPyun YongHyeon struct et_rxbuf_data *rbd; 1916*05884511SPyun YongHyeon struct et_rxdesc_ring *rx_ring; 1917*05884511SPyun YongHyeon struct et_rxstat *st; 1918*05884511SPyun YongHyeon struct ifnet *ifp; 1919*05884511SPyun YongHyeon struct mbuf *m; 1920*05884511SPyun YongHyeon uint32_t rxstat_pos, rxring_pos; 1921*05884511SPyun YongHyeon uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 1922*05884511SPyun YongHyeon int buflen, buf_idx, npost[2], ring_idx; 1923*05884511SPyun YongHyeon int rxst_index, rxst_wrap; 19244d52a575SXin LI 19254d52a575SXin LI ET_LOCK_ASSERT(sc); 1926*05884511SPyun YongHyeon 19274d52a575SXin LI ifp = sc->ifp; 19284d52a575SXin LI rxsd = &sc->sc_rx_status; 19294d52a575SXin LI rxst_ring = &sc->sc_rxstat_ring; 19304d52a575SXin LI 19314d52a575SXin LI if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 19324d52a575SXin LI return; 19334d52a575SXin LI 19344d52a575SXin LI bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 19354d52a575SXin LI BUS_DMASYNC_POSTREAD); 19364d52a575SXin LI bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 19374d52a575SXin LI BUS_DMASYNC_POSTREAD); 19384d52a575SXin LI 1939*05884511SPyun YongHyeon npost[0] = npost[1] = 0; 194026e07b50SPyun YongHyeon rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 19414d52a575SXin LI rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 194223263665SPyun YongHyeon rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 194323263665SPyun YongHyeon ET_RXS_STATRING_INDEX_SHIFT; 19444d52a575SXin LI 19454d52a575SXin LI while (rxst_index != rxst_ring->rsr_index || 19464d52a575SXin LI rxst_wrap != rxst_ring->rsr_wrap) { 1947*05884511SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1948*05884511SPyun YongHyeon break; 19494d52a575SXin LI 19504d52a575SXin LI MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 19514d52a575SXin LI st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 1952*05884511SPyun YongHyeon rxst_info1 = le32toh(st->rxst_info1); 195326e07b50SPyun YongHyeon rxst_info2 = le32toh(st->rxst_info2); 195426e07b50SPyun YongHyeon buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 195523263665SPyun YongHyeon ET_RXST_INFO2_LEN_SHIFT; 195626e07b50SPyun YongHyeon buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 195723263665SPyun YongHyeon ET_RXST_INFO2_BUFIDX_SHIFT; 195826e07b50SPyun YongHyeon ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 195923263665SPyun YongHyeon ET_RXST_INFO2_RINGIDX_SHIFT; 19604d52a575SXin LI 19614d52a575SXin LI if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 19624d52a575SXin LI rxst_ring->rsr_index = 0; 19634d52a575SXin LI rxst_ring->rsr_wrap ^= 1; 19644d52a575SXin LI } 196523263665SPyun YongHyeon rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 19664d52a575SXin LI if (rxst_ring->rsr_wrap) 19674d52a575SXin LI rxstat_pos |= ET_RXSTAT_POS_WRAP; 19684d52a575SXin LI CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 19694d52a575SXin LI 19704d52a575SXin LI if (ring_idx >= ET_RX_NRING) { 19714d52a575SXin LI ifp->if_ierrors++; 19724d52a575SXin LI if_printf(ifp, "invalid ring index %d\n", ring_idx); 19734d52a575SXin LI continue; 19744d52a575SXin LI } 19754d52a575SXin LI if (buf_idx >= ET_RX_NDESC) { 19764d52a575SXin LI ifp->if_ierrors++; 19774d52a575SXin LI if_printf(ifp, "invalid buf index %d\n", buf_idx); 19784d52a575SXin LI continue; 19794d52a575SXin LI } 19804d52a575SXin LI 19814d52a575SXin LI rbd = &sc->sc_rx_data[ring_idx]; 19824d52a575SXin LI m = rbd->rbd_buf[buf_idx].rb_mbuf; 1983*05884511SPyun YongHyeon if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 1984*05884511SPyun YongHyeon /* Discard errored frame. */ 1985*05884511SPyun YongHyeon ifp->if_ierrors++; 1986*05884511SPyun YongHyeon rbd->rbd_discard(rbd, buf_idx); 1987*05884511SPyun YongHyeon } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 1988*05884511SPyun YongHyeon /* No available mbufs, discard it. */ 1989*05884511SPyun YongHyeon ifp->if_iqdrops++; 1990*05884511SPyun YongHyeon rbd->rbd_discard(rbd, buf_idx); 1991*05884511SPyun YongHyeon } else { 1992*05884511SPyun YongHyeon buflen -= ETHER_CRC_LEN; 1993*05884511SPyun YongHyeon if (buflen < ETHER_HDR_LEN) { 19944d52a575SXin LI m_freem(m); 19954d52a575SXin LI ifp->if_ierrors++; 19964d52a575SXin LI } else { 1997*05884511SPyun YongHyeon m->m_pkthdr.len = m->m_len = buflen; 19984d52a575SXin LI m->m_pkthdr.rcvif = ifp; 19994d52a575SXin LI ifp->if_ipackets++; 20004d52a575SXin LI ET_UNLOCK(sc); 20014d52a575SXin LI ifp->if_input(ifp, m); 20024d52a575SXin LI ET_LOCK(sc); 20034d52a575SXin LI } 20044d52a575SXin LI } 20054d52a575SXin LI 20064d52a575SXin LI rx_ring = &sc->sc_rx_ring[ring_idx]; 20074d52a575SXin LI if (buf_idx != rx_ring->rr_index) { 2008*05884511SPyun YongHyeon if_printf(ifp, 2009*05884511SPyun YongHyeon "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 20104d52a575SXin LI ring_idx, buf_idx, rx_ring->rr_index); 20114d52a575SXin LI } 20124d52a575SXin LI 20134d52a575SXin LI MPASS(rx_ring->rr_index < ET_RX_NDESC); 20144d52a575SXin LI if (++rx_ring->rr_index == ET_RX_NDESC) { 20154d52a575SXin LI rx_ring->rr_index = 0; 20164d52a575SXin LI rx_ring->rr_wrap ^= 1; 20174d52a575SXin LI } 201823263665SPyun YongHyeon rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 20194d52a575SXin LI if (rx_ring->rr_wrap) 20204d52a575SXin LI rxring_pos |= ET_RX_RING_POS_WRAP; 20214d52a575SXin LI CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 20224d52a575SXin LI } 2023*05884511SPyun YongHyeon 2024*05884511SPyun YongHyeon bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2025*05884511SPyun YongHyeon BUS_DMASYNC_PREREAD); 2026*05884511SPyun YongHyeon bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2027*05884511SPyun YongHyeon BUS_DMASYNC_PREREAD); 20284d52a575SXin LI } 20294d52a575SXin LI 20304d52a575SXin LI static int 20314d52a575SXin LI et_encap(struct et_softc *sc, struct mbuf **m0) 20324d52a575SXin LI { 2033*05884511SPyun YongHyeon struct et_txdesc_ring *tx_ring; 2034*05884511SPyun YongHyeon struct et_txbuf_data *tbd; 20354d52a575SXin LI struct et_txdesc *td; 2036*05884511SPyun YongHyeon struct mbuf *m; 2037*05884511SPyun YongHyeon bus_dma_segment_t segs[ET_NSEG_MAX]; 20384d52a575SXin LI bus_dmamap_t map; 2039*05884511SPyun YongHyeon uint32_t csum_flags, last_td_ctrl2, tx_ready_pos; 2040*05884511SPyun YongHyeon int error, i, idx, first_idx, last_idx, nsegs; 20414d52a575SXin LI 2042*05884511SPyun YongHyeon tx_ring = &sc->sc_tx_ring; 20434d52a575SXin LI MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2044*05884511SPyun YongHyeon tbd = &sc->sc_tx_data; 20454d52a575SXin LI first_idx = tx_ring->tr_ready_index; 20464d52a575SXin LI map = tbd->tbd_buf[first_idx].tb_dmap; 20474d52a575SXin LI 2048*05884511SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2049*05884511SPyun YongHyeon 0); 2050*05884511SPyun YongHyeon if (error == EFBIG) { 2051*05884511SPyun YongHyeon m = m_collapse(*m0, M_DONTWAIT, ET_NSEG_MAX); 2052*05884511SPyun YongHyeon if (m == NULL) { 2053*05884511SPyun YongHyeon m_freem(*m0); 2054*05884511SPyun YongHyeon *m0 = NULL; 2055*05884511SPyun YongHyeon return (ENOMEM); 20564d52a575SXin LI } 2057*05884511SPyun YongHyeon *m0 = m; 2058*05884511SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2059*05884511SPyun YongHyeon &nsegs, 0); 2060*05884511SPyun YongHyeon if (error != 0) { 2061*05884511SPyun YongHyeon m_freem(*m0); 2062*05884511SPyun YongHyeon *m0 = NULL; 2063*05884511SPyun YongHyeon return (error); 20644d52a575SXin LI } 2065*05884511SPyun YongHyeon } else if (error != 0) 2066*05884511SPyun YongHyeon return (error); 20674d52a575SXin LI 2068*05884511SPyun YongHyeon /* Check for descriptor overruns. */ 2069*05884511SPyun YongHyeon if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2070*05884511SPyun YongHyeon bus_dmamap_unload(sc->sc_tx_tag, map); 2071*05884511SPyun YongHyeon return (ENOBUFS); 20724d52a575SXin LI } 2073*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 20744d52a575SXin LI 20754d52a575SXin LI last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2076*05884511SPyun YongHyeon sc->sc_tx += nsegs; 20774d52a575SXin LI if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 20784d52a575SXin LI sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 20794d52a575SXin LI last_td_ctrl2 |= ET_TDCTRL2_INTR; 20804d52a575SXin LI } 20814d52a575SXin LI 2082*05884511SPyun YongHyeon m = *m0; 20839955274cSPyun YongHyeon csum_flags = 0; 20849955274cSPyun YongHyeon if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 20859955274cSPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 20869955274cSPyun YongHyeon csum_flags |= ET_TDCTRL2_CSUM_IP; 20879955274cSPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 20889955274cSPyun YongHyeon csum_flags |= ET_TDCTRL2_CSUM_UDP; 20899955274cSPyun YongHyeon else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 20909955274cSPyun YongHyeon csum_flags |= ET_TDCTRL2_CSUM_TCP; 20919955274cSPyun YongHyeon } 20924d52a575SXin LI last_idx = -1; 2093*05884511SPyun YongHyeon for (i = 0; i < nsegs; ++i) { 20944d52a575SXin LI idx = (first_idx + i) % ET_TX_NDESC; 20954d52a575SXin LI td = &tx_ring->tr_desc[idx]; 209626e07b50SPyun YongHyeon td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 209726e07b50SPyun YongHyeon td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 209826e07b50SPyun YongHyeon td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2099*05884511SPyun YongHyeon if (i == nsegs - 1) { 2100*05884511SPyun YongHyeon /* Last frag */ 21019955274cSPyun YongHyeon td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 21024d52a575SXin LI last_idx = idx; 21039955274cSPyun YongHyeon } else 21049955274cSPyun YongHyeon td->td_ctrl2 = htole32(csum_flags); 21054d52a575SXin LI 21064d52a575SXin LI MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 21074d52a575SXin LI if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 21084d52a575SXin LI tx_ring->tr_ready_index = 0; 21094d52a575SXin LI tx_ring->tr_ready_wrap ^= 1; 21104d52a575SXin LI } 21114d52a575SXin LI } 21124d52a575SXin LI td = &tx_ring->tr_desc[first_idx]; 2113*05884511SPyun YongHyeon /* First frag */ 2114*05884511SPyun YongHyeon td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 21154d52a575SXin LI 21164d52a575SXin LI MPASS(last_idx >= 0); 21174d52a575SXin LI tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 21184d52a575SXin LI tbd->tbd_buf[last_idx].tb_dmap = map; 21194d52a575SXin LI tbd->tbd_buf[last_idx].tb_mbuf = m; 21204d52a575SXin LI 2121*05884511SPyun YongHyeon tbd->tbd_used += nsegs; 21224d52a575SXin LI MPASS(tbd->tbd_used <= ET_TX_NDESC); 21234d52a575SXin LI 21244d52a575SXin LI bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 21254d52a575SXin LI BUS_DMASYNC_PREWRITE); 212623263665SPyun YongHyeon tx_ready_pos = tx_ring->tr_ready_index & ET_TX_READY_POS_INDEX_MASK; 21274d52a575SXin LI if (tx_ring->tr_ready_wrap) 21284d52a575SXin LI tx_ready_pos |= ET_TX_READY_POS_WRAP; 21294d52a575SXin LI CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 2130*05884511SPyun YongHyeon return (0); 21314d52a575SXin LI } 21324d52a575SXin LI 21334d52a575SXin LI static void 21344d52a575SXin LI et_txeof(struct et_softc *sc) 21354d52a575SXin LI { 21364d52a575SXin LI struct et_txdesc_ring *tx_ring; 21374d52a575SXin LI struct et_txbuf_data *tbd; 2138*05884511SPyun YongHyeon struct et_txbuf *tb; 2139*05884511SPyun YongHyeon struct ifnet *ifp; 21404d52a575SXin LI uint32_t tx_done; 21414d52a575SXin LI int end, wrap; 21424d52a575SXin LI 21434d52a575SXin LI ET_LOCK_ASSERT(sc); 2144*05884511SPyun YongHyeon 21454d52a575SXin LI ifp = sc->ifp; 21464d52a575SXin LI tx_ring = &sc->sc_tx_ring; 21474d52a575SXin LI tbd = &sc->sc_tx_data; 21484d52a575SXin LI 21494d52a575SXin LI if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 21504d52a575SXin LI return; 21514d52a575SXin LI 21524d52a575SXin LI if (tbd->tbd_used == 0) 21534d52a575SXin LI return; 21544d52a575SXin LI 2155*05884511SPyun YongHyeon bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2156*05884511SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 2157*05884511SPyun YongHyeon 21584d52a575SXin LI tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 215923263665SPyun YongHyeon end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 21604d52a575SXin LI wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 21614d52a575SXin LI 21624d52a575SXin LI while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 21634d52a575SXin LI MPASS(tbd->tbd_start_index < ET_TX_NDESC); 21644d52a575SXin LI tb = &tbd->tbd_buf[tbd->tbd_start_index]; 21654d52a575SXin LI if (tb->tb_mbuf != NULL) { 2166*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2167*05884511SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 2168*05884511SPyun YongHyeon bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 21694d52a575SXin LI m_freem(tb->tb_mbuf); 21704d52a575SXin LI tb->tb_mbuf = NULL; 21714d52a575SXin LI ifp->if_opackets++; 21724d52a575SXin LI } 21734d52a575SXin LI 21744d52a575SXin LI if (++tbd->tbd_start_index == ET_TX_NDESC) { 21754d52a575SXin LI tbd->tbd_start_index = 0; 21764d52a575SXin LI tbd->tbd_start_wrap ^= 1; 21774d52a575SXin LI } 21784d52a575SXin LI 21794d52a575SXin LI MPASS(tbd->tbd_used > 0); 21804d52a575SXin LI tbd->tbd_used--; 21814d52a575SXin LI } 21824d52a575SXin LI 21834d52a575SXin LI if (tbd->tbd_used == 0) 21844d52a575SXin LI sc->watchdog_timer = 0; 2185*05884511SPyun YongHyeon if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 21864d52a575SXin LI ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 21874d52a575SXin LI } 21884d52a575SXin LI static void 21894d52a575SXin LI et_tick(void *xsc) 21904d52a575SXin LI { 21914d52a575SXin LI struct et_softc *sc = xsc; 21924d52a575SXin LI struct ifnet *ifp; 21934d52a575SXin LI struct mii_data *mii; 21944d52a575SXin LI 21954d52a575SXin LI ET_LOCK_ASSERT(sc); 21964d52a575SXin LI ifp = sc->ifp; 21974d52a575SXin LI mii = device_get_softc(sc->sc_miibus); 21984d52a575SXin LI 21994d52a575SXin LI mii_tick(mii); 22004d52a575SXin LI if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 && 22014d52a575SXin LI (mii->mii_media_status & IFM_ACTIVE) && 22024d52a575SXin LI IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 22034d52a575SXin LI if_printf(ifp, "Link up, enable TX/RX\n"); 22044d52a575SXin LI if (et_enable_txrx(sc, 0) == 0) 22054d52a575SXin LI et_start_locked(ifp); 22064d52a575SXin LI } 2207*05884511SPyun YongHyeon if (et_watchdog(sc) == EJUSTRETURN) 2208*05884511SPyun YongHyeon return; 22094d52a575SXin LI callout_reset(&sc->sc_tick, hz, et_tick, sc); 22104d52a575SXin LI } 22114d52a575SXin LI 22124d52a575SXin LI static int 2213*05884511SPyun YongHyeon et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 22144d52a575SXin LI { 2215*05884511SPyun YongHyeon struct et_softc *sc; 2216*05884511SPyun YongHyeon struct et_rxdesc *desc; 22174d52a575SXin LI struct et_rxbuf *rb; 22184d52a575SXin LI struct mbuf *m; 2219*05884511SPyun YongHyeon bus_dma_segment_t segs[1]; 22204d52a575SXin LI bus_dmamap_t dmap; 2221*05884511SPyun YongHyeon int nsegs; 22224d52a575SXin LI 22234d52a575SXin LI MPASS(buf_idx < ET_RX_NDESC); 2224*05884511SPyun YongHyeon m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2225*05884511SPyun YongHyeon if (m == NULL) 2226*05884511SPyun YongHyeon return (ENOBUFS); 2227*05884511SPyun YongHyeon m->m_len = m->m_pkthdr.len = MCLBYTES; 2228*05884511SPyun YongHyeon m_adj(m, ETHER_ALIGN); 2229*05884511SPyun YongHyeon 2230*05884511SPyun YongHyeon sc = rbd->rbd_softc; 22314d52a575SXin LI rb = &rbd->rbd_buf[buf_idx]; 22324d52a575SXin LI 2233*05884511SPyun YongHyeon if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2234*05884511SPyun YongHyeon segs, &nsegs, 0) != 0) { 22354d52a575SXin LI m_freem(m); 2236*05884511SPyun YongHyeon return (ENOBUFS); 22374d52a575SXin LI } 2238*05884511SPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 22394d52a575SXin LI 2240*05884511SPyun YongHyeon if (rb->rb_mbuf != NULL) { 2241*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 22424d52a575SXin LI BUS_DMASYNC_POSTREAD); 2243*05884511SPyun YongHyeon bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 22444d52a575SXin LI } 22454d52a575SXin LI dmap = rb->rb_dmap; 2246*05884511SPyun YongHyeon rb->rb_dmap = sc->sc_rx_sparemap; 2247*05884511SPyun YongHyeon sc->sc_rx_sparemap = dmap; 2248*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 22494d52a575SXin LI 2250*05884511SPyun YongHyeon rb->rb_mbuf = m; 2251*05884511SPyun YongHyeon desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2252*05884511SPyun YongHyeon desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2253*05884511SPyun YongHyeon desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2254*05884511SPyun YongHyeon desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2255*05884511SPyun YongHyeon bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2256*05884511SPyun YongHyeon BUS_DMASYNC_PREWRITE); 2257*05884511SPyun YongHyeon return (0); 2258*05884511SPyun YongHyeon } 2259*05884511SPyun YongHyeon 2260*05884511SPyun YongHyeon static void 2261*05884511SPyun YongHyeon et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2262*05884511SPyun YongHyeon { 2263*05884511SPyun YongHyeon struct et_rxdesc *desc; 2264*05884511SPyun YongHyeon 2265*05884511SPyun YongHyeon desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2266*05884511SPyun YongHyeon desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2267*05884511SPyun YongHyeon bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2268*05884511SPyun YongHyeon BUS_DMASYNC_PREWRITE); 2269*05884511SPyun YongHyeon } 2270*05884511SPyun YongHyeon 2271*05884511SPyun YongHyeon static int 2272*05884511SPyun YongHyeon et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2273*05884511SPyun YongHyeon { 2274*05884511SPyun YongHyeon struct et_softc *sc; 2275*05884511SPyun YongHyeon struct et_rxdesc *desc; 2276*05884511SPyun YongHyeon struct et_rxbuf *rb; 2277*05884511SPyun YongHyeon struct mbuf *m; 2278*05884511SPyun YongHyeon bus_dma_segment_t segs[1]; 2279*05884511SPyun YongHyeon bus_dmamap_t dmap; 2280*05884511SPyun YongHyeon int nsegs; 2281*05884511SPyun YongHyeon 2282*05884511SPyun YongHyeon MPASS(buf_idx < ET_RX_NDESC); 2283*05884511SPyun YongHyeon MGETHDR(m, M_DONTWAIT, MT_DATA); 2284*05884511SPyun YongHyeon if (m == NULL) 2285*05884511SPyun YongHyeon return (ENOBUFS); 2286*05884511SPyun YongHyeon m->m_len = m->m_pkthdr.len = MHLEN; 2287*05884511SPyun YongHyeon m_adj(m, ETHER_ALIGN); 2288*05884511SPyun YongHyeon 2289*05884511SPyun YongHyeon sc = rbd->rbd_softc; 2290*05884511SPyun YongHyeon rb = &rbd->rbd_buf[buf_idx]; 2291*05884511SPyun YongHyeon 2292*05884511SPyun YongHyeon if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2293*05884511SPyun YongHyeon m, segs, &nsegs, 0) != 0) { 2294*05884511SPyun YongHyeon m_freem(m); 2295*05884511SPyun YongHyeon return (ENOBUFS); 2296*05884511SPyun YongHyeon } 2297*05884511SPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2298*05884511SPyun YongHyeon 2299*05884511SPyun YongHyeon if (rb->rb_mbuf != NULL) { 2300*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2301*05884511SPyun YongHyeon BUS_DMASYNC_POSTREAD); 2302*05884511SPyun YongHyeon bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2303*05884511SPyun YongHyeon } 2304*05884511SPyun YongHyeon dmap = rb->rb_dmap; 2305*05884511SPyun YongHyeon rb->rb_dmap = sc->sc_rx_mini_sparemap; 2306*05884511SPyun YongHyeon sc->sc_rx_mini_sparemap = dmap; 2307*05884511SPyun YongHyeon bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2308*05884511SPyun YongHyeon 2309*05884511SPyun YongHyeon rb->rb_mbuf = m; 2310*05884511SPyun YongHyeon desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2311*05884511SPyun YongHyeon desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2312*05884511SPyun YongHyeon desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2313*05884511SPyun YongHyeon desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2314*05884511SPyun YongHyeon bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2315*05884511SPyun YongHyeon BUS_DMASYNC_PREWRITE); 2316*05884511SPyun YongHyeon return (0); 23174d52a575SXin LI } 23184d52a575SXin LI 23194d52a575SXin LI /* 23204d52a575SXin LI * Create sysctl tree 23214d52a575SXin LI */ 23224d52a575SXin LI static void 23234d52a575SXin LI et_add_sysctls(struct et_softc * sc) 23244d52a575SXin LI { 23254d52a575SXin LI struct sysctl_ctx_list *ctx; 23264d52a575SXin LI struct sysctl_oid_list *children; 23274d52a575SXin LI 23284d52a575SXin LI ctx = device_get_sysctl_ctx(sc->dev); 23294d52a575SXin LI children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 23304d52a575SXin LI 23314d52a575SXin LI SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 23324d52a575SXin LI CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_npkts, "I", 23334d52a575SXin LI "RX IM, # packets per RX interrupt"); 23344d52a575SXin LI SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 23354d52a575SXin LI CTLTYPE_INT | CTLFLAG_RW, sc, 0, et_sysctl_rx_intr_delay, "I", 23364d52a575SXin LI "RX IM, RX interrupt delay (x10 usec)"); 23374d52a575SXin LI SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 23384d52a575SXin LI CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 23394d52a575SXin LI "TX IM, # segments per TX interrupt"); 23404d52a575SXin LI SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 23414d52a575SXin LI CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 23424d52a575SXin LI } 23434d52a575SXin LI 23444d52a575SXin LI static int 23454d52a575SXin LI et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 23464d52a575SXin LI { 23474d52a575SXin LI struct et_softc *sc = arg1; 23484d52a575SXin LI struct ifnet *ifp = sc->ifp; 23494d52a575SXin LI int error = 0, v; 23504d52a575SXin LI 23514d52a575SXin LI v = sc->sc_rx_intr_npkts; 23524d52a575SXin LI error = sysctl_handle_int(oidp, &v, 0, req); 23534d52a575SXin LI if (error || req->newptr == NULL) 23544d52a575SXin LI goto back; 23554d52a575SXin LI if (v <= 0) { 23564d52a575SXin LI error = EINVAL; 23574d52a575SXin LI goto back; 23584d52a575SXin LI } 23594d52a575SXin LI 23604d52a575SXin LI if (sc->sc_rx_intr_npkts != v) { 23614d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) 23624d52a575SXin LI CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 23634d52a575SXin LI sc->sc_rx_intr_npkts = v; 23644d52a575SXin LI } 23654d52a575SXin LI back: 2366398f1b65SPyun YongHyeon return (error); 23674d52a575SXin LI } 23684d52a575SXin LI 23694d52a575SXin LI static int 23704d52a575SXin LI et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 23714d52a575SXin LI { 23724d52a575SXin LI struct et_softc *sc = arg1; 23734d52a575SXin LI struct ifnet *ifp = sc->ifp; 23744d52a575SXin LI int error = 0, v; 23754d52a575SXin LI 23764d52a575SXin LI v = sc->sc_rx_intr_delay; 23774d52a575SXin LI error = sysctl_handle_int(oidp, &v, 0, req); 23784d52a575SXin LI if (error || req->newptr == NULL) 23794d52a575SXin LI goto back; 23804d52a575SXin LI if (v <= 0) { 23814d52a575SXin LI error = EINVAL; 23824d52a575SXin LI goto back; 23834d52a575SXin LI } 23844d52a575SXin LI 23854d52a575SXin LI if (sc->sc_rx_intr_delay != v) { 23864d52a575SXin LI if (ifp->if_drv_flags & IFF_DRV_RUNNING) 23874d52a575SXin LI CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 23884d52a575SXin LI sc->sc_rx_intr_delay = v; 23894d52a575SXin LI } 23904d52a575SXin LI back: 2391398f1b65SPyun YongHyeon return (error); 23924d52a575SXin LI } 23934d52a575SXin LI 23944d52a575SXin LI static void 23954d52a575SXin LI et_setmedia(struct et_softc *sc) 23964d52a575SXin LI { 23974d52a575SXin LI struct mii_data *mii = device_get_softc(sc->sc_miibus); 23984d52a575SXin LI uint32_t cfg2, ctrl; 23994d52a575SXin LI 24004d52a575SXin LI cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 24014d52a575SXin LI cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 24024d52a575SXin LI ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 24034d52a575SXin LI cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 240423263665SPyun YongHyeon ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 240523263665SPyun YongHyeon ET_MAC_CFG2_PREAMBLE_LEN_MASK); 24064d52a575SXin LI 24074d52a575SXin LI ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 24084d52a575SXin LI ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 24094d52a575SXin LI 24104d52a575SXin LI if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 24114d52a575SXin LI cfg2 |= ET_MAC_CFG2_MODE_GMII; 24124d52a575SXin LI } else { 24134d52a575SXin LI cfg2 |= ET_MAC_CFG2_MODE_MII; 24144d52a575SXin LI ctrl |= ET_MAC_CTRL_MODE_MII; 24154d52a575SXin LI } 24164d52a575SXin LI 24174d52a575SXin LI if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 24184d52a575SXin LI cfg2 |= ET_MAC_CFG2_FDX; 24194d52a575SXin LI else 24204d52a575SXin LI ctrl |= ET_MAC_CTRL_GHDX; 24214d52a575SXin LI 24224d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 24234d52a575SXin LI CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 24244d52a575SXin LI } 24254d52a575SXin LI 24260442028aSPyun YongHyeon static int 24270442028aSPyun YongHyeon et_suspend(device_t dev) 24280442028aSPyun YongHyeon { 24290442028aSPyun YongHyeon struct et_softc *sc; 24300442028aSPyun YongHyeon 24310442028aSPyun YongHyeon sc = device_get_softc(dev); 24320442028aSPyun YongHyeon ET_LOCK(sc); 24330442028aSPyun YongHyeon if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 24340442028aSPyun YongHyeon et_stop(sc); 24350442028aSPyun YongHyeon ET_UNLOCK(sc); 24360442028aSPyun YongHyeon return (0); 24370442028aSPyun YongHyeon } 24380442028aSPyun YongHyeon 24390442028aSPyun YongHyeon static int 24400442028aSPyun YongHyeon et_resume(device_t dev) 24410442028aSPyun YongHyeon { 24420442028aSPyun YongHyeon struct et_softc *sc; 24430442028aSPyun YongHyeon 24440442028aSPyun YongHyeon sc = device_get_softc(dev); 24450442028aSPyun YongHyeon ET_LOCK(sc); 24460442028aSPyun YongHyeon if ((sc->ifp->if_flags & IFF_UP) != 0) 24470442028aSPyun YongHyeon et_init_locked(sc); 24480442028aSPyun YongHyeon ET_UNLOCK(sc); 24490442028aSPyun YongHyeon return (0); 24500442028aSPyun YongHyeon } 2451