1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2022 Soren Schmidt <sos@deepcore.dk> 5 * Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $Id: eqos.c 1059 2022-12-08 19:32:32Z sos $ 30 */ 31 32 /* 33 * DesignWare Ethernet Quality-of-Service controller 34 */ 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/endian.h> 44 #include <sys/module.h> 45 #include <sys/bus.h> 46 #include <sys/callout.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/mbuf.h> 50 #include <sys/systm.h> 51 #include <machine/bus.h> 52 53 #include <net/ethernet.h> 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/bpf.h> 59 60 #include <dev/mii/mii.h> 61 #include <dev/mii/miivar.h> 62 63 #include "miibus_if.h" 64 #include "if_eqos_if.h" 65 66 #ifdef FDT 67 #include <dev/ofw/openfirm.h> 68 #include <dev/ofw/ofw_bus.h> 69 #include <dev/ofw/ofw_bus_subr.h> 70 #include <dev/clk/clk.h> 71 #endif 72 73 #include <dev/eqos/if_eqos_reg.h> 74 #include <dev/eqos/if_eqos_var.h> 75 76 #define DESC_BOUNDARY (1ULL << 32) 77 #define DESC_ALIGN sizeof(struct eqos_dma_desc) 78 #define DESC_OFFSET(n) ((n) * sizeof(struct eqos_dma_desc)) 79 80 #define TX_DESC_COUNT EQOS_DMA_DESC_COUNT 81 #define TX_DESC_SIZE (TX_DESC_COUNT * DESC_ALIGN) 82 #define TX_MAX_SEGS (TX_DESC_COUNT / 2) 83 #define TX_NEXT(n) (((n) + 1 ) % TX_DESC_COUNT) 84 #define TX_QUEUED(h, t) ((((h) - (t)) + TX_DESC_COUNT) % TX_DESC_COUNT) 85 86 #define RX_DESC_COUNT EQOS_DMA_DESC_COUNT 87 #define RX_DESC_SIZE (RX_DESC_COUNT * DESC_ALIGN) 88 #define RX_NEXT(n) (((n) + 1) % RX_DESC_COUNT) 89 90 #define MII_BUSY_RETRY 1000 91 #define WATCHDOG_TIMEOUT_SECS 3 92 93 #define EQOS_LOCK(sc) mtx_lock(&(sc)->lock) 94 #define EQOS_UNLOCK(sc) mtx_unlock(&(sc)->lock) 95 #define EQOS_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED) 96 97 #define RD4(sc, o) bus_read_4(sc->res[EQOS_RES_MEM], (o)) 98 #define WR4(sc, o, v) bus_write_4(sc->res[EQOS_RES_MEM], (o), (v)) 99 100 101 static struct resource_spec eqos_spec[] = { 102 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 103 { SYS_RES_IRQ, 0, RF_ACTIVE }, 104 { -1, 0 } 105 }; 106 107 static void eqos_tick(void *softc); 108 109 110 static int 111 eqos_miibus_readreg(device_t dev, int phy, int reg) 112 { 113 struct eqos_softc *sc = device_get_softc(dev); 114 uint32_t addr; 115 int retry, val; 116 117 addr = sc->csr_clock_range | 118 (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 119 (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | 120 GMAC_MAC_MDIO_ADDRESS_GOC_READ | 121 GMAC_MAC_MDIO_ADDRESS_GB; 122 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 123 124 DELAY(100); 125 126 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 127 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); 128 if (!(addr & GMAC_MAC_MDIO_ADDRESS_GB)) { 129 val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF; 130 break; 131 } 132 DELAY(10); 133 } 134 if (!retry) { 135 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 136 phy, reg); 137 return (ETIMEDOUT); 138 } 139 return (val); 140 } 141 142 static int 143 eqos_miibus_writereg(device_t dev, int phy, int reg, int val) 144 { 145 struct eqos_softc *sc = device_get_softc(dev); 146 uint32_t addr; 147 int retry; 148 149 WR4(sc, GMAC_MAC_MDIO_DATA, val); 150 151 addr = sc->csr_clock_range | 152 (phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | 153 (reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | 154 GMAC_MAC_MDIO_ADDRESS_GOC_WRITE | 155 GMAC_MAC_MDIO_ADDRESS_GB; 156 WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); 157 158 DELAY(100); 159 160 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 161 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); 162 if (!(addr & GMAC_MAC_MDIO_ADDRESS_GB)) 163 break; 164 DELAY(10); 165 } 166 if (!retry) { 167 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 168 phy, reg); 169 return (ETIMEDOUT); 170 } 171 return (0); 172 } 173 174 static void 175 eqos_miibus_statchg(device_t dev) 176 { 177 struct eqos_softc *sc = device_get_softc(dev); 178 struct mii_data *mii = device_get_softc(sc->miibus); 179 uint32_t reg; 180 181 EQOS_ASSERT_LOCKED(sc); 182 183 if (mii->mii_media_status & IFM_ACTIVE) 184 sc->link_up = true; 185 else 186 sc->link_up = false; 187 188 reg = RD4(sc, GMAC_MAC_CONFIGURATION); 189 190 switch (IFM_SUBTYPE(mii->mii_media_active)) { 191 case IFM_10_T: 192 reg |= GMAC_MAC_CONFIGURATION_PS; 193 reg &= ~GMAC_MAC_CONFIGURATION_FES; 194 break; 195 case IFM_100_TX: 196 reg |= GMAC_MAC_CONFIGURATION_PS; 197 reg |= GMAC_MAC_CONFIGURATION_FES; 198 break; 199 case IFM_1000_T: 200 case IFM_1000_SX: 201 reg &= ~GMAC_MAC_CONFIGURATION_PS; 202 reg &= ~GMAC_MAC_CONFIGURATION_FES; 203 break; 204 case IFM_2500_T: 205 case IFM_2500_SX: 206 reg &= ~GMAC_MAC_CONFIGURATION_PS; 207 reg |= GMAC_MAC_CONFIGURATION_FES; 208 break; 209 default: 210 sc->link_up = false; 211 return; 212 } 213 214 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX)) 215 reg |= GMAC_MAC_CONFIGURATION_DM; 216 else 217 reg &= ~GMAC_MAC_CONFIGURATION_DM; 218 219 WR4(sc, GMAC_MAC_CONFIGURATION, reg); 220 221 IF_EQOS_SET_SPEED(dev, IFM_SUBTYPE(mii->mii_media_active)); 222 223 WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1); 224 } 225 226 static void 227 eqos_media_status(if_t ifp, struct ifmediareq *ifmr) 228 { 229 struct eqos_softc *sc = if_getsoftc(ifp); 230 struct mii_data *mii = device_get_softc(sc->miibus); 231 232 EQOS_LOCK(sc); 233 mii_pollstat(mii); 234 ifmr->ifm_active = mii->mii_media_active; 235 ifmr->ifm_status = mii->mii_media_status; 236 EQOS_UNLOCK(sc); 237 } 238 239 static int 240 eqos_media_change(if_t ifp) 241 { 242 struct eqos_softc *sc = if_getsoftc(ifp); 243 int error; 244 245 EQOS_LOCK(sc); 246 error = mii_mediachg(device_get_softc(sc->miibus)); 247 EQOS_UNLOCK(sc); 248 return (error); 249 } 250 251 static void 252 eqos_setup_txdesc(struct eqos_softc *sc, int index, int flags, 253 bus_addr_t paddr, u_int len, u_int total_len) 254 { 255 uint32_t tdes2, tdes3; 256 257 if (!paddr || !len) { 258 tdes2 = 0; 259 tdes3 = flags; 260 } else { 261 tdes2 = (flags & EQOS_TDES3_LD) ? EQOS_TDES2_IOC : 0; 262 tdes3 = flags; 263 } 264 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, BUS_DMASYNC_PREWRITE); 265 sc->tx.desc_ring[index].des0 = htole32((uint32_t)paddr); 266 sc->tx.desc_ring[index].des1 = htole32((uint32_t)(paddr >> 32)); 267 sc->tx.desc_ring[index].des2 = htole32(tdes2 | len); 268 sc->tx.desc_ring[index].des3 = htole32(tdes3 | total_len); 269 } 270 271 static int 272 eqos_setup_txbuf(struct eqos_softc *sc, struct mbuf *m) 273 { 274 bus_dma_segment_t segs[TX_MAX_SEGS]; 275 int first = sc->tx.head; 276 int error, nsegs, idx; 277 uint32_t flags; 278 279 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, 280 sc->tx.buf_map[first].map, m, segs, &nsegs, 0); 281 if (error == EFBIG) { 282 struct mbuf *mb; 283 284 device_printf(sc->dev, "TX packet too big trying defrag\n"); 285 bus_dmamap_unload(sc->tx.buf_tag, sc->tx.buf_map[first].map); 286 if (!(mb = m_defrag(m, M_NOWAIT))) 287 return (ENOMEM); 288 m = mb; 289 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, 290 sc->tx.buf_map[first].map, m, segs, &nsegs, 0); 291 } 292 if (error) 293 return (ENOMEM); 294 295 if (TX_QUEUED(sc->tx.head, sc->tx.tail) + nsegs > TX_DESC_COUNT) { 296 bus_dmamap_unload(sc->tx.buf_tag, sc->tx.buf_map[first].map); 297 device_printf(sc->dev, "TX packet no more queue space\n"); 298 return (ENOMEM); 299 } 300 301 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[first].map, 302 BUS_DMASYNC_PREWRITE); 303 304 sc->tx.buf_map[first].mbuf = m; 305 306 for (flags = EQOS_TDES3_FD, idx = 0; idx < nsegs; idx++) { 307 if (idx == (nsegs - 1)) 308 flags |= EQOS_TDES3_LD; 309 eqos_setup_txdesc(sc, sc->tx.head, flags, segs[idx].ds_addr, 310 segs[idx].ds_len, m->m_pkthdr.len); 311 flags &= ~EQOS_TDES3_FD; 312 flags |= EQOS_TDES3_OWN; 313 sc->tx.head = TX_NEXT(sc->tx.head); 314 } 315 316 /* 317 * Defer setting OWN bit on the first descriptor 318 * until all descriptors have been updated 319 */ 320 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, BUS_DMASYNC_PREWRITE); 321 sc->tx.desc_ring[first].des3 |= htole32(EQOS_TDES3_OWN); 322 323 return (0); 324 } 325 326 static void 327 eqos_setup_rxdesc(struct eqos_softc *sc, int index, bus_addr_t paddr) 328 { 329 330 sc->rx.desc_ring[index].des0 = htole32((uint32_t)paddr); 331 sc->rx.desc_ring[index].des1 = htole32((uint32_t)(paddr >> 32)); 332 sc->rx.desc_ring[index].des2 = htole32(0); 333 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, BUS_DMASYNC_PREWRITE); 334 sc->rx.desc_ring[index].des3 = 335 htole32(EQOS_RDES3_OWN | EQOS_RDES3_IOC | EQOS_RDES3_BUF1V); 336 } 337 338 static int 339 eqos_setup_rxbuf(struct eqos_softc *sc, int index, struct mbuf *m) 340 { 341 struct bus_dma_segment seg; 342 int error, nsegs; 343 344 m_adj(m, ETHER_ALIGN); 345 346 error = bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, 347 sc->rx.buf_map[index].map, m, &seg, &nsegs, 0); 348 if (error) 349 return (error); 350 351 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 352 BUS_DMASYNC_PREREAD); 353 354 sc->rx.buf_map[index].mbuf = m; 355 eqos_setup_rxdesc(sc, index, seg.ds_addr); 356 357 return (0); 358 } 359 360 static struct mbuf * 361 eqos_alloc_mbufcl(struct eqos_softc *sc) 362 { 363 struct mbuf *m; 364 365 if ((m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR))) 366 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 367 return (m); 368 } 369 370 static void 371 eqos_enable_intr(struct eqos_softc *sc) 372 { 373 374 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 375 GMAC_DMA_CHAN0_INTR_ENABLE_NIE | 376 GMAC_DMA_CHAN0_INTR_ENABLE_AIE | 377 GMAC_DMA_CHAN0_INTR_ENABLE_FBE | 378 GMAC_DMA_CHAN0_INTR_ENABLE_RIE | 379 GMAC_DMA_CHAN0_INTR_ENABLE_TIE); 380 } 381 382 static void 383 eqos_disable_intr(struct eqos_softc *sc) 384 { 385 386 WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0); 387 } 388 389 static uint32_t 390 eqos_bitrev32(uint32_t x) 391 { 392 393 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 394 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 395 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 396 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 397 return ((x >> 16) | (x << 16)); 398 } 399 400 static u_int 401 eqos_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 402 { 403 uint32_t crc, *hash = arg; 404 405 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN); 406 crc &= 0x7f; 407 crc = eqos_bitrev32(~crc) >> 26; 408 hash[crc >> 5] |= 1 << (crc & 0x1f); 409 return (1); 410 } 411 412 static void 413 eqos_setup_rxfilter(struct eqos_softc *sc) 414 { 415 if_t ifp = sc->ifp; 416 uint32_t pfil, hash[2]; 417 const uint8_t *eaddr; 418 uint32_t val; 419 420 EQOS_ASSERT_LOCKED(sc); 421 422 pfil = RD4(sc, GMAC_MAC_PACKET_FILTER); 423 pfil &= ~(GMAC_MAC_PACKET_FILTER_PR | 424 GMAC_MAC_PACKET_FILTER_PM | 425 GMAC_MAC_PACKET_FILTER_HMC | 426 GMAC_MAC_PACKET_FILTER_PCF_MASK); 427 hash[0] = hash[1] = 0xffffffff; 428 429 if ((if_getflags(ifp) & IFF_PROMISC)) { 430 pfil |= GMAC_MAC_PACKET_FILTER_PR | 431 GMAC_MAC_PACKET_FILTER_PCF_ALL; 432 } else if ((if_getflags(ifp) & IFF_ALLMULTI)) { 433 pfil |= GMAC_MAC_PACKET_FILTER_PM; 434 } else { 435 hash[0] = hash[1] = 0; 436 pfil |= GMAC_MAC_PACKET_FILTER_HMC; 437 if_foreach_llmaddr(ifp, eqos_hash_maddr, hash); 438 } 439 440 /* Write our unicast address */ 441 eaddr = if_getlladdr(ifp); 442 val = eaddr[4] | (eaddr[5] << 8); 443 WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val); 444 val = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | (eaddr[3] << 24); 445 WR4(sc, GMAC_MAC_ADDRESS0_LOW, val); 446 447 /* Multicast hash filters */ 448 WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[0]); 449 WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[1]); 450 451 /* Packet filter config */ 452 WR4(sc, GMAC_MAC_PACKET_FILTER, pfil); 453 } 454 455 static int 456 eqos_reset(struct eqos_softc *sc) 457 { 458 uint32_t val; 459 int retry; 460 461 WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR); 462 for (retry = 5000; retry > 0; retry--) { 463 DELAY(1000); 464 val = RD4(sc, GMAC_DMA_MODE); 465 if (!(val & GMAC_DMA_MODE_SWR)) 466 return (0); 467 } 468 return (ETIMEDOUT); 469 } 470 471 static void 472 eqos_init_rings(struct eqos_softc *sc) 473 { 474 475 WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR_HI, 476 (uint32_t)(sc->tx.desc_ring_paddr >> 32)); 477 WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR, 478 (uint32_t)sc->tx.desc_ring_paddr); 479 WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1); 480 481 WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR_HI, 482 (uint32_t)(sc->rx.desc_ring_paddr >> 32)); 483 WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR, 484 (uint32_t)sc->rx.desc_ring_paddr); 485 WR4(sc, GMAC_DMA_CHAN0_RX_RING_LEN, RX_DESC_COUNT - 1); 486 487 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, 488 (uint32_t)sc->rx.desc_ring_paddr + DESC_OFFSET(RX_DESC_COUNT)); 489 } 490 491 static void 492 eqos_init(void *if_softc) 493 { 494 struct eqos_softc *sc = if_softc; 495 if_t ifp = sc->ifp; 496 struct mii_data *mii = device_get_softc(sc->miibus); 497 uint32_t val, mtl_tx_val, mtl_rx_val; 498 499 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 500 return; 501 502 EQOS_LOCK(sc); 503 504 eqos_init_rings(sc); 505 506 eqos_setup_rxfilter(sc); 507 508 WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->csr_clock / 1000000) - 1); 509 510 /* Enable transmit and receive DMA */ 511 val = RD4(sc, GMAC_DMA_CHAN0_CONTROL); 512 val &= ~GMAC_DMA_CHAN0_CONTROL_DSL_MASK; 513 val |= ((DESC_ALIGN - 16) / 8) << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT; 514 if (sc->pblx8) 515 val |= GMAC_DMA_CHAN0_CONTROL_PBLX8; 516 WR4(sc, GMAC_DMA_CHAN0_CONTROL, val); 517 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); 518 if (sc->txpbl > 0) 519 val |= (sc->txpbl << GMAC_DMA_CHAN0_TXRX_PBL_SHIFT); 520 val |= GMAC_DMA_CHAN0_TX_CONTROL_OSP; 521 val |= GMAC_DMA_CHAN0_TX_CONTROL_START; 522 WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val); 523 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); 524 if (sc->rxpbl > 0) 525 val |= (sc->rxpbl << GMAC_DMA_CHAN0_TXRX_PBL_SHIFT); 526 val &= ~GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK; 527 val |= (MCLBYTES << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT); 528 val |= GMAC_DMA_CHAN0_RX_CONTROL_START; 529 WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val); 530 531 /* Disable counters */ 532 WR4(sc, GMAC_MMC_CONTROL, 533 GMAC_MMC_CONTROL_CNTFREEZ | 534 GMAC_MMC_CONTROL_CNTPRST | 535 GMAC_MMC_CONTROL_CNTPRSTLVL); 536 537 /* Configure operation modes */ 538 if (sc->thresh_dma_mode) { 539 mtl_tx_val = sc->ttc; 540 mtl_rx_val = sc->rtc; 541 } else { 542 mtl_tx_val = GMAC_MTL_TXQ0_OPERATION_MODE_TSF; 543 mtl_rx_val = GMAC_MTL_RXQ0_OPERATION_MODE_RSF; 544 } 545 546 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, 547 mtl_tx_val | 548 GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN); 549 WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, 550 mtl_rx_val | 551 GMAC_MTL_RXQ0_OPERATION_MODE_FEP | 552 GMAC_MTL_RXQ0_OPERATION_MODE_FUP); 553 554 /* Enable flow control */ 555 val = RD4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL); 556 val |= 0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT; 557 val |= GMAC_MAC_Q0_TX_FLOW_CTRL_TFE; 558 WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, val); 559 val = RD4(sc, GMAC_MAC_RX_FLOW_CTRL); 560 val |= GMAC_MAC_RX_FLOW_CTRL_RFE; 561 WR4(sc, GMAC_MAC_RX_FLOW_CTRL, val); 562 563 /* set RX queue mode. must be in DCB mode. */ 564 WR4(sc, GMAC_RXQ_CTRL0, (GMAC_RXQ_CTRL0_EN_MASK << 16) | 565 GMAC_RXQ_CTRL0_EN_DCB); 566 567 /* Enable transmitter and receiver */ 568 val = RD4(sc, GMAC_MAC_CONFIGURATION); 569 val |= GMAC_MAC_CONFIGURATION_BE; 570 val |= GMAC_MAC_CONFIGURATION_JD; 571 val |= GMAC_MAC_CONFIGURATION_JE; 572 val |= GMAC_MAC_CONFIGURATION_DCRS; 573 val |= GMAC_MAC_CONFIGURATION_TE; 574 val |= GMAC_MAC_CONFIGURATION_RE; 575 WR4(sc, GMAC_MAC_CONFIGURATION, val); 576 577 eqos_enable_intr(sc); 578 579 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 580 581 mii_mediachg(mii); 582 callout_reset(&sc->callout, hz, eqos_tick, sc); 583 584 EQOS_UNLOCK(sc); 585 } 586 587 static void 588 eqos_start_locked(if_t ifp) 589 { 590 struct eqos_softc *sc = if_getsoftc(ifp); 591 struct mbuf *m; 592 int pending = 0; 593 594 if (!sc->link_up) 595 return; 596 597 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 598 IFF_DRV_RUNNING) 599 return; 600 601 while (true) { 602 if (TX_QUEUED(sc->tx.head, sc->tx.tail) >= 603 TX_DESC_COUNT - TX_MAX_SEGS) { 604 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 605 break; 606 } 607 608 if (!(m = if_dequeue(ifp))) 609 break; 610 611 if (eqos_setup_txbuf(sc, m)) { 612 if_sendq_prepend(ifp, m); 613 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 614 break; 615 } 616 bpf_mtap_if(ifp, m); 617 pending++; 618 } 619 620 if (pending) { 621 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map, 622 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 623 624 /* Start and run TX DMA */ 625 WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR, 626 (uint32_t)sc->tx.desc_ring_paddr + DESC_OFFSET(sc->tx.head)); 627 sc->tx_watchdog = WATCHDOG_TIMEOUT_SECS; 628 } 629 } 630 631 static void 632 eqos_start(if_t ifp) 633 { 634 struct eqos_softc *sc = if_getsoftc(ifp); 635 636 EQOS_LOCK(sc); 637 eqos_start_locked(ifp); 638 EQOS_UNLOCK(sc); 639 } 640 641 static void 642 eqos_stop(struct eqos_softc *sc) 643 { 644 if_t ifp = sc->ifp; 645 uint32_t val; 646 int retry; 647 648 EQOS_LOCK(sc); 649 650 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 651 652 callout_stop(&sc->callout); 653 654 /* Disable receiver */ 655 val = RD4(sc, GMAC_MAC_CONFIGURATION); 656 val &= ~GMAC_MAC_CONFIGURATION_RE; 657 WR4(sc, GMAC_MAC_CONFIGURATION, val); 658 659 /* Stop receive DMA */ 660 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); 661 val &= ~GMAC_DMA_CHAN0_RX_CONTROL_START; 662 WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val); 663 664 /* Stop transmit DMA */ 665 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); 666 val &= ~GMAC_DMA_CHAN0_TX_CONTROL_START; 667 WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val); 668 669 /* Flush data in the TX FIFO */ 670 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 671 val |= GMAC_MTL_TXQ0_OPERATION_MODE_FTQ; 672 WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val); 673 for (retry = 10000; retry > 0; retry--) { 674 val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE); 675 if (!(val & GMAC_MTL_TXQ0_OPERATION_MODE_FTQ)) 676 break; 677 DELAY(10); 678 } 679 if (!retry) 680 device_printf(sc->dev, "timeout flushing TX queue\n"); 681 682 /* Disable transmitter */ 683 val = RD4(sc, GMAC_MAC_CONFIGURATION); 684 val &= ~GMAC_MAC_CONFIGURATION_TE; 685 WR4(sc, GMAC_MAC_CONFIGURATION, val); 686 687 eqos_disable_intr(sc); 688 689 EQOS_UNLOCK(sc); 690 } 691 692 static void 693 eqos_rxintr(struct eqos_softc *sc) 694 { 695 if_t ifp = sc->ifp; 696 struct mbuf *m; 697 uint32_t rdes3; 698 int error, length; 699 700 while (true) { 701 rdes3 = le32toh(sc->rx.desc_ring[sc->rx.head].des3); 702 if ((rdes3 & EQOS_RDES3_OWN)) 703 break; 704 705 if (rdes3 & EQOS_RDES3_RE) { 706 printf("Receive error rdes3=%08x\n", rdes3); 707 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 708 } 709 if (rdes3 & EQOS_RDES3_OE) { 710 if (rdes3 & EQOS_RDES3_LENGTH_MASK) { 711 printf("Receive overflow error rdes3=%08x\n", rdes3); 712 } 713 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 714 } 715 716 bus_dmamap_sync(sc->rx.buf_tag, 717 sc->rx.buf_map[sc->rx.head].map, BUS_DMASYNC_POSTREAD); 718 bus_dmamap_unload(sc->rx.buf_tag, 719 sc->rx.buf_map[sc->rx.head].map); 720 721 length = rdes3 & EQOS_RDES3_LENGTH_MASK; 722 if (length) { 723 m = sc->rx.buf_map[sc->rx.head].mbuf; 724 m->m_pkthdr.rcvif = ifp; 725 m->m_pkthdr.len = length; 726 m->m_len = length; 727 m->m_nextpkt = NULL; 728 729 /* Remove trailing FCS */ 730 m_adj(m, -ETHER_CRC_LEN); 731 732 EQOS_UNLOCK(sc); 733 if_input(ifp, m); 734 EQOS_LOCK(sc); 735 } 736 737 if ((m = eqos_alloc_mbufcl(sc))) { 738 if ((error = eqos_setup_rxbuf(sc, sc->rx.head, m))) 739 printf("ERROR: Hole in RX ring!!\n"); 740 } else 741 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 742 743 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 744 745 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR, 746 (uint32_t)sc->rx.desc_ring_paddr + DESC_OFFSET(sc->rx.head)); 747 748 sc->rx.head = RX_NEXT(sc->rx.head); 749 } 750 } 751 752 static void 753 eqos_txintr(struct eqos_softc *sc) 754 { 755 if_t ifp = sc->ifp; 756 struct eqos_bufmap *bmap; 757 uint32_t tdes3; 758 759 EQOS_ASSERT_LOCKED(sc); 760 761 while (sc->tx.tail != sc->tx.head) { 762 tdes3 = le32toh(sc->tx.desc_ring[sc->tx.tail].des3); 763 if ((tdes3 & EQOS_TDES3_OWN)) 764 break; 765 766 bmap = &sc->tx.buf_map[sc->tx.tail]; 767 if (bmap->mbuf) { 768 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 769 BUS_DMASYNC_POSTWRITE); 770 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 771 m_freem(bmap->mbuf); 772 bmap->mbuf = NULL; 773 } 774 775 eqos_setup_txdesc(sc, sc->tx.tail, 0, 0, 0, 0); 776 777 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 778 779 /* Last descriptor in a packet contains DMA status */ 780 if ((tdes3 & EQOS_TDES3_LD)) { 781 if ((tdes3 & EQOS_TDES3_DE)) { 782 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 783 } else if ((tdes3 & EQOS_TDES3_ES)) { 784 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 785 } else { 786 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 787 } 788 } 789 sc->tx.tail = TX_NEXT(sc->tx.tail); 790 } 791 if (sc->tx.tail == sc->tx.head) 792 sc->tx_watchdog = 0; 793 eqos_start_locked(sc->ifp); 794 } 795 796 static void 797 eqos_intr_mtl(struct eqos_softc *sc, uint32_t mtl_status) 798 { 799 uint32_t mtl_istat = 0; 800 801 if ((mtl_status & GMAC_MTL_INTERRUPT_STATUS_Q0IS)) { 802 uint32_t mtl_clear = 0; 803 804 mtl_istat = RD4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS); 805 if ((mtl_istat & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS)) { 806 mtl_clear |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS; 807 } 808 if ((mtl_istat & GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS)) { 809 mtl_clear |= GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS; 810 } 811 if (mtl_clear) { 812 mtl_clear |= (mtl_istat & 813 (GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE | 814 GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE)); 815 WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, mtl_clear); 816 } 817 } 818 if (bootverbose) 819 device_printf(sc->dev, 820 "GMAC_MTL_INTERRUPT_STATUS = 0x%08X, " 821 "GMAC_MTL_INTERRUPT_STATUS_Q0IS = 0x%08X\n", 822 mtl_status, mtl_istat); 823 } 824 825 static void 826 eqos_tick(void *softc) 827 { 828 struct eqos_softc *sc = softc; 829 struct mii_data *mii = device_get_softc(sc->miibus); 830 bool link_status; 831 832 EQOS_ASSERT_LOCKED(sc); 833 834 if (sc->tx_watchdog > 0) 835 if (!--sc->tx_watchdog) { 836 device_printf(sc->dev, "watchdog timeout\n"); 837 eqos_txintr(sc); 838 } 839 840 link_status = sc->link_up; 841 mii_tick(mii); 842 if (sc->link_up && !link_status) 843 eqos_start_locked(sc->ifp); 844 845 callout_reset(&sc->callout, hz, eqos_tick, sc); 846 } 847 848 static void 849 eqos_intr(void *arg) 850 { 851 struct eqos_softc *sc = arg; 852 uint32_t mac_status, mtl_status, dma_status, rx_tx_status; 853 854 mac_status = RD4(sc, GMAC_MAC_INTERRUPT_STATUS); 855 mac_status &= RD4(sc, GMAC_MAC_INTERRUPT_ENABLE); 856 857 if (mac_status) 858 device_printf(sc->dev, "MAC interrupt\n"); 859 860 if ((mtl_status = RD4(sc, GMAC_MTL_INTERRUPT_STATUS))) 861 eqos_intr_mtl(sc, mtl_status); 862 863 dma_status = RD4(sc, GMAC_DMA_CHAN0_STATUS); 864 dma_status &= RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE); 865 866 if (dma_status) 867 WR4(sc, GMAC_DMA_CHAN0_STATUS, dma_status); 868 869 EQOS_LOCK(sc); 870 871 if (dma_status & GMAC_DMA_CHAN0_STATUS_RI) 872 eqos_rxintr(sc); 873 874 if (dma_status & GMAC_DMA_CHAN0_STATUS_TI) 875 eqos_txintr(sc); 876 877 EQOS_UNLOCK(sc); 878 879 if (!(mac_status | mtl_status | dma_status)) { 880 device_printf(sc->dev, 881 "spurious interrupt mac=%08x mtl=%08x dma=%08x\n", 882 RD4(sc, GMAC_MAC_INTERRUPT_STATUS), 883 RD4(sc, GMAC_MTL_INTERRUPT_STATUS), 884 RD4(sc, GMAC_DMA_CHAN0_STATUS)); 885 } 886 if ((rx_tx_status = RD4(sc, GMAC_MAC_RX_TX_STATUS))) 887 device_printf(sc->dev, "RX/TX status interrupt\n"); 888 } 889 890 static int 891 eqos_ioctl(if_t ifp, u_long cmd, caddr_t data) 892 { 893 struct eqos_softc *sc = if_getsoftc(ifp); 894 struct ifreq *ifr = (struct ifreq *)data; 895 struct mii_data *mii; 896 int flags, mask; 897 int error = 0; 898 899 switch (cmd) { 900 case SIOCSIFFLAGS: 901 if (if_getflags(ifp) & IFF_UP) { 902 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 903 flags = if_getflags(ifp); 904 if ((flags & (IFF_PROMISC|IFF_ALLMULTI))) { 905 EQOS_LOCK(sc); 906 eqos_setup_rxfilter(sc); 907 EQOS_UNLOCK(sc); 908 } 909 } else { 910 eqos_init(sc); 911 } 912 } else { 913 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 914 eqos_stop(sc); 915 } 916 break; 917 918 case SIOCADDMULTI: 919 case SIOCDELMULTI: 920 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 921 EQOS_LOCK(sc); 922 eqos_setup_rxfilter(sc); 923 EQOS_UNLOCK(sc); 924 } 925 break; 926 927 case SIOCSIFMEDIA: 928 case SIOCGIFMEDIA: 929 mii = device_get_softc(sc->miibus); 930 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 931 break; 932 933 case SIOCSIFCAP: 934 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 935 if (mask & IFCAP_VLAN_MTU) 936 if_togglecapenable(ifp, IFCAP_VLAN_MTU); 937 if (mask & IFCAP_RXCSUM) 938 if_togglecapenable(ifp, IFCAP_RXCSUM); 939 if (mask & IFCAP_TXCSUM) 940 if_togglecapenable(ifp, IFCAP_TXCSUM); 941 if ((if_getcapenable(ifp) & IFCAP_TXCSUM)) 942 if_sethwassistbits(ifp, 943 CSUM_IP | CSUM_UDP | CSUM_TCP, 0); 944 else 945 if_sethwassistbits(ifp, 946 0, CSUM_IP | CSUM_UDP | CSUM_TCP); 947 break; 948 949 default: 950 error = ether_ioctl(ifp, cmd, data); 951 break; 952 } 953 954 return (error); 955 } 956 957 static void 958 eqos_get_eaddr(struct eqos_softc *sc, uint8_t *eaddr) 959 { 960 uint32_t maclo, machi; 961 962 maclo = htobe32(RD4(sc, GMAC_MAC_ADDRESS0_LOW)); 963 machi = htobe16(RD4(sc, GMAC_MAC_ADDRESS0_HIGH) & 0xFFFF); 964 965 /* if no valid MAC address generate random */ 966 if (maclo == 0xffffffff && machi == 0xffff) { 967 maclo = 0xf2 | (arc4random() & 0xffff0000); 968 machi = arc4random() & 0x0000ffff; 969 } 970 eaddr[0] = maclo & 0xff; 971 eaddr[1] = (maclo >> 8) & 0xff; 972 eaddr[2] = (maclo >> 16) & 0xff; 973 eaddr[3] = (maclo >> 24) & 0xff; 974 eaddr[4] = machi & 0xff; 975 eaddr[5] = (machi >> 8) & 0xff; 976 } 977 978 static void 979 eqos_axi_configure(struct eqos_softc *sc) 980 { 981 uint32_t val; 982 983 val = RD4(sc, GMAC_DMA_SYSBUS_MODE); 984 985 /* Max Write Outstanding Req Limit */ 986 val &= ~GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK; 987 val |= 0x03 << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT; 988 989 /* Max Read Outstanding Req Limit */ 990 val &= ~GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK; 991 val |= 0x07 << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT; 992 993 /* Allowed Burst Length's */ 994 val |= GMAC_DMA_SYSBUS_MODE_BLEN16; 995 val |= GMAC_DMA_SYSBUS_MODE_BLEN8; 996 val |= GMAC_DMA_SYSBUS_MODE_BLEN4; 997 998 /* Fixed Burst Length */ 999 val |= GMAC_DMA_SYSBUS_MODE_MB; 1000 1001 WR4(sc, GMAC_DMA_SYSBUS_MODE, val); 1002 } 1003 1004 static void 1005 eqos_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1006 { 1007 1008 if (!error) 1009 *(bus_addr_t *)arg = segs[0].ds_addr; 1010 } 1011 1012 static int 1013 eqos_setup_dma(struct eqos_softc *sc) 1014 { 1015 struct mbuf *m; 1016 int error, i; 1017 1018 /* Set up TX descriptor ring, descriptors, and dma maps */ 1019 error = bus_dma_tag_create( 1020 bus_get_dma_tag(sc->dev), /* Parent tag */ 1021 DESC_ALIGN, DESC_BOUNDARY, /* alignment, boundary */ 1022 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1023 BUS_SPACE_MAXADDR, /* highaddr */ 1024 NULL, NULL, /* filterfunc, filterarg */ 1025 TX_DESC_SIZE, 1, /* maxsize, nsegs */ 1026 TX_DESC_SIZE, /* maxsegsize */ 1027 0, /* flags */ 1028 NULL, NULL, /* lockfunc, lockarg */ 1029 &sc->tx.desc_tag); 1030 if (error != 0) { 1031 device_printf(sc->dev, "could not create TX ring DMA tag\n"); 1032 return (error); 1033 } 1034 1035 error = bus_dmamem_alloc(sc->tx.desc_tag, 1036 (void**)&sc->tx.desc_ring, 1037 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 1038 &sc->tx.desc_map); 1039 if (error != 0) { 1040 device_printf(sc->dev, 1041 "could not allocate TX descriptor ring.\n"); 1042 return (error); 1043 } 1044 1045 1046 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map, 1047 sc->tx.desc_ring, TX_DESC_SIZE, 1048 eqos_get1paddr, &sc->tx.desc_ring_paddr, 1049 0); 1050 if (error != 0) { 1051 device_printf(sc->dev, 1052 "could not load TX descriptor ring map.\n"); 1053 return (error); 1054 } 1055 1056 error = bus_dma_tag_create( 1057 bus_get_dma_tag(sc->dev), /* Parent tag */ 1058 1, 0, /* alignment, boundary */ 1059 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1060 BUS_SPACE_MAXADDR, /* highaddr */ 1061 NULL, NULL, /* filterfunc, filterarg */ 1062 MCLBYTES*TX_MAX_SEGS, TX_MAX_SEGS, /* maxsize, nsegs */ 1063 MCLBYTES, /* maxsegsize */ 1064 0, /* flags */ 1065 NULL, NULL, /* lockfunc, lockarg */ 1066 &sc->tx.buf_tag); 1067 if (error != 0) { 1068 device_printf(sc->dev, "could not create TX buffer DMA tag.\n"); 1069 return (error); 1070 } 1071 1072 for (i = 0; i < TX_DESC_COUNT; i++) { 1073 if ((error = bus_dmamap_create(sc->tx.buf_tag, BUS_DMA_COHERENT, 1074 &sc->tx.buf_map[i].map))) { 1075 device_printf(sc->dev, "cannot create TX buffer map\n"); 1076 return (error); 1077 } 1078 eqos_setup_txdesc(sc, i, EQOS_TDES3_OWN, 0, 0, 0); 1079 } 1080 1081 /* Set up RX descriptor ring, descriptors, dma maps, and mbufs */ 1082 error = bus_dma_tag_create( 1083 bus_get_dma_tag(sc->dev), /* Parent tag */ 1084 DESC_ALIGN, DESC_BOUNDARY, /* alignment, boundary */ 1085 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1086 BUS_SPACE_MAXADDR, /* highaddr */ 1087 NULL, NULL, /* filterfunc, filterarg */ 1088 RX_DESC_SIZE, 1, /* maxsize, nsegs */ 1089 RX_DESC_SIZE, /* maxsegsize */ 1090 0, /* flags */ 1091 NULL, NULL, /* lockfunc, lockarg */ 1092 &sc->rx.desc_tag); 1093 if (error != 0) { 1094 device_printf(sc->dev, "could not create RX ring DMA tag.\n"); 1095 return (error); 1096 } 1097 1098 error = bus_dmamem_alloc(sc->rx.desc_tag, 1099 (void **)&sc->rx.desc_ring, 1100 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 1101 &sc->rx.desc_map); 1102 if (error != 0) { 1103 device_printf(sc->dev, 1104 "could not allocate RX descriptor ring.\n"); 1105 return (error); 1106 } 1107 1108 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map, 1109 sc->rx.desc_ring, RX_DESC_SIZE, 1110 eqos_get1paddr, &sc->rx.desc_ring_paddr, 1111 0); 1112 if (error != 0) { 1113 device_printf(sc->dev, 1114 "could not load RX descriptor ring map.\n"); 1115 return (error); 1116 } 1117 1118 error = bus_dma_tag_create( 1119 bus_get_dma_tag(sc->dev), /* Parent tag */ 1120 1, 0, /* alignment, boundary */ 1121 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1122 BUS_SPACE_MAXADDR, /* highaddr */ 1123 NULL, NULL, /* filterfunc, filterarg */ 1124 MCLBYTES, 1, /* maxsize, nsegs */ 1125 MCLBYTES, /* maxsegsize */ 1126 0, /* flags */ 1127 NULL, NULL, /* lockfunc, lockarg */ 1128 &sc->rx.buf_tag); 1129 if (error != 0) { 1130 device_printf(sc->dev, "could not create RX buf DMA tag.\n"); 1131 return (error); 1132 } 1133 1134 for (i = 0; i < RX_DESC_COUNT; i++) { 1135 if ((error = bus_dmamap_create(sc->rx.buf_tag, BUS_DMA_COHERENT, 1136 &sc->rx.buf_map[i].map))) { 1137 device_printf(sc->dev, "cannot create RX buffer map\n"); 1138 return (error); 1139 } 1140 if (!(m = eqos_alloc_mbufcl(sc))) { 1141 device_printf(sc->dev, "cannot allocate RX mbuf\n"); 1142 return (ENOMEM); 1143 } 1144 if ((error = eqos_setup_rxbuf(sc, i, m))) { 1145 device_printf(sc->dev, "cannot create RX buffer\n"); 1146 return (error); 1147 } 1148 } 1149 1150 if (bootverbose) 1151 device_printf(sc->dev, "TX ring @ 0x%lx, RX ring @ 0x%lx\n", 1152 sc->tx.desc_ring_paddr, sc->rx.desc_ring_paddr); 1153 return (0); 1154 } 1155 1156 static int 1157 eqos_attach(device_t dev) 1158 { 1159 struct eqos_softc *sc = device_get_softc(dev); 1160 if_t ifp; 1161 uint32_t ver; 1162 uint8_t eaddr[ETHER_ADDR_LEN]; 1163 u_int userver, snpsver; 1164 int error; 1165 int n; 1166 1167 /* default values */ 1168 sc->thresh_dma_mode = false; 1169 sc->pblx8 = true; 1170 sc->txpbl = 0; 1171 sc->rxpbl = 0; 1172 sc->ttc = 0x10; 1173 sc->rtc = 0; 1174 1175 /* setup resources */ 1176 if (bus_alloc_resources(dev, eqos_spec, sc->res)) { 1177 device_printf(dev, "Could not allocate resources\n"); 1178 bus_release_resources(dev, eqos_spec, sc->res); 1179 return (ENXIO); 1180 } 1181 1182 if ((error = IF_EQOS_INIT(dev))) 1183 return (error); 1184 1185 sc->dev = dev; 1186 ver = RD4(sc, GMAC_MAC_VERSION); 1187 userver = (ver & GMAC_MAC_VERSION_USERVER_MASK) >> 1188 GMAC_MAC_VERSION_USERVER_SHIFT; 1189 snpsver = ver & GMAC_MAC_VERSION_SNPSVER_MASK; 1190 1191 if (snpsver != 0x51 && snpsver != 0x52) { 1192 device_printf(dev, "EQOS version 0x%02x not supported\n", 1193 snpsver); 1194 return (ENXIO); 1195 } 1196 1197 for (n = 0; n < 4; n++) 1198 sc->hw_feature[n] = RD4(sc, GMAC_MAC_HW_FEATURE(n)); 1199 1200 if (bootverbose) { 1201 device_printf(dev, "DesignWare EQOS ver 0x%02x (0x%02x)\n", 1202 snpsver, userver); 1203 device_printf(dev, "hw features %08x %08x %08x %08x\n", 1204 sc->hw_feature[0], sc->hw_feature[1], 1205 sc->hw_feature[2], sc->hw_feature[3]); 1206 } 1207 1208 mtx_init(&sc->lock, "eqos lock", MTX_NETWORK_LOCK, MTX_DEF); 1209 callout_init_mtx(&sc->callout, &sc->lock, 0); 1210 1211 eqos_get_eaddr(sc, eaddr); 1212 if (bootverbose) 1213 device_printf(sc->dev, "Ethernet address %6D\n", eaddr, ":"); 1214 1215 /* Soft reset EMAC core */ 1216 if ((error = eqos_reset(sc))) { 1217 device_printf(sc->dev, "reset timeout!\n"); 1218 return (error); 1219 } 1220 1221 /* Configure AXI Bus mode parameters */ 1222 eqos_axi_configure(sc); 1223 1224 /* Setup DMA descriptors */ 1225 if (eqos_setup_dma(sc)) { 1226 device_printf(sc->dev, "failed to setup DMA descriptors\n"); 1227 return (EINVAL); 1228 } 1229 1230 /* setup interrupt delivery */ 1231 if ((bus_setup_intr(dev, sc->res[EQOS_RES_IRQ0], EQOS_INTR_FLAGS, 1232 NULL, eqos_intr, sc, &sc->irq_handle))) { 1233 device_printf(dev, "unable to setup 1st interrupt\n"); 1234 bus_release_resources(dev, eqos_spec, sc->res); 1235 return (ENXIO); 1236 } 1237 1238 /* Setup ethernet interface */ 1239 ifp = sc->ifp = if_alloc(IFT_ETHER); 1240 if_setsoftc(ifp, sc); 1241 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 1242 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1243 if_setstartfn(ifp, eqos_start); 1244 if_setioctlfn(ifp, eqos_ioctl); 1245 if_setinitfn(ifp, eqos_init); 1246 if_setsendqlen(ifp, TX_DESC_COUNT - 1); 1247 if_setsendqready(ifp); 1248 if_setcapabilities(ifp, IFCAP_VLAN_MTU /*| IFCAP_HWCSUM*/); 1249 if_setcapenable(ifp, if_getcapabilities(ifp)); 1250 1251 /* Attach MII driver */ 1252 if ((error = mii_attach(sc->dev, &sc->miibus, ifp, eqos_media_change, 1253 eqos_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, 1254 MII_OFFSET_ANY, 0))) { 1255 device_printf(sc->dev, "PHY attach failed\n"); 1256 return (ENXIO); 1257 } 1258 1259 /* Attach ethernet interface */ 1260 ether_ifattach(ifp, eaddr); 1261 1262 return (0); 1263 } 1264 1265 static int 1266 eqos_detach(device_t dev) 1267 { 1268 struct eqos_softc *sc = device_get_softc(dev); 1269 int i; 1270 1271 if (device_is_attached(dev)) { 1272 EQOS_LOCK(sc); 1273 eqos_stop(sc); 1274 EQOS_UNLOCK(sc); 1275 if_setflagbits(sc->ifp, 0, IFF_UP); 1276 ether_ifdetach(sc->ifp); 1277 } 1278 1279 bus_generic_detach(dev); 1280 1281 if (sc->irq_handle) 1282 bus_teardown_intr(dev, sc->res[EQOS_RES_IRQ0], 1283 sc->irq_handle); 1284 1285 if (sc->ifp) 1286 if_free(sc->ifp); 1287 1288 bus_release_resources(dev, eqos_spec, sc->res); 1289 1290 if (sc->tx.desc_tag) { 1291 if (sc->tx.desc_map) { 1292 bus_dmamap_unload(sc->tx.desc_tag, sc->tx.desc_map); 1293 bus_dmamem_free(sc->tx.desc_tag, sc->tx.desc_ring, 1294 sc->tx.desc_map); 1295 } 1296 bus_dma_tag_destroy(sc->tx.desc_tag); 1297 } 1298 if (sc->tx.buf_tag) { 1299 for (i = 0; i < TX_DESC_COUNT; i++) { 1300 m_free(sc->tx.buf_map[i].mbuf); 1301 bus_dmamap_destroy(sc->tx.buf_tag, 1302 sc->tx.buf_map[i].map); 1303 } 1304 bus_dma_tag_destroy(sc->tx.buf_tag); 1305 } 1306 1307 if (sc->rx.desc_tag) { 1308 if (sc->rx.desc_map) { 1309 bus_dmamap_unload(sc->rx.desc_tag, sc->rx.desc_map); 1310 bus_dmamem_free(sc->rx.desc_tag, sc->rx.desc_ring, 1311 sc->rx.desc_map); 1312 } 1313 bus_dma_tag_destroy(sc->rx.desc_tag); 1314 } 1315 if (sc->rx.buf_tag) { 1316 for (i = 0; i < RX_DESC_COUNT; i++) { 1317 m_free(sc->rx.buf_map[i].mbuf); 1318 bus_dmamap_destroy(sc->rx.buf_tag, 1319 sc->rx.buf_map[i].map); 1320 } 1321 bus_dma_tag_destroy(sc->rx.buf_tag); 1322 } 1323 1324 mtx_destroy(&sc->lock); 1325 1326 return (0); 1327 } 1328 1329 1330 static device_method_t eqos_methods[] = { 1331 /* Device Interface */ 1332 DEVMETHOD(device_attach, eqos_attach), 1333 DEVMETHOD(device_detach, eqos_detach), 1334 1335 /* MII Interface */ 1336 DEVMETHOD(miibus_readreg, eqos_miibus_readreg), 1337 DEVMETHOD(miibus_writereg, eqos_miibus_writereg), 1338 DEVMETHOD(miibus_statchg, eqos_miibus_statchg), 1339 1340 DEVMETHOD_END 1341 }; 1342 1343 driver_t eqos_driver = { 1344 "eqos", 1345 eqos_methods, 1346 sizeof(struct eqos_softc), 1347 }; 1348 1349 DRIVER_MODULE(miibus, eqos, miibus_driver, 0, 0); 1350