1*9c067b84SDoug Ambrisko /* SPDX-License-Identifier: BSD-3-Clause 2*9c067b84SDoug Ambrisko * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3*9c067b84SDoug Ambrisko * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4*9c067b84SDoug Ambrisko */ 5*9c067b84SDoug Ambrisko 6*9c067b84SDoug Ambrisko #include "enic.h" 7*9c067b84SDoug Ambrisko #include "vnic_dev.h" 8*9c067b84SDoug Ambrisko #include "vnic_wq.h" 9*9c067b84SDoug Ambrisko 10*9c067b84SDoug Ambrisko void vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index, 11*9c067b84SDoug Ambrisko unsigned int fetch_index, unsigned int posted_index, 12*9c067b84SDoug Ambrisko unsigned int error_interrupt_enable, 13*9c067b84SDoug Ambrisko unsigned int error_interrupt_offset) 14*9c067b84SDoug Ambrisko { 15*9c067b84SDoug Ambrisko u64 paddr; 16*9c067b84SDoug Ambrisko unsigned int count = wq->ring.desc_count; 17*9c067b84SDoug Ambrisko 18*9c067b84SDoug Ambrisko paddr = (u64)wq->ring.base_addr | VNIC_PADDR_TARGET; 19*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_8(wq->ctrl, TX_RING_BASE, paddr); 20*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_RING_SIZE, count); 21*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_FETCH_INDEX, fetch_index); 22*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_POSTED_INDEX, posted_index); 23*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_CQ_INDEX, cq_index); 24*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_INTR_ENABLE, error_interrupt_enable); 25*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_INTR_OFFSET, error_interrupt_offset); 26*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_STATUS, 0); 27*9c067b84SDoug Ambrisko 28*9c067b84SDoug Ambrisko wq->head_idx = fetch_index; 29*9c067b84SDoug Ambrisko wq->tail_idx = wq->head_idx; 30*9c067b84SDoug Ambrisko } 31*9c067b84SDoug Ambrisko 32*9c067b84SDoug Ambrisko void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index, 33*9c067b84SDoug Ambrisko unsigned int error_interrupt_enable, 34*9c067b84SDoug Ambrisko unsigned int error_interrupt_offset) 35*9c067b84SDoug Ambrisko { 36*9c067b84SDoug Ambrisko vnic_wq_init_start(wq, cq_index, 0, 0, 37*9c067b84SDoug Ambrisko error_interrupt_enable, 38*9c067b84SDoug Ambrisko error_interrupt_offset); 39*9c067b84SDoug Ambrisko wq->cq_pend = 0; 40*9c067b84SDoug Ambrisko wq->last_completed_index = 0; 41*9c067b84SDoug Ambrisko } 42*9c067b84SDoug Ambrisko 43*9c067b84SDoug Ambrisko unsigned int vnic_wq_error_status(struct vnic_wq *wq) 44*9c067b84SDoug Ambrisko { 45*9c067b84SDoug Ambrisko return ENIC_BUS_READ_4(wq->ctrl, TX_ERROR_STATUS); 46*9c067b84SDoug Ambrisko } 47*9c067b84SDoug Ambrisko 48*9c067b84SDoug Ambrisko void vnic_wq_enable(struct vnic_wq *wq) 49*9c067b84SDoug Ambrisko { 50*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_ENABLE, 1); 51*9c067b84SDoug Ambrisko } 52*9c067b84SDoug Ambrisko 53*9c067b84SDoug Ambrisko int vnic_wq_disable(struct vnic_wq *wq) 54*9c067b84SDoug Ambrisko { 55*9c067b84SDoug Ambrisko unsigned int wait; 56*9c067b84SDoug Ambrisko 57*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_ENABLE, 0); 58*9c067b84SDoug Ambrisko 59*9c067b84SDoug Ambrisko /* Wait for HW to ACK disable request */ 60*9c067b84SDoug Ambrisko for (wait = 0; wait < 1000; wait++) { 61*9c067b84SDoug Ambrisko if (!(ENIC_BUS_READ_4(wq->ctrl, TX_RUNNING))) 62*9c067b84SDoug Ambrisko return 0; 63*9c067b84SDoug Ambrisko udelay(10); 64*9c067b84SDoug Ambrisko } 65*9c067b84SDoug Ambrisko 66*9c067b84SDoug Ambrisko pr_err("Failed to disable WQ[%d]\n", wq->index); 67*9c067b84SDoug Ambrisko 68*9c067b84SDoug Ambrisko return -ETIMEDOUT; 69*9c067b84SDoug Ambrisko } 70*9c067b84SDoug Ambrisko 71*9c067b84SDoug Ambrisko void vnic_wq_clean(struct vnic_wq *wq) 72*9c067b84SDoug Ambrisko { 73*9c067b84SDoug Ambrisko unsigned int to_clean = wq->tail_idx; 74*9c067b84SDoug Ambrisko 75*9c067b84SDoug Ambrisko while (vnic_wq_desc_used(wq) > 0) { 76*9c067b84SDoug Ambrisko to_clean = buf_idx_incr(wq->ring.desc_count, to_clean); 77*9c067b84SDoug Ambrisko wq->ring.desc_avail++; 78*9c067b84SDoug Ambrisko } 79*9c067b84SDoug Ambrisko 80*9c067b84SDoug Ambrisko wq->head_idx = 0; 81*9c067b84SDoug Ambrisko wq->tail_idx = 0; 82*9c067b84SDoug Ambrisko wq->last_completed_index = 0; 83*9c067b84SDoug Ambrisko 84*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_FETCH_INDEX, 0); 85*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_POSTED_INDEX, 0); 86*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_STATUS, 0); 87*9c067b84SDoug Ambrisko 88*9c067b84SDoug Ambrisko vnic_dev_clear_desc_ring(&wq->ring); 89*9c067b84SDoug Ambrisko } 90