1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Alstom Group. 5 * Copyright (c) 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/endian.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/rman.h> 34 #include <sys/socket.h> 35 #include <sys/sockio.h> 36 37 #include <machine/bus.h> 38 #include <machine/resource.h> 39 40 #include <net/ethernet.h> 41 #include <net/if.h> 42 #include <net/if_dl.h> 43 #include <net/if_var.h> 44 #include <net/if_types.h> 45 #include <net/if_media.h> 46 #include <net/iflib.h> 47 #include <net/rss_config.h> 48 49 #include <dev/enetc/enetc_hw.h> 50 #include <dev/enetc/enetc.h> 51 #include <dev/enetc/enetc_mdio.h> 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/ofw_bus_subr.h> 59 60 #include "ifdi_if.h" 61 #include "miibus_if.h" 62 63 static device_register_t enetc_register; 64 65 static ifdi_attach_pre_t enetc_attach_pre; 66 static ifdi_attach_post_t enetc_attach_post; 67 static ifdi_detach_t enetc_detach; 68 69 static ifdi_tx_queues_alloc_t enetc_tx_queues_alloc; 70 static ifdi_rx_queues_alloc_t enetc_rx_queues_alloc; 71 static ifdi_queues_free_t enetc_queues_free; 72 73 static ifdi_init_t enetc_init; 74 static ifdi_stop_t enetc_stop; 75 76 static ifdi_msix_intr_assign_t enetc_msix_intr_assign; 77 static ifdi_tx_queue_intr_enable_t enetc_tx_queue_intr_enable; 78 static ifdi_rx_queue_intr_enable_t enetc_rx_queue_intr_enable; 79 static ifdi_intr_enable_t enetc_intr_enable; 80 static ifdi_intr_disable_t enetc_intr_disable; 81 82 static int enetc_isc_txd_encap(void*, if_pkt_info_t); 83 static void enetc_isc_txd_flush(void*, uint16_t, qidx_t); 84 static int enetc_isc_txd_credits_update(void*, uint16_t, bool); 85 static int enetc_isc_rxd_available(void*, uint16_t, qidx_t, qidx_t); 86 static int enetc_isc_rxd_pkt_get(void*, if_rxd_info_t); 87 static void enetc_isc_rxd_refill(void*, if_rxd_update_t); 88 static void enetc_isc_rxd_flush(void*, uint16_t, uint8_t, qidx_t); 89 90 static void enetc_vlan_register(if_ctx_t, uint16_t); 91 static void enetc_vlan_unregister(if_ctx_t, uint16_t); 92 93 static uint64_t enetc_get_counter(if_ctx_t, ift_counter); 94 static int enetc_promisc_set(if_ctx_t, int); 95 static int enetc_mtu_set(if_ctx_t, uint32_t); 96 static void enetc_setup_multicast(if_ctx_t); 97 static void enetc_timer(if_ctx_t, uint16_t); 98 static void enetc_update_admin_status(if_ctx_t); 99 static bool enetc_if_needs_restart(if_ctx_t, enum iflib_restart_event); 100 101 static miibus_readreg_t enetc_miibus_readreg; 102 static miibus_writereg_t enetc_miibus_writereg; 103 static miibus_linkchg_t enetc_miibus_linkchg; 104 static miibus_statchg_t enetc_miibus_statchg; 105 106 static int enetc_media_change(if_t); 107 static void enetc_media_status(if_t, struct ifmediareq*); 108 109 static int enetc_fixed_media_change(if_t); 110 static void enetc_fixed_media_status(if_t, struct ifmediareq*); 111 112 static void enetc_max_nqueues(struct enetc_softc*, int*, int*); 113 static int enetc_setup_phy(struct enetc_softc*); 114 115 static void enetc_get_hwaddr(struct enetc_softc*); 116 static void enetc_set_hwaddr(struct enetc_softc*); 117 static int enetc_setup_rss(struct enetc_softc*); 118 119 static void enetc_init_hw(struct enetc_softc*); 120 static void enetc_init_ctrl(struct enetc_softc*); 121 static void enetc_init_tx(struct enetc_softc*); 122 static void enetc_init_rx(struct enetc_softc*); 123 124 static int enetc_ctrl_send(struct enetc_softc*, 125 uint16_t, uint16_t, iflib_dma_info_t); 126 127 static const char enetc_driver_version[] = "1.0.0"; 128 129 static const pci_vendor_info_t enetc_vendor_info_array[] = { 130 PVID(PCI_VENDOR_FREESCALE, ENETC_DEV_ID_PF, 131 "Freescale ENETC PCIe Gigabit Ethernet Controller"), 132 PVID_END 133 }; 134 135 #define ENETC_IFCAPS (IFCAP_VLAN_MTU | IFCAP_RXCSUM | IFCAP_JUMBO_MTU | \ 136 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER) 137 138 static device_method_t enetc_methods[] = { 139 DEVMETHOD(device_register, enetc_register), 140 DEVMETHOD(device_probe, iflib_device_probe), 141 DEVMETHOD(device_attach, iflib_device_attach), 142 DEVMETHOD(device_detach, iflib_device_detach), 143 DEVMETHOD(device_shutdown, iflib_device_shutdown), 144 DEVMETHOD(device_suspend, iflib_device_suspend), 145 DEVMETHOD(device_resume, iflib_device_resume), 146 147 DEVMETHOD(miibus_readreg, enetc_miibus_readreg), 148 DEVMETHOD(miibus_writereg, enetc_miibus_writereg), 149 DEVMETHOD(miibus_linkchg, enetc_miibus_linkchg), 150 DEVMETHOD(miibus_statchg, enetc_miibus_statchg), 151 152 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 153 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 154 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 155 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 156 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 157 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 158 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 159 160 DEVMETHOD_END 161 }; 162 163 static driver_t enetc_driver = { 164 "enetc", enetc_methods, sizeof(struct enetc_softc) 165 }; 166 167 DRIVER_MODULE(miibus, enetc, miibus_fdt_driver, NULL, NULL); 168 /* Make sure miibus gets procesed first. */ 169 DRIVER_MODULE_ORDERED(enetc, pci, enetc_driver, NULL, NULL, SI_ORDER_ANY); 170 MODULE_VERSION(enetc, 1); 171 172 IFLIB_PNP_INFO(pci, enetc, enetc_vendor_info_array); 173 174 MODULE_DEPEND(enetc, ether, 1, 1, 1); 175 MODULE_DEPEND(enetc, iflib, 1, 1, 1); 176 MODULE_DEPEND(enetc, miibus, 1, 1, 1); 177 178 static device_method_t enetc_iflib_methods[] = { 179 DEVMETHOD(ifdi_attach_pre, enetc_attach_pre), 180 DEVMETHOD(ifdi_attach_post, enetc_attach_post), 181 DEVMETHOD(ifdi_detach, enetc_detach), 182 183 DEVMETHOD(ifdi_init, enetc_init), 184 DEVMETHOD(ifdi_stop, enetc_stop), 185 186 DEVMETHOD(ifdi_tx_queues_alloc, enetc_tx_queues_alloc), 187 DEVMETHOD(ifdi_rx_queues_alloc, enetc_rx_queues_alloc), 188 DEVMETHOD(ifdi_queues_free, enetc_queues_free), 189 190 DEVMETHOD(ifdi_msix_intr_assign, enetc_msix_intr_assign), 191 DEVMETHOD(ifdi_tx_queue_intr_enable, enetc_tx_queue_intr_enable), 192 DEVMETHOD(ifdi_rx_queue_intr_enable, enetc_rx_queue_intr_enable), 193 DEVMETHOD(ifdi_intr_enable, enetc_intr_enable), 194 DEVMETHOD(ifdi_intr_disable, enetc_intr_disable), 195 196 DEVMETHOD(ifdi_vlan_register, enetc_vlan_register), 197 DEVMETHOD(ifdi_vlan_unregister, enetc_vlan_unregister), 198 199 DEVMETHOD(ifdi_get_counter, enetc_get_counter), 200 DEVMETHOD(ifdi_mtu_set, enetc_mtu_set), 201 DEVMETHOD(ifdi_multi_set, enetc_setup_multicast), 202 DEVMETHOD(ifdi_promisc_set, enetc_promisc_set), 203 DEVMETHOD(ifdi_timer, enetc_timer), 204 DEVMETHOD(ifdi_update_admin_status, enetc_update_admin_status), 205 206 DEVMETHOD(ifdi_needs_restart, enetc_if_needs_restart), 207 208 DEVMETHOD_END 209 }; 210 211 static driver_t enetc_iflib_driver = { 212 "enetc", enetc_iflib_methods, sizeof(struct enetc_softc) 213 }; 214 215 static struct if_txrx enetc_txrx = { 216 .ift_txd_encap = enetc_isc_txd_encap, 217 .ift_txd_flush = enetc_isc_txd_flush, 218 .ift_txd_credits_update = enetc_isc_txd_credits_update, 219 .ift_rxd_available = enetc_isc_rxd_available, 220 .ift_rxd_pkt_get = enetc_isc_rxd_pkt_get, 221 .ift_rxd_refill = enetc_isc_rxd_refill, 222 .ift_rxd_flush = enetc_isc_rxd_flush 223 }; 224 225 static struct if_shared_ctx enetc_sctx_init = { 226 .isc_magic = IFLIB_MAGIC, 227 228 .isc_q_align = ENETC_RING_ALIGN, 229 230 .isc_tx_maxsize = ENETC_MAX_FRAME_LEN, 231 .isc_tx_maxsegsize = PAGE_SIZE, 232 233 .isc_rx_maxsize = ENETC_MAX_FRAME_LEN, 234 .isc_rx_maxsegsize = ENETC_MAX_FRAME_LEN, 235 .isc_rx_nsegments = ENETC_MAX_SCATTER, 236 237 .isc_admin_intrcnt = 0, 238 239 .isc_nfl = 1, 240 .isc_nrxqs = 1, 241 .isc_ntxqs = 1, 242 243 .isc_vendor_info = enetc_vendor_info_array, 244 .isc_driver_version = enetc_driver_version, 245 .isc_driver = &enetc_iflib_driver, 246 247 .isc_flags = IFLIB_DRIVER_MEDIA | IFLIB_PRESERVE_TX_INDICES, 248 .isc_ntxd_min = {ENETC_MIN_DESC}, 249 .isc_ntxd_max = {ENETC_MAX_DESC}, 250 .isc_ntxd_default = {ENETC_DEFAULT_DESC}, 251 .isc_nrxd_min = {ENETC_MIN_DESC}, 252 .isc_nrxd_max = {ENETC_MAX_DESC}, 253 .isc_nrxd_default = {ENETC_DEFAULT_DESC} 254 }; 255 256 static void* 257 enetc_register(device_t dev) 258 { 259 260 if (!ofw_bus_status_okay(dev)) 261 return (NULL); 262 263 return (&enetc_sctx_init); 264 } 265 266 static void 267 enetc_max_nqueues(struct enetc_softc *sc, int *max_tx_nqueues, 268 int *max_rx_nqueues) 269 { 270 uint32_t val; 271 272 val = ENETC_PORT_RD4(sc, ENETC_PCAPR0); 273 *max_tx_nqueues = MIN(ENETC_PCAPR0_TXBDR(val), ENETC_MAX_QUEUES); 274 *max_rx_nqueues = MIN(ENETC_PCAPR0_RXBDR(val), ENETC_MAX_QUEUES); 275 } 276 277 static int 278 enetc_setup_fixed(struct enetc_softc *sc, phandle_t node) 279 { 280 ssize_t size; 281 int speed; 282 283 size = OF_getencprop(node, "speed", &speed, sizeof(speed)); 284 if (size <= 0) { 285 device_printf(sc->dev, 286 "Device has fixed-link node without link speed specified\n"); 287 return (ENXIO); 288 } 289 switch (speed) { 290 case 10: 291 speed = IFM_10_T; 292 break; 293 case 100: 294 speed = IFM_100_TX; 295 break; 296 case 1000: 297 speed = IFM_1000_T; 298 break; 299 case 2500: 300 speed = IFM_2500_T; 301 break; 302 default: 303 device_printf(sc->dev, "Unsupported link speed value of %d\n", 304 speed); 305 return (ENXIO); 306 } 307 speed |= IFM_ETHER; 308 309 if (OF_hasprop(node, "full-duplex")) 310 speed |= IFM_FDX; 311 else 312 speed |= IFM_HDX; 313 314 sc->fixed_link = true; 315 316 ifmedia_init(&sc->fixed_ifmedia, 0, enetc_fixed_media_change, 317 enetc_fixed_media_status); 318 ifmedia_add(&sc->fixed_ifmedia, speed, 0, NULL); 319 ifmedia_set(&sc->fixed_ifmedia, speed); 320 sc->shared->isc_media = &sc->fixed_ifmedia; 321 322 return (0); 323 } 324 325 static int 326 enetc_setup_phy(struct enetc_softc *sc) 327 { 328 phandle_t node, fixed_link, phy_handle; 329 struct mii_data *miid; 330 int phy_addr, error; 331 ssize_t size; 332 333 node = ofw_bus_get_node(sc->dev); 334 fixed_link = ofw_bus_find_child(node, "fixed-link"); 335 if (fixed_link != 0) 336 return (enetc_setup_fixed(sc, fixed_link)); 337 338 size = OF_getencprop(node, "phy-handle", &phy_handle, sizeof(phy_handle)); 339 if (size <= 0) { 340 device_printf(sc->dev, 341 "Failed to acquire PHY handle from FDT.\n"); 342 return (ENXIO); 343 } 344 phy_handle = OF_node_from_xref(phy_handle); 345 size = OF_getencprop(phy_handle, "reg", &phy_addr, sizeof(phy_addr)); 346 if (size <= 0) { 347 device_printf(sc->dev, "Failed to obtain PHY address\n"); 348 return (ENXIO); 349 } 350 error = mii_attach(sc->dev, &sc->miibus, iflib_get_ifp(sc->ctx), 351 enetc_media_change, enetc_media_status, 352 BMSR_DEFCAPMASK, phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 353 if (error != 0) { 354 device_printf(sc->dev, "mii_attach failed\n"); 355 return (error); 356 } 357 miid = device_get_softc(sc->miibus); 358 sc->shared->isc_media = &miid->mii_media; 359 360 return (0); 361 } 362 363 static int 364 enetc_attach_pre(if_ctx_t ctx) 365 { 366 if_softc_ctx_t scctx; 367 struct enetc_softc *sc; 368 int error, rid; 369 370 sc = iflib_get_softc(ctx); 371 scctx = iflib_get_softc_ctx(ctx); 372 sc->ctx = ctx; 373 sc->dev = iflib_get_dev(ctx); 374 sc->shared = scctx; 375 376 mtx_init(&sc->mii_lock, "enetc_mdio", NULL, MTX_DEF); 377 378 pci_save_state(sc->dev); 379 pcie_flr(sc->dev, 1000, false); 380 pci_restore_state(sc->dev); 381 382 rid = PCIR_BAR(ENETC_BAR_REGS); 383 sc->regs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 384 if (sc->regs == NULL) { 385 device_printf(sc->dev, 386 "Failed to allocate BAR %d\n", ENETC_BAR_REGS); 387 return (ENXIO); 388 } 389 390 error = iflib_dma_alloc_align(ctx, 391 ENETC_MIN_DESC * sizeof(struct enetc_cbd), 392 ENETC_RING_ALIGN, 393 &sc->ctrl_queue.dma, 394 0); 395 if (error != 0) { 396 device_printf(sc->dev, "Failed to allocate control ring\n"); 397 goto fail; 398 } 399 sc->ctrl_queue.ring = (struct enetc_cbd*)sc->ctrl_queue.dma.idi_vaddr; 400 401 scctx->isc_txrx = &enetc_txrx; 402 scctx->isc_tx_nsegments = ENETC_MAX_SCATTER; 403 enetc_max_nqueues(sc, &scctx->isc_nrxqsets_max, &scctx->isc_ntxqsets_max); 404 405 if (scctx->isc_ntxd[0] % ENETC_DESC_ALIGN != 0) { 406 device_printf(sc->dev, 407 "The number of TX descriptors has to be a multiple of %d\n", 408 ENETC_DESC_ALIGN); 409 error = EINVAL; 410 goto fail; 411 } 412 if (scctx->isc_nrxd[0] % ENETC_DESC_ALIGN != 0) { 413 device_printf(sc->dev, 414 "The number of RX descriptors has to be a multiple of %d\n", 415 ENETC_DESC_ALIGN); 416 error = EINVAL; 417 goto fail; 418 } 419 scctx->isc_txqsizes[0] = scctx->isc_ntxd[0] * sizeof(union enetc_tx_bd); 420 scctx->isc_rxqsizes[0] = scctx->isc_nrxd[0] * sizeof(union enetc_rx_bd); 421 scctx->isc_txd_size[0] = sizeof(union enetc_tx_bd); 422 scctx->isc_rxd_size[0] = sizeof(union enetc_rx_bd); 423 scctx->isc_tx_csum_flags = 0; 424 scctx->isc_capabilities = scctx->isc_capenable = ENETC_IFCAPS; 425 426 error = enetc_mtu_set(ctx, ETHERMTU); 427 if (error != 0) 428 goto fail; 429 430 scctx->isc_msix_bar = pci_msix_table_bar(sc->dev); 431 432 error = enetc_setup_phy(sc); 433 if (error != 0) 434 goto fail; 435 436 enetc_get_hwaddr(sc); 437 438 return (0); 439 fail: 440 enetc_detach(ctx); 441 return (error); 442 } 443 444 static int 445 enetc_attach_post(if_ctx_t ctx) 446 { 447 448 enetc_init_hw(iflib_get_softc(ctx)); 449 return (0); 450 } 451 452 static int 453 enetc_detach(if_ctx_t ctx) 454 { 455 struct enetc_softc *sc; 456 int error = 0, i; 457 458 sc = iflib_get_softc(ctx); 459 460 if (sc->rx_queues != NULL) { 461 for (i = 0; i < sc->rx_num_queues; i++) 462 iflib_irq_free(ctx, &sc->rx_queues[i].irq); 463 } 464 465 bus_generic_detach(sc->dev); 466 467 if (sc->regs != NULL) { 468 error = bus_release_resource(sc->dev, SYS_RES_MEMORY, 469 rman_get_rid(sc->regs), sc->regs); 470 sc->regs = NULL; 471 } 472 473 if (sc->ctrl_queue.dma.idi_size != 0) 474 iflib_dma_free(&sc->ctrl_queue.dma); 475 476 mtx_destroy(&sc->mii_lock); 477 478 return (error); 479 } 480 481 static int 482 enetc_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 483 int ntxqs, int ntxqsets) 484 { 485 struct enetc_softc *sc; 486 struct enetc_tx_queue *queue; 487 int i; 488 489 sc = iflib_get_softc(ctx); 490 491 MPASS(ntxqs == 1); 492 493 sc->tx_queues = mallocarray(sc->tx_num_queues, 494 sizeof(struct enetc_tx_queue), M_DEVBUF, M_NOWAIT | M_ZERO); 495 if (sc->tx_queues == NULL) { 496 device_printf(sc->dev, 497 "Failed to allocate memory for TX queues.\n"); 498 return (ENOMEM); 499 } 500 501 for (i = 0; i < sc->tx_num_queues; i++) { 502 queue = &sc->tx_queues[i]; 503 queue->sc = sc; 504 queue->ring = (union enetc_tx_bd*)(vaddrs[i]); 505 queue->ring_paddr = paddrs[i]; 506 queue->cidx = 0; 507 } 508 509 return (0); 510 } 511 512 static int 513 enetc_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 514 int nrxqs, int nrxqsets) 515 { 516 struct enetc_softc *sc; 517 struct enetc_rx_queue *queue; 518 int i; 519 520 sc = iflib_get_softc(ctx); 521 MPASS(nrxqs == 1); 522 523 sc->rx_queues = mallocarray(sc->rx_num_queues, 524 sizeof(struct enetc_rx_queue), M_DEVBUF, M_NOWAIT | M_ZERO); 525 if (sc->rx_queues == NULL) { 526 device_printf(sc->dev, 527 "Failed to allocate memory for RX queues.\n"); 528 return (ENOMEM); 529 } 530 531 for (i = 0; i < sc->rx_num_queues; i++) { 532 queue = &sc->rx_queues[i]; 533 queue->sc = sc; 534 queue->qid = i; 535 queue->ring = (union enetc_rx_bd*)(vaddrs[i]); 536 queue->ring_paddr = paddrs[i]; 537 } 538 539 return (0); 540 } 541 542 static void 543 enetc_queues_free(if_ctx_t ctx) 544 { 545 struct enetc_softc *sc; 546 547 sc = iflib_get_softc(ctx); 548 549 if (sc->tx_queues != NULL) { 550 free(sc->tx_queues, M_DEVBUF); 551 sc->tx_queues = NULL; 552 } 553 if (sc->rx_queues != NULL) { 554 free(sc->rx_queues, M_DEVBUF); 555 sc->rx_queues = NULL; 556 } 557 } 558 559 static void 560 enetc_get_hwaddr(struct enetc_softc *sc) 561 { 562 struct ether_addr hwaddr; 563 uint16_t high; 564 uint32_t low; 565 566 low = ENETC_PORT_RD4(sc, ENETC_PSIPMAR0(0)); 567 high = ENETC_PORT_RD2(sc, ENETC_PSIPMAR1(0)); 568 569 memcpy(&hwaddr.octet[0], &low, 4); 570 memcpy(&hwaddr.octet[4], &high, 2); 571 572 if (ETHER_IS_BROADCAST(hwaddr.octet) || 573 ETHER_IS_MULTICAST(hwaddr.octet) || 574 ETHER_IS_ZERO(hwaddr.octet)) { 575 ether_gen_addr(iflib_get_ifp(sc->ctx), &hwaddr); 576 device_printf(sc->dev, 577 "Failed to obtain MAC address, using a random one\n"); 578 memcpy(&low, &hwaddr.octet[0], 4); 579 memcpy(&high, &hwaddr.octet[4], 2); 580 } 581 582 iflib_set_mac(sc->ctx, hwaddr.octet); 583 } 584 585 static void 586 enetc_set_hwaddr(struct enetc_softc *sc) 587 { 588 if_t ifp; 589 uint16_t high; 590 uint32_t low; 591 uint8_t *hwaddr; 592 593 ifp = iflib_get_ifp(sc->ctx); 594 hwaddr = (uint8_t*)if_getlladdr(ifp); 595 low = *((uint32_t*)hwaddr); 596 high = *((uint16_t*)(hwaddr+4)); 597 598 ENETC_PORT_WR4(sc, ENETC_PSIPMAR0(0), low); 599 ENETC_PORT_WR2(sc, ENETC_PSIPMAR1(0), high); 600 } 601 602 static int 603 enetc_setup_rss(struct enetc_softc *sc) 604 { 605 struct iflib_dma_info dma; 606 int error, i, buckets_num = 0; 607 uint8_t rss_key[RSS_KEYSIZE]; 608 uint8_t *rss_table; 609 uint32_t reg; 610 611 reg = ENETC_RD4(sc, ENETC_SIPCAPR0); 612 if (reg & ENETC_SIPCAPR0_RSS) { 613 reg = ENETC_RD4(sc, ENETC_SIRSSCAPR); 614 buckets_num = ENETC_SIRSSCAPR_GET_NUM_RSS(reg); 615 } 616 if (buckets_num == 0) 617 return (ENOTSUP); 618 619 _Static_assert(ENETC_RSSHASH_KEY_SIZE == RSS_KEYSIZE, 620 "RSS key size mismatch"); 621 rss_getkey(rss_key); 622 for (i = 0; i < ENETC_RSSHASH_KEY_SIZE / sizeof(uint32_t); i++) { 623 reg = le32dec(rss_key + i * sizeof(reg)); 624 ENETC_PORT_WR4(sc, ENETC_PRSSK(i), reg); 625 } 626 627 ENETC_WR4(sc, ENETC_SIRBGCR, sc->rx_num_queues); 628 629 error = iflib_dma_alloc_align(sc->ctx, 630 buckets_num * sizeof(*rss_table), 631 ENETC_RING_ALIGN, 632 &dma, 633 0); 634 if (error != 0) { 635 device_printf(sc->dev, "Failed to allocate DMA buffer for RSS\n"); 636 return (error); 637 } 638 rss_table = (uint8_t *)dma.idi_vaddr; 639 640 for (i = 0; i < buckets_num; i++) 641 rss_table[i] = i % sc->rx_num_queues; 642 643 error = enetc_ctrl_send(sc, (BDCR_CMD_RSS << 8) | BDCR_CMD_RSS_WRITE, 644 buckets_num * sizeof(*rss_table), &dma); 645 if (error != 0) 646 device_printf(sc->dev, "Failed to setup RSS table\n"); 647 648 iflib_dma_free(&dma); 649 650 return (error); 651 } 652 653 static int 654 enetc_ctrl_send(struct enetc_softc *sc, uint16_t cmd, uint16_t size, 655 iflib_dma_info_t dma) 656 { 657 struct enetc_ctrl_queue *queue; 658 struct enetc_cbd *desc; 659 int timeout = 1000; 660 661 queue = &sc->ctrl_queue; 662 desc = &queue->ring[queue->pidx]; 663 664 if (++queue->pidx == ENETC_MIN_DESC) 665 queue->pidx = 0; 666 667 desc->addr[0] = (uint32_t)dma->idi_paddr; 668 desc->addr[1] = (uint32_t)(dma->idi_paddr >> 32); 669 desc->index = 0; 670 desc->length = (uint16_t)size; 671 desc->cmd = (uint8_t)cmd; 672 desc->cls = (uint8_t)(cmd >> 8); 673 desc->status_flags = 0; 674 675 /* Sync command packet, */ 676 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_PREWRITE); 677 /* and the control ring. */ 678 bus_dmamap_sync(queue->dma.idi_tag, queue->dma.idi_map, BUS_DMASYNC_PREWRITE); 679 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx); 680 681 while (--timeout != 0) { 682 DELAY(20); 683 if (ENETC_RD4(sc, ENETC_SICBDRCIR) == queue->pidx) 684 break; 685 } 686 687 if (timeout == 0) 688 return (ETIMEDOUT); 689 690 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_POSTREAD); 691 return (0); 692 } 693 694 static void 695 enetc_init_hw(struct enetc_softc *sc) 696 { 697 uint32_t val; 698 int error; 699 700 ENETC_PORT_WR4(sc, ENETC_PM0_CMD_CFG, 701 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC | 702 ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 703 ENETC_PORT_WR4(sc, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); 704 val = ENETC_PSICFGR0_SET_TXBDR(sc->tx_num_queues); 705 val |= ENETC_PSICFGR0_SET_RXBDR(sc->rx_num_queues); 706 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 707 ENETC_PORT_WR4(sc, ENETC_PSICFGR0(0), val); 708 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VUTA(1)); 709 ENETC_PORT_WR4(sc, ENETC_PVCLCTR, ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 710 ENETC_PORT_WR4(sc, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); 711 ENETC_PORT_WR4(sc, ENETC_PAR_PORT_CFG, ENETC_PAR_PORT_L4CD); 712 ENETC_PORT_WR4(sc, ENETC_PMR, ENETC_PMR_SI0EN | ENETC_PMR_PSPEED_1000M); 713 714 ENETC_WR4(sc, ENETC_SICAR0, 715 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 716 ENETC_WR4(sc, ENETC_SICAR1, ENETC_SICAR_MSI); 717 ENETC_WR4(sc, ENETC_SICAR2, 718 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 719 720 enetc_init_ctrl(sc); 721 error = enetc_setup_rss(sc); 722 if (error != 0) 723 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN); 724 else 725 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN | ENETC_SIMR_RSSE); 726 727 } 728 729 static void 730 enetc_init_ctrl(struct enetc_softc *sc) 731 { 732 struct enetc_ctrl_queue *queue = &sc->ctrl_queue; 733 734 ENETC_WR4(sc, ENETC_SICBDRBAR0, 735 (uint32_t)queue->dma.idi_paddr); 736 ENETC_WR4(sc, ENETC_SICBDRBAR1, 737 (uint32_t)(queue->dma.idi_paddr >> 32)); 738 ENETC_WR4(sc, ENETC_SICBDRLENR, 739 queue->dma.idi_size / sizeof(struct enetc_cbd)); 740 741 queue->pidx = 0; 742 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx); 743 ENETC_WR4(sc, ENETC_SICBDRCIR, queue->pidx); 744 ENETC_WR4(sc, ENETC_SICBDRMR, ENETC_SICBDRMR_EN); 745 } 746 747 static void 748 enetc_init_tx(struct enetc_softc *sc) 749 { 750 struct enetc_tx_queue *queue; 751 int i; 752 753 for (i = 0; i < sc->tx_num_queues; i++) { 754 queue = &sc->tx_queues[i]; 755 756 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR0, 757 (uint32_t)queue->ring_paddr); 758 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR1, 759 (uint32_t)(queue->ring_paddr >> 32)); 760 ENETC_TXQ_WR4(sc, i, ENETC_TBLENR, sc->tx_queue_size); 761 762 /* 763 * Even though it is undoccumented resetting the TX ring 764 * indices results in TX hang. 765 * Do the same as Linux and simply keep those unchanged 766 * for the drivers lifetime. 767 */ 768 #if 0 769 ENETC_TXQ_WR4(sc, i, ENETC_TBPIR, 0); 770 ENETC_TXQ_WR4(sc, i, ENETC_TBCIR, 0); 771 #endif 772 ENETC_TXQ_WR4(sc, i, ENETC_TBMR, ENETC_TBMR_EN); 773 } 774 775 } 776 777 static void 778 enetc_init_rx(struct enetc_softc *sc) 779 { 780 struct enetc_rx_queue *queue; 781 uint32_t rx_buf_size; 782 int i; 783 784 rx_buf_size = iflib_get_rx_mbuf_sz(sc->ctx); 785 786 for (i = 0; i < sc->rx_num_queues; i++) { 787 queue = &sc->rx_queues[i]; 788 789 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR0, 790 (uint32_t)queue->ring_paddr); 791 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR1, 792 (uint32_t)(queue->ring_paddr >> 32)); 793 ENETC_RXQ_WR4(sc, i, ENETC_RBLENR, sc->rx_queue_size); 794 ENETC_RXQ_WR4(sc, i, ENETC_RBBSR, rx_buf_size); 795 ENETC_RXQ_WR4(sc, i, ENETC_RBPIR, 0); 796 ENETC_RXQ_WR4(sc, i, ENETC_RBCIR, 0); 797 queue->enabled = false; 798 } 799 } 800 801 static u_int 802 enetc_hash_mac(void *arg, struct sockaddr_dl *sdl, u_int cnt) 803 { 804 uint64_t *bitmap = arg; 805 uint64_t address = 0; 806 uint8_t hash = 0; 807 bool bit; 808 int i, j; 809 810 bcopy(LLADDR(sdl), &address, ETHER_ADDR_LEN); 811 812 /* 813 * The six bit hash is calculated by xoring every 814 * 6th bit of the address. 815 * It is then used as an index in a bitmap that is 816 * written to the device. 817 */ 818 for (i = 0; i < 6; i++) { 819 bit = 0; 820 for (j = 0; j < 8; j++) 821 bit ^= !!(address & BIT(i + j*6)); 822 823 hash |= bit << i; 824 } 825 826 *bitmap |= (1 << hash); 827 return (1); 828 } 829 830 static void 831 enetc_setup_multicast(if_ctx_t ctx) 832 { 833 struct enetc_softc *sc; 834 if_t ifp; 835 uint64_t bitmap = 0; 836 uint8_t revid; 837 838 sc = iflib_get_softc(ctx); 839 ifp = iflib_get_ifp(ctx); 840 revid = pci_get_revid(sc->dev); 841 842 if_foreach_llmaddr(ifp, enetc_hash_mac, &bitmap); 843 844 /* 845 * In revid 1 of this chip the positions multicast and unicast 846 * hash filter registers are flipped. 847 */ 848 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR0(0, revid == 1), bitmap & UINT32_MAX); 849 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR1(0), bitmap >> 32); 850 851 } 852 853 static uint8_t 854 enetc_hash_vid(uint16_t vid) 855 { 856 uint8_t hash = 0; 857 bool bit; 858 int i; 859 860 for (i = 0; i < 6; i++) { 861 bit = vid & BIT(i); 862 bit ^= !!(vid & BIT(i + 6)); 863 hash |= bit << i; 864 } 865 866 return (hash); 867 } 868 869 static void 870 enetc_vlan_register(if_ctx_t ctx, uint16_t vid) 871 { 872 struct enetc_softc *sc; 873 uint8_t hash; 874 uint64_t bitmap; 875 876 sc = iflib_get_softc(ctx); 877 hash = enetc_hash_vid(vid); 878 879 /* Check if hash is already present in the bitmap. */ 880 if (++sc->vlan_bitmap[hash] != 1) 881 return; 882 883 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0)); 884 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32; 885 bitmap |= BIT(hash); 886 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX); 887 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32); 888 } 889 890 static void 891 enetc_vlan_unregister(if_ctx_t ctx, uint16_t vid) 892 { 893 struct enetc_softc *sc; 894 uint8_t hash; 895 uint64_t bitmap; 896 897 sc = iflib_get_softc(ctx); 898 hash = enetc_hash_vid(vid); 899 900 MPASS(sc->vlan_bitmap[hash] > 0); 901 if (--sc->vlan_bitmap[hash] != 0) 902 return; 903 904 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0)); 905 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32; 906 bitmap &= ~BIT(hash); 907 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX); 908 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32); 909 } 910 911 static void 912 enetc_init(if_ctx_t ctx) 913 { 914 struct enetc_softc *sc; 915 struct mii_data *miid; 916 if_t ifp; 917 uint16_t max_frame_length; 918 int baudrate; 919 920 sc = iflib_get_softc(ctx); 921 ifp = iflib_get_ifp(ctx); 922 923 max_frame_length = sc->shared->isc_max_frame_size; 924 MPASS(max_frame_length < ENETC_MAX_FRAME_LEN); 925 926 /* Set max RX and TX frame lengths. */ 927 ENETC_PORT_WR4(sc, ENETC_PM0_MAXFRM, max_frame_length); 928 ENETC_PORT_WR4(sc, ENETC_PTCMSDUR(0), max_frame_length); 929 ENETC_PORT_WR4(sc, ENETC_PTXMBAR, 2 * max_frame_length); 930 931 /* Set "VLAN promiscious" mode if filtering is disabled. */ 932 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) 933 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, 934 ENETC_PSIPVMR_SET_VUTA(1) | ENETC_PSIPVMR_SET_VP(1)); 935 else 936 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, 937 ENETC_PSIPVMR_SET_VUTA(1)); 938 939 sc->rbmr = ENETC_RBMR_EN; 940 941 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 942 sc->rbmr |= ENETC_RBMR_VTE; 943 944 /* Write MAC address to hardware. */ 945 enetc_set_hwaddr(sc); 946 947 enetc_init_tx(sc); 948 enetc_init_rx(sc); 949 950 if (sc->fixed_link) { 951 baudrate = ifmedia_baudrate(sc->fixed_ifmedia.ifm_cur->ifm_media); 952 iflib_link_state_change(sc->ctx, LINK_STATE_UP, baudrate); 953 } else { 954 /* 955 * Can't return an error from this function, there is not much 956 * we can do if this fails. 957 */ 958 miid = device_get_softc(sc->miibus); 959 (void)mii_mediachg(miid); 960 } 961 962 enetc_promisc_set(ctx, if_getflags(ifp)); 963 } 964 965 static void 966 enetc_disable_txq(struct enetc_softc *sc, int qid) 967 { 968 qidx_t cidx, pidx; 969 int timeout = 10000; /* this * DELAY(100) = 1s */ 970 971 /* At this point iflib shouldn't be enquing any more frames. */ 972 pidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBPIR); 973 cidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR); 974 975 while (pidx != cidx && timeout--) { 976 DELAY(100); 977 cidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR); 978 } 979 980 if (pidx != cidx) 981 device_printf(sc->dev, 982 "Timeout while waiting for txq%d to stop transmitting packets\n", 983 qid); 984 985 ENETC_TXQ_WR4(sc, qid, ENETC_TBMR, 0); 986 } 987 988 static void 989 enetc_stop(if_ctx_t ctx) 990 { 991 struct enetc_softc *sc; 992 int i; 993 994 sc = iflib_get_softc(ctx); 995 996 for (i = 0; i < sc->rx_num_queues; i++) 997 ENETC_RXQ_WR4(sc, i, ENETC_RBMR, 0); 998 999 for (i = 0; i < sc->tx_num_queues; i++) 1000 enetc_disable_txq(sc, i); 1001 } 1002 1003 static int 1004 enetc_msix_intr_assign(if_ctx_t ctx, int msix) 1005 { 1006 struct enetc_softc *sc; 1007 struct enetc_rx_queue *rx_queue; 1008 struct enetc_tx_queue *tx_queue; 1009 int vector = 0, i, error; 1010 char irq_name[16]; 1011 1012 sc = iflib_get_softc(ctx); 1013 1014 MPASS(sc->rx_num_queues + 1 <= ENETC_MSIX_COUNT); 1015 MPASS(sc->rx_num_queues == sc->tx_num_queues); 1016 1017 for (i = 0; i < sc->rx_num_queues; i++, vector++) { 1018 rx_queue = &sc->rx_queues[i]; 1019 snprintf(irq_name, sizeof(irq_name), "rxtxq%d", i); 1020 error = iflib_irq_alloc_generic(ctx, 1021 &rx_queue->irq, vector + 1, IFLIB_INTR_RXTX, 1022 NULL, rx_queue, i, irq_name); 1023 if (error != 0) 1024 goto fail; 1025 1026 ENETC_WR4(sc, ENETC_SIMSIRRV(i), vector); 1027 ENETC_RXQ_WR4(sc, i, ENETC_RBICR1, ENETC_RX_INTR_TIME_THR); 1028 ENETC_RXQ_WR4(sc, i, ENETC_RBICR0, 1029 ENETC_RBICR0_ICEN | ENETC_RBICR0_SET_ICPT(ENETC_RX_INTR_PKT_THR)); 1030 } 1031 vector = 0; 1032 for (i = 0; i < sc->tx_num_queues; i++, vector++) { 1033 tx_queue = &sc->tx_queues[i]; 1034 snprintf(irq_name, sizeof(irq_name), "txq%d", i); 1035 iflib_softirq_alloc_generic(ctx, &tx_queue->irq, 1036 IFLIB_INTR_TX, tx_queue, i, irq_name); 1037 1038 ENETC_WR4(sc, ENETC_SIMSITRV(i), vector); 1039 } 1040 1041 return (0); 1042 fail: 1043 for (i = 0; i < sc->rx_num_queues; i++) { 1044 rx_queue = &sc->rx_queues[i]; 1045 iflib_irq_free(ctx, &rx_queue->irq); 1046 } 1047 return (error); 1048 } 1049 1050 static int 1051 enetc_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 1052 { 1053 struct enetc_softc *sc; 1054 1055 sc = iflib_get_softc(ctx); 1056 ENETC_TXQ_RD4(sc, qid, ENETC_TBIDR); 1057 return (0); 1058 } 1059 1060 static int 1061 enetc_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 1062 { 1063 struct enetc_softc *sc; 1064 1065 sc = iflib_get_softc(ctx); 1066 ENETC_RXQ_RD4(sc, qid, ENETC_RBIDR); 1067 return (0); 1068 } 1069 static void 1070 enetc_intr_enable(if_ctx_t ctx) 1071 { 1072 struct enetc_softc *sc; 1073 int i; 1074 1075 sc = iflib_get_softc(ctx); 1076 1077 for (i = 0; i < sc->rx_num_queues; i++) 1078 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, ENETC_RBIER_RXTIE); 1079 1080 for (i = 0; i < sc->tx_num_queues; i++) 1081 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, ENETC_TBIER_TXF); 1082 } 1083 1084 static void 1085 enetc_intr_disable(if_ctx_t ctx) 1086 { 1087 struct enetc_softc *sc; 1088 int i; 1089 1090 sc = iflib_get_softc(ctx); 1091 1092 for (i = 0; i < sc->rx_num_queues; i++) 1093 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, 0); 1094 1095 for (i = 0; i < sc->tx_num_queues; i++) 1096 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, 0); 1097 } 1098 1099 static int 1100 enetc_isc_txd_encap(void *data, if_pkt_info_t ipi) 1101 { 1102 struct enetc_softc *sc = data; 1103 struct enetc_tx_queue *queue; 1104 union enetc_tx_bd *desc; 1105 bus_dma_segment_t *segs; 1106 qidx_t pidx, queue_len; 1107 qidx_t i = 0; 1108 1109 queue = &sc->tx_queues[ipi->ipi_qsidx]; 1110 segs = ipi->ipi_segs; 1111 pidx = ipi->ipi_pidx; 1112 queue_len = sc->tx_queue_size; 1113 1114 /* 1115 * First descriptor is special. We use it to set frame 1116 * related information and offloads, e.g. VLAN tag. 1117 */ 1118 desc = &queue->ring[pidx]; 1119 bzero(desc, sizeof(*desc)); 1120 desc->frm_len = ipi->ipi_len; 1121 desc->addr = segs[i].ds_addr; 1122 desc->buf_len = segs[i].ds_len; 1123 if (ipi->ipi_flags & IPI_TX_INTR) 1124 desc->flags = ENETC_TXBD_FLAGS_FI; 1125 1126 i++; 1127 if (++pidx == queue_len) 1128 pidx = 0; 1129 1130 if (ipi->ipi_mflags & M_VLANTAG) { 1131 /* VLAN tag is inserted in a separate descriptor. */ 1132 desc->flags |= ENETC_TXBD_FLAGS_EX; 1133 desc = &queue->ring[pidx]; 1134 bzero(desc, sizeof(*desc)); 1135 desc->ext.vid = ipi->ipi_vtag; 1136 desc->ext.e_flags = ENETC_TXBD_E_FLAGS_VLAN_INS; 1137 if (++pidx == queue_len) 1138 pidx = 0; 1139 } 1140 1141 /* Now add remaining descriptors. */ 1142 for (; i < ipi->ipi_nsegs; i++) { 1143 desc = &queue->ring[pidx]; 1144 bzero(desc, sizeof(*desc)); 1145 desc->addr = segs[i].ds_addr; 1146 desc->buf_len = segs[i].ds_len; 1147 1148 if (++pidx == queue_len) 1149 pidx = 0; 1150 } 1151 1152 desc->flags |= ENETC_TXBD_FLAGS_F; 1153 ipi->ipi_new_pidx = pidx; 1154 1155 return (0); 1156 } 1157 1158 static void 1159 enetc_isc_txd_flush(void *data, uint16_t qid, qidx_t pidx) 1160 { 1161 struct enetc_softc *sc = data; 1162 1163 ENETC_TXQ_WR4(sc, qid, ENETC_TBPIR, pidx); 1164 } 1165 1166 static int 1167 enetc_isc_txd_credits_update(void *data, uint16_t qid, bool clear) 1168 { 1169 struct enetc_softc *sc = data; 1170 struct enetc_tx_queue *queue; 1171 int cidx, hw_cidx, count; 1172 1173 queue = &sc->tx_queues[qid]; 1174 hw_cidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR) & ENETC_TBCIR_IDX_MASK; 1175 cidx = queue->cidx; 1176 1177 /* 1178 * RM states that the ring can hold at most ring_size - 1 descriptors. 1179 * Thanks to that we can assume that the ring is empty if cidx == pidx. 1180 * This requirement is guaranteed implicitly by iflib as it will only 1181 * encap a new frame if we have at least nfrags + 2 descriptors available 1182 * on the ring. This driver uses at most one additional descriptor for 1183 * VLAN tag insertion. 1184 * Also RM states that the TBCIR register is only updated once all 1185 * descriptors in the chain have been processed. 1186 */ 1187 if (cidx == hw_cidx) 1188 return (0); 1189 1190 if (!clear) 1191 return (1); 1192 1193 count = hw_cidx - cidx; 1194 if (count < 0) 1195 count += sc->tx_queue_size; 1196 1197 queue->cidx = hw_cidx; 1198 1199 return (count); 1200 } 1201 1202 static int 1203 enetc_isc_rxd_available(void *data, uint16_t qid, qidx_t pidx, qidx_t budget) 1204 { 1205 struct enetc_softc *sc = data; 1206 struct enetc_rx_queue *queue; 1207 qidx_t hw_pidx, queue_len; 1208 union enetc_rx_bd *desc; 1209 int count = 0; 1210 1211 queue = &sc->rx_queues[qid]; 1212 desc = &queue->ring[pidx]; 1213 queue_len = sc->rx_queue_size; 1214 1215 if (desc->r.lstatus == 0) 1216 return (0); 1217 1218 if (budget == 1) 1219 return (1); 1220 1221 hw_pidx = ENETC_RXQ_RD4(sc, qid, ENETC_RBPIR); 1222 while (pidx != hw_pidx && count < budget) { 1223 desc = &queue->ring[pidx]; 1224 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F) 1225 count++; 1226 1227 if (++pidx == queue_len) 1228 pidx = 0; 1229 } 1230 1231 return (count); 1232 } 1233 1234 static int 1235 enetc_isc_rxd_pkt_get(void *data, if_rxd_info_t ri) 1236 { 1237 struct enetc_softc *sc = data; 1238 struct enetc_rx_queue *queue; 1239 union enetc_rx_bd *desc; 1240 uint16_t buf_len, pkt_size = 0; 1241 qidx_t cidx, queue_len; 1242 uint32_t status; 1243 int i; 1244 1245 cidx = ri->iri_cidx; 1246 queue = &sc->rx_queues[ri->iri_qsidx]; 1247 desc = &queue->ring[cidx]; 1248 status = desc->r.lstatus; 1249 queue_len = sc->rx_queue_size; 1250 1251 /* 1252 * Ready bit will be set only when all descriptors 1253 * in the chain have been processed. 1254 */ 1255 if ((status & ENETC_RXBD_LSTATUS_R) == 0) 1256 return (EAGAIN); 1257 1258 /* Pass RSS hash. */ 1259 if (status & ENETC_RXBD_FLAG_RSSV) { 1260 ri->iri_flowid = desc->r.rss_hash; 1261 ri->iri_rsstype = M_HASHTYPE_OPAQUE_HASH; 1262 } 1263 1264 /* Pass IP checksum status. */ 1265 ri->iri_csum_flags = CSUM_IP_CHECKED; 1266 if ((desc->r.parse_summary & ENETC_RXBD_PARSER_ERROR) == 0) 1267 ri->iri_csum_flags |= CSUM_IP_VALID; 1268 1269 /* Pass extracted VLAN tag. */ 1270 if (status & ENETC_RXBD_FLAG_VLAN) { 1271 ri->iri_vtag = desc->r.vlan_opt; 1272 ri->iri_flags = M_VLANTAG; 1273 } 1274 1275 for (i = 0; i < ENETC_MAX_SCATTER; i++) { 1276 buf_len = desc->r.buf_len; 1277 ri->iri_frags[i].irf_idx = cidx; 1278 ri->iri_frags[i].irf_len = buf_len; 1279 pkt_size += buf_len; 1280 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F) 1281 break; 1282 1283 if (++cidx == queue_len) 1284 cidx = 0; 1285 1286 desc = &queue->ring[cidx]; 1287 } 1288 ri->iri_nfrags = i + 1; 1289 ri->iri_len = pkt_size; 1290 1291 MPASS(desc->r.lstatus & ENETC_RXBD_LSTATUS_F); 1292 if (status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK)) 1293 return (EBADMSG); 1294 1295 return (0); 1296 } 1297 1298 static void 1299 enetc_isc_rxd_refill(void *data, if_rxd_update_t iru) 1300 { 1301 struct enetc_softc *sc = data; 1302 struct enetc_rx_queue *queue; 1303 union enetc_rx_bd *desc; 1304 qidx_t pidx, queue_len; 1305 uint64_t *paddrs; 1306 int i, count; 1307 1308 queue = &sc->rx_queues[iru->iru_qsidx]; 1309 paddrs = iru->iru_paddrs; 1310 pidx = iru->iru_pidx; 1311 count = iru->iru_count; 1312 queue_len = sc->rx_queue_size; 1313 1314 for (i = 0; i < count; i++) { 1315 desc = &queue->ring[pidx]; 1316 bzero(desc, sizeof(*desc)); 1317 1318 desc->w.addr = paddrs[i]; 1319 if (++pidx == queue_len) 1320 pidx = 0; 1321 } 1322 /* 1323 * After enabling the queue NIC will prefetch the first 1324 * 8 descriptors. It probably assumes that the RX is fully 1325 * refilled when cidx == pidx. 1326 * Enable it only if we have enough descriptors ready on the ring. 1327 */ 1328 if (!queue->enabled && pidx >= 8) { 1329 ENETC_RXQ_WR4(sc, iru->iru_qsidx, ENETC_RBMR, sc->rbmr); 1330 queue->enabled = true; 1331 } 1332 } 1333 1334 static void 1335 enetc_isc_rxd_flush(void *data, uint16_t qid, uint8_t flid, qidx_t pidx) 1336 { 1337 struct enetc_softc *sc = data; 1338 1339 ENETC_RXQ_WR4(sc, qid, ENETC_RBCIR, pidx); 1340 } 1341 1342 static uint64_t 1343 enetc_get_counter(if_ctx_t ctx, ift_counter cnt) 1344 { 1345 struct enetc_softc *sc; 1346 if_t ifp; 1347 1348 sc = iflib_get_softc(ctx); 1349 ifp = iflib_get_ifp(ctx); 1350 1351 switch (cnt) { 1352 case IFCOUNTER_IERRORS: 1353 return (ENETC_PORT_RD8(sc, ENETC_PM0_RERR)); 1354 case IFCOUNTER_OERRORS: 1355 return (if_get_counter_default(ifp, cnt) + 1356 ENETC_PORT_RD8(sc, ENETC_PM0_TERR)); 1357 default: 1358 return (if_get_counter_default(ifp, cnt)); 1359 } 1360 } 1361 1362 static int 1363 enetc_mtu_set(if_ctx_t ctx, uint32_t mtu) 1364 { 1365 struct enetc_softc *sc = iflib_get_softc(ctx); 1366 uint32_t max_frame_size; 1367 1368 max_frame_size = mtu + 1369 ETHER_HDR_LEN + 1370 ETHER_CRC_LEN + 1371 sizeof(struct ether_vlan_header); 1372 1373 if (max_frame_size > ENETC_MAX_FRAME_LEN) 1374 return (EINVAL); 1375 1376 sc->shared->isc_max_frame_size = max_frame_size; 1377 1378 return (0); 1379 } 1380 1381 static int 1382 enetc_promisc_set(if_ctx_t ctx, int flags) 1383 { 1384 struct enetc_softc *sc; 1385 uint32_t reg = 0; 1386 1387 sc = iflib_get_softc(ctx); 1388 1389 if (flags & IFF_PROMISC) 1390 reg = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); 1391 else if (flags & IFF_ALLMULTI) 1392 reg = ENETC_PSIPMR_SET_MP(0); 1393 1394 ENETC_PORT_WR4(sc, ENETC_PSIPMR, reg); 1395 1396 return (0); 1397 } 1398 1399 static void 1400 enetc_timer(if_ctx_t ctx, uint16_t qid) 1401 { 1402 /* 1403 * Poll PHY status. Do this only for qid 0 to save 1404 * some cycles. 1405 */ 1406 if (qid == 0) 1407 iflib_admin_intr_deferred(ctx); 1408 } 1409 1410 static void 1411 enetc_update_admin_status(if_ctx_t ctx) 1412 { 1413 struct enetc_softc *sc; 1414 struct mii_data *miid; 1415 1416 sc = iflib_get_softc(ctx); 1417 1418 if (!sc->fixed_link) { 1419 miid = device_get_softc(sc->miibus); 1420 mii_tick(miid); 1421 } 1422 } 1423 1424 static bool 1425 enetc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 1426 { 1427 switch (event) { 1428 case IFLIB_RESTART_VLAN_CONFIG: 1429 default: 1430 return (false); 1431 } 1432 } 1433 1434 static int 1435 enetc_miibus_readreg(device_t dev, int phy, int reg) 1436 { 1437 struct enetc_softc *sc; 1438 int val; 1439 1440 sc = iflib_get_softc(device_get_softc(dev)); 1441 1442 mtx_lock(&sc->mii_lock); 1443 val = enetc_mdio_read(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE, 1444 phy, reg); 1445 mtx_unlock(&sc->mii_lock); 1446 1447 return (val); 1448 } 1449 1450 static int 1451 enetc_miibus_writereg(device_t dev, int phy, int reg, int data) 1452 { 1453 struct enetc_softc *sc; 1454 int ret; 1455 1456 sc = iflib_get_softc(device_get_softc(dev)); 1457 1458 mtx_lock(&sc->mii_lock); 1459 ret = enetc_mdio_write(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE, 1460 phy, reg, data); 1461 mtx_unlock(&sc->mii_lock); 1462 1463 return (ret); 1464 } 1465 1466 static void 1467 enetc_miibus_linkchg(device_t dev) 1468 { 1469 1470 enetc_miibus_statchg(dev); 1471 } 1472 1473 static void 1474 enetc_miibus_statchg(device_t dev) 1475 { 1476 struct enetc_softc *sc; 1477 struct mii_data *miid; 1478 int link_state, baudrate; 1479 1480 sc = iflib_get_softc(device_get_softc(dev)); 1481 miid = device_get_softc(sc->miibus); 1482 1483 baudrate = ifmedia_baudrate(miid->mii_media_active); 1484 if (miid->mii_media_status & IFM_AVALID) { 1485 if (miid->mii_media_status & IFM_ACTIVE) 1486 link_state = LINK_STATE_UP; 1487 else 1488 link_state = LINK_STATE_DOWN; 1489 } else { 1490 link_state = LINK_STATE_UNKNOWN; 1491 } 1492 1493 iflib_link_state_change(sc->ctx, link_state, baudrate); 1494 1495 } 1496 1497 static int 1498 enetc_media_change(if_t ifp) 1499 { 1500 struct enetc_softc *sc; 1501 struct mii_data *miid; 1502 1503 sc = iflib_get_softc(if_getsoftc(ifp)); 1504 miid = device_get_softc(sc->miibus); 1505 1506 mii_mediachg(miid); 1507 return (0); 1508 } 1509 1510 static void 1511 enetc_media_status(if_t ifp, struct ifmediareq* ifmr) 1512 { 1513 struct enetc_softc *sc; 1514 struct mii_data *miid; 1515 1516 sc = iflib_get_softc(if_getsoftc(ifp)); 1517 miid = device_get_softc(sc->miibus); 1518 1519 mii_pollstat(miid); 1520 1521 ifmr->ifm_active = miid->mii_media_active; 1522 ifmr->ifm_status = miid->mii_media_status; 1523 } 1524 1525 static int 1526 enetc_fixed_media_change(if_t ifp) 1527 { 1528 1529 if_printf(ifp, "Can't change media in fixed-link mode.\n"); 1530 return (0); 1531 } 1532 static void 1533 enetc_fixed_media_status(if_t ifp, struct ifmediareq* ifmr) 1534 { 1535 struct enetc_softc *sc; 1536 1537 sc = iflib_get_softc(if_getsoftc(ifp)); 1538 1539 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1540 ifmr->ifm_active = sc->fixed_ifmedia.ifm_cur->ifm_media; 1541 return; 1542 } 1543