1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2021 Alstom Group. 5 * Copyright (c) 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/rman.h> 37 #include <sys/socket.h> 38 #include <sys/sockio.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 43 #include <net/ethernet.h> 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_var.h> 47 #include <net/if_types.h> 48 #include <net/if_media.h> 49 #include <net/iflib.h> 50 51 #include <dev/enetc/enetc_hw.h> 52 #include <dev/enetc/enetc.h> 53 #include <dev/enetc/enetc_mdio.h> 54 #include <dev/mii/mii.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 62 #include "ifdi_if.h" 63 #include "miibus_if.h" 64 65 static device_register_t enetc_register; 66 67 static ifdi_attach_pre_t enetc_attach_pre; 68 static ifdi_attach_post_t enetc_attach_post; 69 static ifdi_detach_t enetc_detach; 70 71 static ifdi_tx_queues_alloc_t enetc_tx_queues_alloc; 72 static ifdi_rx_queues_alloc_t enetc_rx_queues_alloc; 73 static ifdi_queues_free_t enetc_queues_free; 74 75 static ifdi_init_t enetc_init; 76 static ifdi_stop_t enetc_stop; 77 78 static ifdi_msix_intr_assign_t enetc_msix_intr_assign; 79 static ifdi_tx_queue_intr_enable_t enetc_tx_queue_intr_enable; 80 static ifdi_rx_queue_intr_enable_t enetc_rx_queue_intr_enable; 81 static ifdi_intr_enable_t enetc_intr_enable; 82 static ifdi_intr_disable_t enetc_intr_disable; 83 84 static int enetc_isc_txd_encap(void*, if_pkt_info_t); 85 static void enetc_isc_txd_flush(void*, uint16_t, qidx_t); 86 static int enetc_isc_txd_credits_update(void*, uint16_t, bool); 87 static int enetc_isc_rxd_available(void*, uint16_t, qidx_t, qidx_t); 88 static int enetc_isc_rxd_pkt_get(void*, if_rxd_info_t); 89 static void enetc_isc_rxd_refill(void*, if_rxd_update_t); 90 static void enetc_isc_rxd_flush(void*, uint16_t, uint8_t, qidx_t); 91 92 static void enetc_vlan_register(if_ctx_t, uint16_t); 93 static void enetc_vlan_unregister(if_ctx_t, uint16_t); 94 95 static uint64_t enetc_get_counter(if_ctx_t, ift_counter); 96 static int enetc_promisc_set(if_ctx_t, int); 97 static int enetc_mtu_set(if_ctx_t, uint32_t); 98 static void enetc_setup_multicast(if_ctx_t); 99 static void enetc_timer(if_ctx_t, uint16_t); 100 static void enetc_update_admin_status(if_ctx_t); 101 102 static miibus_readreg_t enetc_miibus_readreg; 103 static miibus_writereg_t enetc_miibus_writereg; 104 static miibus_linkchg_t enetc_miibus_linkchg; 105 static miibus_statchg_t enetc_miibus_statchg; 106 107 static int enetc_media_change(if_t); 108 static void enetc_media_status(if_t, struct ifmediareq*); 109 110 static int enetc_fixed_media_change(if_t); 111 static void enetc_fixed_media_status(if_t, struct ifmediareq*); 112 113 static void enetc_max_nqueues(struct enetc_softc*, int*, int*); 114 static int enetc_setup_phy(struct enetc_softc*); 115 116 static void enetc_get_hwaddr(struct enetc_softc*); 117 static void enetc_set_hwaddr(struct enetc_softc*); 118 static int enetc_setup_rss(struct enetc_softc*); 119 120 static void enetc_init_hw(struct enetc_softc*); 121 static void enetc_init_ctrl(struct enetc_softc*); 122 static void enetc_init_tx(struct enetc_softc*); 123 static void enetc_init_rx(struct enetc_softc*); 124 125 static int enetc_ctrl_send(struct enetc_softc*, 126 uint16_t, uint16_t, iflib_dma_info_t); 127 128 static const char enetc_driver_version[] = "1.0.0"; 129 130 static pci_vendor_info_t enetc_vendor_info_array[] = { 131 PVID(PCI_VENDOR_FREESCALE, ENETC_DEV_ID_PF, 132 "Freescale ENETC PCIe Gigabit Ethernet Controller"), 133 PVID_END 134 }; 135 136 #define ENETC_IFCAPS (IFCAP_VLAN_MTU | IFCAP_RXCSUM | IFCAP_JUMBO_MTU | \ 137 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER) 138 139 static device_method_t enetc_methods[] = { 140 DEVMETHOD(device_register, enetc_register), 141 DEVMETHOD(device_probe, iflib_device_probe), 142 DEVMETHOD(device_attach, iflib_device_attach), 143 DEVMETHOD(device_detach, iflib_device_detach), 144 DEVMETHOD(device_shutdown, iflib_device_shutdown), 145 DEVMETHOD(device_suspend, iflib_device_suspend), 146 DEVMETHOD(device_resume, iflib_device_resume), 147 148 DEVMETHOD(miibus_readreg, enetc_miibus_readreg), 149 DEVMETHOD(miibus_writereg, enetc_miibus_writereg), 150 DEVMETHOD(miibus_linkchg, enetc_miibus_linkchg), 151 DEVMETHOD(miibus_statchg, enetc_miibus_statchg), 152 153 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 154 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 155 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 156 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 157 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 158 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 159 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 160 161 DEVMETHOD_END 162 }; 163 164 static driver_t enetc_driver = { 165 "enetc", enetc_methods, sizeof(struct enetc_softc) 166 }; 167 168 static devclass_t enetc_devclass; 169 DRIVER_MODULE(miibus, enetc, miibus_fdt_driver, miibus_fdt_devclass, NULL, NULL); 170 /* Make sure miibus gets procesed first. */ 171 DRIVER_MODULE_ORDERED(enetc, pci, enetc_driver, enetc_devclass, NULL, NULL, 172 SI_ORDER_ANY); 173 MODULE_VERSION(enetc, 1); 174 175 IFLIB_PNP_INFO(pci, enetc, enetc_vendor_info_array); 176 177 MODULE_DEPEND(enetc, ether, 1, 1, 1); 178 MODULE_DEPEND(enetc, iflib, 1, 1, 1); 179 MODULE_DEPEND(enetc, miibus, 1, 1, 1); 180 181 static device_method_t enetc_iflib_methods[] = { 182 DEVMETHOD(ifdi_attach_pre, enetc_attach_pre), 183 DEVMETHOD(ifdi_attach_post, enetc_attach_post), 184 DEVMETHOD(ifdi_detach, enetc_detach), 185 186 DEVMETHOD(ifdi_init, enetc_init), 187 DEVMETHOD(ifdi_stop, enetc_stop), 188 189 DEVMETHOD(ifdi_tx_queues_alloc, enetc_tx_queues_alloc), 190 DEVMETHOD(ifdi_rx_queues_alloc, enetc_rx_queues_alloc), 191 DEVMETHOD(ifdi_queues_free, enetc_queues_free), 192 193 DEVMETHOD(ifdi_msix_intr_assign, enetc_msix_intr_assign), 194 DEVMETHOD(ifdi_tx_queue_intr_enable, enetc_tx_queue_intr_enable), 195 DEVMETHOD(ifdi_rx_queue_intr_enable, enetc_rx_queue_intr_enable), 196 DEVMETHOD(ifdi_intr_enable, enetc_intr_enable), 197 DEVMETHOD(ifdi_intr_disable, enetc_intr_disable), 198 199 DEVMETHOD(ifdi_vlan_register, enetc_vlan_register), 200 DEVMETHOD(ifdi_vlan_unregister, enetc_vlan_unregister), 201 202 DEVMETHOD(ifdi_get_counter, enetc_get_counter), 203 DEVMETHOD(ifdi_mtu_set, enetc_mtu_set), 204 DEVMETHOD(ifdi_multi_set, enetc_setup_multicast), 205 DEVMETHOD(ifdi_promisc_set, enetc_promisc_set), 206 DEVMETHOD(ifdi_timer, enetc_timer), 207 DEVMETHOD(ifdi_update_admin_status, enetc_update_admin_status), 208 209 DEVMETHOD_END 210 }; 211 212 static driver_t enetc_iflib_driver = { 213 "enetc", enetc_iflib_methods, sizeof(struct enetc_softc) 214 }; 215 216 static struct if_txrx enetc_txrx = { 217 .ift_txd_encap = enetc_isc_txd_encap, 218 .ift_txd_flush = enetc_isc_txd_flush, 219 .ift_txd_credits_update = enetc_isc_txd_credits_update, 220 .ift_rxd_available = enetc_isc_rxd_available, 221 .ift_rxd_pkt_get = enetc_isc_rxd_pkt_get, 222 .ift_rxd_refill = enetc_isc_rxd_refill, 223 .ift_rxd_flush = enetc_isc_rxd_flush 224 }; 225 226 static struct if_shared_ctx enetc_sctx_init = { 227 .isc_magic = IFLIB_MAGIC, 228 229 .isc_q_align = ENETC_RING_ALIGN, 230 231 .isc_tx_maxsize = ENETC_MAX_FRAME_LEN, 232 .isc_tx_maxsegsize = PAGE_SIZE, 233 234 .isc_rx_maxsize = ENETC_MAX_FRAME_LEN, 235 .isc_rx_maxsegsize = ENETC_MAX_FRAME_LEN, 236 .isc_rx_nsegments = ENETC_MAX_SCATTER, 237 238 .isc_admin_intrcnt = 0, 239 240 .isc_nfl = 1, 241 .isc_nrxqs = 1, 242 .isc_ntxqs = 1, 243 244 .isc_vendor_info = enetc_vendor_info_array, 245 .isc_driver_version = enetc_driver_version, 246 .isc_driver = &enetc_iflib_driver, 247 248 .isc_flags = IFLIB_DRIVER_MEDIA | IFLIB_PRESERVE_TX_INDICES, 249 .isc_ntxd_min = {ENETC_MIN_DESC}, 250 .isc_ntxd_max = {ENETC_MAX_DESC}, 251 .isc_ntxd_default = {ENETC_DEFAULT_DESC}, 252 .isc_nrxd_min = {ENETC_MIN_DESC}, 253 .isc_nrxd_max = {ENETC_MAX_DESC}, 254 .isc_nrxd_default = {ENETC_DEFAULT_DESC} 255 }; 256 257 static void* 258 enetc_register(device_t dev) 259 { 260 261 if (!ofw_bus_status_okay(dev)) 262 return (NULL); 263 264 return (&enetc_sctx_init); 265 } 266 267 static void 268 enetc_max_nqueues(struct enetc_softc *sc, int *max_tx_nqueues, 269 int *max_rx_nqueues) 270 { 271 uint32_t val; 272 273 val = ENETC_PORT_RD4(sc, ENETC_PCAPR0); 274 *max_tx_nqueues = MIN(ENETC_PCAPR0_TXBDR(val), ENETC_MAX_QUEUES); 275 *max_rx_nqueues = MIN(ENETC_PCAPR0_RXBDR(val), ENETC_MAX_QUEUES); 276 } 277 278 static int 279 enetc_setup_fixed(struct enetc_softc *sc, phandle_t node) 280 { 281 ssize_t size; 282 int speed; 283 284 size = OF_getencprop(node, "speed", &speed, sizeof(speed)); 285 if (size <= 0) { 286 device_printf(sc->dev, 287 "Device has fixed-link node without link speed specified\n"); 288 return (ENXIO); 289 } 290 switch (speed) { 291 case 10: 292 speed = IFM_10_T; 293 break; 294 case 100: 295 speed = IFM_100_TX; 296 break; 297 case 1000: 298 speed = IFM_1000_T; 299 break; 300 case 2500: 301 speed = IFM_2500_T; 302 break; 303 default: 304 device_printf(sc->dev, "Unsupported link speed value of %d\n", 305 speed); 306 return (ENXIO); 307 } 308 speed |= IFM_ETHER; 309 310 if (OF_hasprop(node, "full-duplex")) 311 speed |= IFM_FDX; 312 else 313 speed |= IFM_HDX; 314 315 sc->fixed_link = true; 316 317 ifmedia_init(&sc->fixed_ifmedia, 0, enetc_fixed_media_change, 318 enetc_fixed_media_status); 319 ifmedia_add(&sc->fixed_ifmedia, speed, 0, NULL); 320 ifmedia_set(&sc->fixed_ifmedia, speed); 321 sc->shared->isc_media = &sc->fixed_ifmedia; 322 323 return (0); 324 } 325 326 static int 327 enetc_setup_phy(struct enetc_softc *sc) 328 { 329 phandle_t node, fixed_link, phy_handle; 330 struct mii_data *miid; 331 int phy_addr, error; 332 ssize_t size; 333 334 node = ofw_bus_get_node(sc->dev); 335 fixed_link = ofw_bus_find_child(node, "fixed-link"); 336 if (fixed_link != 0) 337 return (enetc_setup_fixed(sc, fixed_link)); 338 339 size = OF_getencprop(node, "phy-handle", &phy_handle, sizeof(phy_handle)); 340 if (size <= 0) { 341 device_printf(sc->dev, 342 "Failed to acquire PHY handle from FDT.\n"); 343 return (ENXIO); 344 } 345 phy_handle = OF_node_from_xref(phy_handle); 346 size = OF_getencprop(phy_handle, "reg", &phy_addr, sizeof(phy_addr)); 347 if (size <= 0) { 348 device_printf(sc->dev, "Failed to obtain PHY address\n"); 349 return (ENXIO); 350 } 351 error = mii_attach(sc->dev, &sc->miibus, iflib_get_ifp(sc->ctx), 352 enetc_media_change, enetc_media_status, 353 BMSR_DEFCAPMASK, phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 354 if (error != 0) { 355 device_printf(sc->dev, "mii_attach failed\n"); 356 return (error); 357 } 358 miid = device_get_softc(sc->miibus); 359 sc->shared->isc_media = &miid->mii_media; 360 361 return (0); 362 } 363 364 static int 365 enetc_attach_pre(if_ctx_t ctx) 366 { 367 struct ifnet *ifp; 368 if_softc_ctx_t scctx; 369 struct enetc_softc *sc; 370 int error, rid; 371 372 sc = iflib_get_softc(ctx); 373 scctx = iflib_get_softc_ctx(ctx); 374 sc->ctx = ctx; 375 sc->dev = iflib_get_dev(ctx); 376 sc->shared = scctx; 377 ifp = iflib_get_ifp(ctx); 378 379 mtx_init(&sc->mii_lock, "enetc_mdio", NULL, MTX_DEF); 380 381 pci_save_state(sc->dev); 382 pcie_flr(sc->dev, 1000, false); 383 pci_restore_state(sc->dev); 384 385 rid = PCIR_BAR(ENETC_BAR_REGS); 386 sc->regs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 387 if (sc->regs == NULL) { 388 device_printf(sc->dev, 389 "Failed to allocate BAR %d\n", ENETC_BAR_REGS); 390 return (ENXIO); 391 } 392 393 error = iflib_dma_alloc_align(ctx, 394 ENETC_MIN_DESC * sizeof(struct enetc_cbd), 395 ENETC_RING_ALIGN, 396 &sc->ctrl_queue.dma, 397 0); 398 if (error != 0) { 399 device_printf(sc->dev, "Failed to allocate control ring\n"); 400 goto fail; 401 } 402 sc->ctrl_queue.ring = (struct enetc_cbd*)sc->ctrl_queue.dma.idi_vaddr; 403 404 scctx->isc_txrx = &enetc_txrx; 405 scctx->isc_tx_nsegments = ENETC_MAX_SCATTER; 406 enetc_max_nqueues(sc, &scctx->isc_nrxqsets_max, &scctx->isc_ntxqsets_max); 407 408 if (scctx->isc_ntxd[0] % ENETC_DESC_ALIGN != 0) { 409 device_printf(sc->dev, 410 "The number of TX descriptors has to be a multiple of %d\n", 411 ENETC_DESC_ALIGN); 412 error = EINVAL; 413 goto fail; 414 } 415 if (scctx->isc_nrxd[0] % ENETC_DESC_ALIGN != 0) { 416 device_printf(sc->dev, 417 "The number of RX descriptors has to be a multiple of %d\n", 418 ENETC_DESC_ALIGN); 419 error = EINVAL; 420 goto fail; 421 } 422 scctx->isc_txqsizes[0] = scctx->isc_ntxd[0] * sizeof(union enetc_tx_bd); 423 scctx->isc_rxqsizes[0] = scctx->isc_nrxd[0] * sizeof(union enetc_rx_bd); 424 scctx->isc_txd_size[0] = sizeof(union enetc_tx_bd); 425 scctx->isc_rxd_size[0] = sizeof(union enetc_rx_bd); 426 scctx->isc_tx_csum_flags = 0; 427 scctx->isc_capabilities = scctx->isc_capenable = ENETC_IFCAPS; 428 429 error = enetc_mtu_set(ctx, ETHERMTU); 430 if (error != 0) 431 goto fail; 432 433 scctx->isc_msix_bar = pci_msix_table_bar(sc->dev); 434 435 error = enetc_setup_phy(sc); 436 if (error != 0) 437 goto fail; 438 439 enetc_get_hwaddr(sc); 440 441 return (0); 442 fail: 443 enetc_detach(ctx); 444 return (error); 445 } 446 447 static int 448 enetc_attach_post(if_ctx_t ctx) 449 { 450 451 enetc_init_hw(iflib_get_softc(ctx)); 452 return (0); 453 } 454 455 static int 456 enetc_detach(if_ctx_t ctx) 457 { 458 struct enetc_softc *sc; 459 int error = 0, i; 460 461 sc = iflib_get_softc(ctx); 462 463 for (i = 0; i < sc->rx_num_queues; i++) 464 iflib_irq_free(ctx, &sc->rx_queues[i].irq); 465 466 if (sc->miibus != NULL) 467 device_delete_child(sc->dev, sc->miibus); 468 469 if (sc->regs != NULL) 470 error = bus_release_resource(sc->dev, SYS_RES_MEMORY, 471 rman_get_rid(sc->regs), sc->regs); 472 473 if (sc->ctrl_queue.dma.idi_size != 0) 474 iflib_dma_free(&sc->ctrl_queue.dma); 475 476 mtx_destroy(&sc->mii_lock); 477 478 return (error); 479 } 480 481 static int 482 enetc_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 483 int ntxqs, int ntxqsets) 484 { 485 struct enetc_softc *sc; 486 struct enetc_tx_queue *queue; 487 int i; 488 489 sc = iflib_get_softc(ctx); 490 491 MPASS(ntxqs == 1); 492 493 sc->tx_queues = mallocarray(sc->tx_num_queues, 494 sizeof(struct enetc_tx_queue), M_DEVBUF, M_NOWAIT | M_ZERO); 495 if (sc->tx_queues == NULL) { 496 device_printf(sc->dev, 497 "Failed to allocate memory for TX queues.\n"); 498 return (ENOMEM); 499 } 500 501 for (i = 0; i < sc->tx_num_queues; i++) { 502 queue = &sc->tx_queues[i]; 503 queue->sc = sc; 504 queue->ring = (union enetc_tx_bd*)(vaddrs[i]); 505 queue->ring_paddr = paddrs[i]; 506 queue->next_to_clean = 0; 507 queue->ring_full = false; 508 } 509 510 return (0); 511 } 512 513 static int 514 enetc_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 515 int nrxqs, int nrxqsets) 516 { 517 struct enetc_softc *sc; 518 struct enetc_rx_queue *queue; 519 int i; 520 521 sc = iflib_get_softc(ctx); 522 MPASS(nrxqs == 1); 523 524 sc->rx_queues = mallocarray(sc->rx_num_queues, 525 sizeof(struct enetc_rx_queue), M_DEVBUF, M_NOWAIT | M_ZERO); 526 if (sc->rx_queues == NULL) { 527 device_printf(sc->dev, 528 "Failed to allocate memory for RX queues.\n"); 529 return (ENOMEM); 530 } 531 532 for (i = 0; i < sc->rx_num_queues; i++) { 533 queue = &sc->rx_queues[i]; 534 queue->sc = sc; 535 queue->qid = i; 536 queue->ring = (union enetc_rx_bd*)(vaddrs[i]); 537 queue->ring_paddr = paddrs[i]; 538 } 539 540 return (0); 541 } 542 543 static void 544 enetc_queues_free(if_ctx_t ctx) 545 { 546 struct enetc_softc *sc; 547 548 sc = iflib_get_softc(ctx); 549 550 if (sc->tx_queues != NULL) { 551 free(sc->tx_queues, M_DEVBUF); 552 sc->tx_queues = NULL; 553 } 554 if (sc->rx_queues != NULL) { 555 free(sc->rx_queues, M_DEVBUF); 556 sc->rx_queues = NULL; 557 } 558 } 559 560 static void 561 enetc_get_hwaddr(struct enetc_softc *sc) 562 { 563 struct ether_addr hwaddr; 564 uint16_t high; 565 uint32_t low; 566 567 low = ENETC_PORT_RD4(sc, ENETC_PSIPMAR0(0)); 568 high = ENETC_PORT_RD2(sc, ENETC_PSIPMAR1(0)); 569 570 memcpy(&hwaddr.octet[0], &low, 4); 571 memcpy(&hwaddr.octet[4], &high, 2); 572 573 if (ETHER_IS_BROADCAST(hwaddr.octet) || 574 ETHER_IS_MULTICAST(hwaddr.octet) || 575 ETHER_IS_ZERO(hwaddr.octet)) { 576 ether_gen_addr(iflib_get_ifp(sc->ctx), &hwaddr); 577 device_printf(sc->dev, 578 "Failed to obtain MAC address, using a random one\n"); 579 memcpy(&low, &hwaddr.octet[0], 4); 580 memcpy(&high, &hwaddr.octet[4], 2); 581 } 582 583 iflib_set_mac(sc->ctx, hwaddr.octet); 584 } 585 586 static void 587 enetc_set_hwaddr(struct enetc_softc *sc) 588 { 589 struct ifnet *ifp; 590 uint16_t high; 591 uint32_t low; 592 uint8_t *hwaddr; 593 594 ifp = iflib_get_ifp(sc->ctx); 595 hwaddr = (uint8_t*)if_getlladdr(ifp); 596 low = *((uint32_t*)hwaddr); 597 high = *((uint16_t*)(hwaddr+4)); 598 599 ENETC_PORT_WR4(sc, ENETC_PSIPMAR0(0), low); 600 ENETC_PORT_WR2(sc, ENETC_PSIPMAR1(0), high); 601 } 602 603 static int 604 enetc_setup_rss(struct enetc_softc *sc) 605 { 606 struct iflib_dma_info dma; 607 int error, i, buckets_num = 0; 608 uint8_t *rss_table; 609 uint32_t reg; 610 611 reg = ENETC_RD4(sc, ENETC_SIPCAPR0); 612 if (reg & ENETC_SIPCAPR0_RSS) { 613 reg = ENETC_RD4(sc, ENETC_SIRSSCAPR); 614 buckets_num = ENETC_SIRSSCAPR_GET_NUM_RSS(reg); 615 } 616 if (buckets_num == 0) 617 return (ENOTSUP); 618 619 for (i = 0; i < ENETC_RSSHASH_KEY_SIZE / sizeof(uint32_t); i++) { 620 arc4rand((uint8_t *)®, sizeof(reg), 0); 621 ENETC_PORT_WR4(sc, ENETC_PRSSK(i), reg); 622 } 623 624 ENETC_WR4(sc, ENETC_SIRBGCR, sc->rx_num_queues); 625 626 error = iflib_dma_alloc_align(sc->ctx, 627 buckets_num * sizeof(*rss_table), 628 ENETC_RING_ALIGN, 629 &dma, 630 0); 631 if (error != 0) { 632 device_printf(sc->dev, "Failed to allocate DMA buffer for RSS\n"); 633 return (error); 634 } 635 rss_table = (uint8_t *)dma.idi_vaddr; 636 637 for (i = 0; i < buckets_num; i++) 638 rss_table[i] = i % sc->rx_num_queues; 639 640 error = enetc_ctrl_send(sc, (BDCR_CMD_RSS << 8) | BDCR_CMD_RSS_WRITE, 641 buckets_num * sizeof(*rss_table), &dma); 642 if (error != 0) 643 device_printf(sc->dev, "Failed to setup RSS table\n"); 644 645 iflib_dma_free(&dma); 646 647 return (error); 648 } 649 650 static int 651 enetc_ctrl_send(struct enetc_softc *sc, uint16_t cmd, uint16_t size, 652 iflib_dma_info_t dma) 653 { 654 struct enetc_ctrl_queue *queue; 655 struct enetc_cbd *desc; 656 int timeout = 1000; 657 658 queue = &sc->ctrl_queue; 659 desc = &queue->ring[queue->pidx]; 660 661 if (++queue->pidx == ENETC_MIN_DESC) 662 queue->pidx = 0; 663 664 desc->addr[0] = (uint32_t)dma->idi_paddr; 665 desc->addr[1] = (uint32_t)(dma->idi_paddr >> 32); 666 desc->index = 0; 667 desc->length = (uint16_t)size; 668 desc->cmd = (uint8_t)cmd; 669 desc->cls = (uint8_t)(cmd >> 8); 670 desc->status_flags = 0; 671 672 /* Sync command packet, */ 673 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_PREWRITE); 674 /* and the control ring. */ 675 bus_dmamap_sync(queue->dma.idi_tag, queue->dma.idi_map, BUS_DMASYNC_PREWRITE); 676 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx); 677 678 while (--timeout != 0) { 679 DELAY(20); 680 if (ENETC_RD4(sc, ENETC_SICBDRCIR) == queue->pidx) 681 break; 682 } 683 684 if (timeout == 0) 685 return (ETIMEDOUT); 686 687 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_POSTREAD); 688 return (0); 689 } 690 691 static void 692 enetc_init_hw(struct enetc_softc *sc) 693 { 694 uint32_t val; 695 int error; 696 697 ENETC_PORT_WR4(sc, ENETC_PM0_CMD_CFG, 698 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC | 699 ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 700 ENETC_PORT_WR4(sc, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); 701 val = ENETC_PSICFGR0_SET_TXBDR(sc->tx_num_queues); 702 val |= ENETC_PSICFGR0_SET_RXBDR(sc->rx_num_queues); 703 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 704 ENETC_PORT_WR4(sc, ENETC_PSICFGR0(0), val); 705 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VUTA(1)); 706 ENETC_PORT_WR4(sc, ENETC_PVCLCTR, ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 707 ENETC_PORT_WR4(sc, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); 708 ENETC_PORT_WR4(sc, ENETC_PAR_PORT_CFG, ENETC_PAR_PORT_L4CD); 709 ENETC_PORT_WR4(sc, ENETC_PMR, ENETC_PMR_SI0EN | ENETC_PMR_PSPEED_1000M); 710 711 ENETC_WR4(sc, ENETC_SICAR0, 712 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 713 ENETC_WR4(sc, ENETC_SICAR1, ENETC_SICAR_MSI); 714 ENETC_WR4(sc, ENETC_SICAR2, 715 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 716 717 enetc_init_ctrl(sc); 718 error = enetc_setup_rss(sc); 719 if (error != 0) 720 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN); 721 else 722 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN | ENETC_SIMR_RSSE); 723 724 } 725 726 static void 727 enetc_init_ctrl(struct enetc_softc *sc) 728 { 729 struct enetc_ctrl_queue *queue = &sc->ctrl_queue; 730 731 ENETC_WR4(sc, ENETC_SICBDRBAR0, 732 (uint32_t)queue->dma.idi_paddr); 733 ENETC_WR4(sc, ENETC_SICBDRBAR1, 734 (uint32_t)(queue->dma.idi_paddr >> 32)); 735 ENETC_WR4(sc, ENETC_SICBDRLENR, 736 queue->dma.idi_size / sizeof(struct enetc_cbd)); 737 738 queue->pidx = 0; 739 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx); 740 ENETC_WR4(sc, ENETC_SICBDRCIR, queue->pidx); 741 ENETC_WR4(sc, ENETC_SICBDRMR, ENETC_SICBDRMR_EN); 742 } 743 744 static void 745 enetc_init_tx(struct enetc_softc *sc) 746 { 747 struct enetc_tx_queue *queue; 748 int i; 749 750 for (i = 0; i < sc->tx_num_queues; i++) { 751 queue = &sc->tx_queues[i]; 752 753 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR0, 754 (uint32_t)queue->ring_paddr); 755 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR1, 756 (uint32_t)(queue->ring_paddr >> 32)); 757 ENETC_TXQ_WR4(sc, i, ENETC_TBLENR, sc->tx_queue_size); 758 759 /* 760 * Even though it is undoccumented resetting the TX ring 761 * indices results in TX hang. 762 * Do the same as Linux and simply keep those unchanged 763 * for the drivers lifetime. 764 */ 765 #if 0 766 ENETC_TXQ_WR4(sc, i, ENETC_TBPIR, 0); 767 ENETC_TXQ_WR4(sc, i, ENETC_TBCIR, 0); 768 #endif 769 ENETC_TXQ_WR4(sc, i, ENETC_TBMR, ENETC_TBMR_EN); 770 } 771 772 } 773 774 static void 775 enetc_init_rx(struct enetc_softc *sc) 776 { 777 struct enetc_rx_queue *queue; 778 uint32_t rx_buf_size; 779 int i; 780 781 rx_buf_size = iflib_get_rx_mbuf_sz(sc->ctx); 782 783 for (i = 0; i < sc->rx_num_queues; i++) { 784 queue = &sc->rx_queues[i]; 785 786 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR0, 787 (uint32_t)queue->ring_paddr); 788 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR1, 789 (uint32_t)(queue->ring_paddr >> 32)); 790 ENETC_RXQ_WR4(sc, i, ENETC_RBLENR, sc->rx_queue_size); 791 ENETC_RXQ_WR4(sc, i, ENETC_RBBSR, rx_buf_size); 792 ENETC_RXQ_WR4(sc, i, ENETC_RBPIR, 0); 793 ENETC_RXQ_WR4(sc, i, ENETC_RBCIR, 0); 794 queue->enabled = false; 795 } 796 } 797 798 static u_int 799 enetc_hash_mac(void *arg, struct sockaddr_dl *sdl, u_int cnt) 800 { 801 uint64_t *bitmap = arg; 802 uint64_t address = 0; 803 uint8_t hash = 0; 804 bool bit; 805 int i, j; 806 807 bcopy(LLADDR(sdl), &address, ETHER_ADDR_LEN); 808 809 /* 810 * The six bit hash is calculated by xoring every 811 * 6th bit of the address. 812 * It is then used as an index in a bitmap that is 813 * written to the device. 814 */ 815 for (i = 0; i < 6; i++) { 816 bit = 0; 817 for (j = 0; j < 8; j++) 818 bit ^= !!(address & BIT(i + j*6)); 819 820 hash |= bit << i; 821 } 822 823 *bitmap |= (1 << hash); 824 return (1); 825 } 826 827 static void 828 enetc_setup_multicast(if_ctx_t ctx) 829 { 830 struct enetc_softc *sc; 831 struct ifnet *ifp; 832 uint64_t bitmap = 0; 833 uint8_t revid; 834 835 sc = iflib_get_softc(ctx); 836 ifp = iflib_get_ifp(ctx); 837 revid = pci_get_revid(sc->dev); 838 839 if_foreach_llmaddr(ifp, enetc_hash_mac, &bitmap); 840 841 /* 842 * In revid 1 of this chip the positions multicast and unicast 843 * hash filter registers are flipped. 844 */ 845 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR0(0, revid == 1), bitmap & UINT32_MAX); 846 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR1(0), bitmap >> 32); 847 848 } 849 850 static uint8_t 851 enetc_hash_vid(uint16_t vid) 852 { 853 uint8_t hash = 0; 854 bool bit; 855 int i; 856 857 for (i = 0;i < 6;i++) { 858 bit = vid & BIT(i); 859 bit ^= !!(vid & BIT(i + 6)); 860 hash |= bit << i; 861 } 862 863 return (hash); 864 } 865 866 static void 867 enetc_vlan_register(if_ctx_t ctx, uint16_t vid) 868 { 869 struct enetc_softc *sc; 870 uint8_t hash; 871 uint64_t bitmap; 872 873 sc = iflib_get_softc(ctx); 874 hash = enetc_hash_vid(vid); 875 876 /* Check if hash is alredy present in the bitmap. */ 877 if (++sc->vlan_bitmap[hash] != 1) 878 return; 879 880 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0)); 881 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32; 882 bitmap |= BIT(hash); 883 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX); 884 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32); 885 } 886 887 static void 888 enetc_vlan_unregister(if_ctx_t ctx, uint16_t vid) 889 { 890 struct enetc_softc *sc; 891 uint8_t hash; 892 uint64_t bitmap; 893 894 sc = iflib_get_softc(ctx); 895 hash = enetc_hash_vid(vid); 896 897 MPASS(sc->vlan_bitmap[hash] > 0); 898 if (--sc->vlan_bitmap[hash] != 0) 899 return; 900 901 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0)); 902 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32; 903 bitmap &= ~BIT(hash); 904 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX); 905 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32); 906 } 907 908 static void 909 enetc_init(if_ctx_t ctx) 910 { 911 struct enetc_softc *sc; 912 struct mii_data *miid; 913 struct ifnet *ifp; 914 uint16_t max_frame_length; 915 int baudrate; 916 917 sc = iflib_get_softc(ctx); 918 ifp = iflib_get_ifp(ctx); 919 920 max_frame_length = sc->shared->isc_max_frame_size; 921 MPASS(max_frame_length < ENETC_MAX_FRAME_LEN); 922 923 /* Set max RX and TX frame lengths. */ 924 ENETC_PORT_WR4(sc, ENETC_PM0_MAXFRM, max_frame_length); 925 ENETC_PORT_WR4(sc, ENETC_PTCMSDUR(0), max_frame_length); 926 ENETC_PORT_WR4(sc, ENETC_PTXMBAR, 2 * max_frame_length); 927 928 /* Set "VLAN promiscious" mode if filtering is disabled. */ 929 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) 930 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, 931 ENETC_PSIPVMR_SET_VUTA(1) | ENETC_PSIPVMR_SET_VP(1)); 932 else 933 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, 934 ENETC_PSIPVMR_SET_VUTA(1)); 935 936 sc->rbmr = ENETC_RBMR_EN | ENETC_RBMR_AL; 937 938 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 939 sc->rbmr |= ENETC_RBMR_VTE; 940 941 /* Write MAC address to hardware. */ 942 enetc_set_hwaddr(sc); 943 944 enetc_init_tx(sc); 945 enetc_init_rx(sc); 946 947 if (sc->fixed_link) { 948 baudrate = ifmedia_baudrate(sc->fixed_ifmedia.ifm_cur->ifm_media); 949 iflib_link_state_change(sc->ctx, LINK_STATE_UP, baudrate); 950 } else { 951 /* 952 * Can't return an error from this function, there is not much 953 * we can do if this fails. 954 */ 955 miid = device_get_softc(sc->miibus); 956 (void)mii_mediachg(miid); 957 } 958 959 enetc_promisc_set(ctx, if_getflags(ifp)); 960 } 961 962 static void 963 enetc_stop(if_ctx_t ctx) 964 { 965 struct enetc_softc *sc; 966 int i; 967 968 sc = iflib_get_softc(ctx); 969 970 for (i = 0; i < sc->tx_num_queues; i++) 971 ENETC_TXQ_WR4(sc, i, ENETC_TBMR, 0); 972 973 for (i = 0; i < sc->rx_num_queues; i++) 974 ENETC_RXQ_WR4(sc, i, ENETC_RBMR, 0); 975 } 976 977 static int 978 enetc_msix_intr_assign(if_ctx_t ctx, int msix) 979 { 980 struct enetc_softc *sc; 981 struct enetc_rx_queue *rx_queue; 982 struct enetc_tx_queue *tx_queue; 983 int vector = 0, i, error; 984 char irq_name[16]; 985 986 sc = iflib_get_softc(ctx); 987 988 MPASS(sc->rx_num_queues + 1 <= ENETC_MSIX_COUNT); 989 MPASS(sc->rx_num_queues == sc->tx_num_queues); 990 991 for (i = 0; i < sc->rx_num_queues; i++, vector++) { 992 rx_queue = &sc->rx_queues[i]; 993 snprintf(irq_name, sizeof(irq_name), "rxtxq%d", i); 994 error = iflib_irq_alloc_generic(ctx, 995 &rx_queue->irq, vector + 1, IFLIB_INTR_RXTX, 996 NULL, rx_queue, i, irq_name); 997 if (error != 0) 998 goto fail; 999 1000 ENETC_WR4(sc, ENETC_SIMSIRRV(i), vector); 1001 ENETC_RXQ_WR4(sc, i, ENETC_RBICR1, ENETC_RX_INTR_TIME_THR); 1002 ENETC_RXQ_WR4(sc, i, ENETC_RBICR0, 1003 ENETC_RBICR0_ICEN | ENETC_RBICR0_SET_ICPT(ENETC_RX_INTR_PKT_THR)); 1004 } 1005 vector = 0; 1006 for (i = 0;i < sc->tx_num_queues; i++, vector++) { 1007 tx_queue = &sc->tx_queues[i]; 1008 snprintf(irq_name, sizeof(irq_name), "txq%d", i); 1009 iflib_softirq_alloc_generic(ctx, &tx_queue->irq, 1010 IFLIB_INTR_TX, tx_queue, i, irq_name); 1011 1012 ENETC_WR4(sc, ENETC_SIMSITRV(i), vector); 1013 } 1014 1015 return (0); 1016 fail: 1017 for (i = 0; i < sc->rx_num_queues; i++) { 1018 rx_queue = &sc->rx_queues[i]; 1019 iflib_irq_free(ctx, &rx_queue->irq); 1020 } 1021 return (error); 1022 } 1023 1024 static int 1025 enetc_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 1026 { 1027 struct enetc_softc *sc; 1028 1029 sc = iflib_get_softc(ctx); 1030 ENETC_TXQ_RD4(sc, qid, ENETC_TBIDR); 1031 return (0); 1032 } 1033 1034 static int 1035 enetc_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 1036 { 1037 struct enetc_softc *sc; 1038 1039 sc = iflib_get_softc(ctx); 1040 ENETC_RXQ_RD4(sc, qid, ENETC_RBIDR); 1041 return (0); 1042 } 1043 static void 1044 enetc_intr_enable(if_ctx_t ctx) 1045 { 1046 struct enetc_softc *sc; 1047 int i; 1048 1049 sc = iflib_get_softc(ctx); 1050 1051 for (i = 0; i < sc->rx_num_queues; i++) 1052 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, ENETC_RBIER_RXTIE); 1053 1054 for (i = 0; i < sc->tx_num_queues; i++) 1055 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, ENETC_TBIER_TXF); 1056 } 1057 1058 static void 1059 enetc_intr_disable(if_ctx_t ctx) 1060 { 1061 struct enetc_softc *sc; 1062 int i; 1063 1064 sc = iflib_get_softc(ctx); 1065 1066 for (i = 0; i < sc->rx_num_queues; i++) 1067 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, 0); 1068 1069 for (i = 0; i < sc->tx_num_queues; i++) 1070 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, 0); 1071 } 1072 1073 static int 1074 enetc_isc_txd_encap(void *data, if_pkt_info_t ipi) 1075 { 1076 struct enetc_softc *sc = data; 1077 struct enetc_tx_queue *queue; 1078 union enetc_tx_bd *desc; 1079 bus_dma_segment_t *segs; 1080 qidx_t pidx, queue_len; 1081 qidx_t i = 0; 1082 1083 queue = &sc->tx_queues[ipi->ipi_qsidx]; 1084 segs = ipi->ipi_segs; 1085 pidx = ipi->ipi_pidx; 1086 queue_len = sc->tx_queue_size; 1087 1088 /* 1089 * First descriptor is special. We use it to set frame 1090 * related information and offloads, e.g. VLAN tag. 1091 */ 1092 desc = &queue->ring[pidx]; 1093 bzero(desc, sizeof(*desc)); 1094 desc->frm_len = ipi->ipi_len; 1095 desc->addr = segs[i].ds_addr; 1096 desc->buf_len = segs[i].ds_len; 1097 if (ipi->ipi_flags & IPI_TX_INTR) 1098 desc->flags = ENETC_TXBD_FLAGS_FI; 1099 1100 i++; 1101 if (++pidx == queue_len) 1102 pidx = 0; 1103 1104 if (ipi->ipi_mflags & M_VLANTAG) { 1105 /* VLAN tag is inserted in a separate descriptor. */ 1106 desc->flags |= ENETC_TXBD_FLAGS_EX; 1107 desc = &queue->ring[pidx]; 1108 bzero(desc, sizeof(*desc)); 1109 desc->ext.vid = ipi->ipi_vtag; 1110 desc->ext.e_flags = ENETC_TXBD_E_FLAGS_VLAN_INS; 1111 if (++pidx == queue_len) 1112 pidx = 0; 1113 } 1114 1115 /* Now add remaining descriptors. */ 1116 for (;i < ipi->ipi_nsegs; i++) { 1117 desc = &queue->ring[pidx]; 1118 bzero(desc, sizeof(*desc)); 1119 desc->addr = segs[i].ds_addr; 1120 desc->buf_len = segs[i].ds_len; 1121 1122 if (++pidx == queue_len) 1123 pidx = 0; 1124 } 1125 1126 desc->flags |= ENETC_TXBD_FLAGS_F; 1127 ipi->ipi_new_pidx = pidx; 1128 if (pidx == queue->next_to_clean) 1129 queue->ring_full = true; 1130 1131 return (0); 1132 } 1133 1134 static void 1135 enetc_isc_txd_flush(void *data, uint16_t qid, qidx_t pidx) 1136 { 1137 struct enetc_softc *sc = data; 1138 1139 ENETC_TXQ_WR4(sc, qid, ENETC_TBPIR, pidx); 1140 } 1141 1142 static int 1143 enetc_isc_txd_credits_update(void *data, uint16_t qid, bool clear) 1144 { 1145 struct enetc_softc *sc = data; 1146 struct enetc_tx_queue *queue; 1147 qidx_t next_to_clean, next_to_process; 1148 int clean_count; 1149 1150 queue = &sc->tx_queues[qid]; 1151 next_to_process = 1152 ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR) & ENETC_TBCIR_IDX_MASK; 1153 next_to_clean = queue->next_to_clean; 1154 1155 if (next_to_clean == next_to_process && !queue->ring_full) 1156 return (0); 1157 1158 if (!clear) 1159 return (1); 1160 1161 clean_count = next_to_process - next_to_clean; 1162 if (clean_count <= 0) 1163 clean_count += sc->tx_queue_size; 1164 1165 queue->next_to_clean = next_to_process; 1166 queue->ring_full = false; 1167 1168 return (clean_count); 1169 } 1170 1171 static int 1172 enetc_isc_rxd_available(void *data, uint16_t qid, qidx_t pidx, qidx_t budget) 1173 { 1174 struct enetc_softc *sc = data; 1175 struct enetc_rx_queue *queue; 1176 qidx_t hw_pidx, queue_len; 1177 union enetc_rx_bd *desc; 1178 int count = 0; 1179 1180 queue = &sc->rx_queues[qid]; 1181 desc = &queue->ring[pidx]; 1182 queue_len = sc->rx_queue_size; 1183 1184 if (desc->r.lstatus == 0) 1185 return (0); 1186 1187 if (budget == 1) 1188 return (1); 1189 1190 hw_pidx = ENETC_RXQ_RD4(sc, qid, ENETC_RBPIR); 1191 while (pidx != hw_pidx && count < budget) { 1192 desc = &queue->ring[pidx]; 1193 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F) 1194 count++; 1195 1196 if (++pidx == queue_len) 1197 pidx = 0; 1198 } 1199 1200 return (count); 1201 } 1202 1203 static int 1204 enetc_isc_rxd_pkt_get(void *data, if_rxd_info_t ri) 1205 { 1206 struct enetc_softc *sc = data; 1207 struct enetc_rx_queue *queue; 1208 union enetc_rx_bd *desc; 1209 uint16_t buf_len, pkt_size = 0; 1210 qidx_t cidx, queue_len; 1211 uint32_t status; 1212 int i; 1213 1214 cidx = ri->iri_cidx; 1215 queue = &sc->rx_queues[ri->iri_qsidx]; 1216 desc = &queue->ring[cidx]; 1217 status = desc->r.lstatus; 1218 queue_len = sc->rx_queue_size; 1219 1220 /* 1221 * Ready bit will be set only when all descriptors 1222 * in the chain have been processed. 1223 */ 1224 if ((status & ENETC_RXBD_LSTATUS_R) == 0) 1225 return (EAGAIN); 1226 1227 /* Pass RSS hash. */ 1228 if (status & ENETC_RXBD_FLAG_RSSV) { 1229 ri->iri_flowid = desc->r.rss_hash; 1230 ri->iri_rsstype = M_HASHTYPE_OPAQUE_HASH; 1231 } 1232 1233 /* Pass IP checksum status. */ 1234 ri->iri_csum_flags = CSUM_IP_CHECKED; 1235 if ((desc->r.parse_summary & ENETC_RXBD_PARSER_ERROR) == 0) 1236 ri->iri_csum_flags |= CSUM_IP_VALID; 1237 1238 /* Pass extracted VLAN tag. */ 1239 if (status & ENETC_RXBD_FLAG_VLAN) { 1240 ri->iri_vtag = desc->r.vlan_opt; 1241 ri->iri_flags = M_VLANTAG; 1242 } 1243 1244 for (i = 0; i < ENETC_MAX_SCATTER; i++) { 1245 buf_len = desc->r.buf_len; 1246 ri->iri_frags[i].irf_idx = cidx; 1247 ri->iri_frags[i].irf_len = buf_len; 1248 pkt_size += buf_len; 1249 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F) 1250 break; 1251 1252 if (++cidx == queue_len) 1253 cidx = 0; 1254 1255 desc = &queue->ring[cidx]; 1256 } 1257 ri->iri_nfrags = i + 1; 1258 ri->iri_len = pkt_size + ENETC_RX_IP_ALIGN; 1259 ri->iri_pad = ENETC_RX_IP_ALIGN; 1260 1261 MPASS(desc->r.lstatus & ENETC_RXBD_LSTATUS_F); 1262 if (status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK)) 1263 return (EBADMSG); 1264 1265 return (0); 1266 } 1267 1268 static void 1269 enetc_isc_rxd_refill(void *data, if_rxd_update_t iru) 1270 { 1271 struct enetc_softc *sc = data; 1272 struct enetc_rx_queue *queue; 1273 union enetc_rx_bd *desc; 1274 qidx_t pidx, queue_len; 1275 uint64_t *paddrs; 1276 int i, count; 1277 1278 queue = &sc->rx_queues[iru->iru_qsidx]; 1279 paddrs = iru->iru_paddrs; 1280 pidx = iru->iru_pidx; 1281 count = iru->iru_count; 1282 queue_len = sc->rx_queue_size; 1283 1284 for (i = 0; i < count; i++) { 1285 desc = &queue->ring[pidx]; 1286 bzero(desc, sizeof(*desc)); 1287 1288 desc->w.addr = paddrs[i]; 1289 if (++pidx == queue_len) 1290 pidx = 0; 1291 } 1292 /* 1293 * After enabling the queue NIC will prefetch the first 1294 * 8 descriptors. It probably assumes that the RX is fully 1295 * refilled when cidx == pidx. 1296 * Enable it only if we have enough decriptors ready on the ring. 1297 */ 1298 if (!queue->enabled && pidx >= 8) { 1299 ENETC_RXQ_WR4(sc, iru->iru_qsidx, ENETC_RBMR, sc->rbmr); 1300 queue->enabled = true; 1301 } 1302 } 1303 1304 static void 1305 enetc_isc_rxd_flush(void *data, uint16_t qid, uint8_t flid, qidx_t pidx) 1306 { 1307 struct enetc_softc *sc = data; 1308 1309 ENETC_RXQ_WR4(sc, qid, ENETC_RBCIR, pidx); 1310 } 1311 1312 static uint64_t 1313 enetc_get_counter(if_ctx_t ctx, ift_counter cnt) 1314 { 1315 struct enetc_softc *sc; 1316 struct ifnet *ifp; 1317 1318 sc = iflib_get_softc(ctx); 1319 ifp = iflib_get_ifp(ctx); 1320 1321 switch (cnt) { 1322 case IFCOUNTER_IERRORS: 1323 return (ENETC_PORT_RD8(sc, ENETC_PM0_RERR)); 1324 case IFCOUNTER_OERRORS: 1325 return (ENETC_PORT_RD8(sc, ENETC_PM0_TERR)); 1326 default: 1327 return (if_get_counter_default(ifp, cnt)); 1328 } 1329 } 1330 1331 static int 1332 enetc_mtu_set(if_ctx_t ctx, uint32_t mtu) 1333 { 1334 struct enetc_softc *sc = iflib_get_softc(ctx); 1335 uint32_t max_frame_size; 1336 1337 max_frame_size = mtu + 1338 ETHER_HDR_LEN + 1339 ETHER_CRC_LEN + 1340 sizeof(struct ether_vlan_header); 1341 1342 if (max_frame_size > ENETC_MAX_FRAME_LEN) 1343 return (EINVAL); 1344 1345 sc->shared->isc_max_frame_size = max_frame_size; 1346 1347 return (0); 1348 } 1349 1350 static int 1351 enetc_promisc_set(if_ctx_t ctx, int flags) 1352 { 1353 struct enetc_softc *sc; 1354 uint32_t reg = 0; 1355 1356 sc = iflib_get_softc(ctx); 1357 1358 if (flags & IFF_PROMISC) 1359 reg = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); 1360 else if (flags & IFF_ALLMULTI) 1361 reg = ENETC_PSIPMR_SET_MP(0); 1362 1363 ENETC_PORT_WR4(sc, ENETC_PSIPMR, reg); 1364 1365 return (0); 1366 } 1367 1368 static void 1369 enetc_timer(if_ctx_t ctx, uint16_t qid) 1370 { 1371 /* 1372 * Poll PHY status. Do this only for qid 0 to save 1373 * some cycles. 1374 */ 1375 if (qid == 0) 1376 iflib_admin_intr_deferred(ctx); 1377 } 1378 1379 static void 1380 enetc_update_admin_status(if_ctx_t ctx) 1381 { 1382 struct enetc_softc *sc; 1383 struct mii_data *miid; 1384 1385 sc = iflib_get_softc(ctx); 1386 1387 if (!sc->fixed_link) { 1388 miid = device_get_softc(sc->miibus); 1389 mii_tick(miid); 1390 } 1391 } 1392 1393 static int 1394 enetc_miibus_readreg(device_t dev, int phy, int reg) 1395 { 1396 struct enetc_softc *sc; 1397 int val; 1398 1399 sc = iflib_get_softc(device_get_softc(dev)); 1400 1401 mtx_lock(&sc->mii_lock); 1402 val = enetc_mdio_read(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE, 1403 phy, reg); 1404 mtx_unlock(&sc->mii_lock); 1405 1406 return (val); 1407 } 1408 1409 static int 1410 enetc_miibus_writereg(device_t dev, int phy, int reg, int data) 1411 { 1412 struct enetc_softc *sc; 1413 int ret; 1414 1415 sc = iflib_get_softc(device_get_softc(dev)); 1416 1417 mtx_lock(&sc->mii_lock); 1418 ret = enetc_mdio_write(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE, 1419 phy, reg, data); 1420 mtx_unlock(&sc->mii_lock); 1421 1422 return (ret); 1423 } 1424 1425 static void 1426 enetc_miibus_linkchg(device_t dev) 1427 { 1428 1429 enetc_miibus_statchg(dev); 1430 } 1431 1432 static void 1433 enetc_miibus_statchg(device_t dev) 1434 { 1435 struct enetc_softc *sc; 1436 struct mii_data *miid; 1437 int link_state, baudrate; 1438 1439 sc = iflib_get_softc(device_get_softc(dev)); 1440 miid = device_get_softc(sc->miibus); 1441 1442 baudrate = ifmedia_baudrate(miid->mii_media_active); 1443 if (miid->mii_media_status & IFM_AVALID) { 1444 if (miid->mii_media_status & IFM_ACTIVE) 1445 link_state = LINK_STATE_UP; 1446 else 1447 link_state = LINK_STATE_DOWN; 1448 } else { 1449 link_state = LINK_STATE_UNKNOWN; 1450 } 1451 1452 iflib_link_state_change(sc->ctx, link_state, baudrate); 1453 1454 } 1455 1456 static int 1457 enetc_media_change(if_t ifp) 1458 { 1459 struct enetc_softc *sc; 1460 struct mii_data *miid; 1461 1462 sc = iflib_get_softc(ifp->if_softc); 1463 miid = device_get_softc(sc->miibus); 1464 1465 mii_mediachg(miid); 1466 return (0); 1467 } 1468 1469 static void 1470 enetc_media_status(if_t ifp, struct ifmediareq* ifmr) 1471 { 1472 struct enetc_softc *sc; 1473 struct mii_data *miid; 1474 1475 sc = iflib_get_softc(ifp->if_softc); 1476 miid = device_get_softc(sc->miibus); 1477 1478 mii_pollstat(miid); 1479 1480 ifmr->ifm_active = miid->mii_media_active; 1481 ifmr->ifm_status = miid->mii_media_status; 1482 } 1483 1484 static int 1485 enetc_fixed_media_change(if_t ifp) 1486 { 1487 1488 if_printf(ifp, "Can't change media in fixed-link mode.\n"); 1489 return (0); 1490 } 1491 static void 1492 enetc_fixed_media_status(if_t ifp, struct ifmediareq* ifmr) 1493 { 1494 struct enetc_softc *sc; 1495 1496 sc = iflib_get_softc(ifp->if_softc); 1497 1498 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1499 ifmr->ifm_active = sc->fixed_ifmedia.ifm_cur->ifm_media; 1500 return; 1501 } 1502