1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2021 Alstom Group. 5 * Copyright (c) 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/rman.h> 37 #include <sys/socket.h> 38 #include <sys/sockio.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 43 #include <net/ethernet.h> 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_var.h> 47 #include <net/if_types.h> 48 #include <net/if_media.h> 49 #include <net/iflib.h> 50 51 #include <dev/enetc/enetc_hw.h> 52 #include <dev/enetc/enetc.h> 53 #include <dev/enetc/enetc_mdio.h> 54 #include <dev/mii/mii.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 62 #include "ifdi_if.h" 63 #include "miibus_if.h" 64 65 static device_register_t enetc_register; 66 67 static ifdi_attach_pre_t enetc_attach_pre; 68 static ifdi_attach_post_t enetc_attach_post; 69 static ifdi_detach_t enetc_detach; 70 71 static ifdi_tx_queues_alloc_t enetc_tx_queues_alloc; 72 static ifdi_rx_queues_alloc_t enetc_rx_queues_alloc; 73 static ifdi_queues_free_t enetc_queues_free; 74 75 static ifdi_init_t enetc_init; 76 static ifdi_stop_t enetc_stop; 77 78 static ifdi_msix_intr_assign_t enetc_msix_intr_assign; 79 static ifdi_tx_queue_intr_enable_t enetc_tx_queue_intr_enable; 80 static ifdi_rx_queue_intr_enable_t enetc_rx_queue_intr_enable; 81 static ifdi_intr_enable_t enetc_intr_enable; 82 static ifdi_intr_disable_t enetc_intr_disable; 83 84 static int enetc_isc_txd_encap(void*, if_pkt_info_t); 85 static void enetc_isc_txd_flush(void*, uint16_t, qidx_t); 86 static int enetc_isc_txd_credits_update(void*, uint16_t, bool); 87 static int enetc_isc_rxd_available(void*, uint16_t, qidx_t, qidx_t); 88 static int enetc_isc_rxd_pkt_get(void*, if_rxd_info_t); 89 static void enetc_isc_rxd_refill(void*, if_rxd_update_t); 90 static void enetc_isc_rxd_flush(void*, uint16_t, uint8_t, qidx_t); 91 92 static void enetc_vlan_register(if_ctx_t, uint16_t); 93 static void enetc_vlan_unregister(if_ctx_t, uint16_t); 94 95 static uint64_t enetc_get_counter(if_ctx_t, ift_counter); 96 static int enetc_promisc_set(if_ctx_t, int); 97 static int enetc_mtu_set(if_ctx_t, uint32_t); 98 static void enetc_setup_multicast(if_ctx_t); 99 static void enetc_timer(if_ctx_t, uint16_t); 100 static void enetc_update_admin_status(if_ctx_t); 101 102 static miibus_readreg_t enetc_miibus_readreg; 103 static miibus_writereg_t enetc_miibus_writereg; 104 static miibus_linkchg_t enetc_miibus_linkchg; 105 static miibus_statchg_t enetc_miibus_statchg; 106 107 static int enetc_media_change(if_t); 108 static void enetc_media_status(if_t, struct ifmediareq*); 109 110 static int enetc_fixed_media_change(if_t); 111 static void enetc_fixed_media_status(if_t, struct ifmediareq*); 112 113 static void enetc_max_nqueues(struct enetc_softc*, int*, int*); 114 static int enetc_setup_phy(struct enetc_softc*); 115 116 static void enetc_get_hwaddr(struct enetc_softc*); 117 static void enetc_set_hwaddr(struct enetc_softc*); 118 static int enetc_setup_rss(struct enetc_softc*); 119 120 static void enetc_init_hw(struct enetc_softc*); 121 static void enetc_init_ctrl(struct enetc_softc*); 122 static void enetc_init_tx(struct enetc_softc*); 123 static void enetc_init_rx(struct enetc_softc*); 124 125 static int enetc_ctrl_send(struct enetc_softc*, 126 uint16_t, uint16_t, iflib_dma_info_t); 127 128 static const char enetc_driver_version[] = "1.0.0"; 129 130 static pci_vendor_info_t enetc_vendor_info_array[] = { 131 PVID(PCI_VENDOR_FREESCALE, ENETC_DEV_ID_PF, 132 "Freescale ENETC PCIe Gigabit Ethernet Controller"), 133 PVID_END 134 }; 135 136 #define ENETC_IFCAPS (IFCAP_VLAN_MTU | IFCAP_RXCSUM | IFCAP_JUMBO_MTU | \ 137 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER) 138 139 static device_method_t enetc_methods[] = { 140 DEVMETHOD(device_register, enetc_register), 141 DEVMETHOD(device_probe, iflib_device_probe), 142 DEVMETHOD(device_attach, iflib_device_attach), 143 DEVMETHOD(device_detach, iflib_device_detach), 144 DEVMETHOD(device_shutdown, iflib_device_shutdown), 145 DEVMETHOD(device_suspend, iflib_device_suspend), 146 DEVMETHOD(device_resume, iflib_device_resume), 147 148 DEVMETHOD(miibus_readreg, enetc_miibus_readreg), 149 DEVMETHOD(miibus_writereg, enetc_miibus_writereg), 150 DEVMETHOD(miibus_linkchg, enetc_miibus_linkchg), 151 DEVMETHOD(miibus_statchg, enetc_miibus_statchg), 152 153 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 154 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 155 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 156 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 157 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 158 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 159 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 160 161 DEVMETHOD_END 162 }; 163 164 static driver_t enetc_driver = { 165 "enetc", enetc_methods, sizeof(struct enetc_softc) 166 }; 167 168 static devclass_t enetc_devclass; 169 DRIVER_MODULE(miibus, enetc, miibus_fdt_driver, miibus_fdt_devclass, NULL, NULL); 170 /* Make sure miibus gets procesed first. */ 171 DRIVER_MODULE_ORDERED(enetc, pci, enetc_driver, enetc_devclass, NULL, NULL, 172 SI_ORDER_ANY); 173 MODULE_VERSION(enetc, 1); 174 175 IFLIB_PNP_INFO(pci, enetc, enetc_vendor_info_array); 176 177 MODULE_DEPEND(enetc, ether, 1, 1, 1); 178 MODULE_DEPEND(enetc, iflib, 1, 1, 1); 179 MODULE_DEPEND(enetc, miibus, 1, 1, 1); 180 181 static device_method_t enetc_iflib_methods[] = { 182 DEVMETHOD(ifdi_attach_pre, enetc_attach_pre), 183 DEVMETHOD(ifdi_attach_post, enetc_attach_post), 184 DEVMETHOD(ifdi_detach, enetc_detach), 185 186 DEVMETHOD(ifdi_init, enetc_init), 187 DEVMETHOD(ifdi_stop, enetc_stop), 188 189 DEVMETHOD(ifdi_tx_queues_alloc, enetc_tx_queues_alloc), 190 DEVMETHOD(ifdi_rx_queues_alloc, enetc_rx_queues_alloc), 191 DEVMETHOD(ifdi_queues_free, enetc_queues_free), 192 193 DEVMETHOD(ifdi_msix_intr_assign, enetc_msix_intr_assign), 194 DEVMETHOD(ifdi_tx_queue_intr_enable, enetc_tx_queue_intr_enable), 195 DEVMETHOD(ifdi_rx_queue_intr_enable, enetc_rx_queue_intr_enable), 196 DEVMETHOD(ifdi_intr_enable, enetc_intr_enable), 197 DEVMETHOD(ifdi_intr_disable, enetc_intr_disable), 198 199 DEVMETHOD(ifdi_vlan_register, enetc_vlan_register), 200 DEVMETHOD(ifdi_vlan_unregister, enetc_vlan_unregister), 201 202 DEVMETHOD(ifdi_get_counter, enetc_get_counter), 203 DEVMETHOD(ifdi_mtu_set, enetc_mtu_set), 204 DEVMETHOD(ifdi_multi_set, enetc_setup_multicast), 205 DEVMETHOD(ifdi_promisc_set, enetc_promisc_set), 206 DEVMETHOD(ifdi_timer, enetc_timer), 207 DEVMETHOD(ifdi_update_admin_status, enetc_update_admin_status), 208 209 DEVMETHOD_END 210 }; 211 212 static driver_t enetc_iflib_driver = { 213 "enetc", enetc_iflib_methods, sizeof(struct enetc_softc) 214 }; 215 216 static struct if_txrx enetc_txrx = { 217 .ift_txd_encap = enetc_isc_txd_encap, 218 .ift_txd_flush = enetc_isc_txd_flush, 219 .ift_txd_credits_update = enetc_isc_txd_credits_update, 220 .ift_rxd_available = enetc_isc_rxd_available, 221 .ift_rxd_pkt_get = enetc_isc_rxd_pkt_get, 222 .ift_rxd_refill = enetc_isc_rxd_refill, 223 .ift_rxd_flush = enetc_isc_rxd_flush 224 }; 225 226 static struct if_shared_ctx enetc_sctx_init = { 227 .isc_magic = IFLIB_MAGIC, 228 229 .isc_q_align = ENETC_RING_ALIGN, 230 231 .isc_tx_maxsize = ENETC_MAX_FRAME_LEN, 232 .isc_tx_maxsegsize = PAGE_SIZE, 233 234 .isc_rx_maxsize = ENETC_MAX_FRAME_LEN, 235 .isc_rx_maxsegsize = ENETC_MAX_FRAME_LEN, 236 .isc_rx_nsegments = ENETC_MAX_SCATTER, 237 238 .isc_admin_intrcnt = 0, 239 240 .isc_nfl = 1, 241 .isc_nrxqs = 1, 242 .isc_ntxqs = 1, 243 244 .isc_vendor_info = enetc_vendor_info_array, 245 .isc_driver_version = enetc_driver_version, 246 .isc_driver = &enetc_iflib_driver, 247 248 .isc_flags = IFLIB_DRIVER_MEDIA | IFLIB_PRESERVE_TX_INDICES, 249 .isc_ntxd_min = {ENETC_MIN_DESC}, 250 .isc_ntxd_max = {ENETC_MAX_DESC}, 251 .isc_ntxd_default = {ENETC_DEFAULT_DESC}, 252 .isc_nrxd_min = {ENETC_MIN_DESC}, 253 .isc_nrxd_max = {ENETC_MAX_DESC}, 254 .isc_nrxd_default = {ENETC_DEFAULT_DESC} 255 }; 256 257 static void* 258 enetc_register(device_t dev) 259 { 260 261 if (!ofw_bus_status_okay(dev)) 262 return (NULL); 263 264 return (&enetc_sctx_init); 265 } 266 267 static void 268 enetc_max_nqueues(struct enetc_softc *sc, int *max_tx_nqueues, 269 int *max_rx_nqueues) 270 { 271 uint32_t val; 272 273 val = ENETC_PORT_RD4(sc, ENETC_PCAPR0); 274 *max_tx_nqueues = MIN(ENETC_PCAPR0_TXBDR(val), ENETC_MAX_QUEUES); 275 *max_rx_nqueues = MIN(ENETC_PCAPR0_RXBDR(val), ENETC_MAX_QUEUES); 276 } 277 278 static int 279 enetc_setup_fixed(struct enetc_softc *sc, phandle_t node) 280 { 281 ssize_t size; 282 int speed; 283 284 size = OF_getencprop(node, "speed", &speed, sizeof(speed)); 285 if (size <= 0) { 286 device_printf(sc->dev, 287 "Device has fixed-link node without link speed specified\n"); 288 return (ENXIO); 289 } 290 switch (speed) { 291 case 10: 292 speed = IFM_10_T; 293 break; 294 case 100: 295 speed = IFM_100_TX; 296 break; 297 case 1000: 298 speed = IFM_1000_T; 299 break; 300 case 2500: 301 speed = IFM_2500_T; 302 break; 303 default: 304 device_printf(sc->dev, "Unsupported link speed value of %d\n", 305 speed); 306 return (ENXIO); 307 } 308 speed |= IFM_ETHER; 309 310 if (OF_hasprop(node, "full-duplex")) 311 speed |= IFM_FDX; 312 else 313 speed |= IFM_HDX; 314 315 sc->fixed_link = true; 316 317 ifmedia_init(&sc->fixed_ifmedia, 0, enetc_fixed_media_change, 318 enetc_fixed_media_status); 319 ifmedia_add(&sc->fixed_ifmedia, speed, 0, NULL); 320 ifmedia_set(&sc->fixed_ifmedia, speed); 321 sc->shared->isc_media = &sc->fixed_ifmedia; 322 323 return (0); 324 } 325 326 static int 327 enetc_setup_phy(struct enetc_softc *sc) 328 { 329 phandle_t node, fixed_link, phy_handle; 330 struct mii_data *miid; 331 int phy_addr, error; 332 ssize_t size; 333 334 node = ofw_bus_get_node(sc->dev); 335 fixed_link = ofw_bus_find_child(node, "fixed-link"); 336 if (fixed_link != 0) 337 return (enetc_setup_fixed(sc, fixed_link)); 338 339 size = OF_getencprop(node, "phy-handle", &phy_handle, sizeof(phy_handle)); 340 if (size <= 0) { 341 device_printf(sc->dev, 342 "Failed to acquire PHY handle from FDT.\n"); 343 return (ENXIO); 344 } 345 phy_handle = OF_node_from_xref(phy_handle); 346 size = OF_getencprop(phy_handle, "reg", &phy_addr, sizeof(phy_addr)); 347 if (size <= 0) { 348 device_printf(sc->dev, "Failed to obtain PHY address\n"); 349 return (ENXIO); 350 } 351 error = mii_attach(sc->dev, &sc->miibus, iflib_get_ifp(sc->ctx), 352 enetc_media_change, enetc_media_status, 353 BMSR_DEFCAPMASK, phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 354 if (error != 0) { 355 device_printf(sc->dev, "mii_attach failed\n"); 356 return (error); 357 } 358 miid = device_get_softc(sc->miibus); 359 sc->shared->isc_media = &miid->mii_media; 360 361 return (0); 362 } 363 364 static int 365 enetc_attach_pre(if_ctx_t ctx) 366 { 367 if_softc_ctx_t scctx; 368 struct enetc_softc *sc; 369 int error, rid; 370 371 sc = iflib_get_softc(ctx); 372 scctx = iflib_get_softc_ctx(ctx); 373 sc->ctx = ctx; 374 sc->dev = iflib_get_dev(ctx); 375 sc->shared = scctx; 376 377 mtx_init(&sc->mii_lock, "enetc_mdio", NULL, MTX_DEF); 378 379 pci_save_state(sc->dev); 380 pcie_flr(sc->dev, 1000, false); 381 pci_restore_state(sc->dev); 382 383 rid = PCIR_BAR(ENETC_BAR_REGS); 384 sc->regs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 385 if (sc->regs == NULL) { 386 device_printf(sc->dev, 387 "Failed to allocate BAR %d\n", ENETC_BAR_REGS); 388 return (ENXIO); 389 } 390 391 error = iflib_dma_alloc_align(ctx, 392 ENETC_MIN_DESC * sizeof(struct enetc_cbd), 393 ENETC_RING_ALIGN, 394 &sc->ctrl_queue.dma, 395 0); 396 if (error != 0) { 397 device_printf(sc->dev, "Failed to allocate control ring\n"); 398 goto fail; 399 } 400 sc->ctrl_queue.ring = (struct enetc_cbd*)sc->ctrl_queue.dma.idi_vaddr; 401 402 scctx->isc_txrx = &enetc_txrx; 403 scctx->isc_tx_nsegments = ENETC_MAX_SCATTER; 404 enetc_max_nqueues(sc, &scctx->isc_nrxqsets_max, &scctx->isc_ntxqsets_max); 405 406 if (scctx->isc_ntxd[0] % ENETC_DESC_ALIGN != 0) { 407 device_printf(sc->dev, 408 "The number of TX descriptors has to be a multiple of %d\n", 409 ENETC_DESC_ALIGN); 410 error = EINVAL; 411 goto fail; 412 } 413 if (scctx->isc_nrxd[0] % ENETC_DESC_ALIGN != 0) { 414 device_printf(sc->dev, 415 "The number of RX descriptors has to be a multiple of %d\n", 416 ENETC_DESC_ALIGN); 417 error = EINVAL; 418 goto fail; 419 } 420 scctx->isc_txqsizes[0] = scctx->isc_ntxd[0] * sizeof(union enetc_tx_bd); 421 scctx->isc_rxqsizes[0] = scctx->isc_nrxd[0] * sizeof(union enetc_rx_bd); 422 scctx->isc_txd_size[0] = sizeof(union enetc_tx_bd); 423 scctx->isc_rxd_size[0] = sizeof(union enetc_rx_bd); 424 scctx->isc_tx_csum_flags = 0; 425 scctx->isc_capabilities = scctx->isc_capenable = ENETC_IFCAPS; 426 427 error = enetc_mtu_set(ctx, ETHERMTU); 428 if (error != 0) 429 goto fail; 430 431 scctx->isc_msix_bar = pci_msix_table_bar(sc->dev); 432 433 error = enetc_setup_phy(sc); 434 if (error != 0) 435 goto fail; 436 437 enetc_get_hwaddr(sc); 438 439 return (0); 440 fail: 441 enetc_detach(ctx); 442 return (error); 443 } 444 445 static int 446 enetc_attach_post(if_ctx_t ctx) 447 { 448 449 enetc_init_hw(iflib_get_softc(ctx)); 450 return (0); 451 } 452 453 static int 454 enetc_detach(if_ctx_t ctx) 455 { 456 struct enetc_softc *sc; 457 int error = 0, i; 458 459 sc = iflib_get_softc(ctx); 460 461 for (i = 0; i < sc->rx_num_queues; i++) 462 iflib_irq_free(ctx, &sc->rx_queues[i].irq); 463 464 if (sc->miibus != NULL) 465 device_delete_child(sc->dev, sc->miibus); 466 467 if (sc->regs != NULL) 468 error = bus_release_resource(sc->dev, SYS_RES_MEMORY, 469 rman_get_rid(sc->regs), sc->regs); 470 471 if (sc->ctrl_queue.dma.idi_size != 0) 472 iflib_dma_free(&sc->ctrl_queue.dma); 473 474 mtx_destroy(&sc->mii_lock); 475 476 return (error); 477 } 478 479 static int 480 enetc_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 481 int ntxqs, int ntxqsets) 482 { 483 struct enetc_softc *sc; 484 struct enetc_tx_queue *queue; 485 int i; 486 487 sc = iflib_get_softc(ctx); 488 489 MPASS(ntxqs == 1); 490 491 sc->tx_queues = mallocarray(sc->tx_num_queues, 492 sizeof(struct enetc_tx_queue), M_DEVBUF, M_NOWAIT | M_ZERO); 493 if (sc->tx_queues == NULL) { 494 device_printf(sc->dev, 495 "Failed to allocate memory for TX queues.\n"); 496 return (ENOMEM); 497 } 498 499 for (i = 0; i < sc->tx_num_queues; i++) { 500 queue = &sc->tx_queues[i]; 501 queue->sc = sc; 502 queue->ring = (union enetc_tx_bd*)(vaddrs[i]); 503 queue->ring_paddr = paddrs[i]; 504 queue->cidx = 0; 505 } 506 507 return (0); 508 } 509 510 static int 511 enetc_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 512 int nrxqs, int nrxqsets) 513 { 514 struct enetc_softc *sc; 515 struct enetc_rx_queue *queue; 516 int i; 517 518 sc = iflib_get_softc(ctx); 519 MPASS(nrxqs == 1); 520 521 sc->rx_queues = mallocarray(sc->rx_num_queues, 522 sizeof(struct enetc_rx_queue), M_DEVBUF, M_NOWAIT | M_ZERO); 523 if (sc->rx_queues == NULL) { 524 device_printf(sc->dev, 525 "Failed to allocate memory for RX queues.\n"); 526 return (ENOMEM); 527 } 528 529 for (i = 0; i < sc->rx_num_queues; i++) { 530 queue = &sc->rx_queues[i]; 531 queue->sc = sc; 532 queue->qid = i; 533 queue->ring = (union enetc_rx_bd*)(vaddrs[i]); 534 queue->ring_paddr = paddrs[i]; 535 } 536 537 return (0); 538 } 539 540 static void 541 enetc_queues_free(if_ctx_t ctx) 542 { 543 struct enetc_softc *sc; 544 545 sc = iflib_get_softc(ctx); 546 547 if (sc->tx_queues != NULL) { 548 free(sc->tx_queues, M_DEVBUF); 549 sc->tx_queues = NULL; 550 } 551 if (sc->rx_queues != NULL) { 552 free(sc->rx_queues, M_DEVBUF); 553 sc->rx_queues = NULL; 554 } 555 } 556 557 static void 558 enetc_get_hwaddr(struct enetc_softc *sc) 559 { 560 struct ether_addr hwaddr; 561 uint16_t high; 562 uint32_t low; 563 564 low = ENETC_PORT_RD4(sc, ENETC_PSIPMAR0(0)); 565 high = ENETC_PORT_RD2(sc, ENETC_PSIPMAR1(0)); 566 567 memcpy(&hwaddr.octet[0], &low, 4); 568 memcpy(&hwaddr.octet[4], &high, 2); 569 570 if (ETHER_IS_BROADCAST(hwaddr.octet) || 571 ETHER_IS_MULTICAST(hwaddr.octet) || 572 ETHER_IS_ZERO(hwaddr.octet)) { 573 ether_gen_addr(iflib_get_ifp(sc->ctx), &hwaddr); 574 device_printf(sc->dev, 575 "Failed to obtain MAC address, using a random one\n"); 576 memcpy(&low, &hwaddr.octet[0], 4); 577 memcpy(&high, &hwaddr.octet[4], 2); 578 } 579 580 iflib_set_mac(sc->ctx, hwaddr.octet); 581 } 582 583 static void 584 enetc_set_hwaddr(struct enetc_softc *sc) 585 { 586 struct ifnet *ifp; 587 uint16_t high; 588 uint32_t low; 589 uint8_t *hwaddr; 590 591 ifp = iflib_get_ifp(sc->ctx); 592 hwaddr = (uint8_t*)if_getlladdr(ifp); 593 low = *((uint32_t*)hwaddr); 594 high = *((uint16_t*)(hwaddr+4)); 595 596 ENETC_PORT_WR4(sc, ENETC_PSIPMAR0(0), low); 597 ENETC_PORT_WR2(sc, ENETC_PSIPMAR1(0), high); 598 } 599 600 static int 601 enetc_setup_rss(struct enetc_softc *sc) 602 { 603 struct iflib_dma_info dma; 604 int error, i, buckets_num = 0; 605 uint8_t *rss_table; 606 uint32_t reg; 607 608 reg = ENETC_RD4(sc, ENETC_SIPCAPR0); 609 if (reg & ENETC_SIPCAPR0_RSS) { 610 reg = ENETC_RD4(sc, ENETC_SIRSSCAPR); 611 buckets_num = ENETC_SIRSSCAPR_GET_NUM_RSS(reg); 612 } 613 if (buckets_num == 0) 614 return (ENOTSUP); 615 616 for (i = 0; i < ENETC_RSSHASH_KEY_SIZE / sizeof(uint32_t); i++) { 617 arc4rand((uint8_t *)®, sizeof(reg), 0); 618 ENETC_PORT_WR4(sc, ENETC_PRSSK(i), reg); 619 } 620 621 ENETC_WR4(sc, ENETC_SIRBGCR, sc->rx_num_queues); 622 623 error = iflib_dma_alloc_align(sc->ctx, 624 buckets_num * sizeof(*rss_table), 625 ENETC_RING_ALIGN, 626 &dma, 627 0); 628 if (error != 0) { 629 device_printf(sc->dev, "Failed to allocate DMA buffer for RSS\n"); 630 return (error); 631 } 632 rss_table = (uint8_t *)dma.idi_vaddr; 633 634 for (i = 0; i < buckets_num; i++) 635 rss_table[i] = i % sc->rx_num_queues; 636 637 error = enetc_ctrl_send(sc, (BDCR_CMD_RSS << 8) | BDCR_CMD_RSS_WRITE, 638 buckets_num * sizeof(*rss_table), &dma); 639 if (error != 0) 640 device_printf(sc->dev, "Failed to setup RSS table\n"); 641 642 iflib_dma_free(&dma); 643 644 return (error); 645 } 646 647 static int 648 enetc_ctrl_send(struct enetc_softc *sc, uint16_t cmd, uint16_t size, 649 iflib_dma_info_t dma) 650 { 651 struct enetc_ctrl_queue *queue; 652 struct enetc_cbd *desc; 653 int timeout = 1000; 654 655 queue = &sc->ctrl_queue; 656 desc = &queue->ring[queue->pidx]; 657 658 if (++queue->pidx == ENETC_MIN_DESC) 659 queue->pidx = 0; 660 661 desc->addr[0] = (uint32_t)dma->idi_paddr; 662 desc->addr[1] = (uint32_t)(dma->idi_paddr >> 32); 663 desc->index = 0; 664 desc->length = (uint16_t)size; 665 desc->cmd = (uint8_t)cmd; 666 desc->cls = (uint8_t)(cmd >> 8); 667 desc->status_flags = 0; 668 669 /* Sync command packet, */ 670 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_PREWRITE); 671 /* and the control ring. */ 672 bus_dmamap_sync(queue->dma.idi_tag, queue->dma.idi_map, BUS_DMASYNC_PREWRITE); 673 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx); 674 675 while (--timeout != 0) { 676 DELAY(20); 677 if (ENETC_RD4(sc, ENETC_SICBDRCIR) == queue->pidx) 678 break; 679 } 680 681 if (timeout == 0) 682 return (ETIMEDOUT); 683 684 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_POSTREAD); 685 return (0); 686 } 687 688 static void 689 enetc_init_hw(struct enetc_softc *sc) 690 { 691 uint32_t val; 692 int error; 693 694 ENETC_PORT_WR4(sc, ENETC_PM0_CMD_CFG, 695 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC | 696 ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 697 ENETC_PORT_WR4(sc, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); 698 val = ENETC_PSICFGR0_SET_TXBDR(sc->tx_num_queues); 699 val |= ENETC_PSICFGR0_SET_RXBDR(sc->rx_num_queues); 700 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 701 ENETC_PORT_WR4(sc, ENETC_PSICFGR0(0), val); 702 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VUTA(1)); 703 ENETC_PORT_WR4(sc, ENETC_PVCLCTR, ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 704 ENETC_PORT_WR4(sc, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); 705 ENETC_PORT_WR4(sc, ENETC_PAR_PORT_CFG, ENETC_PAR_PORT_L4CD); 706 ENETC_PORT_WR4(sc, ENETC_PMR, ENETC_PMR_SI0EN | ENETC_PMR_PSPEED_1000M); 707 708 ENETC_WR4(sc, ENETC_SICAR0, 709 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 710 ENETC_WR4(sc, ENETC_SICAR1, ENETC_SICAR_MSI); 711 ENETC_WR4(sc, ENETC_SICAR2, 712 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 713 714 enetc_init_ctrl(sc); 715 error = enetc_setup_rss(sc); 716 if (error != 0) 717 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN); 718 else 719 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN | ENETC_SIMR_RSSE); 720 721 } 722 723 static void 724 enetc_init_ctrl(struct enetc_softc *sc) 725 { 726 struct enetc_ctrl_queue *queue = &sc->ctrl_queue; 727 728 ENETC_WR4(sc, ENETC_SICBDRBAR0, 729 (uint32_t)queue->dma.idi_paddr); 730 ENETC_WR4(sc, ENETC_SICBDRBAR1, 731 (uint32_t)(queue->dma.idi_paddr >> 32)); 732 ENETC_WR4(sc, ENETC_SICBDRLENR, 733 queue->dma.idi_size / sizeof(struct enetc_cbd)); 734 735 queue->pidx = 0; 736 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx); 737 ENETC_WR4(sc, ENETC_SICBDRCIR, queue->pidx); 738 ENETC_WR4(sc, ENETC_SICBDRMR, ENETC_SICBDRMR_EN); 739 } 740 741 static void 742 enetc_init_tx(struct enetc_softc *sc) 743 { 744 struct enetc_tx_queue *queue; 745 int i; 746 747 for (i = 0; i < sc->tx_num_queues; i++) { 748 queue = &sc->tx_queues[i]; 749 750 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR0, 751 (uint32_t)queue->ring_paddr); 752 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR1, 753 (uint32_t)(queue->ring_paddr >> 32)); 754 ENETC_TXQ_WR4(sc, i, ENETC_TBLENR, sc->tx_queue_size); 755 756 /* 757 * Even though it is undoccumented resetting the TX ring 758 * indices results in TX hang. 759 * Do the same as Linux and simply keep those unchanged 760 * for the drivers lifetime. 761 */ 762 #if 0 763 ENETC_TXQ_WR4(sc, i, ENETC_TBPIR, 0); 764 ENETC_TXQ_WR4(sc, i, ENETC_TBCIR, 0); 765 #endif 766 ENETC_TXQ_WR4(sc, i, ENETC_TBMR, ENETC_TBMR_EN); 767 } 768 769 } 770 771 static void 772 enetc_init_rx(struct enetc_softc *sc) 773 { 774 struct enetc_rx_queue *queue; 775 uint32_t rx_buf_size; 776 int i; 777 778 rx_buf_size = iflib_get_rx_mbuf_sz(sc->ctx); 779 780 for (i = 0; i < sc->rx_num_queues; i++) { 781 queue = &sc->rx_queues[i]; 782 783 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR0, 784 (uint32_t)queue->ring_paddr); 785 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR1, 786 (uint32_t)(queue->ring_paddr >> 32)); 787 ENETC_RXQ_WR4(sc, i, ENETC_RBLENR, sc->rx_queue_size); 788 ENETC_RXQ_WR4(sc, i, ENETC_RBBSR, rx_buf_size); 789 ENETC_RXQ_WR4(sc, i, ENETC_RBPIR, 0); 790 ENETC_RXQ_WR4(sc, i, ENETC_RBCIR, 0); 791 queue->enabled = false; 792 } 793 } 794 795 static u_int 796 enetc_hash_mac(void *arg, struct sockaddr_dl *sdl, u_int cnt) 797 { 798 uint64_t *bitmap = arg; 799 uint64_t address = 0; 800 uint8_t hash = 0; 801 bool bit; 802 int i, j; 803 804 bcopy(LLADDR(sdl), &address, ETHER_ADDR_LEN); 805 806 /* 807 * The six bit hash is calculated by xoring every 808 * 6th bit of the address. 809 * It is then used as an index in a bitmap that is 810 * written to the device. 811 */ 812 for (i = 0; i < 6; i++) { 813 bit = 0; 814 for (j = 0; j < 8; j++) 815 bit ^= !!(address & BIT(i + j*6)); 816 817 hash |= bit << i; 818 } 819 820 *bitmap |= (1 << hash); 821 return (1); 822 } 823 824 static void 825 enetc_setup_multicast(if_ctx_t ctx) 826 { 827 struct enetc_softc *sc; 828 struct ifnet *ifp; 829 uint64_t bitmap = 0; 830 uint8_t revid; 831 832 sc = iflib_get_softc(ctx); 833 ifp = iflib_get_ifp(ctx); 834 revid = pci_get_revid(sc->dev); 835 836 if_foreach_llmaddr(ifp, enetc_hash_mac, &bitmap); 837 838 /* 839 * In revid 1 of this chip the positions multicast and unicast 840 * hash filter registers are flipped. 841 */ 842 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR0(0, revid == 1), bitmap & UINT32_MAX); 843 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR1(0), bitmap >> 32); 844 845 } 846 847 static uint8_t 848 enetc_hash_vid(uint16_t vid) 849 { 850 uint8_t hash = 0; 851 bool bit; 852 int i; 853 854 for (i = 0;i < 6;i++) { 855 bit = vid & BIT(i); 856 bit ^= !!(vid & BIT(i + 6)); 857 hash |= bit << i; 858 } 859 860 return (hash); 861 } 862 863 static void 864 enetc_vlan_register(if_ctx_t ctx, uint16_t vid) 865 { 866 struct enetc_softc *sc; 867 uint8_t hash; 868 uint64_t bitmap; 869 870 sc = iflib_get_softc(ctx); 871 hash = enetc_hash_vid(vid); 872 873 /* Check if hash is alredy present in the bitmap. */ 874 if (++sc->vlan_bitmap[hash] != 1) 875 return; 876 877 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0)); 878 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32; 879 bitmap |= BIT(hash); 880 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX); 881 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32); 882 } 883 884 static void 885 enetc_vlan_unregister(if_ctx_t ctx, uint16_t vid) 886 { 887 struct enetc_softc *sc; 888 uint8_t hash; 889 uint64_t bitmap; 890 891 sc = iflib_get_softc(ctx); 892 hash = enetc_hash_vid(vid); 893 894 MPASS(sc->vlan_bitmap[hash] > 0); 895 if (--sc->vlan_bitmap[hash] != 0) 896 return; 897 898 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0)); 899 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32; 900 bitmap &= ~BIT(hash); 901 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX); 902 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32); 903 } 904 905 static void 906 enetc_init(if_ctx_t ctx) 907 { 908 struct enetc_softc *sc; 909 struct mii_data *miid; 910 struct ifnet *ifp; 911 uint16_t max_frame_length; 912 int baudrate; 913 914 sc = iflib_get_softc(ctx); 915 ifp = iflib_get_ifp(ctx); 916 917 max_frame_length = sc->shared->isc_max_frame_size; 918 MPASS(max_frame_length < ENETC_MAX_FRAME_LEN); 919 920 /* Set max RX and TX frame lengths. */ 921 ENETC_PORT_WR4(sc, ENETC_PM0_MAXFRM, max_frame_length); 922 ENETC_PORT_WR4(sc, ENETC_PTCMSDUR(0), max_frame_length); 923 ENETC_PORT_WR4(sc, ENETC_PTXMBAR, 2 * max_frame_length); 924 925 /* Set "VLAN promiscious" mode if filtering is disabled. */ 926 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) 927 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, 928 ENETC_PSIPVMR_SET_VUTA(1) | ENETC_PSIPVMR_SET_VP(1)); 929 else 930 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, 931 ENETC_PSIPVMR_SET_VUTA(1)); 932 933 sc->rbmr = ENETC_RBMR_EN; 934 935 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 936 sc->rbmr |= ENETC_RBMR_VTE; 937 938 /* Write MAC address to hardware. */ 939 enetc_set_hwaddr(sc); 940 941 enetc_init_tx(sc); 942 enetc_init_rx(sc); 943 944 if (sc->fixed_link) { 945 baudrate = ifmedia_baudrate(sc->fixed_ifmedia.ifm_cur->ifm_media); 946 iflib_link_state_change(sc->ctx, LINK_STATE_UP, baudrate); 947 } else { 948 /* 949 * Can't return an error from this function, there is not much 950 * we can do if this fails. 951 */ 952 miid = device_get_softc(sc->miibus); 953 (void)mii_mediachg(miid); 954 } 955 956 enetc_promisc_set(ctx, if_getflags(ifp)); 957 } 958 959 static void 960 enetc_disable_txq(struct enetc_softc *sc, int qid) 961 { 962 qidx_t cidx, pidx; 963 int timeout = 10000; /* this * DELAY(100) = 1s */ 964 965 /* At this point iflib shouldn't be enquing any more frames. */ 966 pidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBPIR); 967 cidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR); 968 969 while (pidx != cidx && timeout--) { 970 DELAY(100); 971 cidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR); 972 } 973 974 if (timeout == 0) 975 device_printf(sc->dev, 976 "Timeout while waiting for txq%d to stop transmitting packets\n", 977 qid); 978 979 ENETC_TXQ_WR4(sc, qid, ENETC_TBMR, 0); 980 } 981 982 static void 983 enetc_stop(if_ctx_t ctx) 984 { 985 struct enetc_softc *sc; 986 int i; 987 988 sc = iflib_get_softc(ctx); 989 990 for (i = 0; i < sc->rx_num_queues; i++) 991 ENETC_RXQ_WR4(sc, i, ENETC_RBMR, 0); 992 993 for (i = 0; i < sc->tx_num_queues; i++) 994 enetc_disable_txq(sc, i); 995 } 996 997 static int 998 enetc_msix_intr_assign(if_ctx_t ctx, int msix) 999 { 1000 struct enetc_softc *sc; 1001 struct enetc_rx_queue *rx_queue; 1002 struct enetc_tx_queue *tx_queue; 1003 int vector = 0, i, error; 1004 char irq_name[16]; 1005 1006 sc = iflib_get_softc(ctx); 1007 1008 MPASS(sc->rx_num_queues + 1 <= ENETC_MSIX_COUNT); 1009 MPASS(sc->rx_num_queues == sc->tx_num_queues); 1010 1011 for (i = 0; i < sc->rx_num_queues; i++, vector++) { 1012 rx_queue = &sc->rx_queues[i]; 1013 snprintf(irq_name, sizeof(irq_name), "rxtxq%d", i); 1014 error = iflib_irq_alloc_generic(ctx, 1015 &rx_queue->irq, vector + 1, IFLIB_INTR_RXTX, 1016 NULL, rx_queue, i, irq_name); 1017 if (error != 0) 1018 goto fail; 1019 1020 ENETC_WR4(sc, ENETC_SIMSIRRV(i), vector); 1021 ENETC_RXQ_WR4(sc, i, ENETC_RBICR1, ENETC_RX_INTR_TIME_THR); 1022 ENETC_RXQ_WR4(sc, i, ENETC_RBICR0, 1023 ENETC_RBICR0_ICEN | ENETC_RBICR0_SET_ICPT(ENETC_RX_INTR_PKT_THR)); 1024 } 1025 vector = 0; 1026 for (i = 0;i < sc->tx_num_queues; i++, vector++) { 1027 tx_queue = &sc->tx_queues[i]; 1028 snprintf(irq_name, sizeof(irq_name), "txq%d", i); 1029 iflib_softirq_alloc_generic(ctx, &tx_queue->irq, 1030 IFLIB_INTR_TX, tx_queue, i, irq_name); 1031 1032 ENETC_WR4(sc, ENETC_SIMSITRV(i), vector); 1033 } 1034 1035 return (0); 1036 fail: 1037 for (i = 0; i < sc->rx_num_queues; i++) { 1038 rx_queue = &sc->rx_queues[i]; 1039 iflib_irq_free(ctx, &rx_queue->irq); 1040 } 1041 return (error); 1042 } 1043 1044 static int 1045 enetc_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 1046 { 1047 struct enetc_softc *sc; 1048 1049 sc = iflib_get_softc(ctx); 1050 ENETC_TXQ_RD4(sc, qid, ENETC_TBIDR); 1051 return (0); 1052 } 1053 1054 static int 1055 enetc_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 1056 { 1057 struct enetc_softc *sc; 1058 1059 sc = iflib_get_softc(ctx); 1060 ENETC_RXQ_RD4(sc, qid, ENETC_RBIDR); 1061 return (0); 1062 } 1063 static void 1064 enetc_intr_enable(if_ctx_t ctx) 1065 { 1066 struct enetc_softc *sc; 1067 int i; 1068 1069 sc = iflib_get_softc(ctx); 1070 1071 for (i = 0; i < sc->rx_num_queues; i++) 1072 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, ENETC_RBIER_RXTIE); 1073 1074 for (i = 0; i < sc->tx_num_queues; i++) 1075 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, ENETC_TBIER_TXF); 1076 } 1077 1078 static void 1079 enetc_intr_disable(if_ctx_t ctx) 1080 { 1081 struct enetc_softc *sc; 1082 int i; 1083 1084 sc = iflib_get_softc(ctx); 1085 1086 for (i = 0; i < sc->rx_num_queues; i++) 1087 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, 0); 1088 1089 for (i = 0; i < sc->tx_num_queues; i++) 1090 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, 0); 1091 } 1092 1093 static int 1094 enetc_isc_txd_encap(void *data, if_pkt_info_t ipi) 1095 { 1096 struct enetc_softc *sc = data; 1097 struct enetc_tx_queue *queue; 1098 union enetc_tx_bd *desc; 1099 bus_dma_segment_t *segs; 1100 qidx_t pidx, queue_len; 1101 qidx_t i = 0; 1102 1103 queue = &sc->tx_queues[ipi->ipi_qsidx]; 1104 segs = ipi->ipi_segs; 1105 pidx = ipi->ipi_pidx; 1106 queue_len = sc->tx_queue_size; 1107 1108 /* 1109 * First descriptor is special. We use it to set frame 1110 * related information and offloads, e.g. VLAN tag. 1111 */ 1112 desc = &queue->ring[pidx]; 1113 bzero(desc, sizeof(*desc)); 1114 desc->frm_len = ipi->ipi_len; 1115 desc->addr = segs[i].ds_addr; 1116 desc->buf_len = segs[i].ds_len; 1117 if (ipi->ipi_flags & IPI_TX_INTR) 1118 desc->flags = ENETC_TXBD_FLAGS_FI; 1119 1120 i++; 1121 if (++pidx == queue_len) 1122 pidx = 0; 1123 1124 if (ipi->ipi_mflags & M_VLANTAG) { 1125 /* VLAN tag is inserted in a separate descriptor. */ 1126 desc->flags |= ENETC_TXBD_FLAGS_EX; 1127 desc = &queue->ring[pidx]; 1128 bzero(desc, sizeof(*desc)); 1129 desc->ext.vid = ipi->ipi_vtag; 1130 desc->ext.e_flags = ENETC_TXBD_E_FLAGS_VLAN_INS; 1131 if (++pidx == queue_len) 1132 pidx = 0; 1133 } 1134 1135 /* Now add remaining descriptors. */ 1136 for (;i < ipi->ipi_nsegs; i++) { 1137 desc = &queue->ring[pidx]; 1138 bzero(desc, sizeof(*desc)); 1139 desc->addr = segs[i].ds_addr; 1140 desc->buf_len = segs[i].ds_len; 1141 1142 if (++pidx == queue_len) 1143 pidx = 0; 1144 } 1145 1146 desc->flags |= ENETC_TXBD_FLAGS_F; 1147 ipi->ipi_new_pidx = pidx; 1148 1149 return (0); 1150 } 1151 1152 static void 1153 enetc_isc_txd_flush(void *data, uint16_t qid, qidx_t pidx) 1154 { 1155 struct enetc_softc *sc = data; 1156 1157 ENETC_TXQ_WR4(sc, qid, ENETC_TBPIR, pidx); 1158 } 1159 1160 static int 1161 enetc_isc_txd_credits_update(void *data, uint16_t qid, bool clear) 1162 { 1163 struct enetc_softc *sc = data; 1164 struct enetc_tx_queue *queue; 1165 int cidx, hw_cidx, count; 1166 1167 queue = &sc->tx_queues[qid]; 1168 hw_cidx = ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR) & ENETC_TBCIR_IDX_MASK; 1169 cidx = queue->cidx; 1170 1171 /* 1172 * RM states that the ring can hold at most ring_size - 1 descriptors. 1173 * Thanks to that we can assume that the ring is empty if cidx == pidx. 1174 * This requirement is guaranteed implicitly by iflib as it will only 1175 * encap a new frame if we have at least nfrags + 2 descriptors available 1176 * on the ring. This driver uses at most one additional descriptor for 1177 * VLAN tag insertion. 1178 * Also RM states that the TBCIR register is only updated once all 1179 * descriptors in the chain have been processed. 1180 */ 1181 if (cidx == hw_cidx) 1182 return (0); 1183 1184 if (!clear) 1185 return (1); 1186 1187 count = hw_cidx - cidx; 1188 if (count < 0) 1189 count += sc->tx_queue_size; 1190 1191 queue->cidx = hw_cidx; 1192 1193 return (count); 1194 } 1195 1196 static int 1197 enetc_isc_rxd_available(void *data, uint16_t qid, qidx_t pidx, qidx_t budget) 1198 { 1199 struct enetc_softc *sc = data; 1200 struct enetc_rx_queue *queue; 1201 qidx_t hw_pidx, queue_len; 1202 union enetc_rx_bd *desc; 1203 int count = 0; 1204 1205 queue = &sc->rx_queues[qid]; 1206 desc = &queue->ring[pidx]; 1207 queue_len = sc->rx_queue_size; 1208 1209 if (desc->r.lstatus == 0) 1210 return (0); 1211 1212 if (budget == 1) 1213 return (1); 1214 1215 hw_pidx = ENETC_RXQ_RD4(sc, qid, ENETC_RBPIR); 1216 while (pidx != hw_pidx && count < budget) { 1217 desc = &queue->ring[pidx]; 1218 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F) 1219 count++; 1220 1221 if (++pidx == queue_len) 1222 pidx = 0; 1223 } 1224 1225 return (count); 1226 } 1227 1228 static int 1229 enetc_isc_rxd_pkt_get(void *data, if_rxd_info_t ri) 1230 { 1231 struct enetc_softc *sc = data; 1232 struct enetc_rx_queue *queue; 1233 union enetc_rx_bd *desc; 1234 uint16_t buf_len, pkt_size = 0; 1235 qidx_t cidx, queue_len; 1236 uint32_t status; 1237 int i; 1238 1239 cidx = ri->iri_cidx; 1240 queue = &sc->rx_queues[ri->iri_qsidx]; 1241 desc = &queue->ring[cidx]; 1242 status = desc->r.lstatus; 1243 queue_len = sc->rx_queue_size; 1244 1245 /* 1246 * Ready bit will be set only when all descriptors 1247 * in the chain have been processed. 1248 */ 1249 if ((status & ENETC_RXBD_LSTATUS_R) == 0) 1250 return (EAGAIN); 1251 1252 /* Pass RSS hash. */ 1253 if (status & ENETC_RXBD_FLAG_RSSV) { 1254 ri->iri_flowid = desc->r.rss_hash; 1255 ri->iri_rsstype = M_HASHTYPE_OPAQUE_HASH; 1256 } 1257 1258 /* Pass IP checksum status. */ 1259 ri->iri_csum_flags = CSUM_IP_CHECKED; 1260 if ((desc->r.parse_summary & ENETC_RXBD_PARSER_ERROR) == 0) 1261 ri->iri_csum_flags |= CSUM_IP_VALID; 1262 1263 /* Pass extracted VLAN tag. */ 1264 if (status & ENETC_RXBD_FLAG_VLAN) { 1265 ri->iri_vtag = desc->r.vlan_opt; 1266 ri->iri_flags = M_VLANTAG; 1267 } 1268 1269 for (i = 0; i < ENETC_MAX_SCATTER; i++) { 1270 buf_len = desc->r.buf_len; 1271 ri->iri_frags[i].irf_idx = cidx; 1272 ri->iri_frags[i].irf_len = buf_len; 1273 pkt_size += buf_len; 1274 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F) 1275 break; 1276 1277 if (++cidx == queue_len) 1278 cidx = 0; 1279 1280 desc = &queue->ring[cidx]; 1281 } 1282 ri->iri_nfrags = i + 1; 1283 ri->iri_len = pkt_size; 1284 1285 MPASS(desc->r.lstatus & ENETC_RXBD_LSTATUS_F); 1286 if (status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK)) 1287 return (EBADMSG); 1288 1289 return (0); 1290 } 1291 1292 static void 1293 enetc_isc_rxd_refill(void *data, if_rxd_update_t iru) 1294 { 1295 struct enetc_softc *sc = data; 1296 struct enetc_rx_queue *queue; 1297 union enetc_rx_bd *desc; 1298 qidx_t pidx, queue_len; 1299 uint64_t *paddrs; 1300 int i, count; 1301 1302 queue = &sc->rx_queues[iru->iru_qsidx]; 1303 paddrs = iru->iru_paddrs; 1304 pidx = iru->iru_pidx; 1305 count = iru->iru_count; 1306 queue_len = sc->rx_queue_size; 1307 1308 for (i = 0; i < count; i++) { 1309 desc = &queue->ring[pidx]; 1310 bzero(desc, sizeof(*desc)); 1311 1312 desc->w.addr = paddrs[i]; 1313 if (++pidx == queue_len) 1314 pidx = 0; 1315 } 1316 /* 1317 * After enabling the queue NIC will prefetch the first 1318 * 8 descriptors. It probably assumes that the RX is fully 1319 * refilled when cidx == pidx. 1320 * Enable it only if we have enough descriptors ready on the ring. 1321 */ 1322 if (!queue->enabled && pidx >= 8) { 1323 ENETC_RXQ_WR4(sc, iru->iru_qsidx, ENETC_RBMR, sc->rbmr); 1324 queue->enabled = true; 1325 } 1326 } 1327 1328 static void 1329 enetc_isc_rxd_flush(void *data, uint16_t qid, uint8_t flid, qidx_t pidx) 1330 { 1331 struct enetc_softc *sc = data; 1332 1333 ENETC_RXQ_WR4(sc, qid, ENETC_RBCIR, pidx); 1334 } 1335 1336 static uint64_t 1337 enetc_get_counter(if_ctx_t ctx, ift_counter cnt) 1338 { 1339 struct enetc_softc *sc; 1340 struct ifnet *ifp; 1341 1342 sc = iflib_get_softc(ctx); 1343 ifp = iflib_get_ifp(ctx); 1344 1345 switch (cnt) { 1346 case IFCOUNTER_IERRORS: 1347 return (ENETC_PORT_RD8(sc, ENETC_PM0_RERR)); 1348 case IFCOUNTER_OERRORS: 1349 return (ENETC_PORT_RD8(sc, ENETC_PM0_TERR)); 1350 default: 1351 return (if_get_counter_default(ifp, cnt)); 1352 } 1353 } 1354 1355 static int 1356 enetc_mtu_set(if_ctx_t ctx, uint32_t mtu) 1357 { 1358 struct enetc_softc *sc = iflib_get_softc(ctx); 1359 uint32_t max_frame_size; 1360 1361 max_frame_size = mtu + 1362 ETHER_HDR_LEN + 1363 ETHER_CRC_LEN + 1364 sizeof(struct ether_vlan_header); 1365 1366 if (max_frame_size > ENETC_MAX_FRAME_LEN) 1367 return (EINVAL); 1368 1369 sc->shared->isc_max_frame_size = max_frame_size; 1370 1371 return (0); 1372 } 1373 1374 static int 1375 enetc_promisc_set(if_ctx_t ctx, int flags) 1376 { 1377 struct enetc_softc *sc; 1378 uint32_t reg = 0; 1379 1380 sc = iflib_get_softc(ctx); 1381 1382 if (flags & IFF_PROMISC) 1383 reg = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); 1384 else if (flags & IFF_ALLMULTI) 1385 reg = ENETC_PSIPMR_SET_MP(0); 1386 1387 ENETC_PORT_WR4(sc, ENETC_PSIPMR, reg); 1388 1389 return (0); 1390 } 1391 1392 static void 1393 enetc_timer(if_ctx_t ctx, uint16_t qid) 1394 { 1395 /* 1396 * Poll PHY status. Do this only for qid 0 to save 1397 * some cycles. 1398 */ 1399 if (qid == 0) 1400 iflib_admin_intr_deferred(ctx); 1401 } 1402 1403 static void 1404 enetc_update_admin_status(if_ctx_t ctx) 1405 { 1406 struct enetc_softc *sc; 1407 struct mii_data *miid; 1408 1409 sc = iflib_get_softc(ctx); 1410 1411 if (!sc->fixed_link) { 1412 miid = device_get_softc(sc->miibus); 1413 mii_tick(miid); 1414 } 1415 } 1416 1417 static int 1418 enetc_miibus_readreg(device_t dev, int phy, int reg) 1419 { 1420 struct enetc_softc *sc; 1421 int val; 1422 1423 sc = iflib_get_softc(device_get_softc(dev)); 1424 1425 mtx_lock(&sc->mii_lock); 1426 val = enetc_mdio_read(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE, 1427 phy, reg); 1428 mtx_unlock(&sc->mii_lock); 1429 1430 return (val); 1431 } 1432 1433 static int 1434 enetc_miibus_writereg(device_t dev, int phy, int reg, int data) 1435 { 1436 struct enetc_softc *sc; 1437 int ret; 1438 1439 sc = iflib_get_softc(device_get_softc(dev)); 1440 1441 mtx_lock(&sc->mii_lock); 1442 ret = enetc_mdio_write(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE, 1443 phy, reg, data); 1444 mtx_unlock(&sc->mii_lock); 1445 1446 return (ret); 1447 } 1448 1449 static void 1450 enetc_miibus_linkchg(device_t dev) 1451 { 1452 1453 enetc_miibus_statchg(dev); 1454 } 1455 1456 static void 1457 enetc_miibus_statchg(device_t dev) 1458 { 1459 struct enetc_softc *sc; 1460 struct mii_data *miid; 1461 int link_state, baudrate; 1462 1463 sc = iflib_get_softc(device_get_softc(dev)); 1464 miid = device_get_softc(sc->miibus); 1465 1466 baudrate = ifmedia_baudrate(miid->mii_media_active); 1467 if (miid->mii_media_status & IFM_AVALID) { 1468 if (miid->mii_media_status & IFM_ACTIVE) 1469 link_state = LINK_STATE_UP; 1470 else 1471 link_state = LINK_STATE_DOWN; 1472 } else { 1473 link_state = LINK_STATE_UNKNOWN; 1474 } 1475 1476 iflib_link_state_change(sc->ctx, link_state, baudrate); 1477 1478 } 1479 1480 static int 1481 enetc_media_change(if_t ifp) 1482 { 1483 struct enetc_softc *sc; 1484 struct mii_data *miid; 1485 1486 sc = iflib_get_softc(ifp->if_softc); 1487 miid = device_get_softc(sc->miibus); 1488 1489 mii_mediachg(miid); 1490 return (0); 1491 } 1492 1493 static void 1494 enetc_media_status(if_t ifp, struct ifmediareq* ifmr) 1495 { 1496 struct enetc_softc *sc; 1497 struct mii_data *miid; 1498 1499 sc = iflib_get_softc(ifp->if_softc); 1500 miid = device_get_softc(sc->miibus); 1501 1502 mii_pollstat(miid); 1503 1504 ifmr->ifm_active = miid->mii_media_active; 1505 ifmr->ifm_status = miid->mii_media_status; 1506 } 1507 1508 static int 1509 enetc_fixed_media_change(if_t ifp) 1510 { 1511 1512 if_printf(ifp, "Can't change media in fixed-link mode.\n"); 1513 return (0); 1514 } 1515 static void 1516 enetc_fixed_media_status(if_t ifp, struct ifmediareq* ifmr) 1517 { 1518 struct enetc_softc *sc; 1519 1520 sc = iflib_get_softc(ifp->if_softc); 1521 1522 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1523 ifmr->ifm_active = sc->fixed_ifmedia.ifm_cur->ifm_media; 1524 return; 1525 } 1526