1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2021 Alstom Group. 5 * Copyright (c) 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/rman.h> 37 #include <sys/socket.h> 38 #include <sys/sockio.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 43 #include <net/ethernet.h> 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_var.h> 47 #include <net/if_types.h> 48 #include <net/if_media.h> 49 #include <net/iflib.h> 50 51 #include <dev/enetc/enetc_hw.h> 52 #include <dev/enetc/enetc.h> 53 #include <dev/enetc/enetc_mdio.h> 54 #include <dev/mii/mii.h> 55 #include <dev/mii/miivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 62 #include "ifdi_if.h" 63 #include "miibus_if.h" 64 65 static device_register_t enetc_register; 66 67 static ifdi_attach_pre_t enetc_attach_pre; 68 static ifdi_attach_post_t enetc_attach_post; 69 static ifdi_detach_t enetc_detach; 70 71 static ifdi_tx_queues_alloc_t enetc_tx_queues_alloc; 72 static ifdi_rx_queues_alloc_t enetc_rx_queues_alloc; 73 static ifdi_queues_free_t enetc_queues_free; 74 75 static ifdi_init_t enetc_init; 76 static ifdi_stop_t enetc_stop; 77 78 static ifdi_msix_intr_assign_t enetc_msix_intr_assign; 79 static ifdi_tx_queue_intr_enable_t enetc_tx_queue_intr_enable; 80 static ifdi_rx_queue_intr_enable_t enetc_rx_queue_intr_enable; 81 static ifdi_intr_enable_t enetc_intr_enable; 82 static ifdi_intr_disable_t enetc_intr_disable; 83 84 static int enetc_isc_txd_encap(void*, if_pkt_info_t); 85 static void enetc_isc_txd_flush(void*, uint16_t, qidx_t); 86 static int enetc_isc_txd_credits_update(void*, uint16_t, bool); 87 static int enetc_isc_rxd_available(void*, uint16_t, qidx_t, qidx_t); 88 static int enetc_isc_rxd_pkt_get(void*, if_rxd_info_t); 89 static void enetc_isc_rxd_refill(void*, if_rxd_update_t); 90 static void enetc_isc_rxd_flush(void*, uint16_t, uint8_t, qidx_t); 91 92 static void enetc_vlan_register(if_ctx_t, uint16_t); 93 static void enetc_vlan_unregister(if_ctx_t, uint16_t); 94 95 static uint64_t enetc_get_counter(if_ctx_t, ift_counter); 96 static int enetc_promisc_set(if_ctx_t, int); 97 static int enetc_mtu_set(if_ctx_t, uint32_t); 98 static void enetc_setup_multicast(if_ctx_t); 99 static void enetc_timer(if_ctx_t, uint16_t); 100 static void enetc_update_admin_status(if_ctx_t); 101 102 static miibus_readreg_t enetc_miibus_readreg; 103 static miibus_writereg_t enetc_miibus_writereg; 104 static miibus_linkchg_t enetc_miibus_linkchg; 105 static miibus_statchg_t enetc_miibus_statchg; 106 107 static int enetc_media_change(if_t); 108 static void enetc_media_status(if_t, struct ifmediareq*); 109 110 static int enetc_fixed_media_change(if_t); 111 static void enetc_fixed_media_status(if_t, struct ifmediareq*); 112 113 static void enetc_max_nqueues(struct enetc_softc*, int*, int*); 114 static int enetc_setup_phy(struct enetc_softc*); 115 116 static void enetc_get_hwaddr(struct enetc_softc*); 117 static void enetc_set_hwaddr(struct enetc_softc*); 118 static int enetc_setup_rss(struct enetc_softc*); 119 120 static void enetc_init_hw(struct enetc_softc*); 121 static void enetc_init_ctrl(struct enetc_softc*); 122 static void enetc_init_tx(struct enetc_softc*); 123 static void enetc_init_rx(struct enetc_softc*); 124 125 static int enetc_ctrl_send(struct enetc_softc*, 126 uint16_t, uint16_t, iflib_dma_info_t); 127 128 static const char enetc_driver_version[] = "1.0.0"; 129 130 static pci_vendor_info_t enetc_vendor_info_array[] = { 131 PVID(PCI_VENDOR_FREESCALE, ENETC_DEV_ID_PF, 132 "Freescale ENETC PCIe Gigabit Ethernet Controller"), 133 PVID_END 134 }; 135 136 #define ENETC_IFCAPS (IFCAP_VLAN_MTU | IFCAP_RXCSUM | IFCAP_JUMBO_MTU | \ 137 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER) 138 139 static device_method_t enetc_methods[] = { 140 DEVMETHOD(device_register, enetc_register), 141 DEVMETHOD(device_probe, iflib_device_probe), 142 DEVMETHOD(device_attach, iflib_device_attach), 143 DEVMETHOD(device_detach, iflib_device_detach), 144 DEVMETHOD(device_shutdown, iflib_device_shutdown), 145 DEVMETHOD(device_suspend, iflib_device_suspend), 146 DEVMETHOD(device_resume, iflib_device_resume), 147 148 DEVMETHOD(miibus_readreg, enetc_miibus_readreg), 149 DEVMETHOD(miibus_writereg, enetc_miibus_writereg), 150 DEVMETHOD(miibus_linkchg, enetc_miibus_linkchg), 151 DEVMETHOD(miibus_statchg, enetc_miibus_statchg), 152 153 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 154 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 155 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 156 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 157 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 158 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 159 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 160 161 DEVMETHOD_END 162 }; 163 164 static driver_t enetc_driver = { 165 "enetc", enetc_methods, sizeof(struct enetc_softc) 166 }; 167 168 static devclass_t enetc_devclass; 169 DRIVER_MODULE(miibus, enetc, miibus_fdt_driver, miibus_fdt_devclass, NULL, NULL); 170 /* Make sure miibus gets procesed first. */ 171 DRIVER_MODULE_ORDERED(enetc, pci, enetc_driver, enetc_devclass, NULL, NULL, 172 SI_ORDER_ANY); 173 MODULE_VERSION(enetc, 1); 174 175 IFLIB_PNP_INFO(pci, enetc, enetc_vendor_info_array); 176 177 MODULE_DEPEND(enetc, ether, 1, 1, 1); 178 MODULE_DEPEND(enetc, iflib, 1, 1, 1); 179 MODULE_DEPEND(enetc, miibus, 1, 1, 1); 180 181 static device_method_t enetc_iflib_methods[] = { 182 DEVMETHOD(ifdi_attach_pre, enetc_attach_pre), 183 DEVMETHOD(ifdi_attach_post, enetc_attach_post), 184 DEVMETHOD(ifdi_detach, enetc_detach), 185 186 DEVMETHOD(ifdi_init, enetc_init), 187 DEVMETHOD(ifdi_stop, enetc_stop), 188 189 DEVMETHOD(ifdi_tx_queues_alloc, enetc_tx_queues_alloc), 190 DEVMETHOD(ifdi_rx_queues_alloc, enetc_rx_queues_alloc), 191 DEVMETHOD(ifdi_queues_free, enetc_queues_free), 192 193 DEVMETHOD(ifdi_msix_intr_assign, enetc_msix_intr_assign), 194 DEVMETHOD(ifdi_tx_queue_intr_enable, enetc_tx_queue_intr_enable), 195 DEVMETHOD(ifdi_rx_queue_intr_enable, enetc_rx_queue_intr_enable), 196 DEVMETHOD(ifdi_intr_enable, enetc_intr_enable), 197 DEVMETHOD(ifdi_intr_disable, enetc_intr_disable), 198 199 DEVMETHOD(ifdi_vlan_register, enetc_vlan_register), 200 DEVMETHOD(ifdi_vlan_unregister, enetc_vlan_unregister), 201 202 DEVMETHOD(ifdi_get_counter, enetc_get_counter), 203 DEVMETHOD(ifdi_mtu_set, enetc_mtu_set), 204 DEVMETHOD(ifdi_multi_set, enetc_setup_multicast), 205 DEVMETHOD(ifdi_promisc_set, enetc_promisc_set), 206 DEVMETHOD(ifdi_timer, enetc_timer), 207 DEVMETHOD(ifdi_update_admin_status, enetc_update_admin_status), 208 209 DEVMETHOD_END 210 }; 211 212 static driver_t enetc_iflib_driver = { 213 "enetc", enetc_iflib_methods, sizeof(struct enetc_softc) 214 }; 215 216 static struct if_txrx enetc_txrx = { 217 .ift_txd_encap = enetc_isc_txd_encap, 218 .ift_txd_flush = enetc_isc_txd_flush, 219 .ift_txd_credits_update = enetc_isc_txd_credits_update, 220 .ift_rxd_available = enetc_isc_rxd_available, 221 .ift_rxd_pkt_get = enetc_isc_rxd_pkt_get, 222 .ift_rxd_refill = enetc_isc_rxd_refill, 223 .ift_rxd_flush = enetc_isc_rxd_flush 224 }; 225 226 static struct if_shared_ctx enetc_sctx_init = { 227 .isc_magic = IFLIB_MAGIC, 228 229 .isc_q_align = ENETC_RING_ALIGN, 230 231 .isc_tx_maxsize = ENETC_MAX_FRAME_LEN, 232 .isc_tx_maxsegsize = PAGE_SIZE, 233 234 .isc_rx_maxsize = ENETC_MAX_FRAME_LEN, 235 .isc_rx_maxsegsize = ENETC_MAX_FRAME_LEN, 236 .isc_rx_nsegments = ENETC_MAX_SCATTER, 237 238 .isc_admin_intrcnt = 0, 239 240 .isc_nfl = 1, 241 .isc_nrxqs = 1, 242 .isc_ntxqs = 1, 243 244 .isc_vendor_info = enetc_vendor_info_array, 245 .isc_driver_version = enetc_driver_version, 246 .isc_driver = &enetc_iflib_driver, 247 248 .isc_flags = IFLIB_DRIVER_MEDIA | IFLIB_PRESERVE_TX_INDICES, 249 .isc_ntxd_min = {ENETC_MIN_DESC}, 250 .isc_ntxd_max = {ENETC_MAX_DESC}, 251 .isc_ntxd_default = {ENETC_DEFAULT_DESC}, 252 .isc_nrxd_min = {ENETC_MIN_DESC}, 253 .isc_nrxd_max = {ENETC_MAX_DESC}, 254 .isc_nrxd_default = {ENETC_DEFAULT_DESC} 255 }; 256 257 static void* 258 enetc_register(device_t dev) 259 { 260 261 if (!ofw_bus_status_okay(dev)) 262 return (NULL); 263 264 return (&enetc_sctx_init); 265 } 266 267 static void 268 enetc_max_nqueues(struct enetc_softc *sc, int *max_tx_nqueues, 269 int *max_rx_nqueues) 270 { 271 uint32_t val; 272 273 val = ENETC_PORT_RD4(sc, ENETC_PCAPR0); 274 *max_tx_nqueues = MIN(ENETC_PCAPR0_TXBDR(val), ENETC_MAX_QUEUES); 275 *max_rx_nqueues = MIN(ENETC_PCAPR0_RXBDR(val), ENETC_MAX_QUEUES); 276 } 277 278 static int 279 enetc_setup_fixed(struct enetc_softc *sc, phandle_t node) 280 { 281 ssize_t size; 282 int speed; 283 284 size = OF_getencprop(node, "speed", &speed, sizeof(speed)); 285 if (size <= 0) { 286 device_printf(sc->dev, 287 "Device has fixed-link node without link speed specified\n"); 288 return (ENXIO); 289 } 290 switch (speed) { 291 case 10: 292 speed = IFM_10_T; 293 break; 294 case 100: 295 speed = IFM_100_TX; 296 break; 297 case 1000: 298 speed = IFM_1000_T; 299 break; 300 case 2500: 301 speed = IFM_2500_T; 302 break; 303 default: 304 device_printf(sc->dev, "Unsupported link speed value of %d\n", 305 speed); 306 return (ENXIO); 307 } 308 speed |= IFM_ETHER; 309 310 if (OF_hasprop(node, "full-duplex")) 311 speed |= IFM_FDX; 312 else 313 speed |= IFM_HDX; 314 315 sc->fixed_link = true; 316 317 ifmedia_init(&sc->fixed_ifmedia, 0, enetc_fixed_media_change, 318 enetc_fixed_media_status); 319 ifmedia_add(&sc->fixed_ifmedia, speed, 0, NULL); 320 ifmedia_set(&sc->fixed_ifmedia, speed); 321 sc->shared->isc_media = &sc->fixed_ifmedia; 322 323 return (0); 324 } 325 326 static int 327 enetc_setup_phy(struct enetc_softc *sc) 328 { 329 phandle_t node, fixed_link, phy_handle; 330 struct mii_data *miid; 331 int phy_addr, error; 332 ssize_t size; 333 334 node = ofw_bus_get_node(sc->dev); 335 fixed_link = ofw_bus_find_child(node, "fixed-link"); 336 if (fixed_link != 0) 337 return (enetc_setup_fixed(sc, fixed_link)); 338 339 size = OF_getencprop(node, "phy-handle", &phy_handle, sizeof(phy_handle)); 340 if (size <= 0) { 341 device_printf(sc->dev, 342 "Failed to acquire PHY handle from FDT.\n"); 343 return (ENXIO); 344 } 345 phy_handle = OF_node_from_xref(phy_handle); 346 size = OF_getencprop(phy_handle, "reg", &phy_addr, sizeof(phy_addr)); 347 if (size <= 0) { 348 device_printf(sc->dev, "Failed to obtain PHY address\n"); 349 return (ENXIO); 350 } 351 error = mii_attach(sc->dev, &sc->miibus, iflib_get_ifp(sc->ctx), 352 enetc_media_change, enetc_media_status, 353 BMSR_DEFCAPMASK, phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE); 354 if (error != 0) { 355 device_printf(sc->dev, "mii_attach failed\n"); 356 return (error); 357 } 358 miid = device_get_softc(sc->miibus); 359 sc->shared->isc_media = &miid->mii_media; 360 361 return (0); 362 } 363 364 static int 365 enetc_attach_pre(if_ctx_t ctx) 366 { 367 struct ifnet *ifp; 368 if_softc_ctx_t scctx; 369 struct enetc_softc *sc; 370 int error, rid; 371 372 sc = iflib_get_softc(ctx); 373 scctx = iflib_get_softc_ctx(ctx); 374 sc->ctx = ctx; 375 sc->dev = iflib_get_dev(ctx); 376 sc->shared = scctx; 377 ifp = iflib_get_ifp(ctx); 378 379 pci_save_state(sc->dev); 380 pcie_flr(sc->dev, 1000, false); 381 pci_restore_state(sc->dev); 382 383 rid = PCIR_BAR(ENETC_BAR_REGS); 384 sc->regs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 385 if (sc->regs == NULL) { 386 device_printf(sc->dev, 387 "Failed to allocate BAR %d\n", ENETC_BAR_REGS); 388 return (ENXIO); 389 } 390 391 error = iflib_dma_alloc_align(ctx, 392 ENETC_MIN_DESC * sizeof(struct enetc_cbd), 393 ENETC_RING_ALIGN, 394 &sc->ctrl_queue.dma, 395 0); 396 if (error != 0) { 397 device_printf(sc->dev, "Failed to allocate control ring\n"); 398 goto fail; 399 } 400 sc->ctrl_queue.ring = (struct enetc_cbd*)sc->ctrl_queue.dma.idi_vaddr; 401 402 scctx->isc_txrx = &enetc_txrx; 403 scctx->isc_tx_nsegments = ENETC_MAX_SCATTER; 404 enetc_max_nqueues(sc, &scctx->isc_nrxqsets_max, &scctx->isc_ntxqsets_max); 405 406 if (scctx->isc_ntxd[0] % ENETC_DESC_ALIGN != 0) { 407 device_printf(sc->dev, 408 "The number of TX descriptors has to be a multiple of %d\n", 409 ENETC_DESC_ALIGN); 410 error = EINVAL; 411 goto fail; 412 } 413 if (scctx->isc_nrxd[0] % ENETC_DESC_ALIGN != 0) { 414 device_printf(sc->dev, 415 "The number of RX descriptors has to be a multiple of %d\n", 416 ENETC_DESC_ALIGN); 417 error = EINVAL; 418 goto fail; 419 } 420 scctx->isc_txqsizes[0] = scctx->isc_ntxd[0] * sizeof(union enetc_tx_bd); 421 scctx->isc_rxqsizes[0] = scctx->isc_nrxd[0] * sizeof(union enetc_rx_bd); 422 scctx->isc_txd_size[0] = sizeof(union enetc_tx_bd); 423 scctx->isc_rxd_size[0] = sizeof(union enetc_rx_bd); 424 scctx->isc_tx_csum_flags = 0; 425 scctx->isc_capabilities = scctx->isc_capenable = ENETC_IFCAPS; 426 427 error = enetc_mtu_set(ctx, ETHERMTU); 428 if (error != 0) 429 goto fail; 430 431 scctx->isc_msix_bar = pci_msix_table_bar(sc->dev); 432 433 error = enetc_setup_phy(sc); 434 if (error != 0) 435 goto fail; 436 437 enetc_get_hwaddr(sc); 438 439 return (0); 440 fail: 441 enetc_detach(ctx); 442 return (error); 443 } 444 445 static int 446 enetc_attach_post(if_ctx_t ctx) 447 { 448 449 enetc_init_hw(iflib_get_softc(ctx)); 450 return (0); 451 } 452 453 static int 454 enetc_detach(if_ctx_t ctx) 455 { 456 struct enetc_softc *sc; 457 int error = 0, i; 458 459 sc = iflib_get_softc(ctx); 460 461 for (i = 0; i < sc->rx_num_queues; i++) 462 iflib_irq_free(ctx, &sc->rx_queues[i].irq); 463 464 if (sc->miibus != NULL) 465 device_delete_child(sc->dev, sc->miibus); 466 467 if (sc->regs != NULL) 468 error = bus_release_resource(sc->dev, SYS_RES_MEMORY, 469 rman_get_rid(sc->regs), sc->regs); 470 471 if (sc->ctrl_queue.dma.idi_size != 0) 472 iflib_dma_free(&sc->ctrl_queue.dma); 473 474 return (error); 475 } 476 477 static int 478 enetc_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 479 int ntxqs, int ntxqsets) 480 { 481 struct enetc_softc *sc; 482 struct enetc_tx_queue *queue; 483 int i; 484 485 sc = iflib_get_softc(ctx); 486 487 MPASS(ntxqs == 1); 488 489 sc->tx_queues = mallocarray(sc->tx_num_queues, 490 sizeof(struct enetc_tx_queue), M_DEVBUF, M_NOWAIT | M_ZERO); 491 if (sc->tx_queues == NULL) { 492 device_printf(sc->dev, 493 "Failed to allocate memory for TX queues.\n"); 494 return (ENOMEM); 495 } 496 497 for (i = 0; i < sc->tx_num_queues; i++) { 498 queue = &sc->tx_queues[i]; 499 queue->sc = sc; 500 queue->ring = (union enetc_tx_bd*)(vaddrs[i]); 501 queue->ring_paddr = paddrs[i]; 502 queue->next_to_clean = 0; 503 queue->ring_full = false; 504 } 505 506 return (0); 507 } 508 509 static int 510 enetc_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 511 int nrxqs, int nrxqsets) 512 { 513 struct enetc_softc *sc; 514 struct enetc_rx_queue *queue; 515 int i; 516 517 sc = iflib_get_softc(ctx); 518 MPASS(nrxqs == 1); 519 520 sc->rx_queues = mallocarray(sc->rx_num_queues, 521 sizeof(struct enetc_rx_queue), M_DEVBUF, M_NOWAIT | M_ZERO); 522 if (sc->rx_queues == NULL) { 523 device_printf(sc->dev, 524 "Failed to allocate memory for RX queues.\n"); 525 return (ENOMEM); 526 } 527 528 for (i = 0; i < sc->rx_num_queues; i++) { 529 queue = &sc->rx_queues[i]; 530 queue->sc = sc; 531 queue->qid = i; 532 queue->ring = (union enetc_rx_bd*)(vaddrs[i]); 533 queue->ring_paddr = paddrs[i]; 534 } 535 536 return (0); 537 } 538 539 static void 540 enetc_queues_free(if_ctx_t ctx) 541 { 542 struct enetc_softc *sc; 543 544 sc = iflib_get_softc(ctx); 545 546 if (sc->tx_queues != NULL) { 547 free(sc->tx_queues, M_DEVBUF); 548 sc->tx_queues = NULL; 549 } 550 if (sc->rx_queues != NULL) { 551 free(sc->rx_queues, M_DEVBUF); 552 sc->rx_queues = NULL; 553 } 554 } 555 556 static void 557 enetc_get_hwaddr(struct enetc_softc *sc) 558 { 559 struct ether_addr hwaddr; 560 uint16_t high; 561 uint32_t low; 562 563 low = ENETC_PORT_RD4(sc, ENETC_PSIPMAR0(0)); 564 high = ENETC_PORT_RD2(sc, ENETC_PSIPMAR1(0)); 565 566 memcpy(&hwaddr.octet[0], &low, 4); 567 memcpy(&hwaddr.octet[4], &high, 2); 568 569 if (ETHER_IS_BROADCAST(hwaddr.octet) || 570 ETHER_IS_MULTICAST(hwaddr.octet) || 571 ETHER_IS_ZERO(hwaddr.octet)) { 572 ether_gen_addr(iflib_get_ifp(sc->ctx), &hwaddr); 573 device_printf(sc->dev, 574 "Failed to obtain MAC address, using a random one\n"); 575 memcpy(&low, &hwaddr.octet[0], 4); 576 memcpy(&high, &hwaddr.octet[4], 2); 577 } 578 579 iflib_set_mac(sc->ctx, hwaddr.octet); 580 } 581 582 static void 583 enetc_set_hwaddr(struct enetc_softc *sc) 584 { 585 struct ifnet *ifp; 586 uint16_t high; 587 uint32_t low; 588 uint8_t *hwaddr; 589 590 ifp = iflib_get_ifp(sc->ctx); 591 hwaddr = (uint8_t*)if_getlladdr(ifp); 592 low = *((uint32_t*)hwaddr); 593 high = *((uint16_t*)(hwaddr+4)); 594 595 ENETC_PORT_WR4(sc, ENETC_PSIPMAR0(0), low); 596 ENETC_PORT_WR2(sc, ENETC_PSIPMAR1(0), high); 597 } 598 599 static int 600 enetc_setup_rss(struct enetc_softc *sc) 601 { 602 struct iflib_dma_info dma; 603 int error, i, buckets_num = 0; 604 uint8_t *rss_table; 605 uint32_t reg; 606 607 reg = ENETC_RD4(sc, ENETC_SIPCAPR0); 608 if (reg & ENETC_SIPCAPR0_RSS) { 609 reg = ENETC_RD4(sc, ENETC_SIRSSCAPR); 610 buckets_num = ENETC_SIRSSCAPR_GET_NUM_RSS(reg); 611 } 612 if (buckets_num == 0) 613 return (ENOTSUP); 614 615 for (i = 0; i < ENETC_RSSHASH_KEY_SIZE / sizeof(uint32_t); i++) { 616 arc4rand((uint8_t *)®, sizeof(reg), 0); 617 ENETC_PORT_WR4(sc, ENETC_PRSSK(i), reg); 618 } 619 620 ENETC_WR4(sc, ENETC_SIRBGCR, sc->rx_num_queues); 621 622 error = iflib_dma_alloc_align(sc->ctx, 623 buckets_num * sizeof(*rss_table), 624 ENETC_RING_ALIGN, 625 &dma, 626 0); 627 if (error != 0) { 628 device_printf(sc->dev, "Failed to allocate DMA buffer for RSS\n"); 629 return (error); 630 } 631 rss_table = (uint8_t *)dma.idi_vaddr; 632 633 for (i = 0; i < buckets_num; i++) 634 rss_table[i] = i % sc->rx_num_queues; 635 636 error = enetc_ctrl_send(sc, (BDCR_CMD_RSS << 8) | BDCR_CMD_RSS_WRITE, 637 buckets_num * sizeof(*rss_table), &dma); 638 if (error != 0) 639 device_printf(sc->dev, "Failed to setup RSS table\n"); 640 641 iflib_dma_free(&dma); 642 643 return (error); 644 } 645 646 static int 647 enetc_ctrl_send(struct enetc_softc *sc, uint16_t cmd, uint16_t size, 648 iflib_dma_info_t dma) 649 { 650 struct enetc_ctrl_queue *queue; 651 struct enetc_cbd *desc; 652 int timeout = 1000; 653 654 queue = &sc->ctrl_queue; 655 desc = &queue->ring[queue->pidx]; 656 657 if (++queue->pidx == ENETC_MIN_DESC) 658 queue->pidx = 0; 659 660 desc->addr[0] = (uint32_t)dma->idi_paddr; 661 desc->addr[1] = (uint32_t)(dma->idi_paddr >> 32); 662 desc->index = 0; 663 desc->length = (uint16_t)size; 664 desc->cmd = (uint8_t)cmd; 665 desc->cls = (uint8_t)(cmd >> 8); 666 desc->status_flags = 0; 667 668 /* Sync command packet, */ 669 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_PREWRITE); 670 /* and the control ring. */ 671 bus_dmamap_sync(queue->dma.idi_tag, queue->dma.idi_map, BUS_DMASYNC_PREWRITE); 672 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx); 673 674 while (--timeout != 0) { 675 DELAY(20); 676 if (ENETC_RD4(sc, ENETC_SICBDRCIR) == queue->pidx) 677 break; 678 } 679 680 if (timeout == 0) 681 return (ETIMEDOUT); 682 683 bus_dmamap_sync(dma->idi_tag, dma->idi_map, BUS_DMASYNC_POSTREAD); 684 return (0); 685 } 686 687 static void 688 enetc_init_hw(struct enetc_softc *sc) 689 { 690 uint32_t val; 691 int error; 692 693 ENETC_PORT_WR4(sc, ENETC_PM0_CMD_CFG, 694 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC | 695 ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 696 ENETC_PORT_WR4(sc, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL); 697 val = ENETC_PSICFGR0_SET_TXBDR(sc->tx_num_queues); 698 val |= ENETC_PSICFGR0_SET_RXBDR(sc->rx_num_queues); 699 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 700 ENETC_PORT_WR4(sc, ENETC_PSICFGR0(0), val); 701 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VUTA(1)); 702 ENETC_PORT_WR4(sc, ENETC_PVCLCTR, ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S); 703 ENETC_PORT_WR4(sc, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS); 704 ENETC_PORT_WR4(sc, ENETC_PAR_PORT_CFG, ENETC_PAR_PORT_L4CD); 705 ENETC_PORT_WR4(sc, ENETC_PMR, ENETC_PMR_SI0EN | ENETC_PMR_PSPEED_1000M); 706 707 ENETC_WR4(sc, ENETC_SICAR0, 708 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 709 ENETC_WR4(sc, ENETC_SICAR1, ENETC_SICAR_MSI); 710 ENETC_WR4(sc, ENETC_SICAR2, 711 ENETC_SICAR_RD_COHERENT | ENETC_SICAR_WR_COHERENT); 712 713 enetc_init_ctrl(sc); 714 error = enetc_setup_rss(sc); 715 if (error != 0) 716 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN); 717 else 718 ENETC_WR4(sc, ENETC_SIMR, ENETC_SIMR_EN | ENETC_SIMR_RSSE); 719 720 } 721 722 static void 723 enetc_init_ctrl(struct enetc_softc *sc) 724 { 725 struct enetc_ctrl_queue *queue = &sc->ctrl_queue; 726 727 ENETC_WR4(sc, ENETC_SICBDRBAR0, 728 (uint32_t)queue->dma.idi_paddr); 729 ENETC_WR4(sc, ENETC_SICBDRBAR1, 730 (uint32_t)(queue->dma.idi_paddr >> 32)); 731 ENETC_WR4(sc, ENETC_SICBDRLENR, 732 queue->dma.idi_size / sizeof(struct enetc_cbd)); 733 734 queue->pidx = 0; 735 ENETC_WR4(sc, ENETC_SICBDRPIR, queue->pidx); 736 ENETC_WR4(sc, ENETC_SICBDRCIR, queue->pidx); 737 ENETC_WR4(sc, ENETC_SICBDRMR, ENETC_SICBDRMR_EN); 738 } 739 740 static void 741 enetc_init_tx(struct enetc_softc *sc) 742 { 743 struct enetc_tx_queue *queue; 744 int i; 745 746 for (i = 0; i < sc->tx_num_queues; i++) { 747 queue = &sc->tx_queues[i]; 748 749 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR0, 750 (uint32_t)queue->ring_paddr); 751 ENETC_TXQ_WR4(sc, i, ENETC_TBBAR1, 752 (uint32_t)(queue->ring_paddr >> 32)); 753 ENETC_TXQ_WR4(sc, i, ENETC_TBLENR, sc->tx_queue_size); 754 755 /* 756 * Even though it is undoccumented resetting the TX ring 757 * indices results in TX hang. 758 * Do the same as Linux and simply keep those unchanged 759 * for the drivers lifetime. 760 */ 761 #if 0 762 ENETC_TXQ_WR4(sc, i, ENETC_TBPIR, 0); 763 ENETC_TXQ_WR4(sc, i, ENETC_TBCIR, 0); 764 #endif 765 ENETC_TXQ_WR4(sc, i, ENETC_TBMR, ENETC_TBMR_EN); 766 } 767 768 } 769 770 static void 771 enetc_init_rx(struct enetc_softc *sc) 772 { 773 struct enetc_rx_queue *queue; 774 uint32_t rx_buf_size; 775 int i; 776 777 rx_buf_size = iflib_get_rx_mbuf_sz(sc->ctx); 778 779 for (i = 0; i < sc->rx_num_queues; i++) { 780 queue = &sc->rx_queues[i]; 781 782 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR0, 783 (uint32_t)queue->ring_paddr); 784 ENETC_RXQ_WR4(sc, i, ENETC_RBBAR1, 785 (uint32_t)(queue->ring_paddr >> 32)); 786 ENETC_RXQ_WR4(sc, i, ENETC_RBLENR, sc->rx_queue_size); 787 ENETC_RXQ_WR4(sc, i, ENETC_RBBSR, rx_buf_size); 788 ENETC_RXQ_WR4(sc, i, ENETC_RBPIR, 0); 789 ENETC_RXQ_WR4(sc, i, ENETC_RBCIR, 0); 790 queue->enabled = false; 791 } 792 } 793 794 static u_int 795 enetc_hash_mac(void *arg, struct sockaddr_dl *sdl, u_int cnt) 796 { 797 uint64_t *bitmap = arg; 798 uint64_t address = 0; 799 uint8_t hash = 0; 800 bool bit; 801 int i, j; 802 803 bcopy(LLADDR(sdl), &address, ETHER_ADDR_LEN); 804 805 /* 806 * The six bit hash is calculated by xoring every 807 * 6th bit of the address. 808 * It is then used as an index in a bitmap that is 809 * written to the device. 810 */ 811 for (i = 0; i < 6; i++) { 812 bit = 0; 813 for (j = 0; j < 8; j++) 814 bit ^= address & BIT(i + j*6); 815 816 hash |= bit << i; 817 } 818 819 *bitmap |= (1 << hash); 820 return (1); 821 } 822 823 static void 824 enetc_setup_multicast(if_ctx_t ctx) 825 { 826 struct enetc_softc *sc; 827 struct ifnet *ifp; 828 uint64_t bitmap = 0; 829 uint8_t revid; 830 831 sc = iflib_get_softc(ctx); 832 ifp = iflib_get_ifp(ctx); 833 revid = pci_get_revid(sc->dev); 834 835 if_foreach_llmaddr(ifp, enetc_hash_mac, &bitmap); 836 837 /* 838 * In revid 1 of this chip the positions multicast and unicast 839 * hash filter registers are flipped. 840 */ 841 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR0(0, revid == 1), bitmap & UINT32_MAX); 842 ENETC_PORT_WR4(sc, ENETC_PSIMMHFR1(0), bitmap >> 32); 843 844 } 845 846 static uint8_t 847 enetc_hash_vid(uint16_t vid) 848 { 849 uint8_t hash = 0; 850 bool bit; 851 int i; 852 853 for (i = 0;i < 6;i++) { 854 bit = vid & BIT(i); 855 bit ^= vid & BIT(i + 6); 856 hash |= bit << i; 857 } 858 859 return (hash); 860 } 861 862 static void 863 enetc_vlan_register(if_ctx_t ctx, uint16_t vid) 864 { 865 struct enetc_softc *sc; 866 uint8_t hash; 867 uint64_t bitmap; 868 869 sc = iflib_get_softc(ctx); 870 hash = enetc_hash_vid(vid); 871 872 /* Check if hash is alredy present in the bitmap. */ 873 if (++sc->vlan_bitmap[hash] != 1) 874 return; 875 876 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0)); 877 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32; 878 bitmap |= BIT(hash); 879 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX); 880 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32); 881 } 882 883 static void 884 enetc_vlan_unregister(if_ctx_t ctx, uint16_t vid) 885 { 886 struct enetc_softc *sc; 887 uint8_t hash; 888 uint64_t bitmap; 889 890 sc = iflib_get_softc(ctx); 891 hash = enetc_hash_vid(vid); 892 893 MPASS(sc->vlan_bitmap[hash] > 0); 894 if (--sc->vlan_bitmap[hash] != 0) 895 return; 896 897 bitmap = ENETC_PORT_RD4(sc, ENETC_PSIVHFR0(0)); 898 bitmap |= (uint64_t)ENETC_PORT_RD4(sc, ENETC_PSIVHFR1(0)) << 32; 899 bitmap &= ~BIT(hash); 900 ENETC_PORT_WR4(sc, ENETC_PSIVHFR0(0), bitmap & UINT32_MAX); 901 ENETC_PORT_WR4(sc, ENETC_PSIVHFR1(0), bitmap >> 32); 902 } 903 904 static void 905 enetc_init(if_ctx_t ctx) 906 { 907 struct enetc_softc *sc; 908 struct mii_data *miid; 909 struct ifnet *ifp; 910 uint16_t max_frame_length; 911 int baudrate; 912 913 sc = iflib_get_softc(ctx); 914 ifp = iflib_get_ifp(ctx); 915 916 max_frame_length = sc->shared->isc_max_frame_size; 917 MPASS(max_frame_length < ENETC_MAX_FRAME_LEN); 918 919 /* Set max RX and TX frame lengths. */ 920 ENETC_PORT_WR4(sc, ENETC_PM0_MAXFRM, max_frame_length); 921 ENETC_PORT_WR4(sc, ENETC_PTCMSDUR(0), max_frame_length); 922 ENETC_PORT_WR4(sc, ENETC_PTXMBAR, 2 * max_frame_length); 923 924 /* Set "VLAN promiscious" mode if filtering is disabled. */ 925 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) == 0) 926 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, 927 ENETC_PSIPVMR_SET_VUTA(1) | ENETC_PSIPVMR_SET_VP(1)); 928 else 929 ENETC_PORT_WR4(sc, ENETC_PSIPVMR, 930 ENETC_PSIPVMR_SET_VUTA(1)); 931 932 sc->rbmr = ENETC_RBMR_EN | ENETC_RBMR_AL; 933 934 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 935 sc->rbmr |= ENETC_RBMR_VTE; 936 937 /* Write MAC address to hardware. */ 938 enetc_set_hwaddr(sc); 939 940 enetc_init_tx(sc); 941 enetc_init_rx(sc); 942 943 if (sc->fixed_link) { 944 baudrate = ifmedia_baudrate(sc->fixed_ifmedia.ifm_cur->ifm_media); 945 iflib_link_state_change(sc->ctx, LINK_STATE_UP, baudrate); 946 } else { 947 /* 948 * Can't return an error from this function, there is not much 949 * we can do if this fails. 950 */ 951 miid = device_get_softc(sc->miibus); 952 (void)mii_mediachg(miid); 953 } 954 955 enetc_promisc_set(ctx, if_getflags(ifp)); 956 } 957 958 static void 959 enetc_stop(if_ctx_t ctx) 960 { 961 struct enetc_softc *sc; 962 int i; 963 964 sc = iflib_get_softc(ctx); 965 966 for (i = 0; i < sc->tx_num_queues; i++) 967 ENETC_TXQ_WR4(sc, i, ENETC_TBMR, 0); 968 969 for (i = 0; i < sc->rx_num_queues; i++) 970 ENETC_RXQ_WR4(sc, i, ENETC_RBMR, 0); 971 } 972 973 static int 974 enetc_msix_intr_assign(if_ctx_t ctx, int msix) 975 { 976 struct enetc_softc *sc; 977 struct enetc_rx_queue *rx_queue; 978 struct enetc_tx_queue *tx_queue; 979 int vector = 0, i, error; 980 char irq_name[16]; 981 982 sc = iflib_get_softc(ctx); 983 984 MPASS(sc->rx_num_queues + 1 <= ENETC_MSIX_COUNT); 985 MPASS(sc->rx_num_queues == sc->tx_num_queues); 986 987 for (i = 0; i < sc->rx_num_queues; i++, vector++) { 988 rx_queue = &sc->rx_queues[i]; 989 snprintf(irq_name, sizeof(irq_name), "rxtxq%d", i); 990 error = iflib_irq_alloc_generic(ctx, 991 &rx_queue->irq, vector + 1, IFLIB_INTR_RXTX, 992 NULL, rx_queue, i, irq_name); 993 if (error != 0) 994 goto fail; 995 996 ENETC_WR4(sc, ENETC_SIMSIRRV(i), vector); 997 ENETC_RXQ_WR4(sc, i, ENETC_RBICR1, ENETC_RX_INTR_TIME_THR); 998 ENETC_RXQ_WR4(sc, i, ENETC_RBICR0, 999 ENETC_RBICR0_ICEN | ENETC_RBICR0_SET_ICPT(ENETC_RX_INTR_PKT_THR)); 1000 } 1001 vector = 0; 1002 for (i = 0;i < sc->tx_num_queues; i++, vector++) { 1003 tx_queue = &sc->tx_queues[i]; 1004 snprintf(irq_name, sizeof(irq_name), "txq%d", i); 1005 iflib_softirq_alloc_generic(ctx, &tx_queue->irq, 1006 IFLIB_INTR_TX, tx_queue, i, irq_name); 1007 1008 ENETC_WR4(sc, ENETC_SIMSITRV(i), vector); 1009 } 1010 1011 return (0); 1012 fail: 1013 for (i = 0; i < sc->rx_num_queues; i++) { 1014 rx_queue = &sc->rx_queues[i]; 1015 iflib_irq_free(ctx, &rx_queue->irq); 1016 } 1017 return (error); 1018 } 1019 1020 static int 1021 enetc_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 1022 { 1023 struct enetc_softc *sc; 1024 1025 sc = iflib_get_softc(ctx); 1026 ENETC_TXQ_RD4(sc, qid, ENETC_TBIDR); 1027 return (0); 1028 } 1029 1030 static int 1031 enetc_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid) 1032 { 1033 struct enetc_softc *sc; 1034 1035 sc = iflib_get_softc(ctx); 1036 ENETC_RXQ_RD4(sc, qid, ENETC_RBIDR); 1037 return (0); 1038 } 1039 static void 1040 enetc_intr_enable(if_ctx_t ctx) 1041 { 1042 struct enetc_softc *sc; 1043 int i; 1044 1045 sc = iflib_get_softc(ctx); 1046 1047 for (i = 0; i < sc->rx_num_queues; i++) 1048 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, ENETC_RBIER_RXTIE); 1049 1050 for (i = 0; i < sc->tx_num_queues; i++) 1051 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, ENETC_TBIER_TXF); 1052 } 1053 1054 static void 1055 enetc_intr_disable(if_ctx_t ctx) 1056 { 1057 struct enetc_softc *sc; 1058 int i; 1059 1060 sc = iflib_get_softc(ctx); 1061 1062 for (i = 0; i < sc->rx_num_queues; i++) 1063 ENETC_RXQ_WR4(sc, i, ENETC_RBIER, 0); 1064 1065 for (i = 0; i < sc->tx_num_queues; i++) 1066 ENETC_TXQ_WR4(sc, i, ENETC_TBIER, 0); 1067 } 1068 1069 static int 1070 enetc_isc_txd_encap(void *data, if_pkt_info_t ipi) 1071 { 1072 struct enetc_softc *sc = data; 1073 struct enetc_tx_queue *queue; 1074 union enetc_tx_bd *desc; 1075 bus_dma_segment_t *segs; 1076 qidx_t pidx, queue_len; 1077 qidx_t i = 0; 1078 1079 queue = &sc->tx_queues[ipi->ipi_qsidx]; 1080 segs = ipi->ipi_segs; 1081 pidx = ipi->ipi_pidx; 1082 queue_len = sc->tx_queue_size; 1083 1084 /* 1085 * First descriptor is special. We use it to set frame 1086 * related information and offloads, e.g. VLAN tag. 1087 */ 1088 desc = &queue->ring[pidx]; 1089 bzero(desc, sizeof(*desc)); 1090 desc->frm_len = ipi->ipi_len; 1091 desc->addr = segs[i].ds_addr; 1092 desc->buf_len = segs[i].ds_len; 1093 if (ipi->ipi_flags & IPI_TX_INTR) 1094 desc->flags = ENETC_TXBD_FLAGS_FI; 1095 1096 i++; 1097 if (++pidx == queue_len) 1098 pidx = 0; 1099 1100 if (ipi->ipi_mflags & M_VLANTAG) { 1101 /* VLAN tag is inserted in a separate descriptor. */ 1102 desc->flags |= ENETC_TXBD_FLAGS_EX; 1103 desc = &queue->ring[pidx]; 1104 bzero(desc, sizeof(*desc)); 1105 desc->ext.vid = ipi->ipi_vtag; 1106 desc->ext.e_flags = ENETC_TXBD_E_FLAGS_VLAN_INS; 1107 if (++pidx == queue_len) 1108 pidx = 0; 1109 } 1110 1111 /* Now add remaining descriptors. */ 1112 for (;i < ipi->ipi_nsegs; i++) { 1113 desc = &queue->ring[pidx]; 1114 bzero(desc, sizeof(*desc)); 1115 desc->addr = segs[i].ds_addr; 1116 desc->buf_len = segs[i].ds_len; 1117 1118 if (++pidx == queue_len) 1119 pidx = 0; 1120 } 1121 1122 desc->flags |= ENETC_TXBD_FLAGS_F; 1123 ipi->ipi_new_pidx = pidx; 1124 if (pidx == queue->next_to_clean) 1125 queue->ring_full = true; 1126 1127 return (0); 1128 } 1129 1130 static void 1131 enetc_isc_txd_flush(void *data, uint16_t qid, qidx_t pidx) 1132 { 1133 struct enetc_softc *sc = data; 1134 1135 ENETC_TXQ_WR4(sc, qid, ENETC_TBPIR, pidx); 1136 } 1137 1138 static int 1139 enetc_isc_txd_credits_update(void *data, uint16_t qid, bool clear) 1140 { 1141 struct enetc_softc *sc = data; 1142 struct enetc_tx_queue *queue; 1143 qidx_t next_to_clean, next_to_process; 1144 int clean_count; 1145 1146 queue = &sc->tx_queues[qid]; 1147 next_to_process = 1148 ENETC_TXQ_RD4(sc, qid, ENETC_TBCIR) & ENETC_TBCIR_IDX_MASK; 1149 next_to_clean = queue->next_to_clean; 1150 1151 if (next_to_clean == next_to_process && !queue->ring_full) 1152 return (0); 1153 1154 if (!clear) 1155 return (1); 1156 1157 clean_count = next_to_process - next_to_clean; 1158 if (clean_count <= 0) 1159 clean_count += sc->tx_queue_size; 1160 1161 queue->next_to_clean = next_to_process; 1162 queue->ring_full = false; 1163 1164 return (clean_count); 1165 } 1166 1167 static int 1168 enetc_isc_rxd_available(void *data, uint16_t qid, qidx_t pidx, qidx_t budget) 1169 { 1170 struct enetc_softc *sc = data; 1171 struct enetc_rx_queue *queue; 1172 qidx_t hw_pidx, queue_len; 1173 union enetc_rx_bd *desc; 1174 int count = 0; 1175 1176 queue = &sc->rx_queues[qid]; 1177 desc = &queue->ring[pidx]; 1178 queue_len = sc->rx_queue_size; 1179 1180 if (desc->r.lstatus == 0) 1181 return (0); 1182 1183 if (budget == 1) 1184 return (1); 1185 1186 hw_pidx = ENETC_RXQ_RD4(sc, qid, ENETC_RBPIR); 1187 while (pidx != hw_pidx && count < budget) { 1188 desc = &queue->ring[pidx]; 1189 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F) 1190 count++; 1191 1192 if (++pidx == queue_len) 1193 pidx = 0; 1194 } 1195 1196 return (count); 1197 } 1198 1199 static int 1200 enetc_isc_rxd_pkt_get(void *data, if_rxd_info_t ri) 1201 { 1202 struct enetc_softc *sc = data; 1203 struct enetc_rx_queue *queue; 1204 union enetc_rx_bd *desc; 1205 uint16_t buf_len, pkt_size = 0; 1206 qidx_t cidx, queue_len; 1207 uint32_t status; 1208 int i; 1209 1210 cidx = ri->iri_cidx; 1211 queue = &sc->rx_queues[ri->iri_qsidx]; 1212 desc = &queue->ring[cidx]; 1213 status = desc->r.lstatus; 1214 queue_len = sc->rx_queue_size; 1215 1216 /* 1217 * Ready bit will be set only when all descriptors 1218 * in the chain have been processed. 1219 */ 1220 if ((status & ENETC_RXBD_LSTATUS_R) == 0) 1221 return (EAGAIN); 1222 1223 /* Pass RSS hash. */ 1224 if (status & ENETC_RXBD_FLAG_RSSV) { 1225 ri->iri_flowid = desc->r.rss_hash; 1226 ri->iri_rsstype = M_HASHTYPE_OPAQUE_HASH; 1227 } 1228 1229 /* Pass IP checksum status. */ 1230 ri->iri_csum_flags = CSUM_IP_CHECKED; 1231 if ((desc->r.parse_summary & ENETC_RXBD_PARSER_ERROR) == 0) 1232 ri->iri_csum_flags |= CSUM_IP_VALID; 1233 1234 /* Pass extracted VLAN tag. */ 1235 if (status & ENETC_RXBD_FLAG_VLAN) { 1236 ri->iri_vtag = desc->r.vlan_opt; 1237 ri->iri_flags = M_VLANTAG; 1238 } 1239 1240 for (i = 0; i < ENETC_MAX_SCATTER; i++) { 1241 buf_len = desc->r.buf_len; 1242 ri->iri_frags[i].irf_idx = cidx; 1243 ri->iri_frags[i].irf_len = buf_len; 1244 pkt_size += buf_len; 1245 if (desc->r.lstatus & ENETC_RXBD_LSTATUS_F) 1246 break; 1247 1248 if (++cidx == queue_len) 1249 cidx = 0; 1250 1251 desc = &queue->ring[cidx]; 1252 } 1253 ri->iri_nfrags = i + 1; 1254 ri->iri_len = pkt_size + ENETC_RX_IP_ALIGN; 1255 ri->iri_pad = ENETC_RX_IP_ALIGN; 1256 1257 MPASS(desc->r.lstatus & ENETC_RXBD_LSTATUS_F); 1258 if (status & ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK)) 1259 return (EBADMSG); 1260 1261 return (0); 1262 } 1263 1264 static void 1265 enetc_isc_rxd_refill(void *data, if_rxd_update_t iru) 1266 { 1267 struct enetc_softc *sc = data; 1268 struct enetc_rx_queue *queue; 1269 union enetc_rx_bd *desc; 1270 qidx_t pidx, queue_len; 1271 uint64_t *paddrs; 1272 int i, count; 1273 1274 queue = &sc->rx_queues[iru->iru_qsidx]; 1275 paddrs = iru->iru_paddrs; 1276 pidx = iru->iru_pidx; 1277 count = iru->iru_count; 1278 queue_len = sc->rx_queue_size; 1279 1280 for (i = 0; i < count; i++) { 1281 desc = &queue->ring[pidx]; 1282 bzero(desc, sizeof(*desc)); 1283 1284 desc->w.addr = paddrs[i]; 1285 if (++pidx == queue_len) 1286 pidx = 0; 1287 } 1288 /* 1289 * After enabling the queue NIC will prefetch the first 1290 * 8 descriptors. It probably assumes that the RX is fully 1291 * refilled when cidx == pidx. 1292 * Enable it only if we have enough decriptors ready on the ring. 1293 */ 1294 if (!queue->enabled && pidx >= 8) { 1295 ENETC_RXQ_WR4(sc, iru->iru_qsidx, ENETC_RBMR, sc->rbmr); 1296 queue->enabled = true; 1297 } 1298 } 1299 1300 static void 1301 enetc_isc_rxd_flush(void *data, uint16_t qid, uint8_t flid, qidx_t pidx) 1302 { 1303 struct enetc_softc *sc = data; 1304 1305 ENETC_RXQ_WR4(sc, qid, ENETC_RBCIR, pidx); 1306 } 1307 1308 static uint64_t 1309 enetc_get_counter(if_ctx_t ctx, ift_counter cnt) 1310 { 1311 struct enetc_softc *sc; 1312 struct ifnet *ifp; 1313 1314 sc = iflib_get_softc(ctx); 1315 ifp = iflib_get_ifp(ctx); 1316 1317 switch (cnt) { 1318 case IFCOUNTER_IERRORS: 1319 return (ENETC_PORT_RD8(sc, ENETC_PM0_RERR)); 1320 case IFCOUNTER_OERRORS: 1321 return (ENETC_PORT_RD8(sc, ENETC_PM0_TERR)); 1322 default: 1323 return (if_get_counter_default(ifp, cnt)); 1324 } 1325 } 1326 1327 static int 1328 enetc_mtu_set(if_ctx_t ctx, uint32_t mtu) 1329 { 1330 struct enetc_softc *sc = iflib_get_softc(ctx); 1331 uint32_t max_frame_size; 1332 1333 max_frame_size = mtu + 1334 ETHER_HDR_LEN + 1335 ETHER_CRC_LEN + 1336 sizeof(struct ether_vlan_header); 1337 1338 if (max_frame_size > ENETC_MAX_FRAME_LEN) 1339 return (EINVAL); 1340 1341 sc->shared->isc_max_frame_size = max_frame_size; 1342 1343 return (0); 1344 } 1345 1346 static int 1347 enetc_promisc_set(if_ctx_t ctx, int flags) 1348 { 1349 struct enetc_softc *sc; 1350 uint32_t reg = 0; 1351 1352 sc = iflib_get_softc(ctx); 1353 1354 if (flags & IFF_PROMISC) 1355 reg = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); 1356 else if (flags & IFF_ALLMULTI) 1357 reg = ENETC_PSIPMR_SET_MP(0); 1358 1359 ENETC_PORT_WR4(sc, ENETC_PSIPMR, reg); 1360 1361 return (0); 1362 } 1363 1364 static void 1365 enetc_timer(if_ctx_t ctx, uint16_t qid) 1366 { 1367 /* 1368 * Poll PHY status. Do this only for qid 0 to save 1369 * some cycles. 1370 */ 1371 if (qid == 0) 1372 iflib_admin_intr_deferred(ctx); 1373 } 1374 1375 static void 1376 enetc_update_admin_status(if_ctx_t ctx) 1377 { 1378 struct enetc_softc *sc; 1379 struct mii_data *miid; 1380 1381 sc = iflib_get_softc(ctx); 1382 1383 if (!sc->fixed_link) { 1384 miid = device_get_softc(sc->miibus); 1385 mii_tick(miid); 1386 } 1387 } 1388 1389 static int 1390 enetc_miibus_readreg(device_t dev, int phy, int reg) 1391 { 1392 struct enetc_softc *sc; 1393 1394 sc = iflib_get_softc(device_get_softc(dev)); 1395 return (enetc_mdio_read(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE, 1396 phy, reg)); 1397 } 1398 1399 static int 1400 enetc_miibus_writereg(device_t dev, int phy, int reg, int data) 1401 { 1402 struct enetc_softc *sc; 1403 1404 sc = iflib_get_softc(device_get_softc(dev)); 1405 return (enetc_mdio_write(sc->regs, ENETC_PORT_BASE + ENETC_EMDIO_BASE, 1406 phy, reg, data)); 1407 } 1408 1409 static void 1410 enetc_miibus_linkchg(device_t dev) 1411 { 1412 1413 enetc_miibus_statchg(dev); 1414 } 1415 1416 static void 1417 enetc_miibus_statchg(device_t dev) 1418 { 1419 struct enetc_softc *sc; 1420 struct mii_data *miid; 1421 int link_state, baudrate; 1422 1423 sc = iflib_get_softc(device_get_softc(dev)); 1424 miid = device_get_softc(sc->miibus); 1425 1426 baudrate = ifmedia_baudrate(miid->mii_media_active); 1427 if (miid->mii_media_status & IFM_AVALID) { 1428 if (miid->mii_media_status & IFM_ACTIVE) 1429 link_state = LINK_STATE_UP; 1430 else 1431 link_state = LINK_STATE_DOWN; 1432 } else { 1433 link_state = LINK_STATE_UNKNOWN; 1434 } 1435 1436 iflib_link_state_change(sc->ctx, link_state, baudrate); 1437 1438 } 1439 1440 static int 1441 enetc_media_change(if_t ifp) 1442 { 1443 struct enetc_softc *sc; 1444 struct mii_data *miid; 1445 1446 sc = iflib_get_softc(ifp->if_softc); 1447 miid = device_get_softc(sc->miibus); 1448 1449 mii_mediachg(miid); 1450 return (0); 1451 } 1452 1453 static void 1454 enetc_media_status(if_t ifp, struct ifmediareq* ifmr) 1455 { 1456 struct enetc_softc *sc; 1457 struct mii_data *miid; 1458 1459 sc = iflib_get_softc(ifp->if_softc); 1460 miid = device_get_softc(sc->miibus); 1461 1462 mii_pollstat(miid); 1463 1464 ifmr->ifm_active = miid->mii_media_active; 1465 ifmr->ifm_status = miid->mii_media_status; 1466 } 1467 1468 static int 1469 enetc_fixed_media_change(if_t ifp) 1470 { 1471 1472 if_printf(ifp, "Can't change media in fixed-link mode.\n"); 1473 return (0); 1474 } 1475 static void 1476 enetc_fixed_media_status(if_t ifp, struct ifmediareq* ifmr) 1477 { 1478 struct enetc_softc *sc; 1479 1480 sc = iflib_get_softc(ifp->if_softc); 1481 1482 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1483 ifmr->ifm_active = sc->fixed_ifmedia.ifm_cur->ifm_media; 1484 return; 1485 } 1486