1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Alstom Group. 5 * Copyright (c) 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/bus.h> 31 #include <sys/endian.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/rman.h> 35 36 #include <machine/bus.h> 37 #include <machine/resource.h> 38 39 #include <dev/enetc/enetc_hw.h> 40 #include <dev/enetc/enetc_mdio.h> 41 42 #define ENETC_MDIO_RD4(regs, base, off) \ 43 bus_read_4((regs), (base) + (off)) 44 #define ENETC_MDIO_WR4(regs, base, off, value) \ 45 bus_write_4((regs), (base) + (off), (value)) 46 47 static int 48 enetc_mdio_wait(struct resource *regs, int mdio_base) 49 { 50 int i; 51 uint32_t val; 52 53 i = 0; 54 do { 55 DELAY(100); 56 val = ENETC_MDIO_RD4(regs, mdio_base, ENETC_MDIO_CFG); 57 if ((val & MDIO_CFG_BSY) == 0) 58 return (0); 59 } while (i++ < ENETC_TIMEOUT); 60 61 return (ETIMEDOUT); 62 } 63 64 int 65 enetc_mdio_read(struct resource *regs, int mdio_base, int phy, int reg) 66 { 67 uint32_t mdio_cfg, mdio_ctl; 68 uint16_t dev_addr; 69 70 mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG; 71 if (reg & MII_ADDR_C45) { 72 /* clause 45 */ 73 dev_addr = (reg >> 16) & 0x1f; 74 mdio_cfg |= MDIO_CFG_ENC45; 75 } else { 76 /* clause 22 */ 77 dev_addr = reg & 0x1f; 78 mdio_cfg &= ~MDIO_CFG_ENC45; 79 } 80 81 ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CFG, mdio_cfg); 82 83 if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT) 84 return (EIO); 85 86 /* Set port and device addr. */ 87 mdio_ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(dev_addr); 88 ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CTL, mdio_ctl); 89 90 /* Set the register address. */ 91 if (reg & MII_ADDR_C45) { 92 ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_ADDR, reg & 0xffff); 93 94 if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT) 95 return (EIO); 96 } 97 98 /* Initiate the read. */ 99 ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CTL, mdio_ctl | MDIO_CTL_READ); 100 101 if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT) 102 return (EIO); 103 104 /* Check if any error occurred while reading PHY register. */ 105 if (ENETC_MDIO_RD4(regs, mdio_base, ENETC_MDIO_CFG) & MDIO_CFG_RD_ER) 106 return (ENXIO); 107 108 return (MDIO_DATA(ENETC_MDIO_RD4(regs, mdio_base, ENETC_MDIO_DATA))); 109 } 110 111 int 112 enetc_mdio_write(struct resource *regs, int mdio_base, int phy, int reg, 113 int data) 114 { 115 uint32_t mdio_cfg, mdio_ctl; 116 uint16_t dev_addr; 117 118 mdio_cfg = MDIO_CFG_CLKDIV(ENETC_MDC_DIV) | MDIO_CFG_NEG; 119 if (reg & MII_ADDR_C45) { 120 /* clause 45 */ 121 dev_addr = (reg >> 16) & 0x1f; 122 mdio_cfg |= MDIO_CFG_ENC45; 123 } else { 124 /* clause 22 */ 125 dev_addr = reg & 0x1f; 126 mdio_cfg &= ~MDIO_CFG_ENC45; 127 } 128 129 ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CFG, mdio_cfg); 130 131 if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT) 132 return (EIO); 133 134 /* Set port and device addr. */ 135 mdio_ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(dev_addr); 136 ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_CTL, mdio_ctl); 137 138 /* Set the register address. */ 139 if (reg & MII_ADDR_C45) { 140 ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_ADDR, reg & 0xffff); 141 142 if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT) 143 return (EIO); 144 } 145 146 /* Write the value. */ 147 ENETC_MDIO_WR4(regs, mdio_base, ENETC_MDIO_DATA, MDIO_DATA(data)); 148 149 if (enetc_mdio_wait(regs, mdio_base) == ETIMEDOUT) 150 return (EIO); 151 152 return (0); 153 } 154