1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2021 Alstom Group. 5 * Copyright (c) 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _ENETC_H_ 28 #define _ENETC_H_ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 35 #include <dev/enetc/enetc_hw.h> 36 37 struct enetc_softc; 38 struct enetc_rx_queue { 39 struct enetc_softc *sc; 40 uint16_t qid; 41 42 union enetc_rx_bd *ring; 43 uint64_t ring_paddr; 44 45 struct if_irq irq; 46 bool enabled; 47 }; 48 49 struct enetc_tx_queue { 50 struct enetc_softc *sc; 51 52 union enetc_tx_bd *ring; 53 uint64_t ring_paddr; 54 55 qidx_t next_to_clean; 56 bool ring_full; 57 58 struct if_irq irq; 59 }; 60 61 struct enetc_ctrl_queue { 62 qidx_t pidx; 63 64 struct iflib_dma_info dma; 65 struct enetc_cbd *ring; 66 67 struct if_irq irq; 68 }; 69 70 struct enetc_softc { 71 device_t dev; 72 73 struct mtx mii_lock; 74 75 if_ctx_t ctx; 76 if_softc_ctx_t shared; 77 #define tx_num_queues shared->isc_ntxqsets 78 #define rx_num_queues shared->isc_nrxqsets 79 #define tx_queue_size shared->isc_ntxd[0] 80 #define rx_queue_size shared->isc_nrxd[0] 81 82 struct resource *regs; 83 84 device_t miibus; 85 86 struct enetc_tx_queue *tx_queues; 87 struct enetc_rx_queue *rx_queues; 88 struct enetc_ctrl_queue ctrl_queue; 89 90 /* Default RX queue configuration. */ 91 uint32_t rbmr; 92 /* 93 * Hardware VLAN hash based filtering uses a 64bit bitmap. 94 * We need to know how many vids are in given position to 95 * know when to remove the bit from the bitmap. 96 */ 97 #define VLAN_BITMAP_SIZE 64 98 uint8_t vlan_bitmap[64]; 99 100 struct if_irq admin_irq; 101 int phy_addr; 102 103 struct ifmedia fixed_ifmedia; 104 bool fixed_link; 105 }; 106 107 #define ENETC_RD4(sc, reg) \ 108 bus_read_4((sc)->regs, reg) 109 #define ENETC_WR4(sc, reg, value) \ 110 bus_write_4((sc)->regs, reg, value) 111 112 #define ENETC_PORT_RD8(sc, reg) \ 113 bus_read_8((sc)->regs, ENETC_PORT_BASE + (reg)) 114 #define ENETC_PORT_RD4(sc, reg) \ 115 bus_read_4((sc)->regs, ENETC_PORT_BASE + (reg)) 116 #define ENETC_PORT_WR4(sc, reg, value) \ 117 bus_write_4((sc)->regs, ENETC_PORT_BASE + (reg), value) 118 #define ENETC_PORT_RD2(sc, reg) \ 119 bus_read_2((sc)->regs, ENETC_PORT_BASE + (reg)) 120 #define ENETC_PORT_WR2(sc, reg, value) \ 121 bus_write_2((sc)->regs, ENETC_PORT_BASE + (reg), value) 122 123 #define ENETC_TXQ_RD4(sc, q, reg) \ 124 ENETC_RD4((sc), ENETC_BDR(TX, q, reg)) 125 #define ENETC_TXQ_WR4(sc, q, reg, value) \ 126 ENETC_WR4((sc), ENETC_BDR(TX, q, reg), value) 127 #define ENETC_RXQ_RD4(sc, q, reg) \ 128 ENETC_RD4((sc), ENETC_BDR(RX, q, reg)) 129 #define ENETC_RXQ_WR4(sc, q, reg, value) \ 130 ENETC_WR4((sc), ENETC_BDR(RX, q, reg), value) 131 132 /* Device constants */ 133 134 #define ENETC_MAX_FRAME_LEN 9600 135 136 #define ENETC_MAX_QUEUES 4 137 138 /* Max supported nr of descriptors per frame. */ 139 #define ENETC_MAX_SCATTER 15 140 141 /* 142 * Up to 4096 transmit/receive descriptors are supported, 143 * their number has to be a multple of 64. 144 */ 145 #define ENETC_MIN_DESC 64 146 #define ENETC_MAX_DESC 4096 147 #define ENETC_DEFAULT_DESC 512 148 #define ENETC_DESC_ALIGN 64 149 150 /* Rings have to be 128B aligned. */ 151 #define ENETC_RING_ALIGN 128 152 153 #define ENETC_MSIX_COUNT 32 154 155 #define ENETC_RX_INTR_PKT_THR 16 156 157 /* Rx threshold irq timeout, 100us */ 158 #define ENETC_RX_INTR_TIME_THR ((100ULL * ENETC_CLK) / 1000000ULL) 159 160 #define ENETC_RX_IP_ALIGN 2 161 162 #endif 163