1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Alstom Group. 5 * Copyright (c) 2021 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _ENETC_H_ 28 #define _ENETC_H_ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 33 #include <dev/enetc/enetc_hw.h> 34 35 struct enetc_softc; 36 struct enetc_rx_queue { 37 struct enetc_softc *sc; 38 uint16_t qid; 39 40 union enetc_rx_bd *ring; 41 uint64_t ring_paddr; 42 43 struct if_irq irq; 44 bool enabled; 45 }; 46 47 struct enetc_tx_queue { 48 struct enetc_softc *sc; 49 50 union enetc_tx_bd *ring; 51 uint64_t ring_paddr; 52 53 qidx_t cidx; 54 55 struct if_irq irq; 56 }; 57 58 struct enetc_ctrl_queue { 59 qidx_t pidx; 60 61 struct iflib_dma_info dma; 62 struct enetc_cbd *ring; 63 64 struct if_irq irq; 65 }; 66 67 struct enetc_softc { 68 device_t dev; 69 70 struct mtx mii_lock; 71 72 if_ctx_t ctx; 73 if_softc_ctx_t shared; 74 #define tx_num_queues shared->isc_ntxqsets 75 #define rx_num_queues shared->isc_nrxqsets 76 #define tx_queue_size shared->isc_ntxd[0] 77 #define rx_queue_size shared->isc_nrxd[0] 78 79 struct resource *regs; 80 81 device_t miibus; 82 83 struct enetc_tx_queue *tx_queues; 84 struct enetc_rx_queue *rx_queues; 85 struct enetc_ctrl_queue ctrl_queue; 86 87 /* Default RX queue configuration. */ 88 uint32_t rbmr; 89 /* 90 * Hardware VLAN hash based filtering uses a 64bit bitmap. 91 * We need to know how many vids are in given position to 92 * know when to remove the bit from the bitmap. 93 */ 94 #define VLAN_BITMAP_SIZE 64 95 uint8_t vlan_bitmap[64]; 96 97 struct if_irq admin_irq; 98 int phy_addr; 99 100 struct ifmedia fixed_ifmedia; 101 bool fixed_link; 102 }; 103 104 #define ENETC_RD4(sc, reg) \ 105 bus_read_4((sc)->regs, reg) 106 #define ENETC_WR4(sc, reg, value) \ 107 bus_write_4((sc)->regs, reg, value) 108 109 #define ENETC_PORT_RD8(sc, reg) \ 110 bus_read_8((sc)->regs, ENETC_PORT_BASE + (reg)) 111 #define ENETC_PORT_RD4(sc, reg) \ 112 bus_read_4((sc)->regs, ENETC_PORT_BASE + (reg)) 113 #define ENETC_PORT_WR4(sc, reg, value) \ 114 bus_write_4((sc)->regs, ENETC_PORT_BASE + (reg), value) 115 #define ENETC_PORT_RD2(sc, reg) \ 116 bus_read_2((sc)->regs, ENETC_PORT_BASE + (reg)) 117 #define ENETC_PORT_WR2(sc, reg, value) \ 118 bus_write_2((sc)->regs, ENETC_PORT_BASE + (reg), value) 119 120 #define ENETC_TXQ_RD4(sc, q, reg) \ 121 ENETC_RD4((sc), ENETC_BDR(TX, q, reg)) 122 #define ENETC_TXQ_WR4(sc, q, reg, value) \ 123 ENETC_WR4((sc), ENETC_BDR(TX, q, reg), value) 124 #define ENETC_RXQ_RD4(sc, q, reg) \ 125 ENETC_RD4((sc), ENETC_BDR(RX, q, reg)) 126 #define ENETC_RXQ_WR4(sc, q, reg, value) \ 127 ENETC_WR4((sc), ENETC_BDR(RX, q, reg), value) 128 129 /* Device constants */ 130 131 #define ENETC_MAX_FRAME_LEN 9600 132 133 #define ENETC_MAX_QUEUES 4 134 135 /* Max supported nr of descriptors per frame. */ 136 #define ENETC_MAX_SCATTER 15 137 138 /* 139 * Up to 4096 transmit/receive descriptors are supported, 140 * their number has to be a multiple of 64. 141 */ 142 #define ENETC_MIN_DESC 64 143 #define ENETC_MAX_DESC 4096 144 #define ENETC_DEFAULT_DESC 512 145 #define ENETC_DESC_ALIGN 64 146 147 /* Rings have to be 128B aligned. */ 148 #define ENETC_RING_ALIGN 128 149 150 #define ENETC_MSIX_COUNT 32 151 152 #define ENETC_RX_INTR_PKT_THR 16 153 154 /* Rx threshold irq timeout, 100us */ 155 #define ENETC_RX_INTR_TIME_THR ((100ULL * ENETC_CLK) / 1000000ULL) 156 157 #define ENETC_RX_IP_ALIGN 2 158 159 #endif 160