1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #ifdef DEV_NETMAP 34 35 #include "ena.h" 36 #include "ena_netmap.h" 37 38 #define ENA_NETMAP_MORE_FRAMES 1 39 #define ENA_NETMAP_NO_MORE_FRAMES 0 40 #define ENA_MAX_FRAMES 16384 41 42 struct ena_netmap_ctx { 43 struct netmap_kring *kring; 44 struct ena_adapter *adapter; 45 struct netmap_adapter *na; 46 struct netmap_slot *slots; 47 struct ena_ring *ring; 48 struct ena_com_io_cq *io_cq; 49 struct ena_com_io_sq *io_sq; 50 u_int nm_i; 51 uint16_t nt; 52 uint16_t lim; 53 }; 54 55 /* Netmap callbacks */ 56 static int ena_netmap_reg(struct netmap_adapter *, int); 57 static int ena_netmap_txsync(struct netmap_kring *, int); 58 static int ena_netmap_rxsync(struct netmap_kring *, int); 59 60 /* Helper functions */ 61 static int ena_netmap_tx_frames(struct ena_netmap_ctx *); 62 static int ena_netmap_tx_frame(struct ena_netmap_ctx *); 63 static inline uint16_t ena_netmap_count_slots(struct ena_netmap_ctx *); 64 static inline uint16_t ena_netmap_packet_len(struct netmap_slot *, u_int, 65 uint16_t); 66 static int ena_netmap_copy_data(struct netmap_adapter *, 67 struct netmap_slot *, u_int, uint16_t, uint16_t, void *); 68 static int ena_netmap_map_single_slot(struct netmap_adapter *, 69 struct netmap_slot *, bus_dma_tag_t, bus_dmamap_t, void **, uint64_t *); 70 static int ena_netmap_tx_map_slots(struct ena_netmap_ctx *, 71 struct ena_tx_buffer *, void **, uint16_t *, uint16_t *); 72 static void ena_netmap_unmap_last_socket_chain(struct ena_netmap_ctx *, 73 struct ena_tx_buffer *); 74 static void ena_netmap_tx_cleanup(struct ena_netmap_ctx *); 75 static uint16_t ena_netmap_tx_clean_one(struct ena_netmap_ctx *, 76 uint16_t); 77 static inline int validate_tx_req_id(struct ena_ring *, uint16_t); 78 static int ena_netmap_rx_frames(struct ena_netmap_ctx *); 79 static int ena_netmap_rx_frame(struct ena_netmap_ctx *); 80 static int ena_netmap_rx_load_desc(struct ena_netmap_ctx *, uint16_t, 81 int *); 82 static void ena_netmap_rx_cleanup(struct ena_netmap_ctx *); 83 static void ena_netmap_fill_ctx(struct netmap_kring *, 84 struct ena_netmap_ctx *, uint16_t); 85 86 int 87 ena_netmap_attach(struct ena_adapter *adapter) 88 { 89 struct netmap_adapter na; 90 91 ena_log_nm(adapter->pdev, INFO, "netmap attach\n"); 92 93 bzero(&na, sizeof(na)); 94 na.na_flags = NAF_MOREFRAG; 95 na.ifp = adapter->ifp; 96 na.num_tx_desc = adapter->requested_tx_ring_size; 97 na.num_rx_desc = adapter->requested_rx_ring_size; 98 na.num_tx_rings = adapter->num_io_queues; 99 na.num_rx_rings = adapter->num_io_queues; 100 na.rx_buf_maxsize = adapter->buf_ring_size; 101 na.nm_txsync = ena_netmap_txsync; 102 na.nm_rxsync = ena_netmap_rxsync; 103 na.nm_register = ena_netmap_reg; 104 105 return (netmap_attach(&na)); 106 } 107 108 int 109 ena_netmap_alloc_rx_slot(struct ena_adapter *adapter, 110 struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info) 111 { 112 struct netmap_adapter *na = NA(adapter->ifp); 113 struct netmap_kring *kring; 114 struct netmap_ring *ring; 115 struct netmap_slot *slot; 116 void *addr; 117 uint64_t paddr; 118 int nm_i, qid, head, lim, rc; 119 120 /* if previously allocated frag is not used */ 121 if (unlikely(rx_info->netmap_buf_idx != 0)) 122 return (0); 123 124 qid = rx_ring->qid; 125 kring = na->rx_rings[qid]; 126 nm_i = kring->nr_hwcur; 127 head = kring->rhead; 128 129 ena_log_nm(adapter->pdev, DBG, "nr_hwcur: %d, nr_hwtail: %d, " 130 "rhead: %d, rcur: %d, rtail: %d\n", kring->nr_hwcur, 131 kring->nr_hwtail, kring->rhead, kring->rcur, kring->rtail); 132 133 if ((nm_i == head) && rx_ring->initialized) { 134 ena_log_nm(adapter->pdev, ERR, "No free slots in netmap ring\n"); 135 return (ENOMEM); 136 } 137 138 ring = kring->ring; 139 if (ring == NULL) { 140 ena_log_nm(adapter->pdev, ERR, "Rx ring %d is NULL\n", qid); 141 return (EFAULT); 142 } 143 slot = &ring->slot[nm_i]; 144 145 addr = PNMB(na, slot, &paddr); 146 if (addr == NETMAP_BUF_BASE(na)) { 147 ena_log_nm(adapter->pdev, ERR, "Bad buff in slot\n"); 148 return (EFAULT); 149 } 150 151 rc = netmap_load_map(na, adapter->rx_buf_tag, rx_info->map, addr); 152 if (rc != 0) { 153 ena_log_nm(adapter->pdev, WARN, "DMA mapping error\n"); 154 return (rc); 155 } 156 bus_dmamap_sync(adapter->rx_buf_tag, rx_info->map, BUS_DMASYNC_PREREAD); 157 158 rx_info->ena_buf.paddr = paddr; 159 rx_info->ena_buf.len = ring->nr_buf_size; 160 rx_info->mbuf = NULL; 161 rx_info->netmap_buf_idx = slot->buf_idx; 162 163 slot->buf_idx = 0; 164 165 lim = kring->nkr_num_slots - 1; 166 kring->nr_hwcur = nm_next(nm_i, lim); 167 168 return (0); 169 } 170 171 void 172 ena_netmap_free_rx_slot(struct ena_adapter *adapter, 173 struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info) 174 { 175 struct netmap_adapter *na; 176 struct netmap_kring *kring; 177 struct netmap_slot *slot; 178 int nm_i, qid, lim; 179 180 na = NA(adapter->ifp); 181 if (na == NULL) { 182 ena_log_nm(adapter->pdev, ERR, "netmap adapter is NULL\n"); 183 return; 184 } 185 186 if (na->rx_rings == NULL) { 187 ena_log_nm(adapter->pdev, ERR, "netmap rings are NULL\n"); 188 return; 189 } 190 191 qid = rx_ring->qid; 192 kring = na->rx_rings[qid]; 193 if (kring == NULL) { 194 ena_log_nm(adapter->pdev, ERR, 195 "netmap kernel ring %d is NULL\n", qid); 196 return; 197 } 198 199 lim = kring->nkr_num_slots - 1; 200 nm_i = nm_prev(kring->nr_hwcur, lim); 201 202 if (kring->nr_mode != NKR_NETMAP_ON) 203 return; 204 205 bus_dmamap_sync(adapter->rx_buf_tag, rx_info->map, 206 BUS_DMASYNC_POSTREAD); 207 netmap_unload_map(na, adapter->rx_buf_tag, rx_info->map); 208 209 KASSERT(kring->ring == NULL, ("Netmap Rx ring is NULL\n")); 210 211 slot = &kring->ring->slot[nm_i]; 212 213 ENA_WARN(slot->buf_idx != 0, adapter->ena_dev, "Overwrite slot buf\n"); 214 slot->buf_idx = rx_info->netmap_buf_idx; 215 slot->flags = NS_BUF_CHANGED; 216 217 rx_info->netmap_buf_idx = 0; 218 kring->nr_hwcur = nm_i; 219 } 220 221 static bool 222 ena_ring_in_netmap(struct ena_adapter *adapter, int qid, enum txrx x) 223 { 224 struct netmap_adapter *na; 225 struct netmap_kring *kring; 226 227 if (adapter->ifp->if_capenable & IFCAP_NETMAP) { 228 na = NA(adapter->ifp); 229 kring = (x == NR_RX) ? na->rx_rings[qid] : na->tx_rings[qid]; 230 if (kring->nr_mode == NKR_NETMAP_ON) 231 return true; 232 } 233 return false; 234 } 235 236 bool 237 ena_tx_ring_in_netmap(struct ena_adapter *adapter, int qid) 238 { 239 return ena_ring_in_netmap(adapter, qid, NR_TX); 240 } 241 242 bool 243 ena_rx_ring_in_netmap(struct ena_adapter *adapter, int qid) 244 { 245 return ena_ring_in_netmap(adapter, qid, NR_RX); 246 } 247 248 static void 249 ena_netmap_reset_ring(struct ena_adapter *adapter, int qid, enum txrx x) 250 { 251 if (!ena_ring_in_netmap(adapter, qid, x)) 252 return; 253 254 netmap_reset(NA(adapter->ifp), x, qid, 0); 255 ena_log_nm(adapter->pdev, INFO, "%s ring %d is in netmap mode\n", 256 (x == NR_TX) ? "Tx" : "Rx", qid); 257 } 258 259 void 260 ena_netmap_reset_rx_ring(struct ena_adapter *adapter, int qid) 261 { 262 ena_netmap_reset_ring(adapter, qid, NR_RX); 263 } 264 265 void 266 ena_netmap_reset_tx_ring(struct ena_adapter *adapter, int qid) 267 { 268 ena_netmap_reset_ring(adapter, qid, NR_TX); 269 } 270 271 static int 272 ena_netmap_reg(struct netmap_adapter *na, int onoff) 273 { 274 struct ifnet *ifp = na->ifp; 275 struct ena_adapter* adapter = ifp->if_softc; 276 device_t pdev = adapter->pdev; 277 struct netmap_kring *kring; 278 enum txrx t; 279 int rc, i; 280 281 ENA_LOCK_LOCK(); 282 ENA_FLAG_CLEAR_ATOMIC(ENA_FLAG_TRIGGER_RESET, adapter); 283 ena_down(adapter); 284 285 if (onoff) { 286 ena_log_nm(pdev, INFO, "netmap on\n"); 287 for_rx_tx(t) { 288 for (i = 0; i <= nma_get_nrings(na, t); i++) { 289 kring = NMR(na, t)[i]; 290 if (nm_kring_pending_on(kring)) { 291 kring->nr_mode = NKR_NETMAP_ON; 292 } 293 } 294 } 295 nm_set_native_flags(na); 296 } else { 297 ena_log_nm(pdev, INFO, "netmap off\n"); 298 nm_clear_native_flags(na); 299 for_rx_tx(t) { 300 for (i = 0; i <= nma_get_nrings(na, t); i++) { 301 kring = NMR(na, t)[i]; 302 if (nm_kring_pending_off(kring)) { 303 kring->nr_mode = NKR_NETMAP_OFF; 304 } 305 } 306 } 307 } 308 309 rc = ena_up(adapter); 310 if (rc != 0) { 311 ena_log_nm(pdev, WARN, "ena_up failed with rc=%d\n", rc); 312 adapter->reset_reason = ENA_REGS_RESET_DRIVER_INVALID_STATE; 313 nm_clear_native_flags(na); 314 ena_destroy_device(adapter, false); 315 ENA_FLAG_SET_ATOMIC(ENA_FLAG_DEV_UP_BEFORE_RESET, adapter); 316 rc = ena_restore_device(adapter); 317 } 318 ENA_LOCK_UNLOCK(); 319 320 return (rc); 321 } 322 323 static int 324 ena_netmap_txsync(struct netmap_kring *kring, int flags) 325 { 326 struct ena_netmap_ctx ctx; 327 int rc = 0; 328 329 ena_netmap_fill_ctx(kring, &ctx, ENA_IO_TXQ_IDX(kring->ring_id)); 330 ctx.ring = &ctx.adapter->tx_ring[kring->ring_id]; 331 332 ENA_RING_MTX_LOCK(ctx.ring); 333 if (unlikely(!ENA_FLAG_ISSET(ENA_FLAG_DEV_UP, ctx.adapter))) 334 goto txsync_end; 335 336 if (unlikely(!ENA_FLAG_ISSET(ENA_FLAG_LINK_UP, ctx.adapter))) 337 goto txsync_end; 338 339 rc = ena_netmap_tx_frames(&ctx); 340 ena_netmap_tx_cleanup(&ctx); 341 342 txsync_end: 343 ENA_RING_MTX_UNLOCK(ctx.ring); 344 return (rc); 345 } 346 347 static int 348 ena_netmap_tx_frames(struct ena_netmap_ctx *ctx) 349 { 350 struct ena_ring *tx_ring = ctx->ring; 351 int rc = 0; 352 353 ctx->nm_i = ctx->kring->nr_hwcur; 354 ctx->nt = ctx->ring->next_to_use; 355 356 __builtin_prefetch(&ctx->slots[ctx->nm_i]); 357 358 while (ctx->nm_i != ctx->kring->rhead) { 359 if ((rc = ena_netmap_tx_frame(ctx)) != 0) { 360 /* 361 * When there is no empty space in Tx ring, error is 362 * still being returned. It should not be passed to the 363 * netmap, as application knows current ring state from 364 * netmap ring pointers. Returning error there could 365 * cause application to exit, but the Tx ring is commonly 366 * being full. 367 */ 368 if (rc == ENA_COM_NO_MEM) 369 rc = 0; 370 break; 371 } 372 tx_ring->acum_pkts++; 373 } 374 375 /* If any packet was sent... */ 376 if (likely(ctx->nm_i != ctx->kring->nr_hwcur)) { 377 /* ...send the doorbell to the device. */ 378 ena_com_write_sq_doorbell(ctx->io_sq); 379 counter_u64_add(ctx->ring->tx_stats.doorbells, 1); 380 tx_ring->acum_pkts = 0; 381 382 ctx->ring->next_to_use = ctx->nt; 383 ctx->kring->nr_hwcur = ctx->nm_i; 384 } 385 386 return (rc); 387 } 388 389 static int 390 ena_netmap_tx_frame(struct ena_netmap_ctx *ctx) 391 { 392 struct ena_com_tx_ctx ena_tx_ctx; 393 struct ena_adapter *adapter; 394 struct ena_ring *tx_ring; 395 struct ena_tx_buffer *tx_info; 396 uint16_t req_id; 397 uint16_t header_len; 398 uint16_t packet_len; 399 int nb_hw_desc; 400 int rc; 401 void *push_hdr; 402 403 adapter = ctx->adapter; 404 if (ena_netmap_count_slots(ctx) > adapter->max_tx_sgl_size) { 405 ena_log_nm(adapter->pdev, WARN, "Too many slots per packet\n"); 406 return (EINVAL); 407 } 408 409 tx_ring = ctx->ring; 410 411 req_id = tx_ring->free_tx_ids[ctx->nt]; 412 tx_info = &tx_ring->tx_buffer_info[req_id]; 413 tx_info->num_of_bufs = 0; 414 tx_info->nm_info.sockets_used = 0; 415 416 rc = ena_netmap_tx_map_slots(ctx, tx_info, &push_hdr, &header_len, 417 &packet_len); 418 if (unlikely(rc != 0)) { 419 ena_log_nm(adapter->pdev, ERR, "Failed to map Tx slot\n"); 420 return (rc); 421 } 422 423 bzero(&ena_tx_ctx, sizeof(struct ena_com_tx_ctx)); 424 ena_tx_ctx.ena_bufs = tx_info->bufs; 425 ena_tx_ctx.push_header = push_hdr; 426 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 427 ena_tx_ctx.req_id = req_id; 428 ena_tx_ctx.header_len = header_len; 429 ena_tx_ctx.meta_valid = adapter->disable_meta_caching; 430 431 /* There are no any offloads, as the netmap doesn't support them */ 432 433 if (tx_ring->acum_pkts == DB_THRESHOLD || 434 ena_com_is_doorbell_needed(ctx->io_sq, &ena_tx_ctx)) { 435 ena_com_write_sq_doorbell(ctx->io_sq); 436 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 437 tx_ring->acum_pkts = 0; 438 } 439 440 rc = ena_com_prepare_tx(ctx->io_sq, &ena_tx_ctx, &nb_hw_desc); 441 if (unlikely(rc != 0)) { 442 if (likely(rc == ENA_COM_NO_MEM)) { 443 ena_log_nm(adapter->pdev, DBG, 444 "Tx ring[%d] is out of space\n", tx_ring->que->id); 445 } else { 446 ena_log_nm(adapter->pdev, ERR, 447 "Failed to prepare Tx bufs\n"); 448 ena_trigger_reset(adapter, 449 ENA_REGS_RESET_DRIVER_INVALID_STATE); 450 } 451 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1); 452 453 ena_netmap_unmap_last_socket_chain(ctx, tx_info); 454 return (rc); 455 } 456 457 counter_enter(); 458 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1); 459 counter_u64_add_protected(tx_ring->tx_stats.bytes, packet_len); 460 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1); 461 counter_u64_add_protected(adapter->hw_stats.tx_bytes, packet_len); 462 counter_exit(); 463 464 tx_info->tx_descs = nb_hw_desc; 465 466 ctx->nt = ENA_TX_RING_IDX_NEXT(ctx->nt, ctx->ring->ring_size); 467 468 for (unsigned int i = 0; i < tx_info->num_of_bufs; i++) 469 bus_dmamap_sync(adapter->tx_buf_tag, 470 tx_info->nm_info.map_seg[i], BUS_DMASYNC_PREWRITE); 471 472 return (0); 473 } 474 475 static inline uint16_t 476 ena_netmap_count_slots(struct ena_netmap_ctx *ctx) 477 { 478 uint16_t slots = 1; 479 uint16_t nm = ctx->nm_i; 480 481 while ((ctx->slots[nm].flags & NS_MOREFRAG) != 0) { 482 slots++; 483 nm = nm_next(nm, ctx->lim); 484 } 485 486 return slots; 487 } 488 489 static inline uint16_t 490 ena_netmap_packet_len(struct netmap_slot *slots, u_int slot_index, 491 uint16_t limit) 492 { 493 struct netmap_slot *nm_slot; 494 uint16_t packet_size = 0; 495 496 do { 497 nm_slot = &slots[slot_index]; 498 packet_size += nm_slot->len; 499 slot_index = nm_next(slot_index, limit); 500 } while ((nm_slot->flags & NS_MOREFRAG) != 0); 501 502 return packet_size; 503 } 504 505 static int 506 ena_netmap_copy_data(struct netmap_adapter *na, struct netmap_slot *slots, 507 u_int slot_index, uint16_t limit, uint16_t bytes_to_copy, void *destination) 508 { 509 struct netmap_slot *nm_slot; 510 void *slot_vaddr; 511 uint16_t data_amount; 512 513 do { 514 nm_slot = &slots[slot_index]; 515 slot_vaddr = NMB(na, nm_slot); 516 if (unlikely(slot_vaddr == NULL)) 517 return (EINVAL); 518 519 data_amount = min_t(uint16_t, bytes_to_copy, nm_slot->len); 520 memcpy(destination, slot_vaddr, data_amount); 521 bytes_to_copy -= data_amount; 522 523 slot_index = nm_next(slot_index, limit); 524 } while ((nm_slot->flags & NS_MOREFRAG) != 0 && bytes_to_copy > 0); 525 526 return (0); 527 } 528 529 static int 530 ena_netmap_map_single_slot(struct netmap_adapter *na, struct netmap_slot *slot, 531 bus_dma_tag_t dmatag, bus_dmamap_t dmamap, void **vaddr, uint64_t *paddr) 532 { 533 device_t pdev; 534 int rc; 535 536 pdev = ((struct ena_adapter *)na->ifp->if_softc)->pdev; 537 538 *vaddr = PNMB(na, slot, paddr); 539 if (unlikely(vaddr == NULL)) { 540 ena_log_nm(pdev, ERR, "Slot address is NULL\n"); 541 return (EINVAL); 542 } 543 544 rc = netmap_load_map(na, dmatag, dmamap, *vaddr); 545 if (unlikely(rc != 0)) { 546 ena_log_nm(pdev, ERR, "Failed to map slot %d for DMA\n", 547 slot->buf_idx); 548 return (EINVAL); 549 } 550 551 return (0); 552 } 553 554 static int 555 ena_netmap_tx_map_slots(struct ena_netmap_ctx *ctx, 556 struct ena_tx_buffer *tx_info, void **push_hdr, uint16_t *header_len, 557 uint16_t *packet_len) 558 { 559 struct netmap_slot *slot; 560 struct ena_com_buf *ena_buf; 561 struct ena_adapter *adapter; 562 struct ena_ring *tx_ring; 563 struct ena_netmap_tx_info *nm_info; 564 bus_dmamap_t *nm_maps; 565 void *vaddr; 566 uint64_t paddr; 567 uint32_t *nm_buf_idx; 568 uint32_t slot_head_len; 569 uint32_t frag_len; 570 uint32_t remaining_len; 571 uint16_t push_len; 572 uint16_t delta; 573 int rc; 574 575 adapter = ctx->adapter; 576 tx_ring = ctx->ring; 577 ena_buf = tx_info->bufs; 578 nm_info = &tx_info->nm_info; 579 nm_maps = nm_info->map_seg; 580 nm_buf_idx = nm_info->socket_buf_idx; 581 slot = &ctx->slots[ctx->nm_i]; 582 583 slot_head_len = slot->len; 584 *packet_len = ena_netmap_packet_len(ctx->slots, ctx->nm_i, ctx->lim); 585 remaining_len = *packet_len; 586 delta = 0; 587 588 __builtin_prefetch(&ctx->slots[ctx->nm_i + 1]); 589 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 590 /* 591 * When the device is in LLQ mode, the driver will copy 592 * the header into the device memory space. 593 * The ena_com layer assumes that the header is in a linear 594 * memory space. 595 * This assumption might be wrong since part of the header 596 * can be in the fragmented buffers. 597 * First, check if header fits in the first slot. If not, copy 598 * it to separate buffer that will be holding linearized data. 599 */ 600 push_len = min_t(uint32_t, *packet_len, 601 tx_ring->tx_max_header_size); 602 *header_len = push_len; 603 /* If header is in linear space, just point to socket's data. */ 604 if (likely(push_len <= slot_head_len)) { 605 *push_hdr = NMB(ctx->na, slot); 606 if (unlikely(push_hdr == NULL)) { 607 ena_log_nm(adapter->pdev, ERR, 608 "Slot vaddress is NULL\n"); 609 return (EINVAL); 610 } 611 /* 612 * Otherwise, copy whole portion of header from multiple slots 613 * to intermediate buffer. 614 */ 615 } else { 616 rc = ena_netmap_copy_data(ctx->na, 617 ctx->slots, 618 ctx->nm_i, 619 ctx->lim, 620 push_len, 621 tx_ring->push_buf_intermediate_buf); 622 if (unlikely(rc)) { 623 ena_log_nm(adapter->pdev, ERR, 624 "Failed to copy data from slots to push_buf\n"); 625 return (EINVAL); 626 } 627 628 *push_hdr = tx_ring->push_buf_intermediate_buf; 629 counter_u64_add(tx_ring->tx_stats.llq_buffer_copy, 1); 630 631 delta = push_len - slot_head_len; 632 } 633 634 ena_log_nm(adapter->pdev, DBG, 635 "slot: %d header_buf->vaddr: %p push_len: %d\n", 636 slot->buf_idx, *push_hdr, push_len); 637 638 /* 639 * If header was in linear memory space, map for the dma rest of the data 640 * in the first mbuf of the mbuf chain. 641 */ 642 if (slot_head_len > push_len) { 643 rc = ena_netmap_map_single_slot(ctx->na, 644 slot, 645 adapter->tx_buf_tag, 646 *nm_maps, 647 &vaddr, 648 &paddr); 649 if (unlikely(rc != 0)) { 650 ena_log_nm(adapter->pdev, ERR, 651 "DMA mapping error\n"); 652 return (rc); 653 } 654 nm_maps++; 655 656 ena_buf->paddr = paddr + push_len; 657 ena_buf->len = slot->len - push_len; 658 ena_buf++; 659 660 tx_info->num_of_bufs++; 661 } 662 663 remaining_len -= slot->len; 664 665 /* Save buf idx before advancing */ 666 *nm_buf_idx = slot->buf_idx; 667 nm_buf_idx++; 668 slot->buf_idx = 0; 669 670 /* Advance to the next socket */ 671 ctx->nm_i = nm_next(ctx->nm_i, ctx->lim); 672 slot = &ctx->slots[ctx->nm_i]; 673 nm_info->sockets_used++; 674 675 /* 676 * If header is in non linear space (delta > 0), then skip mbufs 677 * containing header and map the last one containing both header 678 * and the packet data. 679 * The first segment is already counted in. 680 */ 681 while (delta > 0) { 682 __builtin_prefetch(&ctx->slots[ctx->nm_i + 1]); 683 frag_len = slot->len; 684 685 /* 686 * If whole segment contains header just move to the 687 * next one and reduce delta. 688 */ 689 if (unlikely(delta >= frag_len)) { 690 delta -= frag_len; 691 } else { 692 /* 693 * Map the data and then assign it with the 694 * offsets 695 */ 696 rc = ena_netmap_map_single_slot(ctx->na, 697 slot, 698 adapter->tx_buf_tag, 699 *nm_maps, 700 &vaddr, 701 &paddr); 702 if (unlikely(rc != 0)) { 703 ena_log_nm(adapter->pdev, ERR, 704 "DMA mapping error\n"); 705 goto error_map; 706 } 707 nm_maps++; 708 709 ena_buf->paddr = paddr + delta; 710 ena_buf->len = slot->len - delta; 711 ena_buf++; 712 713 tx_info->num_of_bufs++; 714 delta = 0; 715 } 716 717 remaining_len -= slot->len; 718 719 /* Save buf idx before advancing */ 720 *nm_buf_idx = slot->buf_idx; 721 nm_buf_idx++; 722 slot->buf_idx = 0; 723 724 /* Advance to the next socket */ 725 ctx->nm_i = nm_next(ctx->nm_i, ctx->lim); 726 slot = &ctx->slots[ctx->nm_i]; 727 nm_info->sockets_used++; 728 } 729 } else { 730 *push_hdr = NULL; 731 /* 732 * header_len is just a hint for the device. Because netmap is 733 * not giving us any information about packet header length and 734 * it is not guaranteed that all packet headers will be in the 735 * 1st slot, setting header_len to 0 is making the device ignore 736 * this value and resolve header on it's own. 737 */ 738 *header_len = 0; 739 } 740 741 /* Map all remaining data (regular routine for non-LLQ mode) */ 742 while (remaining_len > 0) { 743 __builtin_prefetch(&ctx->slots[ctx->nm_i + 1]); 744 745 rc = ena_netmap_map_single_slot(ctx->na, 746 slot, 747 adapter->tx_buf_tag, 748 *nm_maps, 749 &vaddr, 750 &paddr); 751 if (unlikely(rc != 0)) { 752 ena_log_nm(adapter->pdev, ERR, 753 "DMA mapping error\n"); 754 goto error_map; 755 } 756 nm_maps++; 757 758 ena_buf->paddr = paddr; 759 ena_buf->len = slot->len; 760 ena_buf++; 761 762 tx_info->num_of_bufs++; 763 764 remaining_len -= slot->len; 765 766 /* Save buf idx before advancing */ 767 *nm_buf_idx = slot->buf_idx; 768 nm_buf_idx++; 769 slot->buf_idx = 0; 770 771 /* Advance to the next socket */ 772 ctx->nm_i = nm_next(ctx->nm_i, ctx->lim); 773 slot = &ctx->slots[ctx->nm_i]; 774 nm_info->sockets_used++; 775 } 776 777 return (0); 778 779 error_map: 780 ena_netmap_unmap_last_socket_chain(ctx, tx_info); 781 782 return (rc); 783 } 784 785 static void 786 ena_netmap_unmap_last_socket_chain(struct ena_netmap_ctx *ctx, 787 struct ena_tx_buffer *tx_info) 788 { 789 struct ena_netmap_tx_info *nm_info; 790 int n; 791 792 nm_info = &tx_info->nm_info; 793 794 /** 795 * As the used sockets must not be equal to the buffers used in the LLQ 796 * mode, they must be treated separately. 797 * First, unmap the DMA maps. 798 */ 799 n = tx_info->num_of_bufs; 800 while (n--) { 801 netmap_unload_map(ctx->na, ctx->adapter->tx_buf_tag, 802 nm_info->map_seg[n]); 803 } 804 tx_info->num_of_bufs = 0; 805 806 /* Next, retain the sockets back to the userspace */ 807 n = nm_info->sockets_used; 808 while (n--) { 809 ctx->slots[ctx->nm_i].buf_idx = nm_info->socket_buf_idx[n]; 810 ctx->slots[ctx->nm_i].flags = NS_BUF_CHANGED; 811 nm_info->socket_buf_idx[n] = 0; 812 ctx->nm_i = nm_prev(ctx->nm_i, ctx->lim); 813 } 814 nm_info->sockets_used = 0; 815 } 816 817 static void 818 ena_netmap_tx_cleanup(struct ena_netmap_ctx *ctx) 819 { 820 uint16_t req_id; 821 uint16_t total_tx_descs = 0; 822 823 ctx->nm_i = ctx->kring->nr_hwtail; 824 ctx->nt = ctx->ring->next_to_clean; 825 826 /* Reclaim buffers for completed transmissions */ 827 while (ena_com_tx_comp_req_id_get(ctx->io_cq, &req_id) >= 0) { 828 if (validate_tx_req_id(ctx->ring, req_id) != 0) 829 break; 830 total_tx_descs += ena_netmap_tx_clean_one(ctx, req_id); 831 } 832 833 ctx->kring->nr_hwtail = ctx->nm_i; 834 835 if (total_tx_descs > 0) { 836 /* acknowledge completion of sent packets */ 837 ctx->ring->next_to_clean = ctx->nt; 838 ena_com_comp_ack(ctx->ring->ena_com_io_sq, total_tx_descs); 839 ena_com_update_dev_comp_head(ctx->ring->ena_com_io_cq); 840 } 841 } 842 843 static uint16_t 844 ena_netmap_tx_clean_one(struct ena_netmap_ctx *ctx, uint16_t req_id) 845 { 846 struct ena_tx_buffer *tx_info; 847 struct ena_netmap_tx_info *nm_info; 848 int n; 849 850 tx_info = &ctx->ring->tx_buffer_info[req_id]; 851 nm_info = &tx_info->nm_info; 852 853 /** 854 * As the used sockets must not be equal to the buffers used in the LLQ 855 * mode, they must be treated separately. 856 * First, unmap the DMA maps. 857 */ 858 n = tx_info->num_of_bufs; 859 for (n = 0; n < tx_info->num_of_bufs; n++) { 860 netmap_unload_map(ctx->na, ctx->adapter->tx_buf_tag, 861 nm_info->map_seg[n]); 862 } 863 tx_info->num_of_bufs = 0; 864 865 /* Next, retain the sockets back to the userspace */ 866 for (n = 0; n < nm_info->sockets_used; n++) { 867 ctx->nm_i = nm_next(ctx->nm_i, ctx->lim); 868 ENA_WARN(ctx->slots[ctx->nm_i].buf_idx != 0, 869 ctx->adapter->ena_dev, "Tx idx is not 0.\n"); 870 ctx->slots[ctx->nm_i].buf_idx = nm_info->socket_buf_idx[n]; 871 ctx->slots[ctx->nm_i].flags = NS_BUF_CHANGED; 872 nm_info->socket_buf_idx[n] = 0; 873 } 874 nm_info->sockets_used = 0; 875 876 ctx->ring->free_tx_ids[ctx->nt] = req_id; 877 ctx->nt = ENA_TX_RING_IDX_NEXT(ctx->nt, ctx->lim); 878 879 return tx_info->tx_descs; 880 } 881 882 static inline int 883 validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id) 884 { 885 struct ena_adapter *adapter = tx_ring->adapter; 886 887 if (likely(req_id < tx_ring->ring_size)) 888 return (0); 889 890 ena_log_nm(adapter->pdev, WARN, "Invalid req_id: %hu\n", req_id); 891 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1); 892 893 ena_trigger_reset(adapter, ENA_REGS_RESET_INV_TX_REQ_ID); 894 895 return (EFAULT); 896 } 897 898 static int 899 ena_netmap_rxsync(struct netmap_kring *kring, int flags) 900 { 901 struct ena_netmap_ctx ctx; 902 int rc; 903 904 ena_netmap_fill_ctx(kring, &ctx, ENA_IO_RXQ_IDX(kring->ring_id)); 905 ctx.ring = &ctx.adapter->rx_ring[kring->ring_id]; 906 907 if (ctx.kring->rhead > ctx.lim) { 908 /* Probably not needed to release slots from RX ring. */ 909 return (netmap_ring_reinit(ctx.kring)); 910 } 911 912 if (unlikely((if_getdrvflags(ctx.na->ifp) & IFF_DRV_RUNNING) == 0)) 913 return (0); 914 915 if (unlikely(!ENA_FLAG_ISSET(ENA_FLAG_LINK_UP, ctx.adapter))) 916 return (0); 917 918 if ((rc = ena_netmap_rx_frames(&ctx)) != 0) 919 return (rc); 920 921 ena_netmap_rx_cleanup(&ctx); 922 923 return (0); 924 } 925 926 static inline int 927 ena_netmap_rx_frames(struct ena_netmap_ctx *ctx) 928 { 929 int rc = 0; 930 int frames_counter = 0; 931 932 ctx->nt = ctx->ring->next_to_clean; 933 ctx->nm_i = ctx->kring->nr_hwtail; 934 935 while((rc = ena_netmap_rx_frame(ctx)) == ENA_NETMAP_MORE_FRAMES) { 936 frames_counter++; 937 /* In case of multiple frames, it is not an error. */ 938 rc = 0; 939 if (frames_counter > ENA_MAX_FRAMES) { 940 ena_log_nm(ctx->adapter->pdev, ERR, 941 "Driver is stuck in the Rx loop\n"); 942 break; 943 } 944 }; 945 946 ctx->kring->nr_hwtail = ctx->nm_i; 947 ctx->kring->nr_kflags &= ~NKR_PENDINTR; 948 ctx->ring->next_to_clean = ctx->nt; 949 950 return (rc); 951 } 952 953 static inline int 954 ena_netmap_rx_frame(struct ena_netmap_ctx *ctx) 955 { 956 struct ena_com_rx_ctx ena_rx_ctx; 957 enum ena_regs_reset_reason_types reset_reason; 958 int rc, len = 0; 959 uint16_t buf, nm; 960 961 ena_rx_ctx.ena_bufs = ctx->ring->ena_bufs; 962 ena_rx_ctx.max_bufs = ctx->adapter->max_rx_sgl_size; 963 bus_dmamap_sync(ctx->io_cq->cdesc_addr.mem_handle.tag, 964 ctx->io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_POSTREAD); 965 966 rc = ena_com_rx_pkt(ctx->io_cq, ctx->io_sq, &ena_rx_ctx); 967 if (unlikely(rc != 0)) { 968 ena_log_nm(ctx->adapter->pdev, ERR, 969 "Failed to read pkt from the device with error: %d\n", rc); 970 if (rc == ENA_COM_NO_SPACE) { 971 counter_u64_add(ctx->ring->rx_stats.bad_desc_num, 1); 972 reset_reason = ENA_REGS_RESET_TOO_MANY_RX_DESCS; 973 } else { 974 counter_u64_add(ctx->ring->rx_stats.bad_req_id, 1); 975 reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 976 } 977 ena_trigger_reset(ctx->adapter, reset_reason); 978 return (rc); 979 } 980 if (unlikely(ena_rx_ctx.descs == 0)) 981 return (ENA_NETMAP_NO_MORE_FRAMES); 982 983 ena_log_nm(ctx->adapter->pdev, DBG, 984 "Rx: q %d got packet from ena. descs #:" 985 " %d l3 proto %d l4 proto %d hash: %x\n", ctx->ring->qid, 986 ena_rx_ctx.descs, ena_rx_ctx.l3_proto, ena_rx_ctx.l4_proto, 987 ena_rx_ctx.hash); 988 989 for (buf = 0; buf < ena_rx_ctx.descs; buf++) 990 if ((rc = ena_netmap_rx_load_desc(ctx, buf, &len)) != 0) 991 break; 992 /* 993 * ena_netmap_rx_load_desc doesn't know the number of descriptors. 994 * It just set flag NS_MOREFRAG to all slots, then here flag of 995 * last slot is cleared. 996 */ 997 ctx->slots[nm_prev(ctx->nm_i, ctx->lim)].flags = NS_BUF_CHANGED; 998 999 if (rc != 0) { 1000 goto rx_clear_desc; 1001 } 1002 1003 bus_dmamap_sync(ctx->io_cq->cdesc_addr.mem_handle.tag, 1004 ctx->io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_PREREAD); 1005 1006 counter_enter(); 1007 counter_u64_add_protected(ctx->ring->rx_stats.bytes, len); 1008 counter_u64_add_protected(ctx->adapter->hw_stats.rx_bytes, len); 1009 counter_u64_add_protected(ctx->ring->rx_stats.cnt, 1); 1010 counter_u64_add_protected(ctx->adapter->hw_stats.rx_packets, 1); 1011 counter_exit(); 1012 1013 return (ENA_NETMAP_MORE_FRAMES); 1014 1015 rx_clear_desc: 1016 nm = ctx->nm_i; 1017 1018 /* Remove failed packet from ring */ 1019 while(buf--) { 1020 ctx->slots[nm].flags = 0; 1021 ctx->slots[nm].len = 0; 1022 nm = nm_prev(nm, ctx->lim); 1023 } 1024 1025 return (rc); 1026 } 1027 1028 static inline int 1029 ena_netmap_rx_load_desc(struct ena_netmap_ctx *ctx, uint16_t buf, int *len) 1030 { 1031 struct ena_rx_buffer *rx_info; 1032 uint16_t req_id; 1033 1034 req_id = ctx->ring->ena_bufs[buf].req_id; 1035 rx_info = &ctx->ring->rx_buffer_info[req_id]; 1036 bus_dmamap_sync(ctx->adapter->rx_buf_tag, rx_info->map, 1037 BUS_DMASYNC_POSTREAD); 1038 netmap_unload_map(ctx->na, ctx->adapter->rx_buf_tag, rx_info->map); 1039 1040 ENA_WARN(ctx->slots[ctx->nm_i].buf_idx != 0, ctx->adapter->ena_dev, 1041 "Rx idx is not 0.\n"); 1042 1043 ctx->slots[ctx->nm_i].buf_idx = rx_info->netmap_buf_idx; 1044 rx_info->netmap_buf_idx = 0; 1045 /* 1046 * Set NS_MOREFRAG to all slots. 1047 * Then ena_netmap_rx_frame clears it from last one. 1048 */ 1049 ctx->slots[ctx->nm_i].flags |= NS_MOREFRAG | NS_BUF_CHANGED; 1050 ctx->slots[ctx->nm_i].len = ctx->ring->ena_bufs[buf].len; 1051 *len += ctx->slots[ctx->nm_i].len; 1052 ctx->ring->free_rx_ids[ctx->nt] = req_id; 1053 ena_log_nm(ctx->adapter->pdev, DBG, "rx_info %p, buf_idx %d, paddr %jx, nm: %d\n", 1054 rx_info, ctx->slots[ctx->nm_i].buf_idx, 1055 (uintmax_t)rx_info->ena_buf.paddr, ctx->nm_i); 1056 1057 ctx->nm_i = nm_next(ctx->nm_i, ctx->lim); 1058 ctx->nt = ENA_RX_RING_IDX_NEXT(ctx->nt, ctx->ring->ring_size); 1059 1060 return (0); 1061 } 1062 1063 static inline void 1064 ena_netmap_rx_cleanup(struct ena_netmap_ctx *ctx) 1065 { 1066 int refill_required; 1067 1068 refill_required = ctx->kring->rhead - ctx->kring->nr_hwcur; 1069 if (ctx->kring->nr_hwcur != ctx->kring->nr_hwtail) 1070 refill_required -= 1; 1071 1072 if (refill_required == 0) 1073 return; 1074 else if (refill_required < 0) 1075 refill_required += ctx->kring->nkr_num_slots; 1076 1077 ena_refill_rx_bufs(ctx->ring, refill_required); 1078 } 1079 1080 static inline void 1081 ena_netmap_fill_ctx(struct netmap_kring *kring, struct ena_netmap_ctx *ctx, 1082 uint16_t ena_qid) 1083 { 1084 ctx->kring = kring; 1085 ctx->na = kring->na; 1086 ctx->adapter = ctx->na->ifp->if_softc; 1087 ctx->lim = kring->nkr_num_slots - 1; 1088 ctx->io_cq = &ctx->adapter->ena_dev->io_cq_queues[ena_qid]; 1089 ctx->io_sq = &ctx->adapter->ena_dev->io_sq_queues[ena_qid]; 1090 ctx->slots = kring->ring->slot; 1091 } 1092 1093 void 1094 ena_netmap_unload(struct ena_adapter *adapter, bus_dmamap_t map) 1095 { 1096 struct netmap_adapter *na = NA(adapter->ifp); 1097 1098 netmap_unload_map(na, adapter->tx_buf_tag, map); 1099 } 1100 1101 #endif /* DEV_NETMAP */ 1102