1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 * 32 */ 33 34 #ifndef ENA_H 35 #define ENA_H 36 37 #include <sys/types.h> 38 39 #include "ena-com/ena_com.h" 40 #include "ena-com/ena_eth_com.h" 41 42 #define DRV_MODULE_VER_MAJOR 0 43 #define DRV_MODULE_VER_MINOR 7 44 #define DRV_MODULE_VER_SUBMINOR 0 45 46 #define DRV_MODULE_NAME "ena" 47 48 #ifndef DRV_MODULE_VERSION 49 #define DRV_MODULE_VERSION \ 50 __XSTRING(DRV_MODULE_VER_MAJOR) "." \ 51 __XSTRING(DRV_MODULE_VER_MINOR) "." \ 52 __XSTRING(DRV_MODULE_VER_SUBMINOR) 53 #endif 54 #define DEVICE_NAME "Elastic Network Adapter (ENA)" 55 #define DEVICE_DESC "ENA adapter" 56 57 /* Calculate DMA mask - width for ena cannot exceed 48, so it is safe */ 58 #define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL) 59 60 /* 1 for AENQ + ADMIN */ 61 #define ENA_MAX_MSIX_VEC(io_queues) (1 + (io_queues)) 62 63 #define ENA_REG_BAR 0 64 #define ENA_MEM_BAR 2 65 66 #define ENA_BUS_DMA_SEGS 32 67 68 #define ENA_DEFAULT_RING_SIZE 1024 69 #define ENA_DEFAULT_SMALL_PACKET_LEN 128 70 #define ENA_DEFAULT_MAX_RX_BUFF_ALLOC_SIZE 1536 71 72 #define ENA_RX_REFILL_THRESH_DEVIDER 8 73 74 #define ENA_MAX_PUSH_PKT_SIZE 128 75 76 #define ENA_NAME_MAX_LEN 20 77 #define ENA_IRQNAME_SIZE 40 78 79 #define ENA_PKT_MAX_BUFS 19 80 #define ENA_STALL_TIMEOUT 100 81 82 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 83 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 84 85 #define ENA_HASH_KEY_SIZE 40 86 87 #define ENA_DMA_BITS_MASK 40 88 #define ENA_MAX_FRAME_LEN 10000 89 #define ENA_MIN_FRAME_LEN 60 90 #define ENA_RX_HASH_KEY_NUM 10 91 #define ENA_RX_THASH_TABLE_SIZE (1 << 8) 92 93 #define ENA_TX_CLEANUP_TRESHOLD 128 94 95 #define DB_THRESHOLD 64 96 97 #define TX_COMMIT 32 98 /* 99 * TX budget for cleaning. It should be half of the RX budget to reduce amount 100 * of TCP retransmissions. 101 */ 102 #define TX_BUDGET 128 103 /* RX cleanup budget. -1 stands for infinity. */ 104 #define RX_BUDGET 256 105 /* 106 * How many times we can repeat cleanup in the io irq handling routine if the 107 * RX or TX budget was depleted. 108 */ 109 #define CLEAN_BUDGET 8 110 111 #define RX_IRQ_INTERVAL 20 112 #define TX_IRQ_INTERVAL 50 113 114 #define ENA_MAX_MTU 9216 115 #define ENA_TSO_MAXSIZE PAGE_SIZE 116 #define ENA_TSO_NSEGS ENA_PKT_MAX_BUFS 117 #define ENA_RX_OFFSET NET_SKB_PAD + NET_IP_ALIGN 118 119 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 120 121 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 122 123 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 124 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \ 125 (((idx) + (n)) & ((ring_size) - 1)) 126 127 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 128 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 129 130 #define ENA_MGMNT_IRQ_IDX 0 131 #define ENA_IO_IRQ_FIRST_IDX 1 132 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 133 134 /* 135 * ENA device should send keep alive msg every 1 sec. 136 * We wait for 6 sec just to be on the safe side. 137 */ 138 #define DEFAULT_KEEP_ALIVE_TO (SBT_1S * 6) 139 140 /* Time in jiffies before concluding the transmitter is hung. */ 141 #define DEFAULT_TX_CMP_TO (SBT_1S * 5) 142 143 /* Number of queues to check for missing queues per timer tick */ 144 #define DEFAULT_TX_MONITORED_QUEUES (4) 145 146 /* Max number of timeouted packets before device reset */ 147 #define DEFAULT_TX_CMP_THRESHOLD (128) 148 149 /* 150 * Supported PCI vendor and devices IDs 151 */ 152 #define PCI_VENDOR_ID_AMAZON 0x1d0f 153 154 #define PCI_DEV_ID_ENA_PF 0x0ec2 155 #define PCI_DEV_ID_ENA_LLQ_PF 0x1ec2 156 #define PCI_DEV_ID_ENA_VF 0xec20 157 #define PCI_DEV_ID_ENA_LLQ_VF 0xec21 158 159 struct msix_entry { 160 int entry; 161 int vector; 162 }; 163 164 typedef struct _ena_vendor_info_t { 165 unsigned int vendor_id; 166 unsigned int device_id; 167 unsigned int index; 168 } ena_vendor_info_t; 169 170 struct ena_irq { 171 /* Interrupt resources */ 172 struct resource *res; 173 driver_intr_t *handler; 174 void *data; 175 void *cookie; 176 unsigned int vector; 177 bool requested; 178 int cpu; 179 char name[ENA_IRQNAME_SIZE]; 180 }; 181 182 struct ena_que { 183 struct ena_adapter *adapter; 184 struct ena_ring *tx_ring; 185 struct ena_ring *rx_ring; 186 uint32_t id; 187 int cpu; 188 }; 189 190 struct ena_tx_buffer { 191 struct mbuf *mbuf; 192 /* # of ena desc for this specific mbuf 193 * (includes data desc and metadata desc) */ 194 unsigned int tx_descs; 195 /* # of buffers used by this mbuf */ 196 unsigned int num_of_bufs; 197 bus_dmamap_t map; 198 199 /* Used to detect missing tx packets */ 200 struct bintime timestamp; 201 bool print_once; 202 203 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 204 } __aligned(CACHE_LINE_SIZE); 205 206 struct ena_rx_buffer { 207 struct mbuf *mbuf; 208 bus_dmamap_t map; 209 struct ena_com_buf ena_buf; 210 } __aligned(CACHE_LINE_SIZE); 211 212 213 struct ena_stats_tx { 214 counter_u64_t cnt; 215 counter_u64_t bytes; 216 counter_u64_t queue_stop; 217 counter_u64_t prepare_ctx_err; 218 counter_u64_t queue_wakeup; 219 counter_u64_t dma_mapping_err; 220 /* Not counted */ 221 counter_u64_t unsupported_desc_num; 222 /* Not counted */ 223 counter_u64_t napi_comp; 224 /* Not counted */ 225 counter_u64_t tx_poll; 226 counter_u64_t doorbells; 227 counter_u64_t missing_tx_comp; 228 counter_u64_t bad_req_id; 229 }; 230 231 struct ena_stats_rx { 232 counter_u64_t cnt; 233 counter_u64_t bytes; 234 counter_u64_t refil_partial; 235 counter_u64_t bad_csum; 236 /* Not counted */ 237 counter_u64_t page_alloc_fail; 238 counter_u64_t mbuf_alloc_fail; 239 counter_u64_t dma_mapping_err; 240 counter_u64_t bad_desc_num; 241 /* Not counted */ 242 counter_u64_t small_copy_len_pkt; 243 }; 244 245 246 struct ena_ring { 247 /* Holds the empty requests for TX out of order completions */ 248 uint16_t *free_tx_ids; 249 struct ena_com_dev *ena_dev; 250 struct ena_adapter *adapter; 251 struct ena_com_io_cq *ena_com_io_cq; 252 struct ena_com_io_sq *ena_com_io_sq; 253 254 /* The maximum length the driver can push to the device (For LLQ) */ 255 enum ena_admin_placement_policy_type tx_mem_queue_type; 256 uint16_t rx_small_copy_len; 257 uint16_t qid; 258 uint16_t mtu; 259 uint8_t tx_max_header_size; 260 261 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 262 uint32_t smoothed_interval; 263 enum ena_intr_moder_level moder_tbl_idx; 264 265 struct ena_que *que; 266 struct lro_ctrl lro; 267 268 uint16_t next_to_use; 269 uint16_t next_to_clean; 270 271 union { 272 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 273 struct ena_rx_buffer *rx_buffer_info; /* contex of rx packet */ 274 }; 275 int ring_size; /* number of tx/rx_buffer_info's entries */ 276 277 struct buf_ring *br; /* only for TX */ 278 struct mtx ring_mtx; 279 char mtx_name[16]; 280 struct task enqueue_task; 281 struct taskqueue *enqueue_tq; 282 struct task cmpl_task; 283 struct taskqueue *cmpl_tq; 284 285 union { 286 struct ena_stats_tx tx_stats; 287 struct ena_stats_rx rx_stats; 288 }; 289 290 } __aligned(CACHE_LINE_SIZE); 291 292 struct ena_stats_dev { 293 /* Not counted */ 294 counter_u64_t tx_timeout; 295 /* Not counted */ 296 counter_u64_t io_suspend; 297 /* Not counted */ 298 counter_u64_t io_resume; 299 /* Not counted */ 300 counter_u64_t wd_expired; 301 counter_u64_t interface_up; 302 counter_u64_t interface_down; 303 /* Not counted */ 304 counter_u64_t admin_q_pause; 305 }; 306 307 struct ena_hw_stats { 308 uint64_t rx_packets; 309 uint64_t tx_packets; 310 311 uint64_t rx_bytes; 312 uint64_t tx_bytes; 313 314 uint64_t rx_drops; 315 }; 316 317 /* Board specific private data structure */ 318 struct ena_adapter { 319 struct ena_com_dev *ena_dev; 320 321 /* OS defined structs */ 322 if_t ifp; 323 device_t pdev; 324 struct ifmedia media; 325 326 /* OS resources */ 327 struct resource * memory; 328 struct resource * registers; 329 330 struct mtx global_mtx; 331 struct sx ioctl_sx; 332 333 /* MSI-X */ 334 uint32_t msix_enabled; 335 struct msix_entry *msix_entries; 336 int msix_vecs; 337 338 /* DMA tags used throughout the driver adapter for Tx and Rx */ 339 bus_dma_tag_t tx_buf_tag; 340 bus_dma_tag_t rx_buf_tag; 341 int dma_width; 342 /* 343 * RX packets that shorter that this len will be copied to the skb 344 * header 345 */ 346 unsigned int small_copy_len; 347 348 uint16_t max_tx_sgl_size; 349 uint16_t max_rx_sgl_size; 350 351 uint32_t tx_offload_cap; 352 353 /* Tx fast path data */ 354 int num_queues; 355 356 unsigned int tx_usecs, rx_usecs; /* Interrupt coalescing */ 357 358 unsigned int tx_ring_size; 359 unsigned int rx_ring_size; 360 361 /* RSS*/ 362 uint8_t rss_ind_tbl[ENA_RX_RSS_TABLE_SIZE]; 363 bool rss_support; 364 365 uint32_t msg_enable; 366 367 uint8_t mac_addr[ETHER_ADDR_LEN]; 368 /* mdio and phy*/ 369 370 char name[ENA_NAME_MAX_LEN]; 371 bool link_status; 372 bool trigger_reset; 373 bool up; 374 bool running; 375 376 uint32_t wol; 377 378 /* Queue will represent one TX and one RX ring */ 379 struct ena_que que[ENA_MAX_NUM_IO_QUEUES] 380 __aligned(CACHE_LINE_SIZE); 381 382 /* TX */ 383 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 384 __aligned(CACHE_LINE_SIZE); 385 386 /* RX */ 387 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 388 __aligned(CACHE_LINE_SIZE); 389 390 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 391 392 /* Timer service */ 393 struct callout timer_service; 394 sbintime_t keep_alive_timestamp; 395 uint32_t next_monitored_tx_qid; 396 struct task reset_task; 397 struct taskqueue *reset_tq; 398 int wd_active; 399 sbintime_t keep_alive_timeout; 400 sbintime_t missing_tx_timeout; 401 uint32_t missing_tx_max_queues; 402 uint32_t missing_tx_threshold; 403 404 /* Statistics */ 405 struct ena_stats_dev dev_stats; 406 struct ena_hw_stats hw_stats; 407 }; 408 409 410 #define ENA_DEV_LOCK mtx_lock(&adapter->global_mtx) 411 #define ENA_DEV_UNLOCK mtx_unlock(&adapter->global_mtx) 412 413 #define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx) 414 #define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx) 415 #define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx) 416 417 struct ena_dev *ena_efa_enadev_get(device_t pdev); 418 419 int ena_register_adapter(struct ena_adapter *adapter); 420 void ena_unregister_adapter(struct ena_adapter *adapter); 421 422 int ena_update_stats_counters(struct ena_adapter *adapter); 423 424 static inline int ena_mbuf_count(struct mbuf *mbuf) 425 { 426 int count = 1; 427 428 while ((mbuf = mbuf->m_next) != NULL) 429 ++count; 430 431 return count; 432 } 433 434 #endif /* !(ENA_H) */ 435