1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/kthread.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/smp.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 #include <sys/time.h> 49 #include <sys/eventhandler.h> 50 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <machine/in_cksum.h> 54 55 #include <net/bpf.h> 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_arp.h> 60 #include <net/if_dl.h> 61 #include <net/if_media.h> 62 #include <net/rss_config.h> 63 #include <net/if_types.h> 64 #include <net/if_vlan_var.h> 65 66 #include <netinet/in_rss.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in.h> 69 #include <netinet/if_ether.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/udp.h> 74 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/pcireg.h> 77 78 #include "ena.h" 79 #include "ena_sysctl.h" 80 81 /********************************************************* 82 * Function prototypes 83 *********************************************************/ 84 static int ena_probe(device_t); 85 static void ena_intr_msix_mgmnt(void *); 86 static int ena_allocate_pci_resources(struct ena_adapter*); 87 static void ena_free_pci_resources(struct ena_adapter *); 88 static int ena_change_mtu(if_t, int); 89 static inline void ena_alloc_counters(counter_u64_t *, int); 90 static inline void ena_free_counters(counter_u64_t *, int); 91 static inline void ena_reset_counters(counter_u64_t *, int); 92 static void ena_init_io_rings_common(struct ena_adapter *, 93 struct ena_ring *, uint16_t); 94 static void ena_init_io_rings(struct ena_adapter *); 95 static void ena_free_io_ring_resources(struct ena_adapter *, unsigned int); 96 static void ena_free_all_io_rings_resources(struct ena_adapter *); 97 static int ena_setup_tx_dma_tag(struct ena_adapter *); 98 static int ena_free_tx_dma_tag(struct ena_adapter *); 99 static int ena_setup_rx_dma_tag(struct ena_adapter *); 100 static int ena_free_rx_dma_tag(struct ena_adapter *); 101 static int ena_setup_tx_resources(struct ena_adapter *, int); 102 static void ena_free_tx_resources(struct ena_adapter *, int); 103 static int ena_setup_all_tx_resources(struct ena_adapter *); 104 static void ena_free_all_tx_resources(struct ena_adapter *); 105 static inline int validate_rx_req_id(struct ena_ring *, uint16_t); 106 static int ena_setup_rx_resources(struct ena_adapter *, unsigned int); 107 static void ena_free_rx_resources(struct ena_adapter *, unsigned int); 108 static int ena_setup_all_rx_resources(struct ena_adapter *); 109 static void ena_free_all_rx_resources(struct ena_adapter *); 110 static inline int ena_alloc_rx_mbuf(struct ena_adapter *, struct ena_ring *, 111 struct ena_rx_buffer *); 112 static void ena_free_rx_mbuf(struct ena_adapter *, struct ena_ring *, 113 struct ena_rx_buffer *); 114 static int ena_refill_rx_bufs(struct ena_ring *, uint32_t); 115 static void ena_free_rx_bufs(struct ena_adapter *, unsigned int); 116 static void ena_refill_all_rx_bufs(struct ena_adapter *); 117 static void ena_free_all_rx_bufs(struct ena_adapter *); 118 static void ena_free_tx_bufs(struct ena_adapter *, unsigned int); 119 static void ena_free_all_tx_bufs(struct ena_adapter *); 120 static void ena_destroy_all_tx_queues(struct ena_adapter *); 121 static void ena_destroy_all_rx_queues(struct ena_adapter *); 122 static void ena_destroy_all_io_queues(struct ena_adapter *); 123 static int ena_create_io_queues(struct ena_adapter *); 124 static int ena_tx_cleanup(struct ena_ring *); 125 static void ena_deferred_rx_cleanup(void *, int); 126 static int ena_rx_cleanup(struct ena_ring *); 127 static inline int validate_tx_req_id(struct ena_ring *, uint16_t); 128 static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *, 129 struct mbuf *); 130 static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *, 131 struct ena_com_rx_ctx *, uint16_t *); 132 static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *, 133 struct mbuf *); 134 static void ena_handle_msix(void *); 135 static int ena_enable_msix(struct ena_adapter *); 136 static void ena_setup_mgmnt_intr(struct ena_adapter *); 137 static void ena_setup_io_intr(struct ena_adapter *); 138 static int ena_request_mgmnt_irq(struct ena_adapter *); 139 static int ena_request_io_irq(struct ena_adapter *); 140 static void ena_free_mgmnt_irq(struct ena_adapter *); 141 static void ena_free_io_irq(struct ena_adapter *); 142 static void ena_free_irqs(struct ena_adapter*); 143 static void ena_disable_msix(struct ena_adapter *); 144 static void ena_unmask_all_io_irqs(struct ena_adapter *); 145 static int ena_rss_configure(struct ena_adapter *); 146 static int ena_up_complete(struct ena_adapter *); 147 static int ena_up(struct ena_adapter *); 148 static void ena_down(struct ena_adapter *); 149 static uint64_t ena_get_counter(if_t, ift_counter); 150 static int ena_media_change(if_t); 151 static void ena_media_status(if_t, struct ifmediareq *); 152 static void ena_init(void *); 153 static int ena_ioctl(if_t, u_long, caddr_t); 154 static int ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *); 155 static void ena_update_host_info(struct ena_admin_host_info *, if_t); 156 static void ena_update_hwassist(struct ena_adapter *); 157 static int ena_setup_ifnet(device_t, struct ena_adapter *, 158 struct ena_com_dev_get_features_ctx *); 159 static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *); 160 static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, 161 struct mbuf **mbuf); 162 static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **); 163 static void ena_start_xmit(struct ena_ring *); 164 static int ena_mq_start(if_t, struct mbuf *); 165 static void ena_deferred_mq_start(void *, int); 166 static void ena_qflush(if_t); 167 static int ena_calc_io_queue_num(struct ena_adapter *, 168 struct ena_com_dev_get_features_ctx *); 169 static int ena_calc_queue_size(struct ena_adapter *, uint16_t *, 170 uint16_t *, struct ena_com_dev_get_features_ctx *); 171 static int ena_rss_init_default(struct ena_adapter *); 172 static void ena_rss_init_default_deferred(void *); 173 static void ena_config_host_info(struct ena_com_dev *); 174 static int ena_attach(device_t); 175 static int ena_detach(device_t); 176 static int ena_device_init(struct ena_adapter *, device_t, 177 struct ena_com_dev_get_features_ctx *, int *); 178 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *, 179 int); 180 static void ena_update_on_link_change(void *, struct ena_admin_aenq_entry *); 181 static void unimplemented_aenq_handler(void *, 182 struct ena_admin_aenq_entry *); 183 static void ena_timer_service(void *); 184 185 static char ena_version[] = DEVICE_NAME DRV_MODULE_NAME " v" DRV_MODULE_VERSION; 186 187 static SYSCTL_NODE(_hw, OID_AUTO, ena, CTLFLAG_RD, 0, "ENA driver parameters"); 188 189 /* 190 * Tuneable number of buffers in the buf-ring (drbr) 191 */ 192 static int ena_buf_ring_size = 4096; 193 SYSCTL_INT(_hw_ena, OID_AUTO, buf_ring_size, CTLFLAG_RWTUN, 194 &ena_buf_ring_size, 0, "Size of the bufring"); 195 196 /* 197 * Logging level for changing verbosity of the output 198 */ 199 int ena_log_level = ENA_ALERT | ENA_WARNING; 200 SYSCTL_INT(_hw_ena, OID_AUTO, log_level, CTLFLAG_RWTUN, 201 &ena_log_level, 0, "Logging level indicating verbosity of the logs"); 202 203 static ena_vendor_info_t ena_vendor_info_array[] = { 204 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_PF, 0}, 205 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_PF, 0}, 206 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_VF, 0}, 207 { PCI_VENDOR_ID_AMAZON, PCI_DEV_ID_ENA_LLQ_VF, 0}, 208 /* Last entry */ 209 { 0, 0, 0 } 210 }; 211 212 /* 213 * Contains pointers to event handlers, e.g. link state chage. 214 */ 215 static struct ena_aenq_handlers aenq_handlers; 216 217 void 218 ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error) 219 { 220 if (error != 0) 221 return; 222 *(bus_addr_t *) arg = segs[0].ds_addr; 223 } 224 225 int 226 ena_dma_alloc(device_t dmadev, bus_size_t size, 227 ena_mem_handle_t *dma , int mapflags) 228 { 229 struct ena_adapter* adapter = device_get_softc(dmadev); 230 uint32_t maxsize; 231 uint64_t dma_space_addr; 232 int error; 233 234 maxsize = ((size - 1) / PAGE_SIZE + 1) * PAGE_SIZE; 235 236 dma_space_addr = ENA_DMA_BIT_MASK(adapter->dma_width); 237 if (unlikely(dma_space_addr == 0)) 238 dma_space_addr = BUS_SPACE_MAXADDR; 239 240 error = bus_dma_tag_create(bus_get_dma_tag(dmadev), /* parent */ 241 8, 0, /* alignment, bounds */ 242 dma_space_addr, /* lowaddr of exclusion window */ 243 BUS_SPACE_MAXADDR,/* highaddr of exclusion window */ 244 NULL, NULL, /* filter, filterarg */ 245 maxsize, /* maxsize */ 246 1, /* nsegments */ 247 maxsize, /* maxsegsize */ 248 BUS_DMA_ALLOCNOW, /* flags */ 249 NULL, /* lockfunc */ 250 NULL, /* lockarg */ 251 &dma->tag); 252 if (unlikely(error != 0)) { 253 ena_trace(ENA_ALERT, "bus_dma_tag_create failed: %d\n", error); 254 goto fail_tag; 255 } 256 257 error = bus_dmamem_alloc(dma->tag, (void**) &dma->vaddr, 258 BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->map); 259 if (unlikely(error != 0)) { 260 ena_trace(ENA_ALERT, "bus_dmamem_alloc(%ju) failed: %d\n", 261 (uintmax_t)size, error); 262 goto fail_map_create; 263 } 264 265 dma->paddr = 0; 266 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, 267 size, ena_dmamap_callback, &dma->paddr, mapflags); 268 if (unlikely((error != 0) || (dma->paddr == 0))) { 269 ena_trace(ENA_ALERT, ": bus_dmamap_load failed: %d\n", error); 270 goto fail_map_load; 271 } 272 273 return (0); 274 275 fail_map_load: 276 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 277 fail_map_create: 278 bus_dma_tag_destroy(dma->tag); 279 fail_tag: 280 dma->tag = NULL; 281 282 return (error); 283 } 284 285 static int 286 ena_allocate_pci_resources(struct ena_adapter* adapter) 287 { 288 device_t pdev = adapter->pdev; 289 int rid; 290 291 rid = PCIR_BAR(ENA_REG_BAR); 292 adapter->memory = NULL; 293 adapter->registers = bus_alloc_resource_any(pdev, SYS_RES_MEMORY, 294 &rid, RF_ACTIVE); 295 if (unlikely(adapter->registers == NULL)) { 296 device_printf(pdev, "Unable to allocate bus resource: " 297 "registers\n"); 298 return (ENXIO); 299 } 300 301 return (0); 302 } 303 304 static void 305 ena_free_pci_resources(struct ena_adapter *adapter) 306 { 307 device_t pdev = adapter->pdev; 308 309 if (adapter->memory != NULL) { 310 bus_release_resource(pdev, SYS_RES_MEMORY, 311 PCIR_BAR(ENA_MEM_BAR), adapter->memory); 312 } 313 314 if (adapter->registers != NULL) { 315 bus_release_resource(pdev, SYS_RES_MEMORY, 316 PCIR_BAR(ENA_REG_BAR), adapter->registers); 317 } 318 } 319 320 static int 321 ena_probe(device_t dev) 322 { 323 ena_vendor_info_t *ent; 324 char adapter_name[60]; 325 uint16_t pci_vendor_id = 0; 326 uint16_t pci_device_id = 0; 327 328 pci_vendor_id = pci_get_vendor(dev); 329 pci_device_id = pci_get_device(dev); 330 331 ent = ena_vendor_info_array; 332 while (ent->vendor_id != 0) { 333 if ((pci_vendor_id == ent->vendor_id) && 334 (pci_device_id == ent->device_id)) { 335 ena_trace(ENA_DBG, "vendor=%x device=%x ", 336 pci_vendor_id, pci_device_id); 337 338 sprintf(adapter_name, DEVICE_DESC); 339 device_set_desc_copy(dev, adapter_name); 340 return (BUS_PROBE_DEFAULT); 341 } 342 343 ent++; 344 345 } 346 347 return (ENXIO); 348 } 349 350 static int 351 ena_change_mtu(if_t ifp, int new_mtu) 352 { 353 struct ena_adapter *adapter = if_getsoftc(ifp); 354 int rc; 355 356 if ((new_mtu > adapter->max_mtu) || (new_mtu < ENA_MIN_MTU)) { 357 device_printf(adapter->pdev, "Invalid MTU setting. " 358 "new_mtu: %d max mtu: %d min mtu: %d\n", 359 new_mtu, adapter->max_mtu, ENA_MIN_MTU); 360 return (EINVAL); 361 } 362 363 rc = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu); 364 if (likely(rc == 0)) { 365 ena_trace(ENA_DBG, "set MTU to %d\n", new_mtu); 366 if_setmtu(ifp, new_mtu); 367 } else { 368 device_printf(adapter->pdev, "Failed to set MTU to %d\n", 369 new_mtu); 370 } 371 372 return (rc); 373 } 374 375 static inline void 376 ena_alloc_counters(counter_u64_t *begin, int size) 377 { 378 counter_u64_t *end = (counter_u64_t *)((char *)begin + size); 379 380 for (; begin < end; ++begin) 381 *begin = counter_u64_alloc(M_WAITOK); 382 } 383 384 static inline void 385 ena_free_counters(counter_u64_t *begin, int size) 386 { 387 counter_u64_t *end = (counter_u64_t *)((char *)begin + size); 388 389 for (; begin < end; ++begin) 390 counter_u64_free(*begin); 391 } 392 393 static inline void 394 ena_reset_counters(counter_u64_t *begin, int size) 395 { 396 counter_u64_t *end = (counter_u64_t *)((char *)begin + size); 397 398 for (; begin < end; ++begin) 399 counter_u64_zero(*begin); 400 } 401 402 static void 403 ena_init_io_rings_common(struct ena_adapter *adapter, struct ena_ring *ring, 404 uint16_t qid) 405 { 406 407 ring->qid = qid; 408 ring->adapter = adapter; 409 ring->ena_dev = adapter->ena_dev; 410 } 411 412 static void 413 ena_init_io_rings(struct ena_adapter *adapter) 414 { 415 struct ena_com_dev *ena_dev; 416 struct ena_ring *txr, *rxr; 417 struct ena_que *que; 418 int i; 419 420 ena_dev = adapter->ena_dev; 421 422 for (i = 0; i < adapter->num_queues; i++) { 423 txr = &adapter->tx_ring[i]; 424 rxr = &adapter->rx_ring[i]; 425 426 /* TX/RX common ring state */ 427 ena_init_io_rings_common(adapter, txr, i); 428 ena_init_io_rings_common(adapter, rxr, i); 429 430 /* TX specific ring state */ 431 txr->ring_size = adapter->tx_ring_size; 432 txr->tx_max_header_size = ena_dev->tx_max_header_size; 433 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type; 434 txr->smoothed_interval = 435 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev); 436 437 /* Allocate a buf ring */ 438 txr->br = buf_ring_alloc(ena_buf_ring_size, M_DEVBUF, 439 M_WAITOK, &txr->ring_mtx); 440 441 /* Alloc TX statistics. */ 442 ena_alloc_counters((counter_u64_t *)&txr->tx_stats, 443 sizeof(txr->tx_stats)); 444 445 /* RX specific ring state */ 446 rxr->ring_size = adapter->rx_ring_size; 447 rxr->smoothed_interval = 448 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev); 449 450 /* Alloc RX statistics. */ 451 ena_alloc_counters((counter_u64_t *)&rxr->rx_stats, 452 sizeof(rxr->rx_stats)); 453 454 /* Initialize locks */ 455 snprintf(txr->mtx_name, nitems(txr->mtx_name), "%s:tx(%d)", 456 device_get_nameunit(adapter->pdev), i); 457 snprintf(rxr->mtx_name, nitems(rxr->mtx_name), "%s:rx(%d)", 458 device_get_nameunit(adapter->pdev), i); 459 460 mtx_init(&txr->ring_mtx, txr->mtx_name, NULL, MTX_DEF); 461 mtx_init(&rxr->ring_mtx, rxr->mtx_name, NULL, MTX_DEF); 462 463 que = &adapter->que[i]; 464 que->adapter = adapter; 465 que->id = i; 466 que->tx_ring = txr; 467 que->rx_ring = rxr; 468 469 txr->que = que; 470 rxr->que = que; 471 472 rxr->empty_rx_queue = 0; 473 } 474 } 475 476 static void 477 ena_free_io_ring_resources(struct ena_adapter *adapter, unsigned int qid) 478 { 479 struct ena_ring *txr = &adapter->tx_ring[qid]; 480 struct ena_ring *rxr = &adapter->rx_ring[qid]; 481 482 ena_free_counters((counter_u64_t *)&txr->tx_stats, 483 sizeof(txr->tx_stats)); 484 ena_free_counters((counter_u64_t *)&rxr->rx_stats, 485 sizeof(rxr->rx_stats)); 486 487 ENA_RING_MTX_LOCK(txr); 488 drbr_free(txr->br, M_DEVBUF); 489 ENA_RING_MTX_UNLOCK(txr); 490 491 mtx_destroy(&txr->ring_mtx); 492 mtx_destroy(&rxr->ring_mtx); 493 } 494 495 static void 496 ena_free_all_io_rings_resources(struct ena_adapter *adapter) 497 { 498 int i; 499 500 for (i = 0; i < adapter->num_queues; i++) 501 ena_free_io_ring_resources(adapter, i); 502 503 } 504 505 static int 506 ena_setup_tx_dma_tag(struct ena_adapter *adapter) 507 { 508 int ret; 509 510 /* Create DMA tag for Tx buffers */ 511 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), 512 1, 0, /* alignment, bounds */ 513 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 514 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 515 NULL, NULL, /* filter, filterarg */ 516 ENA_TSO_MAXSIZE, /* maxsize */ 517 adapter->max_tx_sgl_size - 1, /* nsegments */ 518 ENA_TSO_MAXSIZE, /* maxsegsize */ 519 0, /* flags */ 520 NULL, /* lockfunc */ 521 NULL, /* lockfuncarg */ 522 &adapter->tx_buf_tag); 523 524 return (ret); 525 } 526 527 static int 528 ena_free_tx_dma_tag(struct ena_adapter *adapter) 529 { 530 int ret; 531 532 ret = bus_dma_tag_destroy(adapter->tx_buf_tag); 533 534 if (likely(ret == 0)) 535 adapter->tx_buf_tag = NULL; 536 537 return (ret); 538 } 539 540 static int 541 ena_setup_rx_dma_tag(struct ena_adapter *adapter) 542 { 543 int ret; 544 545 /* Create DMA tag for Rx buffers*/ 546 ret = bus_dma_tag_create(bus_get_dma_tag(adapter->pdev), /* parent */ 547 1, 0, /* alignment, bounds */ 548 ENA_DMA_BIT_MASK(adapter->dma_width), /* lowaddr of excl window */ 549 BUS_SPACE_MAXADDR, /* highaddr of excl window */ 550 NULL, NULL, /* filter, filterarg */ 551 MJUM16BYTES, /* maxsize */ 552 1, /* nsegments */ 553 MJUM16BYTES, /* maxsegsize */ 554 0, /* flags */ 555 NULL, /* lockfunc */ 556 NULL, /* lockarg */ 557 &adapter->rx_buf_tag); 558 559 return (ret); 560 } 561 562 static int 563 ena_free_rx_dma_tag(struct ena_adapter *adapter) 564 { 565 int ret; 566 567 ret = bus_dma_tag_destroy(adapter->rx_buf_tag); 568 569 if (likely(ret == 0)) 570 adapter->rx_buf_tag = NULL; 571 572 return (ret); 573 } 574 575 /** 576 * ena_setup_tx_resources - allocate Tx resources (Descriptors) 577 * @adapter: network interface device structure 578 * @qid: queue index 579 * 580 * Returns 0 on success, otherwise on failure. 581 **/ 582 static int 583 ena_setup_tx_resources(struct ena_adapter *adapter, int qid) 584 { 585 struct ena_que *que = &adapter->que[qid]; 586 struct ena_ring *tx_ring = que->tx_ring; 587 int size, i, err; 588 #ifdef RSS 589 cpuset_t cpu_mask; 590 #endif 591 592 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size; 593 594 tx_ring->tx_buffer_info = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 595 if (unlikely(tx_ring->tx_buffer_info == NULL)) 596 return (ENOMEM); 597 598 size = sizeof(uint16_t) * tx_ring->ring_size; 599 tx_ring->free_tx_ids = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 600 if (unlikely(tx_ring->free_tx_ids == NULL)) 601 goto err_buf_info_free; 602 603 /* Req id stack for TX OOO completions */ 604 for (i = 0; i < tx_ring->ring_size; i++) 605 tx_ring->free_tx_ids[i] = i; 606 607 /* Reset TX statistics. */ 608 ena_reset_counters((counter_u64_t *)&tx_ring->tx_stats, 609 sizeof(tx_ring->tx_stats)); 610 611 tx_ring->next_to_use = 0; 612 tx_ring->next_to_clean = 0; 613 614 /* Make sure that drbr is empty */ 615 ENA_RING_MTX_LOCK(tx_ring); 616 drbr_flush(adapter->ifp, tx_ring->br); 617 ENA_RING_MTX_UNLOCK(tx_ring); 618 619 /* ... and create the buffer DMA maps */ 620 for (i = 0; i < tx_ring->ring_size; i++) { 621 err = bus_dmamap_create(adapter->tx_buf_tag, 0, 622 &tx_ring->tx_buffer_info[i].map); 623 if (unlikely(err != 0)) { 624 ena_trace(ENA_ALERT, 625 "Unable to create Tx DMA map for buffer %d\n", i); 626 goto err_buf_info_unmap; 627 } 628 } 629 630 /* Allocate taskqueues */ 631 TASK_INIT(&tx_ring->enqueue_task, 0, ena_deferred_mq_start, tx_ring); 632 tx_ring->enqueue_tq = taskqueue_create_fast("ena_tx_enque", M_NOWAIT, 633 taskqueue_thread_enqueue, &tx_ring->enqueue_tq); 634 if (unlikely(tx_ring->enqueue_tq == NULL)) { 635 ena_trace(ENA_ALERT, 636 "Unable to create taskqueue for enqueue task\n"); 637 i = tx_ring->ring_size; 638 goto err_buf_info_unmap; 639 } 640 641 /* RSS set cpu for thread */ 642 #ifdef RSS 643 CPU_SETOF(que->cpu, &cpu_mask); 644 taskqueue_start_threads_cpuset(&tx_ring->enqueue_tq, 1, PI_NET, 645 &cpu_mask, "%s tx_ring enq (bucket %d)", 646 device_get_nameunit(adapter->pdev), que->cpu); 647 #else /* RSS */ 648 taskqueue_start_threads(&tx_ring->enqueue_tq, 1, PI_NET, 649 "%s txeq %d", device_get_nameunit(adapter->pdev), que->cpu); 650 #endif /* RSS */ 651 652 return (0); 653 654 err_buf_info_unmap: 655 while (i--) { 656 bus_dmamap_destroy(adapter->tx_buf_tag, 657 tx_ring->tx_buffer_info[i].map); 658 } 659 free(tx_ring->free_tx_ids, M_DEVBUF); 660 tx_ring->free_tx_ids = NULL; 661 err_buf_info_free: 662 free(tx_ring->tx_buffer_info, M_DEVBUF); 663 tx_ring->tx_buffer_info = NULL; 664 665 return (ENOMEM); 666 } 667 668 /** 669 * ena_free_tx_resources - Free Tx Resources per Queue 670 * @adapter: network interface device structure 671 * @qid: queue index 672 * 673 * Free all transmit software resources 674 **/ 675 static void 676 ena_free_tx_resources(struct ena_adapter *adapter, int qid) 677 { 678 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 679 680 while (taskqueue_cancel(tx_ring->enqueue_tq, &tx_ring->enqueue_task, 681 NULL)) 682 taskqueue_drain(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 683 684 taskqueue_free(tx_ring->enqueue_tq); 685 686 ENA_RING_MTX_LOCK(tx_ring); 687 /* Flush buffer ring, */ 688 drbr_flush(adapter->ifp, tx_ring->br); 689 690 /* Free buffer DMA maps, */ 691 for (int i = 0; i < tx_ring->ring_size; i++) { 692 m_freem(tx_ring->tx_buffer_info[i].mbuf); 693 tx_ring->tx_buffer_info[i].mbuf = NULL; 694 bus_dmamap_unload(adapter->tx_buf_tag, 695 tx_ring->tx_buffer_info[i].map); 696 bus_dmamap_destroy(adapter->tx_buf_tag, 697 tx_ring->tx_buffer_info[i].map); 698 } 699 ENA_RING_MTX_UNLOCK(tx_ring); 700 701 /* And free allocated memory. */ 702 free(tx_ring->tx_buffer_info, M_DEVBUF); 703 tx_ring->tx_buffer_info = NULL; 704 705 free(tx_ring->free_tx_ids, M_DEVBUF); 706 tx_ring->free_tx_ids = NULL; 707 } 708 709 /** 710 * ena_setup_all_tx_resources - allocate all queues Tx resources 711 * @adapter: network interface device structure 712 * 713 * Returns 0 on success, otherwise on failure. 714 **/ 715 static int 716 ena_setup_all_tx_resources(struct ena_adapter *adapter) 717 { 718 int i, rc; 719 720 for (i = 0; i < adapter->num_queues; i++) { 721 rc = ena_setup_tx_resources(adapter, i); 722 if (rc != 0) { 723 device_printf(adapter->pdev, 724 "Allocation for Tx Queue %u failed\n", i); 725 goto err_setup_tx; 726 } 727 } 728 729 return (0); 730 731 err_setup_tx: 732 /* Rewind the index freeing the rings as we go */ 733 while (i--) 734 ena_free_tx_resources(adapter, i); 735 return (rc); 736 } 737 738 /** 739 * ena_free_all_tx_resources - Free Tx Resources for All Queues 740 * @adapter: network interface device structure 741 * 742 * Free all transmit software resources 743 **/ 744 static void 745 ena_free_all_tx_resources(struct ena_adapter *adapter) 746 { 747 int i; 748 749 for (i = 0; i < adapter->num_queues; i++) 750 ena_free_tx_resources(adapter, i); 751 } 752 753 static inline int 754 validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 755 { 756 if (likely(req_id < rx_ring->ring_size)) 757 return (0); 758 759 device_printf(rx_ring->adapter->pdev, "Invalid rx req_id: %hu\n", 760 req_id); 761 counter_u64_add(rx_ring->rx_stats.bad_req_id, 1); 762 763 /* Trigger device reset */ 764 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 765 rx_ring->adapter->trigger_reset = true; 766 767 return (EFAULT); 768 } 769 770 /** 771 * ena_setup_rx_resources - allocate Rx resources (Descriptors) 772 * @adapter: network interface device structure 773 * @qid: queue index 774 * 775 * Returns 0 on success, otherwise on failure. 776 **/ 777 static int 778 ena_setup_rx_resources(struct ena_adapter *adapter, unsigned int qid) 779 { 780 struct ena_que *que = &adapter->que[qid]; 781 struct ena_ring *rx_ring = que->rx_ring; 782 int size, err, i; 783 #ifdef RSS 784 cpuset_t cpu_mask; 785 #endif 786 787 size = sizeof(struct ena_rx_buffer) * rx_ring->ring_size; 788 789 /* 790 * Alloc extra element so in rx path 791 * we can always prefetch rx_info + 1 792 */ 793 size += sizeof(struct ena_rx_buffer); 794 795 rx_ring->rx_buffer_info = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 796 797 size = sizeof(uint16_t) * rx_ring->ring_size; 798 rx_ring->free_rx_ids = malloc(size, M_DEVBUF, M_WAITOK); 799 800 for (i = 0; i < rx_ring->ring_size; i++) 801 rx_ring->free_rx_ids[i] = i; 802 803 /* Reset RX statistics. */ 804 ena_reset_counters((counter_u64_t *)&rx_ring->rx_stats, 805 sizeof(rx_ring->rx_stats)); 806 807 rx_ring->next_to_clean = 0; 808 rx_ring->next_to_use = 0; 809 810 /* ... and create the buffer DMA maps */ 811 for (i = 0; i < rx_ring->ring_size; i++) { 812 err = bus_dmamap_create(adapter->rx_buf_tag, 0, 813 &(rx_ring->rx_buffer_info[i].map)); 814 if (err != 0) { 815 ena_trace(ENA_ALERT, 816 "Unable to create Rx DMA map for buffer %d\n", i); 817 goto err_buf_info_unmap; 818 } 819 } 820 821 /* Create LRO for the ring */ 822 if ((adapter->ifp->if_capenable & IFCAP_LRO) != 0) { 823 int err = tcp_lro_init(&rx_ring->lro); 824 if (err != 0) { 825 device_printf(adapter->pdev, 826 "LRO[%d] Initialization failed!\n", qid); 827 } else { 828 ena_trace(ENA_INFO, 829 "RX Soft LRO[%d] Initialized\n", qid); 830 rx_ring->lro.ifp = adapter->ifp; 831 } 832 } 833 834 /* Allocate taskqueues */ 835 TASK_INIT(&rx_ring->cmpl_task, 0, ena_deferred_rx_cleanup, rx_ring); 836 rx_ring->cmpl_tq = taskqueue_create_fast("ena RX completion", M_WAITOK, 837 taskqueue_thread_enqueue, &rx_ring->cmpl_tq); 838 839 /* RSS set cpu for thread */ 840 #ifdef RSS 841 CPU_SETOF(que->cpu, &cpu_mask); 842 taskqueue_start_threads_cpuset(&rx_ring->cmpl_tq, 1, PI_NET, &cpu_mask, 843 "%s rx_ring cmpl (bucket %d)", 844 device_get_nameunit(adapter->pdev), que->cpu); 845 #else 846 taskqueue_start_threads(&rx_ring->cmpl_tq, 1, PI_NET, 847 "%s rx_ring cmpl %d", device_get_nameunit(adapter->pdev), que->cpu); 848 #endif 849 850 return (0); 851 852 err_buf_info_unmap: 853 while (i--) { 854 bus_dmamap_destroy(adapter->rx_buf_tag, 855 rx_ring->rx_buffer_info[i].map); 856 } 857 858 free(rx_ring->free_rx_ids, M_DEVBUF); 859 rx_ring->free_rx_ids = NULL; 860 free(rx_ring->rx_buffer_info, M_DEVBUF); 861 rx_ring->rx_buffer_info = NULL; 862 return (ENOMEM); 863 } 864 865 /** 866 * ena_free_rx_resources - Free Rx Resources 867 * @adapter: network interface device structure 868 * @qid: queue index 869 * 870 * Free all receive software resources 871 **/ 872 static void 873 ena_free_rx_resources(struct ena_adapter *adapter, unsigned int qid) 874 { 875 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 876 877 while (taskqueue_cancel(rx_ring->cmpl_tq, &rx_ring->cmpl_task, NULL) != 0) 878 taskqueue_drain(rx_ring->cmpl_tq, &rx_ring->cmpl_task); 879 880 taskqueue_free(rx_ring->cmpl_tq); 881 882 /* Free buffer DMA maps, */ 883 for (int i = 0; i < rx_ring->ring_size; i++) { 884 m_freem(rx_ring->rx_buffer_info[i].mbuf); 885 rx_ring->rx_buffer_info[i].mbuf = NULL; 886 bus_dmamap_unload(adapter->rx_buf_tag, 887 rx_ring->rx_buffer_info[i].map); 888 bus_dmamap_destroy(adapter->rx_buf_tag, 889 rx_ring->rx_buffer_info[i].map); 890 } 891 892 /* free LRO resources, */ 893 tcp_lro_free(&rx_ring->lro); 894 895 /* free allocated memory */ 896 free(rx_ring->rx_buffer_info, M_DEVBUF); 897 rx_ring->rx_buffer_info = NULL; 898 899 free(rx_ring->free_rx_ids, M_DEVBUF); 900 rx_ring->free_rx_ids = NULL; 901 } 902 903 /** 904 * ena_setup_all_rx_resources - allocate all queues Rx resources 905 * @adapter: network interface device structure 906 * 907 * Returns 0 on success, otherwise on failure. 908 **/ 909 static int 910 ena_setup_all_rx_resources(struct ena_adapter *adapter) 911 { 912 int i, rc = 0; 913 914 for (i = 0; i < adapter->num_queues; i++) { 915 rc = ena_setup_rx_resources(adapter, i); 916 if (rc != 0) { 917 device_printf(adapter->pdev, 918 "Allocation for Rx Queue %u failed\n", i); 919 goto err_setup_rx; 920 } 921 } 922 return (0); 923 924 err_setup_rx: 925 /* rewind the index freeing the rings as we go */ 926 while (i--) 927 ena_free_rx_resources(adapter, i); 928 return (rc); 929 } 930 931 /** 932 * ena_free_all_rx_resources - Free Rx resources for all queues 933 * @adapter: network interface device structure 934 * 935 * Free all receive software resources 936 **/ 937 static void 938 ena_free_all_rx_resources(struct ena_adapter *adapter) 939 { 940 int i; 941 942 for (i = 0; i < adapter->num_queues; i++) 943 ena_free_rx_resources(adapter, i); 944 } 945 946 static inline int 947 ena_alloc_rx_mbuf(struct ena_adapter *adapter, 948 struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info) 949 { 950 struct ena_com_buf *ena_buf; 951 bus_dma_segment_t segs[1]; 952 int nsegs, error; 953 954 /* if previous allocated frag is not used */ 955 if (unlikely(rx_info->mbuf != NULL)) 956 return (0); 957 958 /* Get mbuf using UMA allocator */ 959 rx_info->mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM16BYTES); 960 961 if (unlikely(rx_info->mbuf == NULL)) { 962 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 963 return (ENOMEM); 964 } 965 /* Set mbuf length*/ 966 rx_info->mbuf->m_pkthdr.len = rx_info->mbuf->m_len = MJUM16BYTES; 967 968 /* Map packets for DMA */ 969 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 970 "Using tag %p for buffers' DMA mapping, mbuf %p len: %d", 971 adapter->rx_buf_tag,rx_info->mbuf, rx_info->mbuf->m_len); 972 error = bus_dmamap_load_mbuf_sg(adapter->rx_buf_tag, rx_info->map, 973 rx_info->mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 974 if (unlikely((error != 0) || (nsegs != 1))) { 975 ena_trace(ENA_WARNING, "failed to map mbuf, error: %d, " 976 "nsegs: %d\n", error, nsegs); 977 counter_u64_add(rx_ring->rx_stats.dma_mapping_err, 1); 978 goto exit; 979 980 } 981 982 bus_dmamap_sync(adapter->rx_buf_tag, rx_info->map, BUS_DMASYNC_PREREAD); 983 984 ena_buf = &rx_info->ena_buf; 985 ena_buf->paddr = segs[0].ds_addr; 986 ena_buf->len = MJUM16BYTES; 987 988 ena_trace(ENA_DBG | ENA_RSC | ENA_RXPTH, 989 "ALLOC RX BUF: mbuf %p, rx_info %p, len %d, paddr %#jx\n", 990 rx_info->mbuf, rx_info,ena_buf->len, (uintmax_t)ena_buf->paddr); 991 992 return (0); 993 994 exit: 995 m_freem(rx_info->mbuf); 996 rx_info->mbuf = NULL; 997 return (EFAULT); 998 } 999 1000 static void 1001 ena_free_rx_mbuf(struct ena_adapter *adapter, struct ena_ring *rx_ring, 1002 struct ena_rx_buffer *rx_info) 1003 { 1004 1005 if (rx_info->mbuf == NULL) { 1006 ena_trace(ENA_WARNING, "Trying to free unallocated buffer\n"); 1007 return; 1008 } 1009 1010 bus_dmamap_unload(adapter->rx_buf_tag, rx_info->map); 1011 m_freem(rx_info->mbuf); 1012 rx_info->mbuf = NULL; 1013 } 1014 1015 /** 1016 * ena_refill_rx_bufs - Refills ring with descriptors 1017 * @rx_ring: the ring which we want to feed with free descriptors 1018 * @num: number of descriptors to refill 1019 * Refills the ring with newly allocated DMA-mapped mbufs for receiving 1020 **/ 1021 static int 1022 ena_refill_rx_bufs(struct ena_ring *rx_ring, uint32_t num) 1023 { 1024 struct ena_adapter *adapter = rx_ring->adapter; 1025 uint16_t next_to_use, req_id; 1026 uint32_t i; 1027 int rc; 1028 1029 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, "refill qid: %d", 1030 rx_ring->qid); 1031 1032 next_to_use = rx_ring->next_to_use; 1033 1034 for (i = 0; i < num; i++) { 1035 struct ena_rx_buffer *rx_info; 1036 1037 ena_trace(ENA_DBG | ENA_RXPTH | ENA_RSC, 1038 "RX buffer - next to use: %d", next_to_use); 1039 1040 req_id = rx_ring->free_rx_ids[next_to_use]; 1041 rc = validate_rx_req_id(rx_ring, req_id); 1042 if (unlikely(rc != 0)) 1043 break; 1044 1045 rx_info = &rx_ring->rx_buffer_info[req_id]; 1046 1047 rc = ena_alloc_rx_mbuf(adapter, rx_ring, rx_info); 1048 if (unlikely(rc != 0)) { 1049 ena_trace(ENA_WARNING, 1050 "failed to alloc buffer for rx queue %d\n", 1051 rx_ring->qid); 1052 break; 1053 } 1054 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq, 1055 &rx_info->ena_buf, req_id); 1056 if (unlikely(rc != 0)) { 1057 ena_trace(ENA_WARNING, 1058 "failed to add buffer for rx queue %d\n", 1059 rx_ring->qid); 1060 break; 1061 } 1062 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, 1063 rx_ring->ring_size); 1064 } 1065 1066 if (unlikely(i < num)) { 1067 counter_u64_add(rx_ring->rx_stats.refil_partial, 1); 1068 ena_trace(ENA_WARNING, 1069 "refilled rx qid %d with only %d mbufs (from %d)\n", 1070 rx_ring->qid, i, num); 1071 } 1072 1073 if (likely(i != 0)) { 1074 wmb(); 1075 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); 1076 } 1077 rx_ring->next_to_use = next_to_use; 1078 return (i); 1079 } 1080 1081 static void 1082 ena_free_rx_bufs(struct ena_adapter *adapter, unsigned int qid) 1083 { 1084 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 1085 unsigned int i; 1086 1087 for (i = 0; i < rx_ring->ring_size; i++) { 1088 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i]; 1089 1090 if (rx_info->mbuf != NULL) 1091 ena_free_rx_mbuf(adapter, rx_ring, rx_info); 1092 } 1093 } 1094 1095 /** 1096 * ena_refill_all_rx_bufs - allocate all queues Rx buffers 1097 * @adapter: network interface device structure 1098 * 1099 */ 1100 static void 1101 ena_refill_all_rx_bufs(struct ena_adapter *adapter) 1102 { 1103 struct ena_ring *rx_ring; 1104 int i, rc, bufs_num; 1105 1106 for (i = 0; i < adapter->num_queues; i++) { 1107 rx_ring = &adapter->rx_ring[i]; 1108 bufs_num = rx_ring->ring_size - 1; 1109 rc = ena_refill_rx_bufs(rx_ring, bufs_num); 1110 1111 if (unlikely(rc != bufs_num)) 1112 ena_trace(ENA_WARNING, "refilling Queue %d failed. " 1113 "Allocated %d buffers from: %d\n", i, rc, bufs_num); 1114 } 1115 } 1116 1117 static void 1118 ena_free_all_rx_bufs(struct ena_adapter *adapter) 1119 { 1120 int i; 1121 1122 for (i = 0; i < adapter->num_queues; i++) 1123 ena_free_rx_bufs(adapter, i); 1124 } 1125 1126 /** 1127 * ena_free_tx_bufs - Free Tx Buffers per Queue 1128 * @adapter: network interface device structure 1129 * @qid: queue index 1130 **/ 1131 static void 1132 ena_free_tx_bufs(struct ena_adapter *adapter, unsigned int qid) 1133 { 1134 bool print_once = true; 1135 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 1136 1137 ENA_RING_MTX_LOCK(tx_ring); 1138 for (int i = 0; i < tx_ring->ring_size; i++) { 1139 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i]; 1140 1141 if (tx_info->mbuf == NULL) 1142 continue; 1143 1144 if (print_once) { 1145 device_printf(adapter->pdev, 1146 "free uncompleted tx mbuf qid %d idx 0x%x", 1147 qid, i); 1148 print_once = false; 1149 } else { 1150 ena_trace(ENA_DBG, 1151 "free uncompleted tx mbuf qid %d idx 0x%x", 1152 qid, i); 1153 } 1154 1155 bus_dmamap_unload(adapter->tx_buf_tag, tx_info->map); 1156 m_free(tx_info->mbuf); 1157 tx_info->mbuf = NULL; 1158 } 1159 ENA_RING_MTX_UNLOCK(tx_ring); 1160 } 1161 1162 static void 1163 ena_free_all_tx_bufs(struct ena_adapter *adapter) 1164 { 1165 1166 for (int i = 0; i < adapter->num_queues; i++) 1167 ena_free_tx_bufs(adapter, i); 1168 } 1169 1170 static void 1171 ena_destroy_all_tx_queues(struct ena_adapter *adapter) 1172 { 1173 uint16_t ena_qid; 1174 int i; 1175 1176 for (i = 0; i < adapter->num_queues; i++) { 1177 ena_qid = ENA_IO_TXQ_IDX(i); 1178 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1179 } 1180 } 1181 1182 static void 1183 ena_destroy_all_rx_queues(struct ena_adapter *adapter) 1184 { 1185 uint16_t ena_qid; 1186 int i; 1187 1188 for (i = 0; i < adapter->num_queues; i++) { 1189 ena_qid = ENA_IO_RXQ_IDX(i); 1190 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 1191 } 1192 } 1193 1194 static void 1195 ena_destroy_all_io_queues(struct ena_adapter *adapter) 1196 { 1197 ena_destroy_all_tx_queues(adapter); 1198 ena_destroy_all_rx_queues(adapter); 1199 } 1200 1201 static inline int 1202 validate_tx_req_id(struct ena_ring *tx_ring, uint16_t req_id) 1203 { 1204 struct ena_adapter *adapter = tx_ring->adapter; 1205 struct ena_tx_buffer *tx_info = NULL; 1206 1207 if (likely(req_id < tx_ring->ring_size)) { 1208 tx_info = &tx_ring->tx_buffer_info[req_id]; 1209 if (tx_info->mbuf != NULL) 1210 return (0); 1211 } 1212 1213 if (tx_info->mbuf == NULL) 1214 device_printf(adapter->pdev, 1215 "tx_info doesn't have valid mbuf\n"); 1216 else 1217 device_printf(adapter->pdev, "Invalid req_id: %hu\n", req_id); 1218 1219 counter_u64_add(tx_ring->tx_stats.bad_req_id, 1); 1220 1221 return (EFAULT); 1222 } 1223 1224 static int 1225 ena_create_io_queues(struct ena_adapter *adapter) 1226 { 1227 struct ena_com_dev *ena_dev = adapter->ena_dev; 1228 struct ena_com_create_io_ctx ctx; 1229 struct ena_ring *ring; 1230 uint16_t ena_qid; 1231 uint32_t msix_vector; 1232 int rc, i; 1233 1234 /* Create TX queues */ 1235 for (i = 0; i < adapter->num_queues; i++) { 1236 msix_vector = ENA_IO_IRQ_IDX(i); 1237 ena_qid = ENA_IO_TXQ_IDX(i); 1238 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1239 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1240 ctx.queue_size = adapter->tx_ring_size; 1241 ctx.msix_vector = msix_vector; 1242 ctx.qid = ena_qid; 1243 rc = ena_com_create_io_queue(ena_dev, &ctx); 1244 if (rc != 0) { 1245 device_printf(adapter->pdev, 1246 "Failed to create io TX queue #%d rc: %d\n", i, rc); 1247 goto err_tx; 1248 } 1249 ring = &adapter->tx_ring[i]; 1250 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1251 &ring->ena_com_io_sq, 1252 &ring->ena_com_io_cq); 1253 if (rc != 0) { 1254 device_printf(adapter->pdev, 1255 "Failed to get TX queue handlers. TX queue num" 1256 " %d rc: %d\n", i, rc); 1257 ena_com_destroy_io_queue(ena_dev, ena_qid); 1258 goto err_tx; 1259 } 1260 } 1261 1262 /* Create RX queues */ 1263 for (i = 0; i < adapter->num_queues; i++) { 1264 msix_vector = ENA_IO_IRQ_IDX(i); 1265 ena_qid = ENA_IO_RXQ_IDX(i); 1266 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1267 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1268 ctx.queue_size = adapter->rx_ring_size; 1269 ctx.msix_vector = msix_vector; 1270 ctx.qid = ena_qid; 1271 rc = ena_com_create_io_queue(ena_dev, &ctx); 1272 if (unlikely(rc != 0)) { 1273 device_printf(adapter->pdev, 1274 "Failed to create io RX queue[%d] rc: %d\n", i, rc); 1275 goto err_rx; 1276 } 1277 1278 ring = &adapter->rx_ring[i]; 1279 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1280 &ring->ena_com_io_sq, 1281 &ring->ena_com_io_cq); 1282 if (unlikely(rc != 0)) { 1283 device_printf(adapter->pdev, 1284 "Failed to get RX queue handlers. RX queue num" 1285 " %d rc: %d\n", i, rc); 1286 ena_com_destroy_io_queue(ena_dev, ena_qid); 1287 goto err_rx; 1288 } 1289 } 1290 1291 return (0); 1292 1293 err_rx: 1294 while (i--) 1295 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i)); 1296 i = adapter->num_queues; 1297 err_tx: 1298 while (i--) 1299 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i)); 1300 1301 return (ENXIO); 1302 } 1303 1304 /** 1305 * ena_tx_cleanup - clear sent packets and corresponding descriptors 1306 * @tx_ring: ring for which we want to clean packets 1307 * 1308 * Once packets are sent, we ask the device in a loop for no longer used 1309 * descriptors. We find the related mbuf chain in a map (index in an array) 1310 * and free it, then update ring state. 1311 * This is performed in "endless" loop, updating ring pointers every 1312 * TX_COMMIT. The first check of free descriptor is performed before the actual 1313 * loop, then repeated at the loop end. 1314 **/ 1315 static int 1316 ena_tx_cleanup(struct ena_ring *tx_ring) 1317 { 1318 struct ena_adapter *adapter; 1319 struct ena_com_io_cq* io_cq; 1320 uint16_t next_to_clean; 1321 uint16_t req_id; 1322 uint16_t ena_qid; 1323 unsigned int total_done = 0; 1324 int rc; 1325 int commit = TX_COMMIT; 1326 int budget = TX_BUDGET; 1327 int work_done; 1328 1329 adapter = tx_ring->que->adapter; 1330 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 1331 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1332 next_to_clean = tx_ring->next_to_clean; 1333 1334 do { 1335 struct ena_tx_buffer *tx_info; 1336 struct mbuf *mbuf; 1337 1338 rc = ena_com_tx_comp_req_id_get(io_cq, &req_id); 1339 if (unlikely(rc != 0)) 1340 break; 1341 1342 rc = validate_tx_req_id(tx_ring, req_id); 1343 if (unlikely(rc != 0)) 1344 break; 1345 1346 tx_info = &tx_ring->tx_buffer_info[req_id]; 1347 1348 mbuf = tx_info->mbuf; 1349 1350 tx_info->mbuf = NULL; 1351 bintime_clear(&tx_info->timestamp); 1352 1353 if (likely(tx_info->num_of_bufs != 0)) { 1354 /* Map is no longer required */ 1355 bus_dmamap_unload(adapter->tx_buf_tag, tx_info->map); 1356 } 1357 1358 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d mbuf %p completed", 1359 tx_ring->qid, mbuf); 1360 1361 m_freem(mbuf); 1362 1363 total_done += tx_info->tx_descs; 1364 1365 tx_ring->free_tx_ids[next_to_clean] = req_id; 1366 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 1367 tx_ring->ring_size); 1368 1369 if (unlikely(--commit == 0)) { 1370 commit = TX_COMMIT; 1371 /* update ring state every TX_COMMIT descriptor */ 1372 tx_ring->next_to_clean = next_to_clean; 1373 ena_com_comp_ack( 1374 &adapter->ena_dev->io_sq_queues[ena_qid], 1375 total_done); 1376 ena_com_update_dev_comp_head(io_cq); 1377 total_done = 0; 1378 } 1379 } while (likely(--budget)); 1380 1381 work_done = TX_BUDGET - budget; 1382 1383 ena_trace(ENA_DBG | ENA_TXPTH, "tx: q %d done. total pkts: %d", 1384 tx_ring->qid, work_done); 1385 1386 /* If there is still something to commit update ring state */ 1387 if (likely(commit != TX_COMMIT)) { 1388 tx_ring->next_to_clean = next_to_clean; 1389 ena_com_comp_ack(&adapter->ena_dev->io_sq_queues[ena_qid], 1390 total_done); 1391 ena_com_update_dev_comp_head(io_cq); 1392 } 1393 1394 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 1395 1396 return (work_done); 1397 } 1398 1399 static void 1400 ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1401 struct mbuf *mbuf) 1402 { 1403 struct ena_adapter *adapter = rx_ring->adapter; 1404 1405 if (likely(adapter->rss_support)) { 1406 mbuf->m_pkthdr.flowid = ena_rx_ctx->hash; 1407 1408 if (ena_rx_ctx->frag && 1409 (ena_rx_ctx->l3_proto != ENA_ETH_IO_L3_PROTO_UNKNOWN)) { 1410 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1411 return; 1412 } 1413 1414 switch (ena_rx_ctx->l3_proto) { 1415 case ENA_ETH_IO_L3_PROTO_IPV4: 1416 switch (ena_rx_ctx->l4_proto) { 1417 case ENA_ETH_IO_L4_PROTO_TCP: 1418 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV4); 1419 break; 1420 case ENA_ETH_IO_L4_PROTO_UDP: 1421 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV4); 1422 break; 1423 default: 1424 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV4); 1425 } 1426 break; 1427 case ENA_ETH_IO_L3_PROTO_IPV6: 1428 switch (ena_rx_ctx->l4_proto) { 1429 case ENA_ETH_IO_L4_PROTO_TCP: 1430 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_TCP_IPV6); 1431 break; 1432 case ENA_ETH_IO_L4_PROTO_UDP: 1433 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_UDP_IPV6); 1434 break; 1435 default: 1436 M_HASHTYPE_SET(mbuf, M_HASHTYPE_RSS_IPV6); 1437 } 1438 break; 1439 case ENA_ETH_IO_L3_PROTO_UNKNOWN: 1440 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1441 break; 1442 default: 1443 M_HASHTYPE_SET(mbuf, M_HASHTYPE_OPAQUE_HASH); 1444 } 1445 } else { 1446 mbuf->m_pkthdr.flowid = rx_ring->qid; 1447 M_HASHTYPE_SET(mbuf, M_HASHTYPE_NONE); 1448 } 1449 } 1450 1451 /** 1452 * ena_rx_mbuf - assemble mbuf from descriptors 1453 * @rx_ring: ring for which we want to clean packets 1454 * @ena_bufs: buffer info 1455 * @ena_rx_ctx: metadata for this packet(s) 1456 * @next_to_clean: ring pointer, will be updated only upon success 1457 * 1458 **/ 1459 static struct mbuf* 1460 ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs, 1461 struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean) 1462 { 1463 struct mbuf *mbuf; 1464 struct ena_rx_buffer *rx_info; 1465 struct ena_adapter *adapter; 1466 unsigned int descs = ena_rx_ctx->descs; 1467 uint16_t ntc, len, req_id, buf = 0; 1468 1469 ntc = *next_to_clean; 1470 adapter = rx_ring->adapter; 1471 rx_info = &rx_ring->rx_buffer_info[ntc]; 1472 1473 if (unlikely(rx_info->mbuf == NULL)) { 1474 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1475 return (NULL); 1476 } 1477 1478 len = ena_bufs[buf].len; 1479 req_id = ena_bufs[buf].req_id; 1480 rx_info = &rx_ring->rx_buffer_info[req_id]; 1481 1482 ena_trace(ENA_DBG | ENA_RXPTH, "rx_info %p, mbuf %p, paddr %jx", 1483 rx_info, rx_info->mbuf, (uintmax_t)rx_info->ena_buf.paddr); 1484 1485 mbuf = rx_info->mbuf; 1486 mbuf->m_flags |= M_PKTHDR; 1487 mbuf->m_pkthdr.len = len; 1488 mbuf->m_len = len; 1489 mbuf->m_pkthdr.rcvif = rx_ring->que->adapter->ifp; 1490 1491 /* Fill mbuf with hash key and it's interpretation for optimization */ 1492 ena_rx_hash_mbuf(rx_ring, ena_rx_ctx, mbuf); 1493 1494 ena_trace(ENA_DBG | ENA_RXPTH, "rx mbuf 0x%p, flags=0x%x, len: %d", 1495 mbuf, mbuf->m_flags, mbuf->m_pkthdr.len); 1496 1497 /* DMA address is not needed anymore, unmap it */ 1498 bus_dmamap_unload(rx_ring->adapter->rx_buf_tag, rx_info->map); 1499 1500 rx_info->mbuf = NULL; 1501 rx_ring->free_rx_ids[ntc] = req_id; 1502 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1503 1504 /* 1505 * While we have more than 1 descriptors for one rcvd packet, append 1506 * other mbufs to the main one 1507 */ 1508 while (--descs) { 1509 ++buf; 1510 len = ena_bufs[buf].len; 1511 req_id = ena_bufs[buf].req_id; 1512 rx_info = &rx_ring->rx_buffer_info[req_id]; 1513 1514 if (unlikely(rx_info->mbuf == NULL)) { 1515 device_printf(adapter->pdev, "NULL mbuf in rx_info"); 1516 /* 1517 * If one of the required mbufs was not allocated yet, 1518 * we can break there. 1519 * All earlier used descriptors will be reallocated 1520 * later and not used mbufs can be reused. 1521 * The next_to_clean pointer will not be updated in case 1522 * of an error, so caller should advance it manually 1523 * in error handling routine to keep it up to date 1524 * with hw ring. 1525 */ 1526 m_freem(mbuf); 1527 return (NULL); 1528 } 1529 1530 if (unlikely(m_append(mbuf, len, rx_info->mbuf->m_data) == 0)) { 1531 counter_u64_add(rx_ring->rx_stats.mbuf_alloc_fail, 1); 1532 ena_trace(ENA_WARNING, "Failed to append Rx mbuf %p", 1533 mbuf); 1534 } 1535 1536 ena_trace(ENA_DBG | ENA_RXPTH, 1537 "rx mbuf updated. len %d", mbuf->m_pkthdr.len); 1538 1539 /* Free already appended mbuf, it won't be useful anymore */ 1540 bus_dmamap_unload(rx_ring->adapter->rx_buf_tag, rx_info->map); 1541 m_freem(rx_info->mbuf); 1542 rx_info->mbuf = NULL; 1543 1544 rx_ring->free_rx_ids[ntc] = req_id; 1545 ntc = ENA_RX_RING_IDX_NEXT(ntc, rx_ring->ring_size); 1546 } 1547 1548 *next_to_clean = ntc; 1549 1550 return (mbuf); 1551 } 1552 1553 /** 1554 * ena_rx_checksum - indicate in mbuf if hw indicated a good cksum 1555 **/ 1556 static inline void 1557 ena_rx_checksum(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx, 1558 struct mbuf *mbuf) 1559 { 1560 1561 /* if IP and error */ 1562 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) && 1563 ena_rx_ctx->l3_csum_err)) { 1564 /* ipv4 checksum error */ 1565 mbuf->m_pkthdr.csum_flags = 0; 1566 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1567 ena_trace(ENA_DBG, "RX IPv4 header checksum error"); 1568 return; 1569 } 1570 1571 /* if TCP/UDP */ 1572 if ((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1573 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)) { 1574 if (ena_rx_ctx->l4_csum_err) { 1575 /* TCP/UDP checksum error */ 1576 mbuf->m_pkthdr.csum_flags = 0; 1577 counter_u64_add(rx_ring->rx_stats.bad_csum, 1); 1578 ena_trace(ENA_DBG, "RX L4 checksum error"); 1579 } else { 1580 mbuf->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 1581 mbuf->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1582 } 1583 } 1584 } 1585 1586 static void 1587 ena_deferred_rx_cleanup(void *arg, int pending) 1588 { 1589 struct ena_ring *rx_ring = arg; 1590 int budget = CLEAN_BUDGET; 1591 1592 ENA_RING_MTX_LOCK(rx_ring); 1593 /* 1594 * If deferred task was executed, perform cleanup of all awaiting 1595 * descs (or until given budget is depleted to avoid infinite loop). 1596 */ 1597 while (likely(budget--)) { 1598 if (ena_rx_cleanup(rx_ring) == 0) 1599 break; 1600 } 1601 ENA_RING_MTX_UNLOCK(rx_ring); 1602 } 1603 1604 /** 1605 * ena_rx_cleanup - handle rx irq 1606 * @arg: ring for which irq is being handled 1607 **/ 1608 static int 1609 ena_rx_cleanup(struct ena_ring *rx_ring) 1610 { 1611 struct ena_adapter *adapter; 1612 struct mbuf *mbuf; 1613 struct ena_com_rx_ctx ena_rx_ctx; 1614 struct ena_com_io_cq* io_cq; 1615 struct ena_com_io_sq* io_sq; 1616 if_t ifp; 1617 uint16_t ena_qid; 1618 uint16_t next_to_clean; 1619 uint32_t refill_required; 1620 uint32_t refill_threshold; 1621 uint32_t do_if_input = 0; 1622 unsigned int qid; 1623 int rc, i; 1624 int budget = RX_BUDGET; 1625 1626 adapter = rx_ring->que->adapter; 1627 ifp = adapter->ifp; 1628 qid = rx_ring->que->id; 1629 ena_qid = ENA_IO_RXQ_IDX(qid); 1630 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1631 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 1632 next_to_clean = rx_ring->next_to_clean; 1633 1634 ena_trace(ENA_DBG, "rx: qid %d", qid); 1635 1636 do { 1637 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1638 ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size; 1639 ena_rx_ctx.descs = 0; 1640 rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx); 1641 1642 if (unlikely(rc != 0)) 1643 goto error; 1644 1645 if (unlikely(ena_rx_ctx.descs == 0)) 1646 break; 1647 1648 ena_trace(ENA_DBG | ENA_RXPTH, "rx: q %d got packet from ena. " 1649 "descs #: %d l3 proto %d l4 proto %d hash: %x", 1650 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 1651 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 1652 1653 /* Receive mbuf from the ring */ 1654 mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs, 1655 &ena_rx_ctx, &next_to_clean); 1656 1657 /* Exit if we failed to retrieve a buffer */ 1658 if (unlikely(mbuf == NULL)) { 1659 for (i = 0; i < ena_rx_ctx.descs; ++i) { 1660 rx_ring->free_rx_ids[next_to_clean] = 1661 rx_ring->ena_bufs[i].req_id; 1662 next_to_clean = 1663 ENA_RX_RING_IDX_NEXT(next_to_clean, 1664 rx_ring->ring_size); 1665 1666 } 1667 break; 1668 } 1669 1670 if (((ifp->if_capenable & IFCAP_RXCSUM) != 0) || 1671 ((ifp->if_capenable & IFCAP_RXCSUM_IPV6) != 0)) { 1672 ena_rx_checksum(rx_ring, &ena_rx_ctx, mbuf); 1673 } 1674 1675 counter_enter(); 1676 counter_u64_add_protected(rx_ring->rx_stats.bytes, 1677 mbuf->m_pkthdr.len); 1678 counter_u64_add_protected(adapter->hw_stats.rx_bytes, 1679 mbuf->m_pkthdr.len); 1680 counter_exit(); 1681 /* 1682 * LRO is only for IP/TCP packets and TCP checksum of the packet 1683 * should be computed by hardware. 1684 */ 1685 do_if_input = 1; 1686 if (((ifp->if_capenable & IFCAP_LRO) != 0) && 1687 ((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) && 1688 (ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) { 1689 /* 1690 * Send to the stack if: 1691 * - LRO not enabled, or 1692 * - no LRO resources, or 1693 * - lro enqueue fails 1694 */ 1695 if ((rx_ring->lro.lro_cnt != 0) && 1696 (tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0)) 1697 do_if_input = 0; 1698 } 1699 if (do_if_input != 0) { 1700 ena_trace(ENA_DBG | ENA_RXPTH, 1701 "calling if_input() with mbuf %p", mbuf); 1702 (*ifp->if_input)(ifp, mbuf); 1703 } 1704 1705 counter_enter(); 1706 counter_u64_add_protected(rx_ring->rx_stats.cnt, 1); 1707 counter_u64_add_protected(adapter->hw_stats.rx_packets, 1); 1708 counter_exit(); 1709 } while (--budget); 1710 1711 rx_ring->next_to_clean = next_to_clean; 1712 1713 refill_required = ena_com_free_desc(io_sq); 1714 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER; 1715 1716 if (refill_required > refill_threshold) { 1717 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1718 ena_refill_rx_bufs(rx_ring, refill_required); 1719 } 1720 1721 tcp_lro_flush_all(&rx_ring->lro); 1722 1723 return (RX_BUDGET - budget); 1724 1725 error: 1726 counter_u64_add(rx_ring->rx_stats.bad_desc_num, 1); 1727 return (RX_BUDGET - budget); 1728 } 1729 1730 /********************************************************************* 1731 * 1732 * MSIX & Interrupt Service routine 1733 * 1734 **********************************************************************/ 1735 1736 /** 1737 * ena_handle_msix - MSIX Interrupt Handler for admin/async queue 1738 * @arg: interrupt number 1739 **/ 1740 static void 1741 ena_intr_msix_mgmnt(void *arg) 1742 { 1743 struct ena_adapter *adapter = (struct ena_adapter *)arg; 1744 1745 ena_com_admin_q_comp_intr_handler(adapter->ena_dev); 1746 if (likely(adapter->running)) 1747 ena_com_aenq_intr_handler(adapter->ena_dev, arg); 1748 } 1749 1750 /** 1751 * ena_handle_msix - MSIX Interrupt Handler for Tx/Rx 1752 * @arg: interrupt number 1753 **/ 1754 static void 1755 ena_handle_msix(void *arg) 1756 { 1757 struct ena_que *que = arg; 1758 struct ena_adapter *adapter = que->adapter; 1759 if_t ifp = adapter->ifp; 1760 struct ena_ring *tx_ring; 1761 struct ena_ring *rx_ring; 1762 struct ena_com_io_cq* io_cq; 1763 struct ena_eth_io_intr_reg intr_reg; 1764 int qid, ena_qid; 1765 int txc, rxc, i; 1766 1767 if (unlikely((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)) 1768 return; 1769 1770 ena_trace(ENA_DBG, "MSI-X TX/RX routine"); 1771 1772 tx_ring = que->tx_ring; 1773 rx_ring = que->rx_ring; 1774 qid = que->id; 1775 ena_qid = ENA_IO_TXQ_IDX(qid); 1776 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 1777 1778 for (i = 0; i < CLEAN_BUDGET; ++i) { 1779 /* 1780 * If lock cannot be acquired, then deferred cleanup task was 1781 * being executed and rx ring is being cleaned up in 1782 * another thread. 1783 */ 1784 if (likely(ENA_RING_MTX_TRYLOCK(rx_ring) != 0)) { 1785 rxc = ena_rx_cleanup(rx_ring); 1786 ENA_RING_MTX_UNLOCK(rx_ring); 1787 } else { 1788 rxc = 0; 1789 } 1790 1791 /* Protection from calling ena_tx_cleanup from ena_start_xmit */ 1792 ENA_RING_MTX_LOCK(tx_ring); 1793 txc = ena_tx_cleanup(tx_ring); 1794 ENA_RING_MTX_UNLOCK(tx_ring); 1795 1796 if (unlikely((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)) 1797 return; 1798 1799 if ((txc != TX_BUDGET) && (rxc != RX_BUDGET)) 1800 break; 1801 } 1802 1803 /* Signal that work is done and unmask interrupt */ 1804 ena_com_update_intr_reg(&intr_reg, 1805 RX_IRQ_INTERVAL, 1806 TX_IRQ_INTERVAL, 1807 true); 1808 ena_com_unmask_intr(io_cq, &intr_reg); 1809 } 1810 1811 static int 1812 ena_enable_msix(struct ena_adapter *adapter) 1813 { 1814 device_t dev = adapter->pdev; 1815 int msix_vecs, msix_req; 1816 int i, rc = 0; 1817 1818 /* Reserved the max msix vectors we might need */ 1819 msix_vecs = ENA_MAX_MSIX_VEC(adapter->num_queues); 1820 1821 adapter->msix_entries = malloc(msix_vecs * sizeof(struct msix_entry), 1822 M_DEVBUF, M_WAITOK | M_ZERO); 1823 1824 ena_trace(ENA_DBG, "trying to enable MSI-X, vectors: %d", msix_vecs); 1825 1826 for (i = 0; i < msix_vecs; i++) { 1827 adapter->msix_entries[i].entry = i; 1828 /* Vectors must start from 1 */ 1829 adapter->msix_entries[i].vector = i + 1; 1830 } 1831 1832 msix_req = msix_vecs; 1833 rc = pci_alloc_msix(dev, &msix_vecs); 1834 if (unlikely(rc != 0)) { 1835 device_printf(dev, 1836 "Failed to enable MSIX, vectors %d rc %d\n", msix_vecs, rc); 1837 1838 rc = ENOSPC; 1839 goto err_msix_free; 1840 } 1841 1842 if (msix_vecs != msix_req) { 1843 device_printf(dev, "Enable only %d MSI-x (out of %d), reduce " 1844 "the number of queues\n", msix_vecs, msix_req); 1845 adapter->num_queues = msix_vecs - ENA_ADMIN_MSIX_VEC; 1846 } 1847 1848 adapter->msix_vecs = msix_vecs; 1849 adapter->msix_enabled = true; 1850 1851 return (0); 1852 1853 err_msix_free: 1854 free(adapter->msix_entries, M_DEVBUF); 1855 adapter->msix_entries = NULL; 1856 1857 return (rc); 1858 } 1859 1860 static void 1861 ena_setup_mgmnt_intr(struct ena_adapter *adapter) 1862 { 1863 1864 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name, 1865 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s", 1866 device_get_nameunit(adapter->pdev)); 1867 /* 1868 * Handler is NULL on purpose, it will be set 1869 * when mgmnt interrupt is acquired 1870 */ 1871 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler = NULL; 1872 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter; 1873 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector = 1874 adapter->msix_entries[ENA_MGMNT_IRQ_IDX].vector; 1875 } 1876 1877 static void 1878 ena_setup_io_intr(struct ena_adapter *adapter) 1879 { 1880 static int last_bind_cpu = -1; 1881 int irq_idx; 1882 1883 for (int i = 0; i < adapter->num_queues; i++) { 1884 irq_idx = ENA_IO_IRQ_IDX(i); 1885 1886 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE, 1887 "%s-TxRx-%d", device_get_nameunit(adapter->pdev), i); 1888 adapter->irq_tbl[irq_idx].handler = ena_handle_msix; 1889 adapter->irq_tbl[irq_idx].data = &adapter->que[i]; 1890 adapter->irq_tbl[irq_idx].vector = 1891 adapter->msix_entries[irq_idx].vector; 1892 ena_trace(ENA_INFO | ENA_IOQ, "ena_setup_io_intr vector: %d\n", 1893 adapter->msix_entries[irq_idx].vector); 1894 #ifdef RSS 1895 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1896 rss_getcpu(i % rss_getnumbuckets()); 1897 #else 1898 /* 1899 * We still want to bind rings to the corresponding cpu 1900 * using something similar to the RSS round-robin technique. 1901 */ 1902 if (unlikely(last_bind_cpu < 0)) 1903 last_bind_cpu = CPU_FIRST(); 1904 adapter->que[i].cpu = adapter->irq_tbl[irq_idx].cpu = 1905 last_bind_cpu; 1906 last_bind_cpu = CPU_NEXT(last_bind_cpu); 1907 #endif 1908 } 1909 } 1910 1911 static int 1912 ena_request_mgmnt_irq(struct ena_adapter *adapter) 1913 { 1914 struct ena_irq *irq; 1915 unsigned long flags; 1916 int rc, rcc; 1917 1918 flags = RF_ACTIVE | RF_SHAREABLE; 1919 1920 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX]; 1921 irq->res = bus_alloc_resource_any(adapter->pdev, SYS_RES_IRQ, 1922 &irq->vector, flags); 1923 1924 if (unlikely(irq->res == NULL)) { 1925 device_printf(adapter->pdev, "could not allocate " 1926 "irq vector: %d\n", irq->vector); 1927 return (ENXIO); 1928 } 1929 1930 rc = bus_activate_resource(adapter->pdev, SYS_RES_IRQ, 1931 irq->vector, irq->res); 1932 if (unlikely(rc != 0)) { 1933 device_printf(adapter->pdev, "could not activate " 1934 "irq vector: %d\n", irq->vector); 1935 goto err_res_free; 1936 } 1937 1938 rc = bus_setup_intr(adapter->pdev, irq->res, 1939 INTR_TYPE_NET | INTR_MPSAFE, NULL, ena_intr_msix_mgmnt, 1940 irq->data, &irq->cookie); 1941 if (unlikely(rc != 0)) { 1942 device_printf(adapter->pdev, "failed to register " 1943 "interrupt handler for irq %ju: %d\n", 1944 rman_get_start(irq->res), rc); 1945 goto err_res_free; 1946 } 1947 irq->requested = true; 1948 1949 return (rc); 1950 1951 err_res_free: 1952 ena_trace(ENA_INFO | ENA_ADMQ, "releasing resource for irq %d\n", 1953 irq->vector); 1954 rcc = bus_release_resource(adapter->pdev, SYS_RES_IRQ, 1955 irq->vector, irq->res); 1956 if (unlikely(rcc != 0)) 1957 device_printf(adapter->pdev, "dev has no parent while " 1958 "releasing res for irq: %d\n", irq->vector); 1959 irq->res = NULL; 1960 1961 return (rc); 1962 } 1963 1964 static int 1965 ena_request_io_irq(struct ena_adapter *adapter) 1966 { 1967 struct ena_irq *irq; 1968 unsigned long flags = 0; 1969 int rc = 0, i, rcc; 1970 1971 if (unlikely(adapter->msix_enabled == 0)) { 1972 device_printf(adapter->pdev, 1973 "failed to request I/O IRQ: MSI-X is not enabled\n"); 1974 return (EINVAL); 1975 } else { 1976 flags = RF_ACTIVE | RF_SHAREABLE; 1977 } 1978 1979 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) { 1980 irq = &adapter->irq_tbl[i]; 1981 1982 if (unlikely(irq->requested)) 1983 continue; 1984 1985 irq->res = bus_alloc_resource_any(adapter->pdev, SYS_RES_IRQ, 1986 &irq->vector, flags); 1987 if (unlikely(irq->res == NULL)) { 1988 device_printf(adapter->pdev, "could not allocate " 1989 "irq vector: %d\n", irq->vector); 1990 goto err; 1991 } 1992 1993 rc = bus_setup_intr(adapter->pdev, irq->res, 1994 INTR_TYPE_NET | INTR_MPSAFE, NULL, 1995 irq->handler, irq->data, &irq->cookie); 1996 if (unlikely(rc != 0)) { 1997 device_printf(adapter->pdev, "failed to register " 1998 "interrupt handler for irq %ju: %d\n", 1999 rman_get_start(irq->res), rc); 2000 goto err; 2001 } 2002 irq->requested = true; 2003 2004 #ifdef RSS 2005 ena_trace(ENA_INFO, "queue %d - RSS bucket %d\n", 2006 i - ENA_IO_IRQ_FIRST_IDX, irq->cpu); 2007 #else 2008 ena_trace(ENA_INFO, "queue %d - cpu %d\n", 2009 i - ENA_IO_IRQ_FIRST_IDX, irq->cpu); 2010 #endif 2011 } 2012 2013 return (rc); 2014 2015 err: 2016 2017 for (; i >= ENA_IO_IRQ_FIRST_IDX; i--) { 2018 irq = &adapter->irq_tbl[i]; 2019 rcc = 0; 2020 2021 /* Once we entered err: section and irq->requested is true we 2022 free both intr and resources */ 2023 if (irq->requested) 2024 rcc = bus_teardown_intr(adapter->pdev, irq->res, irq->cookie); 2025 if (unlikely(rcc != 0)) 2026 device_printf(adapter->pdev, "could not release" 2027 " irq: %d, error: %d\n", irq->vector, rcc); 2028 2029 /* If we entred err: section without irq->requested set we know 2030 it was bus_alloc_resource_any() that needs cleanup, provided 2031 res is not NULL. In case res is NULL no work in needed in 2032 this iteration */ 2033 rcc = 0; 2034 if (irq->res != NULL) { 2035 rcc = bus_release_resource(adapter->pdev, SYS_RES_IRQ, 2036 irq->vector, irq->res); 2037 } 2038 if (unlikely(rcc != 0)) 2039 device_printf(adapter->pdev, "dev has no parent while " 2040 "releasing res for irq: %d\n", irq->vector); 2041 irq->requested = false; 2042 irq->res = NULL; 2043 } 2044 2045 return (rc); 2046 } 2047 2048 static void 2049 ena_free_mgmnt_irq(struct ena_adapter *adapter) 2050 { 2051 struct ena_irq *irq; 2052 int rc; 2053 2054 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX]; 2055 if (irq->requested) { 2056 ena_trace(ENA_INFO | ENA_ADMQ, "tear down irq: %d\n", 2057 irq->vector); 2058 rc = bus_teardown_intr(adapter->pdev, irq->res, irq->cookie); 2059 if (unlikely(rc != 0)) 2060 device_printf(adapter->pdev, "failed to tear " 2061 "down irq: %d\n", irq->vector); 2062 irq->requested = 0; 2063 } 2064 2065 if (irq->res != NULL) { 2066 ena_trace(ENA_INFO | ENA_ADMQ, "release resource irq: %d\n", 2067 irq->vector); 2068 rc = bus_release_resource(adapter->pdev, SYS_RES_IRQ, 2069 irq->vector, irq->res); 2070 irq->res = NULL; 2071 if (unlikely(rc != 0)) 2072 device_printf(adapter->pdev, "dev has no parent while " 2073 "releasing res for irq: %d\n", irq->vector); 2074 } 2075 } 2076 2077 static void 2078 ena_free_io_irq(struct ena_adapter *adapter) 2079 { 2080 struct ena_irq *irq; 2081 int rc; 2082 2083 for (int i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) { 2084 irq = &adapter->irq_tbl[i]; 2085 if (irq->requested) { 2086 ena_trace(ENA_INFO | ENA_IOQ, "tear down irq: %d\n", 2087 irq->vector); 2088 rc = bus_teardown_intr(adapter->pdev, irq->res, 2089 irq->cookie); 2090 if (unlikely(rc != 0)) { 2091 device_printf(adapter->pdev, "failed to tear " 2092 "down irq: %d\n", irq->vector); 2093 } 2094 irq->requested = 0; 2095 } 2096 2097 if (irq->res != NULL) { 2098 ena_trace(ENA_INFO | ENA_IOQ, "release resource irq: %d\n", 2099 irq->vector); 2100 rc = bus_release_resource(adapter->pdev, SYS_RES_IRQ, 2101 irq->vector, irq->res); 2102 irq->res = NULL; 2103 if (unlikely(rc != 0)) { 2104 device_printf(adapter->pdev, "dev has no parent" 2105 " while releasing res for irq: %d\n", 2106 irq->vector); 2107 } 2108 } 2109 } 2110 } 2111 2112 static void 2113 ena_free_irqs(struct ena_adapter* adapter) 2114 { 2115 2116 ena_free_io_irq(adapter); 2117 ena_free_mgmnt_irq(adapter); 2118 ena_disable_msix(adapter); 2119 } 2120 2121 static void 2122 ena_disable_msix(struct ena_adapter *adapter) 2123 { 2124 2125 pci_release_msi(adapter->pdev); 2126 2127 adapter->msix_vecs = 0; 2128 free(adapter->msix_entries, M_DEVBUF); 2129 adapter->msix_entries = NULL; 2130 } 2131 2132 static void 2133 ena_unmask_all_io_irqs(struct ena_adapter *adapter) 2134 { 2135 struct ena_com_io_cq* io_cq; 2136 struct ena_eth_io_intr_reg intr_reg; 2137 uint16_t ena_qid; 2138 int i; 2139 2140 /* Unmask interrupts for all queues */ 2141 for (i = 0; i < adapter->num_queues; i++) { 2142 ena_qid = ENA_IO_TXQ_IDX(i); 2143 io_cq = &adapter->ena_dev->io_cq_queues[ena_qid]; 2144 ena_com_update_intr_reg(&intr_reg, 0, 0, true); 2145 ena_com_unmask_intr(io_cq, &intr_reg); 2146 } 2147 } 2148 2149 /* Configure the Rx forwarding */ 2150 static int 2151 ena_rss_configure(struct ena_adapter *adapter) 2152 { 2153 struct ena_com_dev *ena_dev = adapter->ena_dev; 2154 int rc; 2155 2156 /* Set indirect table */ 2157 rc = ena_com_indirect_table_set(ena_dev); 2158 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2159 return (rc); 2160 2161 /* Configure hash function (if supported) */ 2162 rc = ena_com_set_hash_function(ena_dev); 2163 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2164 return (rc); 2165 2166 /* Configure hash inputs (if supported) */ 2167 rc = ena_com_set_hash_ctrl(ena_dev); 2168 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) 2169 return (rc); 2170 2171 return (0); 2172 } 2173 2174 static int 2175 ena_up_complete(struct ena_adapter *adapter) 2176 { 2177 int rc; 2178 2179 if (likely(adapter->rss_support)) { 2180 rc = ena_rss_configure(adapter); 2181 if (rc != 0) 2182 return (rc); 2183 } 2184 2185 rc = ena_change_mtu(adapter->ifp, adapter->ifp->if_mtu); 2186 if (unlikely(rc != 0)) 2187 return (rc); 2188 2189 ena_refill_all_rx_bufs(adapter); 2190 ena_reset_counters((counter_u64_t *)&adapter->hw_stats, 2191 sizeof(adapter->hw_stats)); 2192 2193 return (0); 2194 } 2195 2196 static int 2197 ena_up(struct ena_adapter *adapter) 2198 { 2199 int rc = 0; 2200 2201 if (unlikely(device_is_attached(adapter->pdev) == 0)) { 2202 device_printf(adapter->pdev, "device is not attached!\n"); 2203 return (ENXIO); 2204 } 2205 2206 if (unlikely(!adapter->running)) { 2207 device_printf(adapter->pdev, "device is not running!\n"); 2208 return (ENXIO); 2209 } 2210 2211 if (!adapter->up) { 2212 device_printf(adapter->pdev, "device is going UP\n"); 2213 2214 /* setup interrupts for IO queues */ 2215 ena_setup_io_intr(adapter); 2216 rc = ena_request_io_irq(adapter); 2217 if (unlikely(rc != 0)) { 2218 ena_trace(ENA_ALERT, "err_req_irq"); 2219 goto err_req_irq; 2220 } 2221 2222 /* allocate transmit descriptors */ 2223 rc = ena_setup_all_tx_resources(adapter); 2224 if (unlikely(rc != 0)) { 2225 ena_trace(ENA_ALERT, "err_setup_tx"); 2226 goto err_setup_tx; 2227 } 2228 2229 /* allocate receive descriptors */ 2230 rc = ena_setup_all_rx_resources(adapter); 2231 if (unlikely(rc != 0)) { 2232 ena_trace(ENA_ALERT, "err_setup_rx"); 2233 goto err_setup_rx; 2234 } 2235 2236 /* create IO queues for Rx & Tx */ 2237 rc = ena_create_io_queues(adapter); 2238 if (unlikely(rc != 0)) { 2239 ena_trace(ENA_ALERT, 2240 "create IO queues failed"); 2241 goto err_io_que; 2242 } 2243 2244 if (unlikely(adapter->link_status)) 2245 if_link_state_change(adapter->ifp, LINK_STATE_UP); 2246 2247 rc = ena_up_complete(adapter); 2248 if (unlikely(rc != 0)) 2249 goto err_up_complete; 2250 2251 counter_u64_add(adapter->dev_stats.interface_up, 1); 2252 2253 ena_update_hwassist(adapter); 2254 2255 if_setdrvflagbits(adapter->ifp, IFF_DRV_RUNNING, 2256 IFF_DRV_OACTIVE); 2257 2258 callout_reset_sbt(&adapter->timer_service, SBT_1S, SBT_1S, 2259 ena_timer_service, (void *)adapter, 0); 2260 2261 adapter->up = true; 2262 2263 ena_unmask_all_io_irqs(adapter); 2264 } 2265 2266 return (0); 2267 2268 err_up_complete: 2269 ena_destroy_all_io_queues(adapter); 2270 err_io_que: 2271 ena_free_all_rx_resources(adapter); 2272 err_setup_rx: 2273 ena_free_all_tx_resources(adapter); 2274 err_setup_tx: 2275 ena_free_io_irq(adapter); 2276 err_req_irq: 2277 return (rc); 2278 } 2279 2280 static uint64_t 2281 ena_get_counter(if_t ifp, ift_counter cnt) 2282 { 2283 struct ena_adapter *adapter; 2284 struct ena_hw_stats *stats; 2285 2286 adapter = if_getsoftc(ifp); 2287 stats = &adapter->hw_stats; 2288 2289 switch (cnt) { 2290 case IFCOUNTER_IPACKETS: 2291 return (counter_u64_fetch(stats->rx_packets)); 2292 case IFCOUNTER_OPACKETS: 2293 return (counter_u64_fetch(stats->tx_packets)); 2294 case IFCOUNTER_IBYTES: 2295 return (counter_u64_fetch(stats->rx_bytes)); 2296 case IFCOUNTER_OBYTES: 2297 return (counter_u64_fetch(stats->tx_bytes)); 2298 case IFCOUNTER_IQDROPS: 2299 return (counter_u64_fetch(stats->rx_drops)); 2300 default: 2301 return (if_get_counter_default(ifp, cnt)); 2302 } 2303 } 2304 2305 static int 2306 ena_media_change(if_t ifp) 2307 { 2308 /* Media Change is not supported by firmware */ 2309 return (0); 2310 } 2311 2312 static void 2313 ena_media_status(if_t ifp, struct ifmediareq *ifmr) 2314 { 2315 struct ena_adapter *adapter = if_getsoftc(ifp); 2316 ena_trace(ENA_DBG, "enter"); 2317 2318 mtx_lock(&adapter->global_mtx); 2319 2320 ifmr->ifm_status = IFM_AVALID; 2321 ifmr->ifm_active = IFM_ETHER; 2322 2323 if (!adapter->link_status) { 2324 mtx_unlock(&adapter->global_mtx); 2325 ena_trace(ENA_INFO, "link_status = false"); 2326 return; 2327 } 2328 2329 ifmr->ifm_status |= IFM_ACTIVE; 2330 ifmr->ifm_active |= IFM_10G_T | IFM_FDX; 2331 2332 mtx_unlock(&adapter->global_mtx); 2333 } 2334 2335 static void 2336 ena_init(void *arg) 2337 { 2338 struct ena_adapter *adapter = (struct ena_adapter *)arg; 2339 2340 if (!adapter->up) { 2341 sx_xlock(&adapter->ioctl_sx); 2342 ena_up(adapter); 2343 sx_unlock(&adapter->ioctl_sx); 2344 } 2345 } 2346 2347 static int 2348 ena_ioctl(if_t ifp, u_long command, caddr_t data) 2349 { 2350 struct ena_adapter *adapter; 2351 struct ifreq *ifr; 2352 int rc; 2353 2354 adapter = ifp->if_softc; 2355 ifr = (struct ifreq *)data; 2356 2357 /* 2358 * Acquiring lock to prevent from running up and down routines parallel. 2359 */ 2360 rc = 0; 2361 switch (command) { 2362 case SIOCSIFMTU: 2363 sx_xlock(&adapter->ioctl_sx); 2364 ena_down(adapter); 2365 2366 ena_change_mtu(ifp, ifr->ifr_mtu); 2367 2368 rc = ena_up(adapter); 2369 sx_unlock(&adapter->ioctl_sx); 2370 break; 2371 2372 case SIOCSIFFLAGS: 2373 if ((ifp->if_flags & IFF_UP) != 0) { 2374 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2375 if ((ifp->if_flags & (IFF_PROMISC | 2376 IFF_ALLMULTI)) != 0) { 2377 device_printf(adapter->pdev, 2378 "ioctl promisc/allmulti\n"); 2379 } 2380 } else { 2381 sx_xlock(&adapter->ioctl_sx); 2382 rc = ena_up(adapter); 2383 sx_unlock(&adapter->ioctl_sx); 2384 } 2385 } else { 2386 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2387 sx_xlock(&adapter->ioctl_sx); 2388 ena_down(adapter); 2389 sx_unlock(&adapter->ioctl_sx); 2390 } 2391 } 2392 break; 2393 2394 case SIOCADDMULTI: 2395 case SIOCDELMULTI: 2396 break; 2397 2398 case SIOCSIFMEDIA: 2399 case SIOCGIFMEDIA: 2400 rc = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 2401 break; 2402 2403 case SIOCSIFCAP: 2404 { 2405 int reinit = 0; 2406 2407 if (ifr->ifr_reqcap != ifp->if_capenable) { 2408 ifp->if_capenable = ifr->ifr_reqcap; 2409 reinit = 1; 2410 } 2411 2412 if ((reinit != 0) && 2413 ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)) { 2414 sx_xlock(&adapter->ioctl_sx); 2415 ena_down(adapter); 2416 rc = ena_up(adapter); 2417 sx_unlock(&adapter->ioctl_sx); 2418 } 2419 } 2420 2421 break; 2422 default: 2423 rc = ether_ioctl(ifp, command, data); 2424 break; 2425 } 2426 2427 return (rc); 2428 } 2429 2430 static int 2431 ena_get_dev_offloads(struct ena_com_dev_get_features_ctx *feat) 2432 { 2433 int caps = 0; 2434 2435 if ((feat->offload.tx & 2436 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2437 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK | 2438 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK)) != 0) 2439 caps |= IFCAP_TXCSUM; 2440 2441 if ((feat->offload.tx & 2442 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK | 2443 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)) != 0) 2444 caps |= IFCAP_TXCSUM_IPV6; 2445 2446 if ((feat->offload.tx & 2447 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0) 2448 caps |= IFCAP_TSO4; 2449 2450 if ((feat->offload.tx & 2451 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) != 0) 2452 caps |= IFCAP_TSO6; 2453 2454 if ((feat->offload.rx_supported & 2455 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK | 2456 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK)) != 0) 2457 caps |= IFCAP_RXCSUM; 2458 2459 if ((feat->offload.rx_supported & 2460 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) != 0) 2461 caps |= IFCAP_RXCSUM_IPV6; 2462 2463 caps |= IFCAP_LRO | IFCAP_JUMBO_MTU; 2464 2465 return (caps); 2466 } 2467 2468 static void 2469 ena_update_host_info(struct ena_admin_host_info *host_info, if_t ifp) 2470 { 2471 2472 host_info->supported_network_features[0] = 2473 (uint32_t)if_getcapabilities(ifp); 2474 } 2475 2476 static void 2477 ena_update_hwassist(struct ena_adapter *adapter) 2478 { 2479 if_t ifp = adapter->ifp; 2480 uint32_t feat = adapter->tx_offload_cap; 2481 int cap = if_getcapenable(ifp); 2482 int flags = 0; 2483 2484 if_clearhwassist(ifp); 2485 2486 if ((cap & IFCAP_TXCSUM) != 0) { 2487 if ((feat & 2488 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK) != 0) 2489 flags |= CSUM_IP; 2490 if ((feat & 2491 (ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK | 2492 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)) != 0) 2493 flags |= CSUM_IP_UDP | CSUM_IP_TCP; 2494 } 2495 2496 if ((cap & IFCAP_TXCSUM_IPV6) != 0) 2497 flags |= CSUM_IP6_UDP | CSUM_IP6_TCP; 2498 2499 if ((cap & IFCAP_TSO4) != 0) 2500 flags |= CSUM_IP_TSO; 2501 2502 if ((cap & IFCAP_TSO6) != 0) 2503 flags |= CSUM_IP6_TSO; 2504 2505 if_sethwassistbits(ifp, flags, 0); 2506 } 2507 2508 static int 2509 ena_setup_ifnet(device_t pdev, struct ena_adapter *adapter, 2510 struct ena_com_dev_get_features_ctx *feat) 2511 { 2512 if_t ifp; 2513 int caps = 0; 2514 2515 ifp = adapter->ifp = if_gethandle(IFT_ETHER); 2516 if (unlikely(ifp == NULL)) { 2517 ena_trace(ENA_ALERT, "can not allocate ifnet structure\n"); 2518 return (ENXIO); 2519 } 2520 if_initname(ifp, device_get_name(pdev), device_get_unit(pdev)); 2521 if_setdev(ifp, pdev); 2522 if_setsoftc(ifp, adapter); 2523 2524 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 2525 if_setinitfn(ifp, ena_init); 2526 if_settransmitfn(ifp, ena_mq_start); 2527 if_setqflushfn(ifp, ena_qflush); 2528 if_setioctlfn(ifp, ena_ioctl); 2529 if_setgetcounterfn(ifp, ena_get_counter); 2530 2531 if_setsendqlen(ifp, adapter->tx_ring_size); 2532 if_setsendqready(ifp); 2533 if_setmtu(ifp, ETHERMTU); 2534 if_setbaudrate(ifp, 0); 2535 /* Zeroize capabilities... */ 2536 if_setcapabilities(ifp, 0); 2537 if_setcapenable(ifp, 0); 2538 /* check hardware support */ 2539 caps = ena_get_dev_offloads(feat); 2540 /* ... and set them */ 2541 if_setcapabilitiesbit(ifp, caps, 0); 2542 2543 /* TSO parameters */ 2544 ifp->if_hw_tsomax = ENA_TSO_MAXSIZE - 2545 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 2546 ifp->if_hw_tsomaxsegcount = adapter->max_tx_sgl_size - 1; 2547 ifp->if_hw_tsomaxsegsize = ENA_TSO_MAXSIZE; 2548 2549 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2550 if_setcapenable(ifp, if_getcapabilities(ifp)); 2551 2552 /* 2553 * Specify the media types supported by this adapter and register 2554 * callbacks to update media and link information 2555 */ 2556 ifmedia_init(&adapter->media, IFM_IMASK, 2557 ena_media_change, ena_media_status); 2558 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2559 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2560 2561 ether_ifattach(ifp, adapter->mac_addr); 2562 2563 return (0); 2564 } 2565 2566 static void 2567 ena_down(struct ena_adapter *adapter) 2568 { 2569 int rc; 2570 2571 if (adapter->up) { 2572 device_printf(adapter->pdev, "device is going DOWN\n"); 2573 2574 callout_drain(&adapter->timer_service); 2575 2576 adapter->up = false; 2577 if_setdrvflagbits(adapter->ifp, IFF_DRV_OACTIVE, 2578 IFF_DRV_RUNNING); 2579 2580 ena_free_io_irq(adapter); 2581 2582 if (adapter->trigger_reset) { 2583 rc = ena_com_dev_reset(adapter->ena_dev, 2584 adapter->reset_reason); 2585 if (unlikely(rc != 0)) 2586 device_printf(adapter->pdev, 2587 "Device reset failed\n"); 2588 } 2589 2590 ena_destroy_all_io_queues(adapter); 2591 2592 ena_free_all_tx_bufs(adapter); 2593 ena_free_all_rx_bufs(adapter); 2594 ena_free_all_tx_resources(adapter); 2595 ena_free_all_rx_resources(adapter); 2596 2597 counter_u64_add(adapter->dev_stats.interface_down, 1); 2598 } 2599 } 2600 2601 static void 2602 ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct mbuf *mbuf) 2603 { 2604 struct ena_com_tx_meta *ena_meta; 2605 struct ether_vlan_header *eh; 2606 u32 mss; 2607 bool offload; 2608 uint16_t etype; 2609 int ehdrlen; 2610 struct ip *ip; 2611 int iphlen; 2612 struct tcphdr *th; 2613 2614 offload = false; 2615 ena_meta = &ena_tx_ctx->ena_meta; 2616 mss = mbuf->m_pkthdr.tso_segsz; 2617 2618 if (mss != 0) 2619 offload = true; 2620 2621 if ((mbuf->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2622 offload = true; 2623 2624 if ((mbuf->m_pkthdr.csum_flags & CSUM_OFFLOAD) != 0) 2625 offload = true; 2626 2627 if (!offload) { 2628 ena_tx_ctx->meta_valid = 0; 2629 return; 2630 } 2631 2632 /* Determine where frame payload starts. */ 2633 eh = mtod(mbuf, struct ether_vlan_header *); 2634 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2635 etype = ntohs(eh->evl_proto); 2636 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2637 } else { 2638 etype = ntohs(eh->evl_encap_proto); 2639 ehdrlen = ETHER_HDR_LEN; 2640 } 2641 2642 ip = (struct ip *)(mbuf->m_data + ehdrlen); 2643 iphlen = ip->ip_hl << 2; 2644 th = (struct tcphdr *)((caddr_t)ip + iphlen); 2645 2646 if ((mbuf->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2647 ena_tx_ctx->l3_csum_enable = 1; 2648 } 2649 if ((mbuf->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2650 ena_tx_ctx->tso_enable = 1; 2651 ena_meta->l4_hdr_len = (th->th_off); 2652 } 2653 2654 switch (etype) { 2655 case ETHERTYPE_IP: 2656 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 2657 if ((ip->ip_off & htons(IP_DF)) != 0) 2658 ena_tx_ctx->df = 1; 2659 break; 2660 case ETHERTYPE_IPV6: 2661 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 2662 2663 default: 2664 break; 2665 } 2666 2667 if (ip->ip_p == IPPROTO_TCP) { 2668 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 2669 if ((mbuf->m_pkthdr.csum_flags & 2670 (CSUM_IP_TCP | CSUM_IP6_TCP)) != 0) 2671 ena_tx_ctx->l4_csum_enable = 1; 2672 else 2673 ena_tx_ctx->l4_csum_enable = 0; 2674 } else if (ip->ip_p == IPPROTO_UDP) { 2675 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 2676 if ((mbuf->m_pkthdr.csum_flags & 2677 (CSUM_IP_UDP | CSUM_IP6_UDP)) != 0) 2678 ena_tx_ctx->l4_csum_enable = 1; 2679 else 2680 ena_tx_ctx->l4_csum_enable = 0; 2681 } else { 2682 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 2683 ena_tx_ctx->l4_csum_enable = 0; 2684 } 2685 2686 ena_meta->mss = mss; 2687 ena_meta->l3_hdr_len = iphlen; 2688 ena_meta->l3_hdr_offset = ehdrlen; 2689 ena_tx_ctx->meta_valid = 1; 2690 } 2691 2692 static int 2693 ena_check_and_collapse_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2694 { 2695 struct ena_adapter *adapter; 2696 struct mbuf *collapsed_mbuf; 2697 int num_frags; 2698 2699 adapter = tx_ring->adapter; 2700 num_frags = ena_mbuf_count(*mbuf); 2701 2702 /* One segment must be reserved for configuration descriptor. */ 2703 if (num_frags < adapter->max_tx_sgl_size) 2704 return (0); 2705 counter_u64_add(tx_ring->tx_stats.collapse, 1); 2706 2707 collapsed_mbuf = m_collapse(*mbuf, M_NOWAIT, 2708 adapter->max_tx_sgl_size - 1); 2709 if (unlikely(collapsed_mbuf == NULL)) { 2710 counter_u64_add(tx_ring->tx_stats.collapse_err, 1); 2711 return (ENOMEM); 2712 } 2713 2714 /* If mbuf was collapsed succesfully, original mbuf is released. */ 2715 *mbuf = collapsed_mbuf; 2716 2717 return (0); 2718 } 2719 2720 static int 2721 ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf) 2722 { 2723 struct ena_adapter *adapter; 2724 struct ena_tx_buffer *tx_info; 2725 struct ena_com_tx_ctx ena_tx_ctx; 2726 struct ena_com_dev *ena_dev; 2727 struct ena_com_buf *ena_buf; 2728 struct ena_com_io_sq* io_sq; 2729 bus_dma_segment_t segs[ENA_BUS_DMA_SEGS]; 2730 void *push_hdr; 2731 uint16_t next_to_use; 2732 uint16_t req_id; 2733 uint16_t push_len; 2734 uint16_t ena_qid; 2735 uint32_t len, nsegs, header_len; 2736 int i, rc; 2737 int nb_hw_desc; 2738 2739 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2740 adapter = tx_ring->que->adapter; 2741 ena_dev = adapter->ena_dev; 2742 io_sq = &ena_dev->io_sq_queues[ena_qid]; 2743 2744 rc = ena_check_and_collapse_mbuf(tx_ring, mbuf); 2745 if (unlikely(rc != 0)) { 2746 ena_trace(ENA_WARNING, 2747 "Failed to collapse mbuf! err: %d", rc); 2748 return (rc); 2749 } 2750 2751 next_to_use = tx_ring->next_to_use; 2752 req_id = tx_ring->free_tx_ids[next_to_use]; 2753 tx_info = &tx_ring->tx_buffer_info[req_id]; 2754 2755 tx_info->mbuf = *mbuf; 2756 tx_info->num_of_bufs = 0; 2757 2758 ena_buf = tx_info->bufs; 2759 len = (*mbuf)->m_len; 2760 2761 ena_trace(ENA_DBG | ENA_TXPTH, "Tx: %d bytes", (*mbuf)->m_pkthdr.len); 2762 2763 push_len = 0; 2764 header_len = min_t(uint32_t, len, tx_ring->tx_max_header_size); 2765 push_hdr = NULL; 2766 2767 rc = bus_dmamap_load_mbuf_sg(adapter->tx_buf_tag, tx_info->map, 2768 *mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 2769 2770 if (unlikely((rc != 0) || (nsegs == 0))) { 2771 ena_trace(ENA_WARNING, 2772 "dmamap load failed! err: %d nsegs: %d", rc, nsegs); 2773 counter_u64_add(tx_ring->tx_stats.dma_mapping_err, 1); 2774 tx_info->mbuf = NULL; 2775 if (rc == ENOMEM) 2776 return (ENA_COM_NO_MEM); 2777 else 2778 return (ENA_COM_INVAL); 2779 } 2780 2781 for (i = 0; i < nsegs; i++) { 2782 ena_buf->len = segs[i].ds_len; 2783 ena_buf->paddr = segs[i].ds_addr; 2784 ena_buf++; 2785 } 2786 tx_info->num_of_bufs = nsegs; 2787 2788 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2789 ena_tx_ctx.ena_bufs = tx_info->bufs; 2790 ena_tx_ctx.push_header = push_hdr; 2791 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2792 ena_tx_ctx.req_id = req_id; 2793 ena_tx_ctx.header_len = header_len; 2794 2795 /* Set flags and meta data */ 2796 ena_tx_csum(&ena_tx_ctx, *mbuf); 2797 /* Prepare the packet's descriptors and send them to device */ 2798 rc = ena_com_prepare_tx(io_sq, &ena_tx_ctx, &nb_hw_desc); 2799 if (unlikely(rc != 0)) { 2800 device_printf(adapter->pdev, "failed to prepare tx bufs\n"); 2801 counter_u64_add(tx_ring->tx_stats.prepare_ctx_err, 1); 2802 goto dma_error; 2803 } 2804 2805 counter_enter(); 2806 counter_u64_add_protected(tx_ring->tx_stats.cnt, 1); 2807 counter_u64_add_protected(tx_ring->tx_stats.bytes, 2808 (*mbuf)->m_pkthdr.len); 2809 2810 counter_u64_add_protected(adapter->hw_stats.tx_packets, 1); 2811 counter_u64_add_protected(adapter->hw_stats.tx_bytes, 2812 (*mbuf)->m_pkthdr.len); 2813 counter_exit(); 2814 2815 tx_info->tx_descs = nb_hw_desc; 2816 getbinuptime(&tx_info->timestamp); 2817 tx_info->print_once = true; 2818 2819 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 2820 tx_ring->ring_size); 2821 2822 bus_dmamap_sync(adapter->tx_buf_tag, tx_info->map, 2823 BUS_DMASYNC_PREWRITE); 2824 2825 return (0); 2826 2827 dma_error: 2828 tx_info->mbuf = NULL; 2829 bus_dmamap_unload(adapter->tx_buf_tag, tx_info->map); 2830 2831 return (rc); 2832 } 2833 2834 static void 2835 ena_start_xmit(struct ena_ring *tx_ring) 2836 { 2837 struct mbuf *mbuf; 2838 struct ena_adapter *adapter = tx_ring->adapter; 2839 struct ena_com_io_sq* io_sq; 2840 int ena_qid; 2841 int acum_pkts = 0; 2842 int ret = 0; 2843 2844 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) == 0)) 2845 return; 2846 2847 if (unlikely(!adapter->link_status)) 2848 return; 2849 2850 ena_qid = ENA_IO_TXQ_IDX(tx_ring->que->id); 2851 io_sq = &adapter->ena_dev->io_sq_queues[ena_qid]; 2852 2853 while ((mbuf = drbr_peek(adapter->ifp, tx_ring->br)) != NULL) { 2854 ena_trace(ENA_DBG | ENA_TXPTH, "\ndequeued mbuf %p with flags %#x and" 2855 " header csum flags %#jx", 2856 mbuf, mbuf->m_flags, (uint64_t)mbuf->m_pkthdr.csum_flags); 2857 2858 if (unlikely(!ena_com_sq_have_enough_space(io_sq, 2859 ENA_TX_CLEANUP_THRESHOLD))) 2860 ena_tx_cleanup(tx_ring); 2861 2862 if (unlikely((ret = ena_xmit_mbuf(tx_ring, &mbuf)) != 0)) { 2863 if (ret == ENA_COM_NO_MEM) { 2864 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2865 } else if (ret == ENA_COM_NO_SPACE) { 2866 drbr_putback(adapter->ifp, tx_ring->br, mbuf); 2867 } else { 2868 m_freem(mbuf); 2869 drbr_advance(adapter->ifp, tx_ring->br); 2870 } 2871 2872 break; 2873 } 2874 2875 drbr_advance(adapter->ifp, tx_ring->br); 2876 2877 if (unlikely((if_getdrvflags(adapter->ifp) & 2878 IFF_DRV_RUNNING) == 0)) 2879 return; 2880 2881 acum_pkts++; 2882 2883 BPF_MTAP(adapter->ifp, mbuf); 2884 2885 if (unlikely(acum_pkts == DB_THRESHOLD)) { 2886 acum_pkts = 0; 2887 wmb(); 2888 /* Trigger the dma engine */ 2889 ena_com_write_sq_doorbell(io_sq); 2890 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2891 } 2892 2893 } 2894 2895 if (likely(acum_pkts != 0)) { 2896 wmb(); 2897 /* Trigger the dma engine */ 2898 ena_com_write_sq_doorbell(io_sq); 2899 counter_u64_add(tx_ring->tx_stats.doorbells, 1); 2900 } 2901 2902 if (!ena_com_sq_have_enough_space(io_sq, ENA_TX_CLEANUP_THRESHOLD)) 2903 ena_tx_cleanup(tx_ring); 2904 } 2905 2906 static void 2907 ena_deferred_mq_start(void *arg, int pending) 2908 { 2909 struct ena_ring *tx_ring = (struct ena_ring *)arg; 2910 struct ifnet *ifp = tx_ring->adapter->ifp; 2911 2912 while (!drbr_empty(ifp, tx_ring->br) && 2913 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2914 ENA_RING_MTX_LOCK(tx_ring); 2915 ena_start_xmit(tx_ring); 2916 ENA_RING_MTX_UNLOCK(tx_ring); 2917 } 2918 } 2919 2920 static int 2921 ena_mq_start(if_t ifp, struct mbuf *m) 2922 { 2923 struct ena_adapter *adapter = ifp->if_softc; 2924 struct ena_ring *tx_ring; 2925 int ret, is_drbr_empty; 2926 uint32_t i; 2927 2928 if (unlikely((if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) == 0)) 2929 return (ENODEV); 2930 2931 /* Which queue to use */ 2932 /* 2933 * If everything is setup correctly, it should be the 2934 * same bucket that the current CPU we're on is. 2935 * It should improve performance. 2936 */ 2937 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) { 2938 #ifdef RSS 2939 if (rss_hash2bucket(m->m_pkthdr.flowid, 2940 M_HASHTYPE_GET(m), &i) == 0) { 2941 i = i % adapter->num_queues; 2942 2943 } else 2944 #endif 2945 { 2946 i = m->m_pkthdr.flowid % adapter->num_queues; 2947 } 2948 } else { 2949 i = curcpu % adapter->num_queues; 2950 } 2951 tx_ring = &adapter->tx_ring[i]; 2952 2953 /* Check if drbr is empty before putting packet */ 2954 is_drbr_empty = drbr_empty(ifp, tx_ring->br); 2955 ret = drbr_enqueue(ifp, tx_ring->br, m); 2956 if (unlikely(ret != 0)) { 2957 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 2958 return (ret); 2959 } 2960 2961 if ((is_drbr_empty != 0) && (ENA_RING_MTX_TRYLOCK(tx_ring) != 0)) { 2962 ena_start_xmit(tx_ring); 2963 ENA_RING_MTX_UNLOCK(tx_ring); 2964 } else { 2965 taskqueue_enqueue(tx_ring->enqueue_tq, &tx_ring->enqueue_task); 2966 } 2967 2968 return (0); 2969 } 2970 2971 static void 2972 ena_qflush(if_t ifp) 2973 { 2974 struct ena_adapter *adapter = ifp->if_softc; 2975 struct ena_ring *tx_ring = adapter->tx_ring; 2976 int i; 2977 2978 for(i = 0; i < adapter->num_queues; ++i, ++tx_ring) 2979 if (!drbr_empty(ifp, tx_ring->br)) { 2980 ENA_RING_MTX_LOCK(tx_ring); 2981 drbr_flush(ifp, tx_ring->br); 2982 ENA_RING_MTX_UNLOCK(tx_ring); 2983 } 2984 2985 if_qflush(ifp); 2986 } 2987 2988 static int 2989 ena_calc_io_queue_num(struct ena_adapter *adapter, 2990 struct ena_com_dev_get_features_ctx *get_feat_ctx) 2991 { 2992 int io_sq_num, io_cq_num, io_queue_num; 2993 2994 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 2995 io_cq_num = get_feat_ctx->max_queues.max_cq_num; 2996 2997 io_queue_num = min_t(int, mp_ncpus, ENA_MAX_NUM_IO_QUEUES); 2998 io_queue_num = min_t(int, io_queue_num, io_sq_num); 2999 io_queue_num = min_t(int, io_queue_num, io_cq_num); 3000 /* 1 IRQ for for mgmnt and 1 IRQ for each TX/RX pair */ 3001 io_queue_num = min_t(int, io_queue_num, 3002 pci_msix_count(adapter->pdev) - 1); 3003 #ifdef RSS 3004 io_queue_num = min_t(int, io_queue_num, rss_getnumbuckets()); 3005 #endif 3006 3007 return (io_queue_num); 3008 } 3009 3010 static int 3011 ena_calc_queue_size(struct ena_adapter *adapter, uint16_t *max_tx_sgl_size, 3012 uint16_t *max_rx_sgl_size, struct ena_com_dev_get_features_ctx *feat) 3013 { 3014 uint32_t queue_size = ENA_DEFAULT_RING_SIZE; 3015 uint32_t v; 3016 uint32_t q; 3017 3018 queue_size = min_t(uint32_t, queue_size, 3019 feat->max_queues.max_cq_depth); 3020 queue_size = min_t(uint32_t, queue_size, 3021 feat->max_queues.max_sq_depth); 3022 3023 /* round down to the nearest power of 2 */ 3024 v = queue_size; 3025 while (v != 0) { 3026 if (powerof2(queue_size) != 0) 3027 break; 3028 v /= 2; 3029 q = rounddown2(queue_size, v); 3030 if (q != 0) { 3031 queue_size = q; 3032 break; 3033 } 3034 } 3035 3036 if (unlikely(queue_size == 0)) { 3037 device_printf(adapter->pdev, "Invalid queue size\n"); 3038 return (ENA_COM_FAULT); 3039 } 3040 3041 *max_tx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3042 feat->max_queues.max_packet_tx_descs); 3043 *max_rx_sgl_size = min_t(uint16_t, ENA_PKT_MAX_BUFS, 3044 feat->max_queues.max_packet_rx_descs); 3045 3046 return (queue_size); 3047 } 3048 3049 static int 3050 ena_rss_init_default(struct ena_adapter *adapter) 3051 { 3052 struct ena_com_dev *ena_dev = adapter->ena_dev; 3053 device_t dev = adapter->pdev; 3054 int qid, rc, i; 3055 3056 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 3057 if (unlikely(rc != 0)) { 3058 device_printf(dev, "Cannot init indirect table\n"); 3059 return (rc); 3060 } 3061 3062 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 3063 #ifdef RSS 3064 qid = rss_get_indirection_to_bucket(i); 3065 qid = qid % adapter->num_queues; 3066 #else 3067 qid = i % adapter->num_queues; 3068 #endif 3069 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 3070 ENA_IO_RXQ_IDX(qid)); 3071 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3072 device_printf(dev, "Cannot fill indirect table\n"); 3073 goto err_rss_destroy; 3074 } 3075 } 3076 3077 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 3078 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 3079 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3080 device_printf(dev, "Cannot fill hash function\n"); 3081 goto err_rss_destroy; 3082 } 3083 3084 rc = ena_com_set_default_hash_ctrl(ena_dev); 3085 if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) { 3086 device_printf(dev, "Cannot fill hash control\n"); 3087 goto err_rss_destroy; 3088 } 3089 3090 return (0); 3091 3092 err_rss_destroy: 3093 ena_com_rss_destroy(ena_dev); 3094 return (rc); 3095 } 3096 3097 static void 3098 ena_rss_init_default_deferred(void *arg) 3099 { 3100 struct ena_adapter *adapter; 3101 devclass_t dc; 3102 int max; 3103 int rc; 3104 3105 dc = devclass_find("ena"); 3106 if (unlikely(dc == NULL)) { 3107 ena_trace(ENA_ALERT, "No devclass ena\n"); 3108 return; 3109 } 3110 3111 max = devclass_get_maxunit(dc); 3112 while (max-- >= 0) { 3113 adapter = devclass_get_softc(dc, max); 3114 if (adapter != NULL) { 3115 rc = ena_rss_init_default(adapter); 3116 adapter->rss_support = true; 3117 if (unlikely(rc != 0)) { 3118 device_printf(adapter->pdev, 3119 "WARNING: RSS was not properly initialized," 3120 " it will affect bandwidth\n"); 3121 adapter->rss_support = false; 3122 } 3123 } 3124 } 3125 } 3126 SYSINIT(ena_rss_init, SI_SUB_KICK_SCHEDULER, SI_ORDER_SECOND, ena_rss_init_default_deferred, NULL); 3127 3128 static void 3129 ena_config_host_info(struct ena_com_dev *ena_dev) 3130 { 3131 struct ena_admin_host_info *host_info; 3132 int rc; 3133 3134 /* Allocate only the host info */ 3135 rc = ena_com_allocate_host_info(ena_dev); 3136 if (unlikely(rc != 0)) { 3137 ena_trace(ENA_ALERT, "Cannot allocate host info\n"); 3138 return; 3139 } 3140 3141 host_info = ena_dev->host_attr.host_info; 3142 3143 host_info->os_type = ENA_ADMIN_OS_FREEBSD; 3144 host_info->kernel_ver = osreldate; 3145 3146 sprintf(host_info->kernel_ver_str, "%d", osreldate); 3147 host_info->os_dist = 0; 3148 strncpy(host_info->os_dist_str, osrelease, 3149 sizeof(host_info->os_dist_str) - 1); 3150 3151 host_info->driver_version = 3152 (DRV_MODULE_VER_MAJOR) | 3153 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 3154 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 3155 3156 rc = ena_com_set_host_attributes(ena_dev); 3157 if (unlikely(rc != 0)) { 3158 if (rc == EOPNOTSUPP) 3159 ena_trace(ENA_WARNING, "Cannot set host attributes\n"); 3160 else 3161 ena_trace(ENA_ALERT, "Cannot set host attributes\n"); 3162 3163 goto err; 3164 } 3165 3166 return; 3167 3168 err: 3169 ena_com_delete_host_info(ena_dev); 3170 } 3171 3172 static int 3173 ena_device_init(struct ena_adapter *adapter, device_t pdev, 3174 struct ena_com_dev_get_features_ctx *get_feat_ctx, int *wd_active) 3175 { 3176 struct ena_com_dev* ena_dev = adapter->ena_dev; 3177 bool readless_supported; 3178 uint32_t aenq_groups; 3179 int dma_width; 3180 int rc; 3181 3182 rc = ena_com_mmio_reg_read_request_init(ena_dev); 3183 if (unlikely(rc != 0)) { 3184 device_printf(pdev, "failed to init mmio read less\n"); 3185 return (rc); 3186 } 3187 3188 /* 3189 * The PCIe configuration space revision id indicate if mmio reg 3190 * read is disabled 3191 */ 3192 readless_supported = !(pci_get_revid(pdev) & ENA_MMIO_DISABLE_REG_READ); 3193 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 3194 3195 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 3196 if (unlikely(rc != 0)) { 3197 device_printf(pdev, "Can not reset device\n"); 3198 goto err_mmio_read_less; 3199 } 3200 3201 rc = ena_com_validate_version(ena_dev); 3202 if (unlikely(rc != 0)) { 3203 device_printf(pdev, "device version is too low\n"); 3204 goto err_mmio_read_less; 3205 } 3206 3207 dma_width = ena_com_get_dma_width(ena_dev); 3208 if (unlikely(dma_width < 0)) { 3209 device_printf(pdev, "Invalid dma width value %d", dma_width); 3210 rc = dma_width; 3211 goto err_mmio_read_less; 3212 } 3213 adapter->dma_width = dma_width; 3214 3215 /* ENA admin level init */ 3216 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true); 3217 if (unlikely(rc != 0)) { 3218 device_printf(pdev, 3219 "Can not initialize ena admin queue with device\n"); 3220 goto err_mmio_read_less; 3221 } 3222 3223 /* 3224 * To enable the msix interrupts the driver needs to know the number 3225 * of queues. So the driver uses polling mode to retrieve this 3226 * information 3227 */ 3228 ena_com_set_admin_polling_mode(ena_dev, true); 3229 3230 ena_config_host_info(ena_dev); 3231 3232 /* Get Device Attributes */ 3233 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 3234 if (unlikely(rc != 0)) { 3235 device_printf(pdev, 3236 "Cannot get attribute for ena device rc: %d\n", rc); 3237 goto err_admin_init; 3238 } 3239 3240 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 3241 BIT(ENA_ADMIN_FATAL_ERROR) | 3242 BIT(ENA_ADMIN_WARNING) | 3243 BIT(ENA_ADMIN_NOTIFICATION) | 3244 BIT(ENA_ADMIN_KEEP_ALIVE); 3245 3246 aenq_groups &= get_feat_ctx->aenq.supported_groups; 3247 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 3248 if (unlikely(rc != 0)) { 3249 device_printf(pdev, "Cannot configure aenq groups rc: %d\n", rc); 3250 goto err_admin_init; 3251 } 3252 3253 *wd_active = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 3254 3255 return (0); 3256 3257 err_admin_init: 3258 ena_com_delete_host_info(ena_dev); 3259 ena_com_admin_destroy(ena_dev); 3260 err_mmio_read_less: 3261 ena_com_mmio_reg_read_request_destroy(ena_dev); 3262 3263 return (rc); 3264 } 3265 3266 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter, 3267 int io_vectors) 3268 { 3269 struct ena_com_dev *ena_dev = adapter->ena_dev; 3270 int rc; 3271 3272 rc = ena_enable_msix(adapter); 3273 if (unlikely(rc != 0)) { 3274 device_printf(adapter->pdev, "Error with MSI-X enablement\n"); 3275 return (rc); 3276 } 3277 3278 ena_setup_mgmnt_intr(adapter); 3279 3280 rc = ena_request_mgmnt_irq(adapter); 3281 if (unlikely(rc != 0)) { 3282 device_printf(adapter->pdev, "Cannot setup mgmnt queue intr\n"); 3283 goto err_disable_msix; 3284 } 3285 3286 ena_com_set_admin_polling_mode(ena_dev, false); 3287 3288 ena_com_admin_aenq_enable(ena_dev); 3289 3290 return (0); 3291 3292 err_disable_msix: 3293 ena_disable_msix(adapter); 3294 3295 return (rc); 3296 } 3297 3298 /* Function called on ENA_ADMIN_KEEP_ALIVE event */ 3299 static void ena_keep_alive_wd(void *adapter_data, 3300 struct ena_admin_aenq_entry *aenq_e) 3301 { 3302 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3303 struct ena_admin_aenq_keep_alive_desc *desc; 3304 sbintime_t stime; 3305 uint64_t rx_drops; 3306 3307 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3308 3309 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 3310 counter_u64_zero(adapter->hw_stats.rx_drops); 3311 counter_u64_add(adapter->hw_stats.rx_drops, rx_drops); 3312 3313 stime = getsbinuptime(); 3314 atomic_store_rel_64(&adapter->keep_alive_timestamp, stime); 3315 } 3316 3317 /* Check for keep alive expiration */ 3318 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 3319 { 3320 sbintime_t timestamp, time; 3321 3322 if (adapter->wd_active == 0) 3323 return; 3324 3325 if (likely(adapter->keep_alive_timeout == 0)) 3326 return; 3327 3328 timestamp = atomic_load_acq_64(&adapter->keep_alive_timestamp); 3329 time = getsbinuptime() - timestamp; 3330 if (unlikely(time > adapter->keep_alive_timeout)) { 3331 device_printf(adapter->pdev, 3332 "Keep alive watchdog timeout.\n"); 3333 counter_u64_add(adapter->dev_stats.wd_expired, 1); 3334 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 3335 adapter->trigger_reset = true; 3336 } 3337 } 3338 3339 /* Check if admin queue is enabled */ 3340 static void check_for_admin_com_state(struct ena_adapter *adapter) 3341 { 3342 if (unlikely(ena_com_get_admin_running_state(adapter->ena_dev) == 3343 false)) { 3344 device_printf(adapter->pdev, 3345 "ENA admin queue is not in running state!\n"); 3346 counter_u64_add(adapter->dev_stats.admin_q_pause, 1); 3347 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 3348 adapter->trigger_reset = true; 3349 } 3350 } 3351 3352 static int 3353 check_missing_comp_in_queue(struct ena_adapter *adapter, 3354 struct ena_ring *tx_ring) 3355 { 3356 struct bintime curtime, time; 3357 struct ena_tx_buffer *tx_buf; 3358 uint32_t missed_tx = 0; 3359 int i; 3360 3361 getbinuptime(&curtime); 3362 3363 for (i = 0; i < tx_ring->ring_size; i++) { 3364 tx_buf = &tx_ring->tx_buffer_info[i]; 3365 3366 if (bintime_isset(&tx_buf->timestamp) == 0) 3367 continue; 3368 3369 time = curtime; 3370 bintime_sub(&time, &tx_buf->timestamp); 3371 3372 /* Check again if packet is still waiting */ 3373 if (unlikely(bttosbt(time) > adapter->missing_tx_timeout)) { 3374 3375 if (!tx_buf->print_once) 3376 ena_trace(ENA_WARNING, "Found a Tx that wasn't " 3377 "completed on time, qid %d, index %d.\n", 3378 tx_ring->qid, i); 3379 3380 tx_buf->print_once = true; 3381 missed_tx++; 3382 counter_u64_add(tx_ring->tx_stats.missing_tx_comp, 1); 3383 3384 if (unlikely(missed_tx > 3385 adapter->missing_tx_threshold)) { 3386 device_printf(adapter->pdev, 3387 "The number of lost tx completion " 3388 "is above the threshold (%d > %d). " 3389 "Reset the device\n", 3390 missed_tx, adapter->missing_tx_threshold); 3391 adapter->reset_reason = 3392 ENA_REGS_RESET_MISS_TX_CMPL; 3393 adapter->trigger_reset = true; 3394 return (EIO); 3395 } 3396 } 3397 } 3398 3399 return (0); 3400 } 3401 3402 /* 3403 * Check for TX which were not completed on time. 3404 * Timeout is defined by "missing_tx_timeout". 3405 * Reset will be performed if number of incompleted 3406 * transactions exceeds "missing_tx_threshold". 3407 */ 3408 static void 3409 check_for_missing_tx_completions(struct ena_adapter *adapter) 3410 { 3411 struct ena_ring *tx_ring; 3412 int i, budget, rc; 3413 3414 /* Make sure the driver doesn't turn the device in other process */ 3415 rmb(); 3416 3417 if (!adapter->up) 3418 return; 3419 3420 if (adapter->trigger_reset) 3421 return; 3422 3423 if (adapter->missing_tx_timeout == 0) 3424 return; 3425 3426 budget = adapter->missing_tx_max_queues; 3427 3428 for (i = adapter->next_monitored_tx_qid; i < adapter->num_queues; i++) { 3429 tx_ring = &adapter->tx_ring[i]; 3430 3431 rc = check_missing_comp_in_queue(adapter, tx_ring); 3432 if (unlikely(rc != 0)) 3433 return; 3434 3435 budget--; 3436 if (budget == 0) { 3437 i++; 3438 break; 3439 } 3440 } 3441 3442 adapter->next_monitored_tx_qid = i % adapter->num_queues; 3443 } 3444 3445 /* trigger deferred rx cleanup after 2 consecutive detections */ 3446 #define EMPTY_RX_REFILL 2 3447 /* For the rare case where the device runs out of Rx descriptors and the 3448 * msix handler failed to refill new Rx descriptors (due to a lack of memory 3449 * for example). 3450 * This case will lead to a deadlock: 3451 * The device won't send interrupts since all the new Rx packets will be dropped 3452 * The msix handler won't allocate new Rx descriptors so the device won't be 3453 * able to send new packets. 3454 * 3455 * When such a situation is detected - execute rx cleanup task in another thread 3456 */ 3457 static void 3458 check_for_empty_rx_ring(struct ena_adapter *adapter) 3459 { 3460 struct ena_ring *rx_ring; 3461 int i, refill_required; 3462 3463 if (!adapter->up) 3464 return; 3465 3466 if (adapter->trigger_reset) 3467 return; 3468 3469 for (i = 0; i < adapter->num_queues; i++) { 3470 rx_ring = &adapter->rx_ring[i]; 3471 3472 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq); 3473 if (unlikely(refill_required == (rx_ring->ring_size - 1))) { 3474 rx_ring->empty_rx_queue++; 3475 3476 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) { 3477 counter_u64_add(rx_ring->rx_stats.empty_rx_ring, 3478 1); 3479 3480 device_printf(adapter->pdev, 3481 "trigger refill for ring %d\n", i); 3482 3483 taskqueue_enqueue(rx_ring->cmpl_tq, 3484 &rx_ring->cmpl_task); 3485 rx_ring->empty_rx_queue = 0; 3486 } 3487 } else { 3488 rx_ring->empty_rx_queue = 0; 3489 } 3490 } 3491 } 3492 3493 static void 3494 ena_timer_service(void *data) 3495 { 3496 struct ena_adapter *adapter = (struct ena_adapter *)data; 3497 struct ena_admin_host_info *host_info = 3498 adapter->ena_dev->host_attr.host_info; 3499 3500 check_for_missing_keep_alive(adapter); 3501 3502 check_for_admin_com_state(adapter); 3503 3504 check_for_missing_tx_completions(adapter); 3505 3506 check_for_empty_rx_ring(adapter); 3507 3508 if (host_info != NULL) 3509 ena_update_host_info(host_info, adapter->ifp); 3510 3511 if (unlikely(adapter->trigger_reset)) { 3512 device_printf(adapter->pdev, "Trigger reset is on\n"); 3513 taskqueue_enqueue(adapter->reset_tq, &adapter->reset_task); 3514 return; 3515 } 3516 3517 /* 3518 * Schedule another timeout one second from now. 3519 */ 3520 callout_schedule_sbt(&adapter->timer_service, SBT_1S, SBT_1S, 0); 3521 } 3522 3523 static void 3524 ena_reset_task(void *arg, int pending) 3525 { 3526 struct ena_com_dev_get_features_ctx get_feat_ctx; 3527 struct ena_adapter *adapter = (struct ena_adapter *)arg; 3528 struct ena_com_dev *ena_dev = adapter->ena_dev; 3529 bool dev_up; 3530 int rc; 3531 3532 if (unlikely(!adapter->trigger_reset)) { 3533 device_printf(adapter->pdev, 3534 "device reset scheduled but trigger_reset is off\n"); 3535 return; 3536 } 3537 3538 sx_xlock(&adapter->ioctl_sx); 3539 3540 callout_drain(&adapter->timer_service); 3541 3542 dev_up = adapter->up; 3543 3544 ena_com_set_admin_running_state(ena_dev, false); 3545 ena_down(adapter); 3546 ena_free_mgmnt_irq(adapter); 3547 ena_disable_msix(adapter); 3548 ena_com_abort_admin_commands(ena_dev); 3549 ena_com_wait_for_abort_completion(ena_dev); 3550 ena_com_admin_destroy(ena_dev); 3551 ena_com_mmio_reg_read_request_destroy(ena_dev); 3552 3553 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3554 adapter->trigger_reset = false; 3555 3556 /* Finished destroy part. Restart the device */ 3557 rc = ena_device_init(adapter, adapter->pdev, &get_feat_ctx, 3558 &adapter->wd_active); 3559 if (unlikely(rc != 0)) { 3560 device_printf(adapter->pdev, 3561 "ENA device init failed! (err: %d)\n", rc); 3562 goto err_dev_free; 3563 } 3564 3565 rc = ena_enable_msix_and_set_admin_interrupts(adapter, 3566 adapter->num_queues); 3567 if (unlikely(rc != 0)) { 3568 device_printf(adapter->pdev, "Enable MSI-X failed\n"); 3569 goto err_com_free; 3570 } 3571 3572 /* If the interface was up before the reset bring it up */ 3573 if (dev_up) { 3574 rc = ena_up(adapter); 3575 if (unlikely(rc != 0)) { 3576 device_printf(adapter->pdev, 3577 "Failed to create I/O queues\n"); 3578 goto err_msix_free; 3579 } 3580 } 3581 3582 callout_reset_sbt(&adapter->timer_service, SBT_1S, SBT_1S, 3583 ena_timer_service, (void *)adapter, 0); 3584 3585 sx_unlock(&adapter->ioctl_sx); 3586 3587 return; 3588 3589 err_msix_free: 3590 ena_free_mgmnt_irq(adapter); 3591 ena_disable_msix(adapter); 3592 err_com_free: 3593 ena_com_admin_destroy(ena_dev); 3594 err_dev_free: 3595 device_printf(adapter->pdev, "ENA reset failed!\n"); 3596 adapter->running = false; 3597 sx_unlock(&adapter->ioctl_sx); 3598 } 3599 3600 /** 3601 * ena_attach - Device Initialization Routine 3602 * @pdev: device information struct 3603 * 3604 * Returns 0 on success, otherwise on failure. 3605 * 3606 * ena_attach initializes an adapter identified by a device structure. 3607 * The OS initialization, configuring of the adapter private structure, 3608 * and a hardware reset occur. 3609 **/ 3610 static int 3611 ena_attach(device_t pdev) 3612 { 3613 struct ena_com_dev_get_features_ctx get_feat_ctx; 3614 static int version_printed; 3615 struct ena_adapter *adapter; 3616 struct ena_com_dev *ena_dev = NULL; 3617 uint16_t tx_sgl_size = 0; 3618 uint16_t rx_sgl_size = 0; 3619 int io_queue_num; 3620 int queue_size; 3621 int rc; 3622 adapter = device_get_softc(pdev); 3623 adapter->pdev = pdev; 3624 3625 mtx_init(&adapter->global_mtx, "ENA global mtx", NULL, MTX_DEF); 3626 sx_init(&adapter->ioctl_sx, "ENA ioctl sx"); 3627 3628 /* Set up the timer service */ 3629 callout_init_mtx(&adapter->timer_service, &adapter->global_mtx, 0); 3630 adapter->keep_alive_timeout = DEFAULT_KEEP_ALIVE_TO; 3631 adapter->missing_tx_timeout = DEFAULT_TX_CMP_TO; 3632 adapter->missing_tx_max_queues = DEFAULT_TX_MONITORED_QUEUES; 3633 adapter->missing_tx_threshold = DEFAULT_TX_CMP_THRESHOLD; 3634 3635 if (version_printed++ == 0) 3636 device_printf(pdev, "%s\n", ena_version); 3637 3638 rc = ena_allocate_pci_resources(adapter); 3639 if (unlikely(rc != 0)) { 3640 device_printf(pdev, "PCI resource allocation failed!\n"); 3641 ena_free_pci_resources(adapter); 3642 return (rc); 3643 } 3644 3645 /* Allocate memory for ena_dev structure */ 3646 ena_dev = malloc(sizeof(struct ena_com_dev), M_DEVBUF, 3647 M_WAITOK | M_ZERO); 3648 3649 adapter->ena_dev = ena_dev; 3650 ena_dev->dmadev = pdev; 3651 ena_dev->bus = malloc(sizeof(struct ena_bus), M_DEVBUF, 3652 M_WAITOK | M_ZERO); 3653 3654 /* Store register resources */ 3655 ((struct ena_bus*)(ena_dev->bus))->reg_bar_t = 3656 rman_get_bustag(adapter->registers); 3657 ((struct ena_bus*)(ena_dev->bus))->reg_bar_h = 3658 rman_get_bushandle(adapter->registers); 3659 3660 if (unlikely(((struct ena_bus*)(ena_dev->bus))->reg_bar_h == 0)) { 3661 device_printf(pdev, "failed to pmap registers bar\n"); 3662 rc = ENXIO; 3663 goto err_bus_free; 3664 } 3665 3666 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3667 3668 /* Device initialization */ 3669 rc = ena_device_init(adapter, pdev, &get_feat_ctx, &adapter->wd_active); 3670 if (unlikely(rc != 0)) { 3671 device_printf(pdev, "ENA device init failed! (err: %d)\n", rc); 3672 rc = ENXIO; 3673 goto err_bus_free; 3674 } 3675 3676 adapter->keep_alive_timestamp = getsbinuptime(); 3677 3678 adapter->tx_offload_cap = get_feat_ctx.offload.tx; 3679 3680 /* Set for sure that interface is not up */ 3681 adapter->up = false; 3682 3683 memcpy(adapter->mac_addr, get_feat_ctx.dev_attr.mac_addr, 3684 ETHER_ADDR_LEN); 3685 3686 /* calculate IO queue number to create */ 3687 io_queue_num = ena_calc_io_queue_num(adapter, &get_feat_ctx); 3688 3689 ENA_ASSERT(io_queue_num > 0, "Invalid queue number: %d\n", 3690 io_queue_num); 3691 adapter->num_queues = io_queue_num; 3692 3693 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 3694 3695 /* calculatre ring sizes */ 3696 queue_size = ena_calc_queue_size(adapter,&tx_sgl_size, 3697 &rx_sgl_size, &get_feat_ctx); 3698 if (unlikely((queue_size <= 0) || (io_queue_num <= 0))) { 3699 rc = ENA_COM_FAULT; 3700 goto err_com_free; 3701 } 3702 3703 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3704 3705 adapter->tx_ring_size = queue_size; 3706 adapter->rx_ring_size = queue_size; 3707 3708 adapter->max_tx_sgl_size = tx_sgl_size; 3709 adapter->max_rx_sgl_size = rx_sgl_size; 3710 3711 /* set up dma tags for rx and tx buffers */ 3712 rc = ena_setup_tx_dma_tag(adapter); 3713 if (unlikely(rc != 0)) { 3714 device_printf(pdev, "Failed to create TX DMA tag\n"); 3715 goto err_com_free; 3716 } 3717 3718 rc = ena_setup_rx_dma_tag(adapter); 3719 if (unlikely(rc != 0)) { 3720 device_printf(pdev, "Failed to create RX DMA tag\n"); 3721 goto err_tx_tag_free; 3722 } 3723 3724 /* initialize rings basic information */ 3725 device_printf(pdev, "initalize %d io queues\n", io_queue_num); 3726 ena_init_io_rings(adapter); 3727 3728 /* setup network interface */ 3729 rc = ena_setup_ifnet(pdev, adapter, &get_feat_ctx); 3730 if (unlikely(rc != 0)) { 3731 device_printf(pdev, "Error with network interface setup\n"); 3732 goto err_io_free; 3733 } 3734 3735 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num); 3736 if (unlikely(rc != 0)) { 3737 device_printf(pdev, 3738 "Failed to enable and set the admin interrupts\n"); 3739 goto err_ifp_free; 3740 } 3741 3742 /* Initialize reset task queue */ 3743 TASK_INIT(&adapter->reset_task, 0, ena_reset_task, adapter); 3744 adapter->reset_tq = taskqueue_create("ena_reset_enqueue", 3745 M_WAITOK | M_ZERO, taskqueue_thread_enqueue, &adapter->reset_tq); 3746 taskqueue_start_threads(&adapter->reset_tq, 1, PI_NET, 3747 "%s rstq", device_get_nameunit(adapter->pdev)); 3748 3749 /* Initialize statistics */ 3750 ena_alloc_counters((counter_u64_t *)&adapter->dev_stats, 3751 sizeof(struct ena_stats_dev)); 3752 ena_alloc_counters((counter_u64_t *)&adapter->hw_stats, 3753 sizeof(struct ena_hw_stats)); 3754 ena_sysctl_add_nodes(adapter); 3755 3756 /* Tell the stack that the interface is not active */ 3757 if_setdrvflagbits(adapter->ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 3758 3759 adapter->running = true; 3760 return (0); 3761 3762 err_ifp_free: 3763 if_detach(adapter->ifp); 3764 if_free(adapter->ifp); 3765 err_io_free: 3766 ena_free_all_io_rings_resources(adapter); 3767 ena_free_rx_dma_tag(adapter); 3768 err_tx_tag_free: 3769 ena_free_tx_dma_tag(adapter); 3770 err_com_free: 3771 ena_com_admin_destroy(ena_dev); 3772 ena_com_delete_host_info(ena_dev); 3773 ena_com_mmio_reg_read_request_destroy(ena_dev); 3774 err_bus_free: 3775 free(ena_dev->bus, M_DEVBUF); 3776 free(ena_dev, M_DEVBUF); 3777 ena_free_pci_resources(adapter); 3778 3779 return (rc); 3780 } 3781 3782 /** 3783 * ena_detach - Device Removal Routine 3784 * @pdev: device information struct 3785 * 3786 * ena_detach is called by the device subsystem to alert the driver 3787 * that it should release a PCI device. 3788 **/ 3789 static int 3790 ena_detach(device_t pdev) 3791 { 3792 struct ena_adapter *adapter = device_get_softc(pdev); 3793 struct ena_com_dev *ena_dev = adapter->ena_dev; 3794 int rc; 3795 3796 /* Make sure VLANS are not using driver */ 3797 if (adapter->ifp->if_vlantrunk != NULL) { 3798 device_printf(adapter->pdev ,"VLAN is in use, detach first\n"); 3799 return (EBUSY); 3800 } 3801 3802 /* Free reset task and callout */ 3803 callout_drain(&adapter->timer_service); 3804 while (taskqueue_cancel(adapter->reset_tq, &adapter->reset_task, NULL)) 3805 taskqueue_drain(adapter->reset_tq, &adapter->reset_task); 3806 taskqueue_free(adapter->reset_tq); 3807 3808 sx_xlock(&adapter->ioctl_sx); 3809 ena_down(adapter); 3810 sx_unlock(&adapter->ioctl_sx); 3811 3812 if (adapter->ifp != NULL) { 3813 ether_ifdetach(adapter->ifp); 3814 if_free(adapter->ifp); 3815 } 3816 3817 ena_free_all_io_rings_resources(adapter); 3818 3819 ena_free_counters((counter_u64_t *)&adapter->hw_stats, 3820 sizeof(struct ena_hw_stats)); 3821 ena_free_counters((counter_u64_t *)&adapter->dev_stats, 3822 sizeof(struct ena_stats_dev)); 3823 3824 if (likely(adapter->rss_support)) 3825 ena_com_rss_destroy(ena_dev); 3826 3827 rc = ena_free_rx_dma_tag(adapter); 3828 if (unlikely(rc != 0)) 3829 device_printf(adapter->pdev, 3830 "Unmapped RX DMA tag associations\n"); 3831 3832 rc = ena_free_tx_dma_tag(adapter); 3833 if (unlikely(rc != 0)) 3834 device_printf(adapter->pdev, 3835 "Unmapped TX DMA tag associations\n"); 3836 3837 /* Reset the device only if the device is running. */ 3838 if (adapter->running) 3839 ena_com_dev_reset(ena_dev, adapter->reset_reason); 3840 3841 ena_com_delete_host_info(ena_dev); 3842 3843 ena_free_irqs(adapter); 3844 3845 ena_com_abort_admin_commands(ena_dev); 3846 3847 ena_com_wait_for_abort_completion(ena_dev); 3848 3849 ena_com_admin_destroy(ena_dev); 3850 3851 ena_com_mmio_reg_read_request_destroy(ena_dev); 3852 3853 ena_free_pci_resources(adapter); 3854 3855 mtx_destroy(&adapter->global_mtx); 3856 sx_destroy(&adapter->ioctl_sx); 3857 3858 if (ena_dev->bus != NULL) 3859 free(ena_dev->bus, M_DEVBUF); 3860 3861 if (ena_dev != NULL) 3862 free(ena_dev, M_DEVBUF); 3863 3864 return (bus_generic_detach(pdev)); 3865 } 3866 3867 /****************************************************************************** 3868 ******************************** AENQ Handlers ******************************* 3869 *****************************************************************************/ 3870 /** 3871 * ena_update_on_link_change: 3872 * Notify the network interface about the change in link status 3873 **/ 3874 static void 3875 ena_update_on_link_change(void *adapter_data, 3876 struct ena_admin_aenq_entry *aenq_e) 3877 { 3878 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3879 struct ena_admin_aenq_link_change_desc *aenq_desc; 3880 int status; 3881 if_t ifp; 3882 3883 aenq_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 3884 ifp = adapter->ifp; 3885 status = aenq_desc->flags & 3886 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 3887 3888 if (status != 0) { 3889 device_printf(adapter->pdev, "link is UP\n"); 3890 if_link_state_change(ifp, LINK_STATE_UP); 3891 } else if (status == 0) { 3892 device_printf(adapter->pdev, "link is DOWN\n"); 3893 if_link_state_change(ifp, LINK_STATE_DOWN); 3894 } else { 3895 device_printf(adapter->pdev, "invalid value recvd\n"); 3896 BUG(); 3897 } 3898 3899 adapter->link_status = status; 3900 } 3901 3902 /** 3903 * This handler will called for unknown event group or unimplemented handlers 3904 **/ 3905 static void 3906 unimplemented_aenq_handler(void *data, 3907 struct ena_admin_aenq_entry *aenq_e) 3908 { 3909 return; 3910 } 3911 3912 static struct ena_aenq_handlers aenq_handlers = { 3913 .handlers = { 3914 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3915 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd, 3916 }, 3917 .unimplemented_handler = unimplemented_aenq_handler 3918 }; 3919 3920 /********************************************************************* 3921 * FreeBSD Device Interface Entry Points 3922 *********************************************************************/ 3923 3924 static device_method_t ena_methods[] = { 3925 /* Device interface */ 3926 DEVMETHOD(device_probe, ena_probe), 3927 DEVMETHOD(device_attach, ena_attach), 3928 DEVMETHOD(device_detach, ena_detach), 3929 DEVMETHOD_END 3930 }; 3931 3932 static driver_t ena_driver = { 3933 "ena", ena_methods, sizeof(struct ena_adapter), 3934 }; 3935 3936 devclass_t ena_devclass; 3937 DRIVER_MODULE(ena, pci, ena_driver, ena_devclass, 0, 0); 3938 MODULE_DEPEND(ena, pci, 1, 1, 1); 3939 MODULE_DEPEND(ena, ether, 1, 1, 1); 3940 3941 /*********************************************************************/ 3942