1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "if_em.h" 30 31 #ifdef RSS 32 #include <net/rss_config.h> 33 #include <netinet/in_rss.h> 34 #endif 35 36 #ifdef VERBOSE_DEBUG 37 #define DPRINTF device_printf 38 #else 39 #define DPRINTF(...) 40 #endif 41 42 /********************************************************************* 43 * Local Function prototypes 44 *********************************************************************/ 45 static int igb_isc_txd_encap(void *arg, if_pkt_info_t pi); 46 static void igb_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx); 47 static int igb_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear); 48 49 static void igb_isc_rxd_refill(void *arg, if_rxd_update_t iru); 50 51 static void igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, 52 qidx_t pidx); 53 static int igb_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, 54 qidx_t budget); 55 56 static int igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri); 57 58 static int igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, 59 uint32_t *cmd_type_len, uint32_t *olinfo_status); 60 static int igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, 61 uint32_t *cmd_type_len, uint32_t *olinfo_status); 62 63 static void igb_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype); 64 static int igb_determine_rsstype(uint16_t pkt_info); 65 66 extern void igb_if_enable_intr(if_ctx_t ctx); 67 extern int em_intr(void *arg); 68 69 struct if_txrx igb_txrx = { 70 .ift_txd_encap = igb_isc_txd_encap, 71 .ift_txd_flush = igb_isc_txd_flush, 72 .ift_txd_credits_update = igb_isc_txd_credits_update, 73 .ift_rxd_available = igb_isc_rxd_available, 74 .ift_rxd_pkt_get = igb_isc_rxd_pkt_get, 75 .ift_rxd_refill = igb_isc_rxd_refill, 76 .ift_rxd_flush = igb_isc_rxd_flush, 77 .ift_legacy_intr = em_intr 78 }; 79 80 /********************************************************************** 81 * 82 * Setup work for hardware segmentation offload (TSO) on 83 * adapters using advanced tx descriptors 84 * 85 **********************************************************************/ 86 static int 87 igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len, 88 uint32_t *olinfo_status) 89 { 90 struct e1000_adv_tx_context_desc *TXD; 91 struct e1000_softc *sc = txr->sc; 92 uint32_t type_tucmd_mlhl = 0, vlan_macip_lens = 0; 93 uint32_t mss_l4len_idx = 0; 94 uint32_t paylen; 95 96 switch(pi->ipi_etype) { 97 case ETHERTYPE_IPV6: 98 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 99 break; 100 case ETHERTYPE_IP: 101 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 102 /* Tell transmit desc to also do IPv4 checksum. */ 103 *olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 104 break; 105 default: 106 panic("%s: CSUM_TSO but no supported IP version (0x%04x)", 107 __func__, ntohs(pi->ipi_etype)); 108 break; 109 } 110 111 TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 112 113 /* This is used in the transmit desc in encap */ 114 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen; 115 116 /* VLAN MACLEN IPLEN */ 117 if (pi->ipi_mflags & M_VLANTAG) { 118 vlan_macip_lens |= (pi->ipi_vtag << E1000_ADVTXD_VLAN_SHIFT); 119 } 120 121 vlan_macip_lens |= pi->ipi_ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 122 vlan_macip_lens |= pi->ipi_ip_hlen; 123 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 124 125 /* ADV DTYPE TUCMD */ 126 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 127 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 128 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 129 130 /* MSS L4LEN IDX */ 131 mss_l4len_idx |= (pi->ipi_tso_segsz << E1000_ADVTXD_MSS_SHIFT); 132 mss_l4len_idx |= (pi->ipi_tcp_hlen << E1000_ADVTXD_L4LEN_SHIFT); 133 /* 82575 needs the queue index added */ 134 if (sc->hw.mac.type == e1000_82575) 135 mss_l4len_idx |= txr->me << 4; 136 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 137 138 TXD->u.seqnum_seed = htole32(0); 139 *cmd_type_len |= E1000_ADVTXD_DCMD_TSE; 140 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 141 *olinfo_status |= paylen << E1000_ADVTXD_PAYLEN_SHIFT; 142 143 return (1); 144 } 145 146 /********************************************************************* 147 * 148 * Advanced Context Descriptor setup for VLAN, CSUM or TSO 149 * 150 **********************************************************************/ 151 static int 152 igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len, 153 uint32_t *olinfo_status) 154 { 155 struct e1000_adv_tx_context_desc *TXD; 156 struct e1000_softc *sc = txr->sc; 157 uint32_t vlan_macip_lens, type_tucmd_mlhl; 158 uint32_t mss_l4len_idx; 159 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0; 160 161 /* First check if TSO is to be used */ 162 if (pi->ipi_csum_flags & CSUM_TSO) 163 return (igb_tso_setup(txr, pi, cmd_type_len, olinfo_status)); 164 165 /* Indicate the whole packet as payload when not doing TSO */ 166 *olinfo_status |= pi->ipi_len << E1000_ADVTXD_PAYLEN_SHIFT; 167 168 /* Now ready a context descriptor */ 169 TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 170 171 /* 172 ** In advanced descriptors the vlan tag must 173 ** be placed into the context descriptor. Hence 174 ** we need to make one even if not doing offloads. 175 */ 176 if (pi->ipi_mflags & M_VLANTAG) { 177 vlan_macip_lens |= (pi->ipi_vtag << E1000_ADVTXD_VLAN_SHIFT); 178 } else if ((pi->ipi_csum_flags & IGB_CSUM_OFFLOAD) == 0) { 179 return (0); 180 } 181 182 /* Set the ether header length */ 183 vlan_macip_lens |= pi->ipi_ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 184 185 switch(pi->ipi_etype) { 186 case ETHERTYPE_IP: 187 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 188 break; 189 case ETHERTYPE_IPV6: 190 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 191 break; 192 default: 193 break; 194 } 195 196 vlan_macip_lens |= pi->ipi_ip_hlen; 197 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 198 199 switch (pi->ipi_ipproto) { 200 case IPPROTO_TCP: 201 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) { 202 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 203 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 204 } 205 break; 206 case IPPROTO_UDP: 207 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) { 208 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP; 209 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 210 } 211 break; 212 case IPPROTO_SCTP: 213 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) { 214 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP; 215 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 216 } 217 break; 218 default: 219 break; 220 } 221 222 /* 82575 needs the queue index added */ 223 if (sc->hw.mac.type == e1000_82575) 224 mss_l4len_idx = txr->me << 4; 225 226 /* Now copy bits into descriptor */ 227 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 228 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 229 TXD->u.seqnum_seed = htole32(0); 230 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 231 232 return (1); 233 } 234 235 static int 236 igb_isc_txd_encap(void *arg, if_pkt_info_t pi) 237 { 238 struct e1000_softc *sc = arg; 239 if_softc_ctx_t scctx = sc->shared; 240 struct em_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx]; 241 struct tx_ring *txr = &que->txr; 242 int nsegs = pi->ipi_nsegs; 243 bus_dma_segment_t *segs = pi->ipi_segs; 244 union e1000_adv_tx_desc *txd = NULL; 245 int i, j, pidx_last; 246 uint32_t olinfo_status, cmd_type_len, txd_flags; 247 qidx_t ntxd; 248 249 pidx_last = olinfo_status = 0; 250 /* Basic descriptor defines */ 251 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | 252 E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT); 253 254 if (pi->ipi_mflags & M_VLANTAG) 255 cmd_type_len |= E1000_ADVTXD_DCMD_VLE; 256 257 i = pi->ipi_pidx; 258 ntxd = scctx->isc_ntxd[0]; 259 txd_flags = pi->ipi_flags & IPI_TX_INTR ? E1000_ADVTXD_DCMD_RS : 0; 260 /* Consume the first descriptor */ 261 i += igb_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status); 262 if (i == scctx->isc_ntxd[0]) 263 i = 0; 264 265 /* 82575 needs the queue index added */ 266 if (sc->hw.mac.type == e1000_82575) 267 olinfo_status |= txr->me << 4; 268 269 for (j = 0; j < nsegs; j++) { 270 bus_size_t seglen; 271 bus_addr_t segaddr; 272 273 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i]; 274 seglen = segs[j].ds_len; 275 segaddr = htole64(segs[j].ds_addr); 276 277 txd->read.buffer_addr = segaddr; 278 txd->read.cmd_type_len = htole32(E1000_TXD_CMD_IFCS | 279 cmd_type_len | seglen); 280 txd->read.olinfo_status = htole32(olinfo_status); 281 pidx_last = i; 282 if (++i == scctx->isc_ntxd[0]) { 283 i = 0; 284 } 285 } 286 if (txd_flags) { 287 txr->tx_rsq[txr->tx_rs_pidx] = pidx_last; 288 txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & (ntxd-1); 289 MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx); 290 } 291 292 txd->read.cmd_type_len |= htole32(E1000_TXD_CMD_EOP | txd_flags); 293 pi->ipi_new_pidx = i; 294 295 /* Sent data accounting for AIM */ 296 txr->tx_bytes += pi->ipi_len; 297 ++txr->tx_packets; 298 299 return (0); 300 } 301 302 static void 303 igb_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx) 304 { 305 struct e1000_softc *sc = arg; 306 struct em_tx_queue *que = &sc->tx_queues[txqid]; 307 struct tx_ring *txr = &que->txr; 308 309 E1000_WRITE_REG(&sc->hw, E1000_TDT(txr->me), pidx); 310 } 311 312 static int 313 igb_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear) 314 { 315 struct e1000_softc *sc = arg; 316 if_softc_ctx_t scctx = sc->shared; 317 struct em_tx_queue *que = &sc->tx_queues[txqid]; 318 struct tx_ring *txr = &que->txr; 319 320 qidx_t processed = 0; 321 int updated; 322 qidx_t cur, prev, ntxd, rs_cidx; 323 int32_t delta; 324 uint8_t status; 325 326 rs_cidx = txr->tx_rs_cidx; 327 if (rs_cidx == txr->tx_rs_pidx) 328 return (0); 329 cur = txr->tx_rsq[rs_cidx]; 330 status = ((union e1000_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 331 updated = !!(status & E1000_TXD_STAT_DD); 332 333 if (!updated) 334 return (0); 335 336 /* If clear is false just let caller know that there 337 * are descriptors to reclaim */ 338 if (!clear) 339 return (1); 340 341 prev = txr->tx_cidx_processed; 342 ntxd = scctx->isc_ntxd[0]; 343 do { 344 MPASS(prev != cur); 345 delta = (int32_t)cur - (int32_t)prev; 346 if (delta < 0) 347 delta += ntxd; 348 MPASS(delta > 0); 349 350 processed += delta; 351 prev = cur; 352 rs_cidx = (rs_cidx + 1) & (ntxd-1); 353 if (rs_cidx == txr->tx_rs_pidx) 354 break; 355 cur = txr->tx_rsq[rs_cidx]; 356 status = ((union e1000_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 357 } while ((status & E1000_TXD_STAT_DD)); 358 359 txr->tx_rs_cidx = rs_cidx; 360 txr->tx_cidx_processed = prev; 361 return (processed); 362 } 363 364 static void 365 igb_isc_rxd_refill(void *arg, if_rxd_update_t iru) 366 { 367 struct e1000_softc *sc = arg; 368 if_softc_ctx_t scctx = sc->shared; 369 uint16_t rxqid = iru->iru_qsidx; 370 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 371 union e1000_adv_rx_desc *rxd; 372 struct rx_ring *rxr = &que->rxr; 373 uint64_t *paddrs; 374 uint32_t next_pidx, pidx; 375 uint16_t count; 376 int i; 377 378 paddrs = iru->iru_paddrs; 379 pidx = iru->iru_pidx; 380 count = iru->iru_count; 381 382 for (i = 0, next_pidx = pidx; i < count; i++) { 383 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[next_pidx]; 384 385 rxd->read.pkt_addr = htole64(paddrs[i]); 386 if (++next_pidx == scctx->isc_nrxd[0]) 387 next_pidx = 0; 388 } 389 } 390 391 static void 392 igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx) 393 { 394 struct e1000_softc *sc = arg; 395 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 396 struct rx_ring *rxr = &que->rxr; 397 398 E1000_WRITE_REG(&sc->hw, E1000_RDT(rxr->me), pidx); 399 } 400 401 static int 402 igb_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget) 403 { 404 struct e1000_softc *sc = arg; 405 if_softc_ctx_t scctx = sc->shared; 406 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 407 struct rx_ring *rxr = &que->rxr; 408 union e1000_adv_rx_desc *rxd; 409 uint32_t staterr = 0; 410 int cnt, i; 411 412 for (cnt = 0, i = idx; cnt < scctx->isc_nrxd[0] && cnt <= budget;) { 413 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[i]; 414 staterr = le32toh(rxd->wb.upper.status_error); 415 416 if ((staterr & E1000_RXD_STAT_DD) == 0) 417 break; 418 if (++i == scctx->isc_nrxd[0]) 419 i = 0; 420 if (staterr & E1000_RXD_STAT_EOP) 421 cnt++; 422 } 423 return (cnt); 424 } 425 426 /**************************************************************** 427 * Routine sends data which has been dma'ed into host memory 428 * to upper layer. Initialize ri structure. 429 * 430 * Returns 0 upon success, errno on failure 431 ***************************************************************/ 432 433 static int 434 igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri) 435 { 436 struct e1000_softc *sc = arg; 437 if_softc_ctx_t scctx = sc->shared; 438 struct em_rx_queue *que = &sc->rx_queues[ri->iri_qsidx]; 439 struct rx_ring *rxr = &que->rxr; 440 union e1000_adv_rx_desc *rxd; 441 442 uint16_t pkt_info, len; 443 uint32_t ptype, staterr; 444 int i, cidx; 445 bool eop; 446 447 staterr = i = 0; 448 cidx = ri->iri_cidx; 449 450 do { 451 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[cidx]; 452 staterr = le32toh(rxd->wb.upper.status_error); 453 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info); 454 455 MPASS ((staterr & E1000_RXD_STAT_DD) != 0); 456 457 len = le16toh(rxd->wb.upper.length); 458 ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGB_PKTTYPE_MASK; 459 460 ri->iri_len += len; 461 rxr->rx_bytes += ri->iri_len; 462 463 rxd->wb.upper.status_error = 0; 464 eop = ((staterr & E1000_RXD_STAT_EOP) == E1000_RXD_STAT_EOP); 465 466 /* Make sure bad packets are discarded */ 467 if (eop && ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) != 0)) { 468 sc->dropped_pkts++; 469 ++rxr->rx_discarded; 470 return (EBADMSG); 471 } 472 ri->iri_frags[i].irf_flid = 0; 473 ri->iri_frags[i].irf_idx = cidx; 474 ri->iri_frags[i].irf_len = len; 475 476 if (++cidx == scctx->isc_nrxd[0]) 477 cidx = 0; 478 #ifdef notyet 479 if (rxr->hdr_split == true) { 480 ri->iri_frags[i].irf_flid = 1; 481 ri->iri_frags[i].irf_idx = cidx; 482 if (++cidx == scctx->isc_nrxd[0]) 483 cidx = 0; 484 } 485 #endif 486 i++; 487 } while (!eop); 488 489 rxr->rx_packets++; 490 491 if ((scctx->isc_capenable & IFCAP_RXCSUM) != 0) 492 igb_rx_checksum(staterr, ri, ptype); 493 494 if (staterr & E1000_RXD_STAT_VP) { 495 if (((sc->hw.mac.type == e1000_i350) || 496 (sc->hw.mac.type == e1000_i354)) && 497 (staterr & E1000_RXDEXT_STATERR_LB)) 498 ri->iri_vtag = be16toh(rxd->wb.upper.vlan); 499 else 500 ri->iri_vtag = le16toh(rxd->wb.upper.vlan); 501 ri->iri_flags |= M_VLANTAG; 502 } 503 504 ri->iri_flowid = 505 le32toh(rxd->wb.lower.hi_dword.rss); 506 ri->iri_rsstype = igb_determine_rsstype(pkt_info); 507 ri->iri_nfrags = i; 508 509 return (0); 510 } 511 512 /********************************************************************* 513 * 514 * Verify that the hardware indicated that the checksum is valid. 515 * Inform the stack about the status of checksum so that stack 516 * doesn't spend time verifying the checksum. 517 * 518 *********************************************************************/ 519 static void 520 igb_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype) 521 { 522 uint16_t status = (uint16_t)staterr; 523 uint8_t errors = (uint8_t)(staterr >> 24); 524 525 if (__predict_false(status & E1000_RXD_STAT_IXSM)) 526 return; 527 528 /* If there is a layer 3 or 4 error we are done */ 529 if (__predict_false(errors & (E1000_RXD_ERR_IPE | E1000_RXD_ERR_TCPE))) 530 return; 531 532 /* IP Checksum Good */ 533 if (status & E1000_RXD_STAT_IPCS) 534 ri->iri_csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID); 535 536 /* Valid L4E checksum */ 537 if (__predict_true(status & 538 (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) { 539 /* SCTP header present */ 540 if (__predict_false((ptype & E1000_RXDADV_PKTTYPE_ETQF) == 0 && 541 (ptype & E1000_RXDADV_PKTTYPE_SCTP) != 0)) { 542 ri->iri_csum_flags |= CSUM_SCTP_VALID; 543 } else { 544 ri->iri_csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 545 ri->iri_csum_data = htons(0xffff); 546 } 547 } 548 } 549 550 /******************************************************************** 551 * 552 * Parse the packet type to determine the appropriate hash 553 * 554 ******************************************************************/ 555 static int 556 igb_determine_rsstype(uint16_t pkt_info) 557 { 558 switch (pkt_info & E1000_RXDADV_RSSTYPE_MASK) { 559 case E1000_RXDADV_RSSTYPE_IPV4_TCP: 560 return M_HASHTYPE_RSS_TCP_IPV4; 561 case E1000_RXDADV_RSSTYPE_IPV4: 562 return M_HASHTYPE_RSS_IPV4; 563 case E1000_RXDADV_RSSTYPE_IPV6_TCP: 564 return M_HASHTYPE_RSS_TCP_IPV6; 565 case E1000_RXDADV_RSSTYPE_IPV6_EX: 566 return M_HASHTYPE_RSS_IPV6_EX; 567 case E1000_RXDADV_RSSTYPE_IPV6: 568 return M_HASHTYPE_RSS_IPV6; 569 case E1000_RXDADV_RSSTYPE_IPV6_TCP_EX: 570 return M_HASHTYPE_RSS_TCP_IPV6_EX; 571 default: 572 return M_HASHTYPE_OPAQUE; 573 } 574 } 575