1 /*- 2 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 #include "if_em.h" 29 30 #ifdef RSS 31 #include <net/rss_config.h> 32 #include <netinet/in_rss.h> 33 #endif 34 35 #ifdef VERBOSE_DEBUG 36 #define DPRINTF device_printf 37 #else 38 #define DPRINTF(...) 39 #endif 40 41 /********************************************************************* 42 * Local Function prototypes 43 *********************************************************************/ 44 static int igb_isc_txd_encap(void *arg, if_pkt_info_t pi); 45 static void igb_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx); 46 static int igb_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear); 47 48 static void igb_isc_rxd_refill(void *arg, if_rxd_update_t iru); 49 50 static void igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx); 51 static int igb_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget); 52 53 static int igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri); 54 55 static int igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status); 56 static int igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status); 57 58 static void igb_rx_checksum(u32 staterr, if_rxd_info_t ri, u32 ptype); 59 static int igb_determine_rsstype(u16 pkt_info); 60 61 extern void igb_if_enable_intr(if_ctx_t ctx); 62 extern int em_intr(void *arg); 63 64 struct if_txrx igb_txrx = { 65 .ift_txd_encap = igb_isc_txd_encap, 66 .ift_txd_flush = igb_isc_txd_flush, 67 .ift_txd_credits_update = igb_isc_txd_credits_update, 68 .ift_rxd_available = igb_isc_rxd_available, 69 .ift_rxd_pkt_get = igb_isc_rxd_pkt_get, 70 .ift_rxd_refill = igb_isc_rxd_refill, 71 .ift_rxd_flush = igb_isc_rxd_flush, 72 .ift_legacy_intr = em_intr 73 }; 74 75 extern if_shared_ctx_t em_sctx; 76 77 /********************************************************************** 78 * 79 * Setup work for hardware segmentation offload (TSO) on 80 * adapters using advanced tx descriptors 81 * 82 **********************************************************************/ 83 static int 84 igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status) 85 { 86 struct e1000_adv_tx_context_desc *TXD; 87 struct adapter *adapter = txr->adapter; 88 u32 type_tucmd_mlhl = 0, vlan_macip_lens = 0; 89 u32 mss_l4len_idx = 0; 90 u32 paylen; 91 92 switch(pi->ipi_etype) { 93 case ETHERTYPE_IPV6: 94 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 95 break; 96 case ETHERTYPE_IP: 97 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 98 /* Tell transmit desc to also do IPv4 checksum. */ 99 *olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 100 break; 101 default: 102 panic("%s: CSUM_TSO but no supported IP version (0x%04x)", 103 __func__, ntohs(pi->ipi_etype)); 104 break; 105 } 106 107 TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 108 109 /* This is used in the transmit desc in encap */ 110 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen; 111 112 /* VLAN MACLEN IPLEN */ 113 if (pi->ipi_mflags & M_VLANTAG) { 114 vlan_macip_lens |= (pi->ipi_vtag << E1000_ADVTXD_VLAN_SHIFT); 115 } 116 117 vlan_macip_lens |= pi->ipi_ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 118 vlan_macip_lens |= pi->ipi_ip_hlen; 119 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 120 121 /* ADV DTYPE TUCMD */ 122 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 123 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 124 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 125 126 /* MSS L4LEN IDX */ 127 mss_l4len_idx |= (pi->ipi_tso_segsz << E1000_ADVTXD_MSS_SHIFT); 128 mss_l4len_idx |= (pi->ipi_tcp_hlen << E1000_ADVTXD_L4LEN_SHIFT); 129 /* 82575 needs the queue index added */ 130 if (adapter->hw.mac.type == e1000_82575) 131 mss_l4len_idx |= txr->me << 4; 132 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 133 134 TXD->seqnum_seed = htole32(0); 135 *cmd_type_len |= E1000_ADVTXD_DCMD_TSE; 136 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 137 *olinfo_status |= paylen << E1000_ADVTXD_PAYLEN_SHIFT; 138 139 return (1); 140 } 141 142 /********************************************************************* 143 * 144 * Advanced Context Descriptor setup for VLAN, CSUM or TSO 145 * 146 **********************************************************************/ 147 static int 148 igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status) 149 { 150 struct e1000_adv_tx_context_desc *TXD; 151 struct adapter *adapter = txr->adapter; 152 u32 vlan_macip_lens, type_tucmd_mlhl; 153 u32 mss_l4len_idx; 154 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0; 155 156 /* First check if TSO is to be used */ 157 if (pi->ipi_csum_flags & CSUM_TSO) 158 return (igb_tso_setup(txr, pi, cmd_type_len, olinfo_status)); 159 160 /* Indicate the whole packet as payload when not doing TSO */ 161 *olinfo_status |= pi->ipi_len << E1000_ADVTXD_PAYLEN_SHIFT; 162 163 /* Now ready a context descriptor */ 164 TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 165 166 /* 167 ** In advanced descriptors the vlan tag must 168 ** be placed into the context descriptor. Hence 169 ** we need to make one even if not doing offloads. 170 */ 171 if (pi->ipi_mflags & M_VLANTAG) { 172 vlan_macip_lens |= (pi->ipi_vtag << E1000_ADVTXD_VLAN_SHIFT); 173 } else if ((pi->ipi_csum_flags & IGB_CSUM_OFFLOAD) == 0) { 174 return (0); 175 } 176 177 /* Set the ether header length */ 178 vlan_macip_lens |= pi->ipi_ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 179 180 switch(pi->ipi_etype) { 181 case ETHERTYPE_IP: 182 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 183 break; 184 case ETHERTYPE_IPV6: 185 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 186 break; 187 default: 188 break; 189 } 190 191 vlan_macip_lens |= pi->ipi_ip_hlen; 192 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 193 194 switch (pi->ipi_ipproto) { 195 case IPPROTO_TCP: 196 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) { 197 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 198 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 199 } 200 break; 201 case IPPROTO_UDP: 202 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) { 203 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP; 204 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 205 } 206 break; 207 case IPPROTO_SCTP: 208 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) { 209 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP; 210 *olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 211 } 212 break; 213 default: 214 break; 215 } 216 217 /* 82575 needs the queue index added */ 218 if (adapter->hw.mac.type == e1000_82575) 219 mss_l4len_idx = txr->me << 4; 220 221 /* Now copy bits into descriptor */ 222 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 223 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 224 TXD->seqnum_seed = htole32(0); 225 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 226 227 return (1); 228 } 229 230 static int 231 igb_isc_txd_encap(void *arg, if_pkt_info_t pi) 232 { 233 struct adapter *sc = arg; 234 if_softc_ctx_t scctx = sc->shared; 235 struct em_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx]; 236 struct tx_ring *txr = &que->txr; 237 int nsegs = pi->ipi_nsegs; 238 bus_dma_segment_t *segs = pi->ipi_segs; 239 union e1000_adv_tx_desc *txd = NULL; 240 int i, j, pidx_last; 241 u32 olinfo_status, cmd_type_len, txd_flags; 242 qidx_t ntxd; 243 244 pidx_last = olinfo_status = 0; 245 /* Basic descriptor defines */ 246 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | 247 E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT); 248 249 if (pi->ipi_mflags & M_VLANTAG) 250 cmd_type_len |= E1000_ADVTXD_DCMD_VLE; 251 252 i = pi->ipi_pidx; 253 ntxd = scctx->isc_ntxd[0]; 254 txd_flags = pi->ipi_flags & IPI_TX_INTR ? E1000_ADVTXD_DCMD_RS : 0; 255 /* Consume the first descriptor */ 256 i += igb_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status); 257 if (i == scctx->isc_ntxd[0]) 258 i = 0; 259 260 /* 82575 needs the queue index added */ 261 if (sc->hw.mac.type == e1000_82575) 262 olinfo_status |= txr->me << 4; 263 264 for (j = 0; j < nsegs; j++) { 265 bus_size_t seglen; 266 bus_addr_t segaddr; 267 268 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i]; 269 seglen = segs[j].ds_len; 270 segaddr = htole64(segs[j].ds_addr); 271 272 txd->read.buffer_addr = segaddr; 273 txd->read.cmd_type_len = htole32(E1000_TXD_CMD_IFCS | 274 cmd_type_len | seglen); 275 txd->read.olinfo_status = htole32(olinfo_status); 276 pidx_last = i; 277 if (++i == scctx->isc_ntxd[0]) { 278 i = 0; 279 } 280 } 281 if (txd_flags) { 282 txr->tx_rsq[txr->tx_rs_pidx] = pidx_last; 283 txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & (ntxd-1); 284 MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx); 285 } 286 287 txd->read.cmd_type_len |= htole32(E1000_TXD_CMD_EOP | txd_flags); 288 pi->ipi_new_pidx = i; 289 290 return (0); 291 } 292 293 static void 294 igb_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx) 295 { 296 struct adapter *adapter = arg; 297 struct em_tx_queue *que = &adapter->tx_queues[txqid]; 298 struct tx_ring *txr = &que->txr; 299 300 E1000_WRITE_REG(&adapter->hw, E1000_TDT(txr->me), pidx); 301 } 302 303 static int 304 igb_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear) 305 { 306 struct adapter *adapter = arg; 307 if_softc_ctx_t scctx = adapter->shared; 308 struct em_tx_queue *que = &adapter->tx_queues[txqid]; 309 struct tx_ring *txr = &que->txr; 310 311 qidx_t processed = 0; 312 int updated; 313 qidx_t cur, prev, ntxd, rs_cidx; 314 int32_t delta; 315 uint8_t status; 316 317 rs_cidx = txr->tx_rs_cidx; 318 if (rs_cidx == txr->tx_rs_pidx) 319 return (0); 320 cur = txr->tx_rsq[rs_cidx]; 321 status = ((union e1000_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 322 updated = !!(status & E1000_TXD_STAT_DD); 323 324 if (!updated) 325 return (0); 326 327 /* If clear is false just let caller know that there 328 * are descriptors to reclaim */ 329 if (!clear) 330 return (1); 331 332 prev = txr->tx_cidx_processed; 333 ntxd = scctx->isc_ntxd[0]; 334 do { 335 delta = (int32_t)cur - (int32_t)prev; 336 MPASS(prev == 0 || delta != 0); 337 if (delta < 0) 338 delta += ntxd; 339 340 processed += delta; 341 prev = cur; 342 rs_cidx = (rs_cidx + 1) & (ntxd-1); 343 if (rs_cidx == txr->tx_rs_pidx) 344 break; 345 cur = txr->tx_rsq[rs_cidx]; 346 status = ((union e1000_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 347 } while ((status & E1000_TXD_STAT_DD)); 348 349 txr->tx_rs_cidx = rs_cidx; 350 txr->tx_cidx_processed = prev; 351 return (processed); 352 } 353 354 static void 355 igb_isc_rxd_refill(void *arg, if_rxd_update_t iru) 356 { 357 struct adapter *sc = arg; 358 if_softc_ctx_t scctx = sc->shared; 359 uint16_t rxqid = iru->iru_qsidx; 360 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 361 union e1000_adv_rx_desc *rxd; 362 struct rx_ring *rxr = &que->rxr; 363 uint64_t *paddrs; 364 uint32_t next_pidx, pidx; 365 uint16_t count; 366 int i; 367 368 paddrs = iru->iru_paddrs; 369 pidx = iru->iru_pidx; 370 count = iru->iru_count; 371 372 for (i = 0, next_pidx = pidx; i < count; i++) { 373 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[next_pidx]; 374 375 rxd->read.pkt_addr = htole64(paddrs[i]); 376 if (++next_pidx == scctx->isc_nrxd[0]) 377 next_pidx = 0; 378 } 379 } 380 381 static void 382 igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx) 383 { 384 struct adapter *sc = arg; 385 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 386 struct rx_ring *rxr = &que->rxr; 387 388 E1000_WRITE_REG(&sc->hw, E1000_RDT(rxr->me), pidx); 389 } 390 391 static int 392 igb_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget) 393 { 394 struct adapter *sc = arg; 395 if_softc_ctx_t scctx = sc->shared; 396 struct em_rx_queue *que = &sc->rx_queues[rxqid]; 397 struct rx_ring *rxr = &que->rxr; 398 union e1000_adv_rx_desc *rxd; 399 u32 staterr = 0; 400 int cnt, i; 401 402 for (cnt = 0, i = idx; cnt < scctx->isc_nrxd[0] && cnt <= budget;) { 403 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[i]; 404 staterr = le32toh(rxd->wb.upper.status_error); 405 406 if ((staterr & E1000_RXD_STAT_DD) == 0) 407 break; 408 if (++i == scctx->isc_nrxd[0]) 409 i = 0; 410 if (staterr & E1000_RXD_STAT_EOP) 411 cnt++; 412 } 413 return (cnt); 414 } 415 416 /**************************************************************** 417 * Routine sends data which has been dma'ed into host memory 418 * to upper layer. Initialize ri structure. 419 * 420 * Returns 0 upon success, errno on failure 421 ***************************************************************/ 422 423 static int 424 igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri) 425 { 426 struct adapter *adapter = arg; 427 if_softc_ctx_t scctx = adapter->shared; 428 struct em_rx_queue *que = &adapter->rx_queues[ri->iri_qsidx]; 429 struct rx_ring *rxr = &que->rxr; 430 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 431 union e1000_adv_rx_desc *rxd; 432 433 u16 pkt_info, len; 434 u16 vtag = 0; 435 u32 ptype; 436 u32 staterr = 0; 437 bool eop; 438 int i = 0; 439 int cidx = ri->iri_cidx; 440 441 do { 442 rxd = (union e1000_adv_rx_desc *)&rxr->rx_base[cidx]; 443 staterr = le32toh(rxd->wb.upper.status_error); 444 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info); 445 446 MPASS ((staterr & E1000_RXD_STAT_DD) != 0); 447 448 len = le16toh(rxd->wb.upper.length); 449 ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGB_PKTTYPE_MASK; 450 451 ri->iri_len += len; 452 rxr->rx_bytes += ri->iri_len; 453 454 rxd->wb.upper.status_error = 0; 455 eop = ((staterr & E1000_RXD_STAT_EOP) == E1000_RXD_STAT_EOP); 456 457 if (((adapter->hw.mac.type == e1000_i350) || 458 (adapter->hw.mac.type == e1000_i354)) && 459 (staterr & E1000_RXDEXT_STATERR_LB)) 460 vtag = be16toh(rxd->wb.upper.vlan); 461 else 462 vtag = le16toh(rxd->wb.upper.vlan); 463 464 /* Make sure bad packets are discarded */ 465 if (eop && ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) != 0)) { 466 adapter->dropped_pkts++; 467 ++rxr->rx_discarded; 468 return (EBADMSG); 469 } 470 ri->iri_frags[i].irf_flid = 0; 471 ri->iri_frags[i].irf_idx = cidx; 472 ri->iri_frags[i].irf_len = len; 473 474 if (++cidx == scctx->isc_nrxd[0]) 475 cidx = 0; 476 #ifdef notyet 477 if (rxr->hdr_split == TRUE) { 478 ri->iri_frags[i].irf_flid = 1; 479 ri->iri_frags[i].irf_idx = cidx; 480 if (++cidx == scctx->isc_nrxd[0]) 481 cidx = 0; 482 } 483 #endif 484 i++; 485 } while (!eop); 486 487 rxr->rx_packets++; 488 489 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 490 igb_rx_checksum(staterr, ri, ptype); 491 492 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 493 (staterr & E1000_RXD_STAT_VP) != 0) { 494 ri->iri_vtag = vtag; 495 ri->iri_flags |= M_VLANTAG; 496 } 497 ri->iri_flowid = 498 le32toh(rxd->wb.lower.hi_dword.rss); 499 ri->iri_rsstype = igb_determine_rsstype(pkt_info); 500 ri->iri_nfrags = i; 501 502 return (0); 503 } 504 505 /********************************************************************* 506 * 507 * Verify that the hardware indicated that the checksum is valid. 508 * Inform the stack about the status of checksum so that stack 509 * doesn't spend time verifying the checksum. 510 * 511 *********************************************************************/ 512 static void 513 igb_rx_checksum(u32 staterr, if_rxd_info_t ri, u32 ptype) 514 { 515 u16 status = (u16)staterr; 516 u8 errors = (u8) (staterr >> 24); 517 bool sctp = FALSE; 518 519 /* Ignore Checksum bit is set */ 520 if (status & E1000_RXD_STAT_IXSM) { 521 ri->iri_csum_flags = 0; 522 return; 523 } 524 525 if ((ptype & E1000_RXDADV_PKTTYPE_ETQF) == 0 && 526 (ptype & E1000_RXDADV_PKTTYPE_SCTP) != 0) 527 sctp = 1; 528 else 529 sctp = 0; 530 531 if (status & E1000_RXD_STAT_IPCS) { 532 /* Did it pass? */ 533 if (!(errors & E1000_RXD_ERR_IPE)) { 534 /* IP Checksum Good */ 535 ri->iri_csum_flags = CSUM_IP_CHECKED; 536 ri->iri_csum_flags |= CSUM_IP_VALID; 537 } else 538 ri->iri_csum_flags = 0; 539 } 540 541 if (status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) { 542 u64 type = (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 543 if (sctp) /* reassign */ 544 type = CSUM_SCTP_VALID; 545 /* Did it pass? */ 546 if (!(errors & E1000_RXD_ERR_TCPE)) { 547 ri->iri_csum_flags |= type; 548 if (sctp == 0) 549 ri->iri_csum_data = htons(0xffff); 550 } 551 } 552 return; 553 } 554 555 /******************************************************************** 556 * 557 * Parse the packet type to determine the appropriate hash 558 * 559 ******************************************************************/ 560 static int 561 igb_determine_rsstype(u16 pkt_info) 562 { 563 switch (pkt_info & E1000_RXDADV_RSSTYPE_MASK) { 564 case E1000_RXDADV_RSSTYPE_IPV4_TCP: 565 return M_HASHTYPE_RSS_TCP_IPV4; 566 case E1000_RXDADV_RSSTYPE_IPV4: 567 return M_HASHTYPE_RSS_IPV4; 568 case E1000_RXDADV_RSSTYPE_IPV6_TCP: 569 return M_HASHTYPE_RSS_TCP_IPV6; 570 case E1000_RXDADV_RSSTYPE_IPV6_EX: 571 return M_HASHTYPE_RSS_IPV6_EX; 572 case E1000_RXDADV_RSSTYPE_IPV6: 573 return M_HASHTYPE_RSS_IPV6; 574 case E1000_RXDADV_RSSTYPE_IPV6_TCP_EX: 575 return M_HASHTYPE_RSS_TCP_IPV6_EX; 576 default: 577 return M_HASHTYPE_OPAQUE; 578 } 579 } 580