1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 36 #ifndef _EM_H_DEFINED_ 37 #define _EM_H_DEFINED_ 38 39 40 /* Tunables */ 41 42 /* 43 * EM_TXD: Maximum number of Transmit Descriptors 44 * Valid Range: 80-256 for 82542 and 82543-based adapters 45 * 80-4096 for others 46 * Default Value: 256 47 * This value is the number of transmit descriptors allocated by the driver. 48 * Increasing this value allows the driver to queue more transmits. Each 49 * descriptor is 16 bytes. 50 * Since TDLEN should be multiple of 128bytes, the number of transmit 51 * desscriptors should meet the following condition. 52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 53 */ 54 #define EM_MIN_TXD 80 55 #define EM_MAX_TXD_82543 256 56 #define EM_MAX_TXD 4096 57 #define EM_DEFAULT_TXD EM_MAX_TXD_82543 58 59 /* 60 * EM_RXD - Maximum number of receive Descriptors 61 * Valid Range: 80-256 for 82542 and 82543-based adapters 62 * 80-4096 for others 63 * Default Value: 256 64 * This value is the number of receive descriptors allocated by the driver. 65 * Increasing this value allows the driver to buffer more incoming packets. 66 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 67 * descriptor. The maximum MTU size is 16110. 68 * Since TDLEN should be multiple of 128bytes, the number of transmit 69 * desscriptors should meet the following condition. 70 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 71 */ 72 #define EM_MIN_RXD 80 73 #define EM_MAX_RXD_82543 256 74 #define EM_MAX_RXD 4096 75 #define EM_DEFAULT_RXD EM_MAX_RXD_82543 76 77 /* 78 * EM_TIDV - Transmit Interrupt Delay Value 79 * Valid Range: 0-65535 (0=off) 80 * Default Value: 64 81 * This value delays the generation of transmit interrupts in units of 82 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 83 * efficiency if properly tuned for specific network traffic. If the 84 * system is reporting dropped transmits, this value may be set too high 85 * causing the driver to run out of available transmit descriptors. 86 */ 87 #define EM_TIDV 64 88 89 /* 90 * EM_TADV - Transmit Absolute Interrupt Delay Value 91 * (Not valid for 82542/82543/82544) 92 * Valid Range: 0-65535 (0=off) 93 * Default Value: 64 94 * This value, in units of 1.024 microseconds, limits the delay in which a 95 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 96 * this value ensures that an interrupt is generated after the initial 97 * packet is sent on the wire within the set amount of time. Proper tuning, 98 * along with EM_TIDV, may improve traffic throughput in specific 99 * network conditions. 100 */ 101 #define EM_TADV 64 102 103 /* 104 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 105 * Valid Range: 0-65535 (0=off) 106 * Default Value: 0 107 * This value delays the generation of receive interrupts in units of 1.024 108 * microseconds. Receive interrupt reduction can improve CPU efficiency if 109 * properly tuned for specific network traffic. Increasing this value adds 110 * extra latency to frame reception and can end up decreasing the throughput 111 * of TCP traffic. If the system is reporting dropped receives, this value 112 * may be set too high, causing the driver to run out of available receive 113 * descriptors. 114 * 115 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 116 * may hang (stop transmitting) under certain network conditions. 117 * If this occurs a WATCHDOG message is logged in the system 118 * event log. In addition, the controller is automatically reset, 119 * restoring the network connection. To eliminate the potential 120 * for the hang ensure that EM_RDTR is set to 0. 121 */ 122 #define EM_RDTR 0 123 124 /* 125 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 126 * Valid Range: 0-65535 (0=off) 127 * Default Value: 64 128 * This value, in units of 1.024 microseconds, limits the delay in which a 129 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 130 * this value ensures that an interrupt is generated after the initial 131 * packet is received within the set amount of time. Proper tuning, 132 * along with EM_RDTR, may improve traffic throughput in specific network 133 * conditions. 134 */ 135 #define EM_RADV 64 136 137 /* 138 * This parameter controls the duration of transmit watchdog timer. 139 */ 140 #define EM_TX_TIMEOUT 5 141 142 /* 143 * This parameter controls when the driver calls the routine to reclaim 144 * transmit descriptors. 145 */ 146 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 147 #define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 148 149 /* 150 * This parameter controls whether or not autonegotation is enabled. 151 * 0 - Disable autonegotiation 152 * 1 - Enable autonegotiation 153 */ 154 #define DO_AUTO_NEG 1 155 156 /* 157 * This parameter control whether or not the driver will wait for 158 * autonegotiation to complete. 159 * 1 - Wait for autonegotiation to complete 160 * 0 - Don't wait for autonegotiation to complete 161 */ 162 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 163 164 /* Tunables -- End */ 165 166 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 167 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 168 ADVERTISE_1000_FULL) 169 170 #define AUTO_ALL_MODES 0 171 172 /* PHY master/slave setting */ 173 #define EM_MASTER_SLAVE e1000_ms_hw_default 174 175 /* 176 * Micellaneous constants 177 */ 178 #define EM_VENDOR_ID 0x8086 179 #define EM_FLASH 0x0014 180 181 #define EM_JUMBO_PBA 0x00000028 182 #define EM_DEFAULT_PBA 0x00000030 183 #define EM_SMARTSPEED_DOWNSHIFT 3 184 #define EM_SMARTSPEED_MAX 15 185 #define EM_MAX_INTR 10 186 187 #define MAX_NUM_MULTICAST_ADDRESSES 128 188 #define PCI_ANY_ID (~0U) 189 #define ETHER_ALIGN 2 190 #define EM_FC_PAUSE_TIME 0x0680 191 #define EM_EEPROM_APME 0x400; 192 193 /* Code compatilbility between 6 and 7 */ 194 #ifndef ETHER_BPF_MTAP 195 #define ETHER_BPF_MTAP BPF_MTAP 196 #endif 197 198 /* 199 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 200 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 201 * also optimize cache line size effect. H/W supports up to cache line size 128. 202 */ 203 #define EM_DBA_ALIGN 128 204 205 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 206 207 /* PCI Config defines */ 208 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 209 #define EM_BAR_TYPE_MASK 0x00000001 210 #define EM_BAR_TYPE_MMEM 0x00000000 211 #define EM_BAR_TYPE_IO 0x00000001 212 #define EM_BAR_TYPE_FLASH 0x0014 213 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 214 #define EM_BAR_MEM_TYPE_MASK 0x00000006 215 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 216 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 217 #define EM_MSIX_BAR 3 /* On 82575 */ 218 219 /* Defines for printing debug information */ 220 #define DEBUG_INIT 0 221 #define DEBUG_IOCTL 0 222 #define DEBUG_HW 0 223 224 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 225 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 226 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 227 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 228 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 229 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 230 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 231 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 232 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 233 234 #define EM_MAX_SCATTER 64 235 #define EM_VFTA_SIZE 128 236 #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 237 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 238 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 239 #define ETH_ZLEN 60 240 #define ETH_ADDR_LEN 6 241 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 242 243 /* 244 * 82574 has a nonstandard address for EIAC 245 * and since its only used in MSIX, and in 246 * the em driver only 82574 uses MSIX we can 247 * solve it just using this define. 248 */ 249 #define EM_EIAC 0x000DC 250 251 /* Used in for 82547 10Mb Half workaround */ 252 #define EM_PBA_BYTES_SHIFT 0xA 253 #define EM_TX_HEAD_ADDR_SHIFT 7 254 #define EM_PBA_TX_MASK 0xFFFF0000 255 #define EM_FIFO_HDR 0x10 256 #define EM_82547_PKT_THRESH 0x3e0 257 258 /* Precision Time Sync (IEEE 1588) defines */ 259 #define ETHERTYPE_IEEE1588 0x88F7 260 #define PICOSECS_PER_TICK 20833 261 #define TSYNC_PORT 319 /* UDP port for the protocol */ 262 263 /* 264 * Bus dma allocation structure used by 265 * e1000_dma_malloc and e1000_dma_free. 266 */ 267 struct em_dma_alloc { 268 bus_addr_t dma_paddr; 269 caddr_t dma_vaddr; 270 bus_dma_tag_t dma_tag; 271 bus_dmamap_t dma_map; 272 bus_dma_segment_t dma_seg; 273 int dma_nseg; 274 }; 275 276 struct adapter; 277 278 struct em_int_delay_info { 279 struct adapter *adapter; /* Back-pointer to the adapter struct */ 280 int offset; /* Register offset to read/write */ 281 int value; /* Current value in usecs */ 282 }; 283 284 /* Our adapter structure */ 285 struct adapter { 286 struct ifnet *ifp; 287 #if __FreeBSD_version >= 800000 288 struct buf_ring *br; 289 #endif 290 struct e1000_hw hw; 291 292 /* FreeBSD operating-system-specific structures. */ 293 struct e1000_osdep osdep; 294 struct device *dev; 295 296 struct resource *memory; 297 struct resource *flash; 298 struct resource *msix; 299 300 struct resource *ioport; 301 int io_rid; 302 303 /* 82574 may use 3 int vectors */ 304 struct resource *res[3]; 305 void *tag[3]; 306 int rid[3]; 307 308 struct ifmedia media; 309 struct callout timer; 310 struct callout tx_fifo_timer; 311 int watchdog_timer; 312 int msi; 313 int if_flags; 314 int max_frame_size; 315 int min_frame_size; 316 struct mtx core_mtx; 317 struct mtx tx_mtx; 318 struct mtx rx_mtx; 319 int em_insert_vlan_header; 320 321 /* Task for FAST handling */ 322 struct task link_task; 323 struct task rxtx_task; 324 struct task rx_task; 325 struct task tx_task; 326 struct taskqueue *tq; /* private task queue */ 327 328 #if __FreeBSD_version >= 700029 329 eventhandler_tag vlan_attach; 330 eventhandler_tag vlan_detach; 331 u32 num_vlans; 332 #endif 333 334 /* Management and WOL features */ 335 int wol; 336 int has_manage; 337 338 /* Info about the board itself */ 339 uint8_t link_active; 340 uint16_t link_speed; 341 uint16_t link_duplex; 342 uint32_t smartspeed; 343 struct em_int_delay_info tx_int_delay; 344 struct em_int_delay_info tx_abs_int_delay; 345 struct em_int_delay_info rx_int_delay; 346 struct em_int_delay_info rx_abs_int_delay; 347 348 /* 349 * Transmit definitions 350 * 351 * We have an array of num_tx_desc descriptors (handled 352 * by the controller) paired with an array of tx_buffers 353 * (at tx_buffer_area). 354 * The index of the next available descriptor is next_avail_tx_desc. 355 * The number of remaining tx_desc is num_tx_desc_avail. 356 */ 357 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 358 struct e1000_tx_desc *tx_desc_base; 359 uint32_t next_avail_tx_desc; 360 uint32_t next_tx_to_clean; 361 volatile uint16_t num_tx_desc_avail; 362 uint16_t num_tx_desc; 363 uint16_t last_hw_offload; 364 uint32_t txd_cmd; 365 struct em_buffer *tx_buffer_area; 366 bus_dma_tag_t txtag; /* dma tag for tx */ 367 uint32_t tx_tso; /* last tx was tso */ 368 369 /* 370 * Receive definitions 371 * 372 * we have an array of num_rx_desc rx_desc (handled by the 373 * controller), and paired with an array of rx_buffers 374 * (at rx_buffer_area). 375 * The next pair to check on receive is at offset next_rx_desc_to_check 376 */ 377 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 378 struct e1000_rx_desc *rx_desc_base; 379 uint32_t next_rx_desc_to_check; 380 uint32_t rx_buffer_len; 381 uint16_t num_rx_desc; 382 int rx_process_limit; 383 struct em_buffer *rx_buffer_area; 384 bus_dma_tag_t rxtag; 385 bus_dmamap_t rx_sparemap; 386 387 /* 388 * First/last mbuf pointers, for 389 * collecting multisegment RX packets. 390 */ 391 struct mbuf *fmp; 392 struct mbuf *lmp; 393 394 /* Misc stats maintained by the driver */ 395 unsigned long dropped_pkts; 396 unsigned long mbuf_alloc_failed; 397 unsigned long mbuf_cluster_failed; 398 unsigned long no_tx_desc_avail1; 399 unsigned long no_tx_desc_avail2; 400 unsigned long no_tx_map_avail; 401 unsigned long no_tx_dma_setup; 402 unsigned long watchdog_events; 403 unsigned long rx_overruns; 404 unsigned long rx_irq; 405 unsigned long tx_irq; 406 unsigned long link_irq; 407 408 /* 82547 workaround */ 409 uint32_t tx_fifo_size; 410 uint32_t tx_fifo_head; 411 uint32_t tx_fifo_head_addr; 412 uint64_t tx_fifo_reset_cnt; 413 uint64_t tx_fifo_wrk_cnt; 414 uint32_t tx_head_addr; 415 416 /* For 82544 PCIX Workaround */ 417 boolean_t pcix_82544; 418 boolean_t in_detach; 419 420 421 struct e1000_hw_stats stats; 422 }; 423 424 /* ****************************************************************************** 425 * vendor_info_array 426 * 427 * This array contains the list of Subvendor/Subdevice IDs on which the driver 428 * should load. 429 * 430 * ******************************************************************************/ 431 typedef struct _em_vendor_info_t { 432 unsigned int vendor_id; 433 unsigned int device_id; 434 unsigned int subvendor_id; 435 unsigned int subdevice_id; 436 unsigned int index; 437 } em_vendor_info_t; 438 439 struct em_buffer { 440 int next_eop; /* Index of the desc to watch */ 441 struct mbuf *m_head; 442 bus_dmamap_t map; /* bus_dma map for packet */ 443 }; 444 445 /* For 82544 PCIX Workaround */ 446 typedef struct _ADDRESS_LENGTH_PAIR 447 { 448 uint64_t address; 449 uint32_t length; 450 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 451 452 typedef struct _DESCRIPTOR_PAIR 453 { 454 ADDRESS_LENGTH_PAIR descriptor[4]; 455 uint32_t elements; 456 } DESC_ARRAY, *PDESC_ARRAY; 457 458 #define EM_CORE_LOCK_INIT(_sc, _name) \ 459 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 460 #define EM_TX_LOCK_INIT(_sc, _name) \ 461 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 462 #define EM_RX_LOCK_INIT(_sc, _name) \ 463 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 464 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 465 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 466 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 467 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 468 #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 469 #define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 470 #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 471 #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 472 #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 473 #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 474 #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 475 #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 476 477 #endif /* _EM_H_DEFINED_ */ 478