1d37cece2SSean Bruno /*- 27282444bSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause 37282444bSPedro F. Giffuni * 47021bf05SStephen Hurd * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5d37cece2SSean Bruno * All rights reserved. 6d37cece2SSean Bruno * 7d37cece2SSean Bruno * Redistribution and use in source and binary forms, with or without 8d37cece2SSean Bruno * modification, are permitted provided that the following conditions 9d37cece2SSean Bruno * are met: 10d37cece2SSean Bruno * 1. Redistributions of source code must retain the above copyright 11d37cece2SSean Bruno * notice, this list of conditions and the following disclaimer. 12d37cece2SSean Bruno * 2. Redistributions in binary form must reproduce the above copyright 13d37cece2SSean Bruno * notice, this list of conditions and the following disclaimer in the 14d37cece2SSean Bruno * documentation and/or other materials provided with the distribution. 15d37cece2SSean Bruno * 16d37cece2SSean Bruno * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17d37cece2SSean Bruno * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18d37cece2SSean Bruno * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19d37cece2SSean Bruno * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20d37cece2SSean Bruno * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21d37cece2SSean Bruno * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22d37cece2SSean Bruno * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23d37cece2SSean Bruno * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24d37cece2SSean Bruno * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25d37cece2SSean Bruno * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26d37cece2SSean Bruno * SUCH DAMAGE. 27d37cece2SSean Bruno */ 28d37cece2SSean Bruno 29dc926051SKevin Bowling 30dc926051SKevin Bowling #ifndef _EM_H_DEFINED_ 31dc926051SKevin Bowling #define _EM_H_DEFINED_ 32dc926051SKevin Bowling 33f2d6ace4SSean Bruno #include "opt_ddb.h" 34f2d6ace4SSean Bruno #include "opt_inet.h" 35f2d6ace4SSean Bruno #include "opt_inet6.h" 36467515a4SEric Joyner #include "opt_rss.h" 37f2d6ace4SSean Bruno 38f2d6ace4SSean Bruno #ifdef HAVE_KERNEL_OPTION_HEADERS 39f2d6ace4SSean Bruno #include "opt_device_polling.h" 40f2d6ace4SSean Bruno #endif 41f2d6ace4SSean Bruno 42f2d6ace4SSean Bruno #include <sys/param.h> 43f2d6ace4SSean Bruno #include <sys/systm.h> 44f2d6ace4SSean Bruno #ifdef DDB 45f2d6ace4SSean Bruno #include <sys/types.h> 46f2d6ace4SSean Bruno #include <ddb/ddb.h> 47f2d6ace4SSean Bruno #endif 48f2d6ace4SSean Bruno #include <sys/buf_ring.h> 49f2d6ace4SSean Bruno #include <sys/bus.h> 50f2d6ace4SSean Bruno #include <sys/endian.h> 51f2d6ace4SSean Bruno #include <sys/kernel.h> 52f2d6ace4SSean Bruno #include <sys/kthread.h> 53f2d6ace4SSean Bruno #include <sys/malloc.h> 54f2d6ace4SSean Bruno #include <sys/mbuf.h> 55f2d6ace4SSean Bruno #include <sys/module.h> 56f2d6ace4SSean Bruno #include <sys/rman.h> 57f2d6ace4SSean Bruno #include <sys/smp.h> 58f2d6ace4SSean Bruno #include <sys/socket.h> 59f2d6ace4SSean Bruno #include <sys/sockio.h> 60f2d6ace4SSean Bruno #include <sys/sysctl.h> 61f2d6ace4SSean Bruno #include <sys/taskqueue.h> 62f2d6ace4SSean Bruno #include <sys/eventhandler.h> 63f2d6ace4SSean Bruno #include <machine/bus.h> 64f2d6ace4SSean Bruno #include <machine/resource.h> 65f2d6ace4SSean Bruno 66f2d6ace4SSean Bruno #include <net/bpf.h> 67f2d6ace4SSean Bruno #include <net/ethernet.h> 68f2d6ace4SSean Bruno #include <net/if.h> 69f2d6ace4SSean Bruno #include <net/if_var.h> 70f2d6ace4SSean Bruno #include <net/if_arp.h> 71f2d6ace4SSean Bruno #include <net/if_dl.h> 72f2d6ace4SSean Bruno #include <net/if_media.h> 73f2d6ace4SSean Bruno #include <net/iflib.h> 74467515a4SEric Joyner #ifdef RSS 75467515a4SEric Joyner #include <net/rss_config.h> 76467515a4SEric Joyner #include <netinet/in_rss.h> 77467515a4SEric Joyner #endif 78f2d6ace4SSean Bruno 79f2d6ace4SSean Bruno #include <net/if_types.h> 80f2d6ace4SSean Bruno #include <net/if_vlan_var.h> 81f2d6ace4SSean Bruno 82f2d6ace4SSean Bruno #include <netinet/in_systm.h> 83f2d6ace4SSean Bruno #include <netinet/in.h> 84f2d6ace4SSean Bruno #include <netinet/if_ether.h> 85f2d6ace4SSean Bruno #include <netinet/ip.h> 86f2d6ace4SSean Bruno #include <netinet/ip6.h> 87f2d6ace4SSean Bruno #include <netinet/tcp.h> 88f2d6ace4SSean Bruno #include <netinet/udp.h> 89f2d6ace4SSean Bruno 90f2d6ace4SSean Bruno #include <machine/in_cksum.h> 91f2d6ace4SSean Bruno #include <dev/led/led.h> 92f2d6ace4SSean Bruno #include <dev/pci/pcivar.h> 93f2d6ace4SSean Bruno #include <dev/pci/pcireg.h> 94f2d6ace4SSean Bruno 95f2d6ace4SSean Bruno #include "e1000_api.h" 96f2d6ace4SSean Bruno #include "e1000_82571.h" 97f2d6ace4SSean Bruno #include "ifdi_if.h" 988cfa0ad2SJack F Vogel 998cfa0ad2SJack F Vogel /* Tunables */ 1008cfa0ad2SJack F Vogel 1018cfa0ad2SJack F Vogel /* 1027d0d6484SSean Bruno * EM_MAX_TXD: Maximum number of Transmit Descriptors 1038cfa0ad2SJack F Vogel * Valid Range: 80-256 for 82542 and 82543-based adapters 1048cfa0ad2SJack F Vogel * 80-4096 for others 1057d0d6484SSean Bruno * Default Value: 1024 1068cfa0ad2SJack F Vogel * This value is the number of transmit descriptors allocated by the driver. 1078cfa0ad2SJack F Vogel * Increasing this value allows the driver to queue more transmits. Each 1088cfa0ad2SJack F Vogel * descriptor is 16 bytes. 1098cfa0ad2SJack F Vogel * Since TDLEN should be multiple of 128bytes, the number of transmit 1108cfa0ad2SJack F Vogel * desscriptors should meet the following condition. 1118cfa0ad2SJack F Vogel * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 1128cfa0ad2SJack F Vogel */ 113f2d6ace4SSean Bruno #define EM_MIN_TXD 128 1148cfa0ad2SJack F Vogel #define EM_MAX_TXD 4096 115a69ed8dfSJack F Vogel #define EM_DEFAULT_TXD 1024 116f2d6ace4SSean Bruno #define EM_DEFAULT_MULTI_TXD 4096 1177d0d6484SSean Bruno #define IGB_MAX_TXD 4096 1188cfa0ad2SJack F Vogel 1198cfa0ad2SJack F Vogel /* 1207d0d6484SSean Bruno * EM_MAX_RXD - Maximum number of receive Descriptors 1218cfa0ad2SJack F Vogel * Valid Range: 80-256 for 82542 and 82543-based adapters 1228cfa0ad2SJack F Vogel * 80-4096 for others 1237d0d6484SSean Bruno * Default Value: 1024 1248cfa0ad2SJack F Vogel * This value is the number of receive descriptors allocated by the driver. 1258cfa0ad2SJack F Vogel * Increasing this value allows the driver to buffer more incoming packets. 1268cfa0ad2SJack F Vogel * Each descriptor is 16 bytes. A receive buffer is also allocated for each 1278cfa0ad2SJack F Vogel * descriptor. The maximum MTU size is 16110. 1288cfa0ad2SJack F Vogel * Since TDLEN should be multiple of 128bytes, the number of transmit 1298cfa0ad2SJack F Vogel * desscriptors should meet the following condition. 1308cfa0ad2SJack F Vogel * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 1318cfa0ad2SJack F Vogel */ 132f2d6ace4SSean Bruno #define EM_MIN_RXD 128 1338cfa0ad2SJack F Vogel #define EM_MAX_RXD 4096 134a69ed8dfSJack F Vogel #define EM_DEFAULT_RXD 1024 135f2d6ace4SSean Bruno #define EM_DEFAULT_MULTI_RXD 4096 1367d0d6484SSean Bruno #define IGB_MAX_RXD 4096 1378cfa0ad2SJack F Vogel 1388cfa0ad2SJack F Vogel /* 1398cfa0ad2SJack F Vogel * EM_TIDV - Transmit Interrupt Delay Value 1408cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1418cfa0ad2SJack F Vogel * Default Value: 64 1428cfa0ad2SJack F Vogel * This value delays the generation of transmit interrupts in units of 1438cfa0ad2SJack F Vogel * 1.024 microseconds. Transmit interrupt reduction can improve CPU 1448cfa0ad2SJack F Vogel * efficiency if properly tuned for specific network traffic. If the 1458cfa0ad2SJack F Vogel * system is reporting dropped transmits, this value may be set too high 1468cfa0ad2SJack F Vogel * causing the driver to run out of available transmit descriptors. 1478cfa0ad2SJack F Vogel */ 1488cfa0ad2SJack F Vogel #define EM_TIDV 64 1498cfa0ad2SJack F Vogel 1508cfa0ad2SJack F Vogel /* 1518cfa0ad2SJack F Vogel * EM_TADV - Transmit Absolute Interrupt Delay Value 1528cfa0ad2SJack F Vogel * (Not valid for 82542/82543/82544) 1538cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1548cfa0ad2SJack F Vogel * Default Value: 64 1558cfa0ad2SJack F Vogel * This value, in units of 1.024 microseconds, limits the delay in which a 1568cfa0ad2SJack F Vogel * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 1578cfa0ad2SJack F Vogel * this value ensures that an interrupt is generated after the initial 1588cfa0ad2SJack F Vogel * packet is sent on the wire within the set amount of time. Proper tuning, 1598cfa0ad2SJack F Vogel * along with EM_TIDV, may improve traffic throughput in specific 1608cfa0ad2SJack F Vogel * network conditions. 1618cfa0ad2SJack F Vogel */ 1628cfa0ad2SJack F Vogel #define EM_TADV 64 1638cfa0ad2SJack F Vogel 1648cfa0ad2SJack F Vogel /* 1658cfa0ad2SJack F Vogel * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 1668cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1678cfa0ad2SJack F Vogel * Default Value: 0 1688cfa0ad2SJack F Vogel * This value delays the generation of receive interrupts in units of 1.024 1698cfa0ad2SJack F Vogel * microseconds. Receive interrupt reduction can improve CPU efficiency if 1708cfa0ad2SJack F Vogel * properly tuned for specific network traffic. Increasing this value adds 1718cfa0ad2SJack F Vogel * extra latency to frame reception and can end up decreasing the throughput 1728cfa0ad2SJack F Vogel * of TCP traffic. If the system is reporting dropped receives, this value 1738cfa0ad2SJack F Vogel * may be set too high, causing the driver to run out of available receive 1748cfa0ad2SJack F Vogel * descriptors. 1758cfa0ad2SJack F Vogel * 1768cfa0ad2SJack F Vogel * CAUTION: When setting EM_RDTR to a value other than 0, adapters 1778cfa0ad2SJack F Vogel * may hang (stop transmitting) under certain network conditions. 1788cfa0ad2SJack F Vogel * If this occurs a WATCHDOG message is logged in the system 1798cfa0ad2SJack F Vogel * event log. In addition, the controller is automatically reset, 1808cfa0ad2SJack F Vogel * restoring the network connection. To eliminate the potential 1818cfa0ad2SJack F Vogel * for the hang ensure that EM_RDTR is set to 0. 1828cfa0ad2SJack F Vogel */ 1838cfa0ad2SJack F Vogel #define EM_RDTR 0 1848cfa0ad2SJack F Vogel 1858cfa0ad2SJack F Vogel /* 1868cfa0ad2SJack F Vogel * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 1878cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1888cfa0ad2SJack F Vogel * Default Value: 64 1898cfa0ad2SJack F Vogel * This value, in units of 1.024 microseconds, limits the delay in which a 1908cfa0ad2SJack F Vogel * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 1918cfa0ad2SJack F Vogel * this value ensures that an interrupt is generated after the initial 1928cfa0ad2SJack F Vogel * packet is received within the set amount of time. Proper tuning, 1938cfa0ad2SJack F Vogel * along with EM_RDTR, may improve traffic throughput in specific network 1948cfa0ad2SJack F Vogel * conditions. 1958cfa0ad2SJack F Vogel */ 1968cfa0ad2SJack F Vogel #define EM_RADV 64 1978cfa0ad2SJack F Vogel 1988cfa0ad2SJack F Vogel /* 199237a6663SGordon Bergling * This parameter controls whether or not autonegotiation is enabled. 2008cfa0ad2SJack F Vogel * 0 - Disable autonegotiation 2018cfa0ad2SJack F Vogel * 1 - Enable autonegotiation 2028cfa0ad2SJack F Vogel */ 2038cfa0ad2SJack F Vogel #define DO_AUTO_NEG 1 2048cfa0ad2SJack F Vogel 2058cfa0ad2SJack F Vogel /* 2068cfa0ad2SJack F Vogel * This parameter control whether or not the driver will wait for 2078cfa0ad2SJack F Vogel * autonegotiation to complete. 2088cfa0ad2SJack F Vogel * 1 - Wait for autonegotiation to complete 2098cfa0ad2SJack F Vogel * 0 - Don't wait for autonegotiation to complete 2108cfa0ad2SJack F Vogel */ 2118cfa0ad2SJack F Vogel #define WAIT_FOR_AUTO_NEG_DEFAULT 0 2128cfa0ad2SJack F Vogel 2138cfa0ad2SJack F Vogel /* Tunables -- End */ 2148cfa0ad2SJack F Vogel 2158cfa0ad2SJack F Vogel #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 2168cfa0ad2SJack F Vogel ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 2178cfa0ad2SJack F Vogel ADVERTISE_1000_FULL) 2188cfa0ad2SJack F Vogel 2198cfa0ad2SJack F Vogel #define AUTO_ALL_MODES 0 2208cfa0ad2SJack F Vogel 2218cfa0ad2SJack F Vogel /* PHY master/slave setting */ 2228cfa0ad2SJack F Vogel #define EM_MASTER_SLAVE e1000_ms_hw_default 2238cfa0ad2SJack F Vogel 2248cfa0ad2SJack F Vogel /* 225dc926051SKevin Bowling * Miscellaneous constants 2268cfa0ad2SJack F Vogel */ 2278cfa0ad2SJack F Vogel #define EM_VENDOR_ID 0x8086 2288cfa0ad2SJack F Vogel #define EM_FLASH 0x0014 2298cfa0ad2SJack F Vogel 2308cfa0ad2SJack F Vogel #define EM_JUMBO_PBA 0x00000028 2318cfa0ad2SJack F Vogel #define EM_DEFAULT_PBA 0x00000030 2328cfa0ad2SJack F Vogel #define EM_SMARTSPEED_DOWNSHIFT 3 2338cfa0ad2SJack F Vogel #define EM_SMARTSPEED_MAX 15 2348ec87fc5SJack F Vogel #define EM_MAX_LOOP 10 2358cfa0ad2SJack F Vogel 2368cfa0ad2SJack F Vogel #define MAX_NUM_MULTICAST_ADDRESSES 128 2378cfa0ad2SJack F Vogel #define PCI_ANY_ID (~0U) 2388cfa0ad2SJack F Vogel #define ETHER_ALIGN 2 2398cfa0ad2SJack F Vogel #define EM_FC_PAUSE_TIME 0x0680 2408cfa0ad2SJack F Vogel #define EM_EEPROM_APME 0x400; 2414edd8523SJack F Vogel #define EM_82544_APME 0x0004; 2428cfa0ad2SJack F Vogel 243d8c2808fSSean Bruno /* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 244d8c2808fSSean Bruno #define IGB_MEDIA_RESET (1 << 0) 245d8c2808fSSean Bruno 246d8c2808fSSean Bruno /* Define the starting Interrupt rate per Queue */ 247*9bf9164fSKevin Bowling #define EM_INTS_PER_SEC 8000 248*9bf9164fSKevin Bowling #define EM_INTS_MULTIPLIER 256 249*9bf9164fSKevin Bowling #define EM_ITR_DIVIDEND 1000000000 250*9bf9164fSKevin Bowling #define EM_INTS_TO_ITR(i) (EM_ITR_DIVIDEND/(i * EM_INTS_MULTIPLIER)) 251*9bf9164fSKevin Bowling #define IGB_ITR_DIVIDEND 1000000 252*9bf9164fSKevin Bowling #define IGB_ITR_SHIFT 2 253*9bf9164fSKevin Bowling #define IGB_QVECTOR_MASK 0x7FFC 254*9bf9164fSKevin Bowling #define IGB_INTS_TO_EITR(i) (((IGB_ITR_DIVIDEND/i) & IGB_QVECTOR_MASK) << \ 255*9bf9164fSKevin Bowling IGB_ITR_SHIFT) 256d8c2808fSSean Bruno 257d8c2808fSSean Bruno #define IGB_LINK_ITR 2000 258d8c2808fSSean Bruno #define I210_LINK_DELAY 1000 259d8c2808fSSean Bruno 260d8c2808fSSean Bruno #define IGB_TXPBSIZE 20408 261d8c2808fSSean Bruno #define IGB_HDR_BUF 128 262d8c2808fSSean Bruno #define IGB_PKTTYPE_MASK 0x0000FFF0 263d8c2808fSSean Bruno #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 264d8c2808fSSean Bruno 265b7a728aaSSean Bruno /* 266b7a728aaSSean Bruno * Driver state logic for the detection of a hung state 267b7a728aaSSean Bruno * in hardware. Set TX_HUNG whenever a TX packet is used 268b7a728aaSSean Bruno * (data is sent) and clear it when txeof() is invoked if 269b7a728aaSSean Bruno * any descriptors from the ring are cleaned/reclaimed. 270b7a728aaSSean Bruno * Increment internal counter if no descriptors are cleaned 271b7a728aaSSean Bruno * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, 272b7a728aaSSean Bruno * reset adapter. 273b7a728aaSSean Bruno */ 274b7a728aaSSean Bruno #define EM_TX_IDLE 0x00000000 275b7a728aaSSean Bruno #define EM_TX_BUSY 0x00000001 276b7a728aaSSean Bruno #define EM_TX_HUNG 0x80000000 277b7a728aaSSean Bruno #define EM_TX_MAXTRIES 10 2787deff7f9SJack F Vogel 279c80429ceSEric Joyner #define PCICFG_DESC_RING_STATUS 0xe4 280c80429ceSEric Joyner #define FLUSH_DESC_REQUIRED 0x100 281c80429ceSEric Joyner 282f2d6ace4SSean Bruno 283f2d6ace4SSean Bruno #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 284f2d6ace4SSean Bruno ((hw->mac.type <= e1000_82576) ? 16 : 8)) 285f2d6ace4SSean Bruno #define IGB_RX_HTHRESH 8 286f2d6ace4SSean Bruno #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 287dc926051SKevin Bowling (sc->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4) 288f2d6ace4SSean Bruno 289f2d6ace4SSean Bruno #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 290f2d6ace4SSean Bruno #define IGB_TX_HTHRESH 1 291f2d6ace4SSean Bruno #define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 292dc926051SKevin Bowling sc->intr_type == IFLIB_INTR_MSIX) ? 1 : 16) 293f2d6ace4SSean Bruno 2948cfa0ad2SJack F Vogel /* 2958cfa0ad2SJack F Vogel * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 2968cfa0ad2SJack F Vogel * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 2978cfa0ad2SJack F Vogel * also optimize cache line size effect. H/W supports up to cache line size 128. 2988cfa0ad2SJack F Vogel */ 2998cfa0ad2SJack F Vogel #define EM_DBA_ALIGN 128 3008cfa0ad2SJack F Vogel 30123c9098bSSean Bruno /* 30223c9098bSSean Bruno * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 30323c9098bSSean Bruno */ 30423c9098bSSean Bruno #define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ 30523c9098bSSean Bruno #define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 30623c9098bSSean Bruno #define TARC_MQ_FIX (1 << 23) | \ 30723c9098bSSean Bruno (1 << 24) | \ 30823c9098bSSean Bruno (1 << 25) /* Handle errata in MQ mode */ 30923c9098bSSean Bruno #define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ 3108cfa0ad2SJack F Vogel 3118cfa0ad2SJack F Vogel /* PCI Config defines */ 3128cfa0ad2SJack F Vogel #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 3138cfa0ad2SJack F Vogel #define EM_BAR_TYPE_MASK 0x00000001 3148cfa0ad2SJack F Vogel #define EM_BAR_TYPE_MMEM 0x00000000 315f2d6ace4SSean Bruno #define EM_BAR_TYPE_IO 0x00000001 3168cfa0ad2SJack F Vogel #define EM_BAR_TYPE_FLASH 0x0014 3178cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 3188cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE_MASK 0x00000006 3198cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE_32BIT 0x00000000 3208cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE_64BIT 0x00000004 3218cfa0ad2SJack F Vogel 3228cfa0ad2SJack F Vogel /* Defines for printing debug information */ 3238cfa0ad2SJack F Vogel #define DEBUG_INIT 0 3248cfa0ad2SJack F Vogel #define DEBUG_IOCTL 0 3258cfa0ad2SJack F Vogel #define DEBUG_HW 0 3268cfa0ad2SJack F Vogel 3278cfa0ad2SJack F Vogel #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 3288cfa0ad2SJack F Vogel #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 3298cfa0ad2SJack F Vogel #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 3308cfa0ad2SJack F Vogel #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 3318cfa0ad2SJack F Vogel #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 3328cfa0ad2SJack F Vogel #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 3338cfa0ad2SJack F Vogel #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 3348cfa0ad2SJack F Vogel #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 3358cfa0ad2SJack F Vogel #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 3368cfa0ad2SJack F Vogel 3370a01ff4dSMarius Strobl #define EM_MAX_SCATTER 40 3389d81738fSJack F Vogel #define EM_VFTA_SIZE 128 3397f87c040SMarius Strobl #define EM_TSO_SIZE 65535 3408cfa0ad2SJack F Vogel #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 3418cfa0ad2SJack F Vogel #define ETH_ZLEN 60 3424f9a44a2SKevin Bowling 3434f9a44a2SKevin Bowling /* Offload bits in mbuf flag */ 3444f9a44a2SKevin Bowling #define EM_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 3454f9a44a2SKevin Bowling CSUM_IP6_UDP | CSUM_IP6_TCP) 3460544676bSStephen Hurd #define IGB_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 3470544676bSStephen Hurd CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ 3484f9a44a2SKevin Bowling CSUM_IP6_SCTP) 3490544676bSStephen Hurd 350f2d6ace4SSean Bruno #define IGB_PKTTYPE_MASK 0x0000FFF0 351f2d6ace4SSean Bruno #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 352f2d6ace4SSean Bruno 3538cfa0ad2SJack F Vogel /* 3548cfa0ad2SJack F Vogel * 82574 has a nonstandard address for EIAC 355b97de13aSMarius Strobl * and since its only used in MSI-X, and in 356b97de13aSMarius Strobl * the em driver only 82574 uses MSI-X we can 3578cfa0ad2SJack F Vogel * solve it just using this define. 3588cfa0ad2SJack F Vogel */ 3598cfa0ad2SJack F Vogel #define EM_EIAC 0x000DC 36023c9098bSSean Bruno /* 36123c9098bSSean Bruno * 82574 only reports 3 MSI-X vectors by default; 36223c9098bSSean Bruno * defines assisting with making it report 5 are 36323c9098bSSean Bruno * located here. 36423c9098bSSean Bruno */ 36523c9098bSSean Bruno #define EM_NVM_PCIE_CTRL 0x1B 36623c9098bSSean Bruno #define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) 36723c9098bSSean Bruno #define EM_NVM_MSIX_N_SHIFT 7 3688cfa0ad2SJack F Vogel 369dc926051SKevin Bowling struct e1000_softc; 3709d81738fSJack F Vogel 3719d81738fSJack F Vogel struct em_int_delay_info { 372dc926051SKevin Bowling struct e1000_softc *sc; /* Back-pointer to the sc struct */ 3739d81738fSJack F Vogel int offset; /* Register offset to read/write */ 3749d81738fSJack F Vogel int value; /* Current value in usecs */ 3759d81738fSJack F Vogel }; 3769d81738fSJack F Vogel 3778ec87fc5SJack F Vogel /* 3788ec87fc5SJack F Vogel * The transmit ring, one per tx queue 3798ec87fc5SJack F Vogel */ 3808ec87fc5SJack F Vogel struct tx_ring { 381dc926051SKevin Bowling struct e1000_softc *sc; 3828ec87fc5SJack F Vogel struct e1000_tx_desc *tx_base; 383f2d6ace4SSean Bruno uint64_t tx_paddr; 38495246abbSSean Bruno qidx_t *tx_rsq; 38595246abbSSean Bruno bool tx_tso; /* last tx was tso */ 38695246abbSSean Bruno uint8_t me; 38795246abbSSean Bruno qidx_t tx_rs_cidx; 38895246abbSSean Bruno qidx_t tx_rs_pidx; 38995246abbSSean Bruno qidx_t tx_cidx_processed; 3908ec87fc5SJack F Vogel /* Interrupt resources */ 3918ec87fc5SJack F Vogel void *tag; 3928ec87fc5SJack F Vogel struct resource *res; 393eaa9db2bSJack F Vogel unsigned long tx_irq; 394f2d6ace4SSean Bruno 395f2d6ace4SSean Bruno /* Saved csum offloading context information */ 396f2d6ace4SSean Bruno int csum_flags; 397f2d6ace4SSean Bruno int csum_lhlen; 398f2d6ace4SSean Bruno int csum_iphlen; 399f2d6ace4SSean Bruno 400f2d6ace4SSean Bruno int csum_thlen; 401f2d6ace4SSean Bruno int csum_mss; 402f2d6ace4SSean Bruno int csum_pktlen; 403f2d6ace4SSean Bruno 404f2d6ace4SSean Bruno uint32_t csum_txd_upper; 405f2d6ace4SSean Bruno uint32_t csum_txd_lower; /* last field */ 4068ec87fc5SJack F Vogel }; 4078ec87fc5SJack F Vogel 4088ec87fc5SJack F Vogel /* 4098ec87fc5SJack F Vogel * The Receive ring, one per rx queue 4108ec87fc5SJack F Vogel */ 4118ec87fc5SJack F Vogel struct rx_ring { 412dc926051SKevin Bowling struct e1000_softc *sc; 413f2d6ace4SSean Bruno struct em_rx_queue *que; 4148ec87fc5SJack F Vogel u32 me; 4158ec87fc5SJack F Vogel u32 payload; 416b834dceaSSean Bruno union e1000_rx_desc_extended *rx_base; 417f2d6ace4SSean Bruno uint64_t rx_paddr; 4188ec87fc5SJack F Vogel 4198ec87fc5SJack F Vogel /* Interrupt resources */ 4208ec87fc5SJack F Vogel void *tag; 4218ec87fc5SJack F Vogel struct resource *res; 422d9f1a5aaSJack F Vogel bool discard; 4238ec87fc5SJack F Vogel 4248ec87fc5SJack F Vogel /* Soft stats */ 425eaa9db2bSJack F Vogel unsigned long rx_irq; 426d9f1a5aaSJack F Vogel unsigned long rx_discarded; 427eaa9db2bSJack F Vogel unsigned long rx_packets; 428eaa9db2bSJack F Vogel unsigned long rx_bytes; 4298ec87fc5SJack F Vogel }; 4308ec87fc5SJack F Vogel 431f2d6ace4SSean Bruno struct em_tx_queue { 432dc926051SKevin Bowling struct e1000_softc *sc; 433f2d6ace4SSean Bruno u32 msix; 434f2d6ace4SSean Bruno u32 eims; /* This queue's EIMS bit */ 435f2d6ace4SSean Bruno u32 me; 436f2d6ace4SSean Bruno struct tx_ring txr; 437f2d6ace4SSean Bruno }; 438f2d6ace4SSean Bruno 439f2d6ace4SSean Bruno struct em_rx_queue { 440dc926051SKevin Bowling struct e1000_softc *sc; 441f2d6ace4SSean Bruno u32 me; 442f2d6ace4SSean Bruno u32 msix; 443f2d6ace4SSean Bruno u32 eims; 444f2d6ace4SSean Bruno struct rx_ring rxr; 445f2d6ace4SSean Bruno u64 irqs; 446f2d6ace4SSean Bruno struct if_irq que_irq; 447f2d6ace4SSean Bruno }; 4488ec87fc5SJack F Vogel 449dc926051SKevin Bowling /* Our softc structure */ 450dc926051SKevin Bowling struct e1000_softc { 4516c8d4b16SJack F Vogel struct e1000_hw hw; 4528cfa0ad2SJack F Vogel 453f2d6ace4SSean Bruno if_softc_ctx_t shared; 454f2d6ace4SSean Bruno if_ctx_t ctx; 455f2d6ace4SSean Bruno #define tx_num_queues shared->isc_ntxqsets 456f2d6ace4SSean Bruno #define rx_num_queues shared->isc_nrxqsets 457f2d6ace4SSean Bruno #define intr_type shared->isc_intr 4586c8d4b16SJack F Vogel /* FreeBSD operating-system-specific structures. */ 4596c8d4b16SJack F Vogel struct e1000_osdep osdep; 4605a9c6582SSean Bruno device_t dev; 46179c7b719SMarius Strobl struct cdev *led_dev; 4628cfa0ad2SJack F Vogel 463f2d6ace4SSean Bruno struct em_tx_queue *tx_queues; 464f2d6ace4SSean Bruno struct em_rx_queue *rx_queues; 465f2d6ace4SSean Bruno struct if_irq irq; 466f2d6ace4SSean Bruno 4676c8d4b16SJack F Vogel struct resource *memory; 4686c8d4b16SJack F Vogel struct resource *flash; 469f2d6ace4SSean Bruno struct resource *ioport; 4706c8d4b16SJack F Vogel 4718ec87fc5SJack F Vogel struct resource *res; 4728ec87fc5SJack F Vogel void *tag; 4738ec87fc5SJack F Vogel u32 linkvec; 4748ec87fc5SJack F Vogel u32 ivars; 4756c8d4b16SJack F Vogel 476f2d6ace4SSean Bruno struct ifmedia *media; 4778ec87fc5SJack F Vogel int msix; 4786c8d4b16SJack F Vogel int if_flags; 4796c8d4b16SJack F Vogel int em_insert_vlan_header; 4808ec87fc5SJack F Vogel u32 ims; 4818ec87fc5SJack F Vogel bool in_detach; 4826c8d4b16SJack F Vogel 483d8c2808fSSean Bruno u32 flags; 4846c8d4b16SJack F Vogel /* Task for FAST handling */ 485f2d6ace4SSean Bruno struct grouptask link_task; 4868ec87fc5SJack F Vogel 4878ec87fc5SJack F Vogel u16 num_vlans; 4888ec87fc5SJack F Vogel u32 txd_cmd; 4898ec87fc5SJack F Vogel 4907deff7f9SJack F Vogel u32 rx_mbuf_sz; 4916c8d4b16SJack F Vogel 4926c8d4b16SJack F Vogel /* Management and WOL features */ 4936c8d4b16SJack F Vogel u32 wol; 4946c8d4b16SJack F Vogel bool has_manage; 4956c8d4b16SJack F Vogel bool has_amt; 4966c8d4b16SJack F Vogel 497dd20cce1SPyun YongHyeon /* Multicast array memory */ 498dd20cce1SPyun YongHyeon u8 *mta; 499d9f1a5aaSJack F Vogel 5007deff7f9SJack F Vogel /* 5017deff7f9SJack F Vogel ** Shadow VFTA table, this is needed because 5027deff7f9SJack F Vogel ** the real vlan filter table gets cleared during 5037deff7f9SJack F Vogel ** a soft reset and the driver needs to be able 5047deff7f9SJack F Vogel ** to repopulate it. 5057deff7f9SJack F Vogel */ 5067deff7f9SJack F Vogel u32 shadow_vfta[EM_VFTA_SIZE]; 5077deff7f9SJack F Vogel 5087deff7f9SJack F Vogel /* Info about the interface */ 509fd33ce41SJack F Vogel u16 link_active; 510fd33ce41SJack F Vogel u16 fc; 5117deff7f9SJack F Vogel u16 link_speed; 5127deff7f9SJack F Vogel u16 link_duplex; 5137deff7f9SJack F Vogel u32 smartspeed; 514f2d6ace4SSean Bruno u32 dmac; 515f2d6ace4SSean Bruno int link_mask; 5162ddf24f8SKevin Bowling int tso_automasked; 517f2d6ace4SSean Bruno 518f2d6ace4SSean Bruno u64 que_mask; 519f2d6ace4SSean Bruno 520293663f4SKevin Bowling /* We need to store this at attach due to e1000 hw/sw locking model */ 521293663f4SKevin Bowling struct e1000_fw_version fw_ver; 522293663f4SKevin Bowling 5236c8d4b16SJack F Vogel struct em_int_delay_info tx_int_delay; 5246c8d4b16SJack F Vogel struct em_int_delay_info tx_abs_int_delay; 5256c8d4b16SJack F Vogel struct em_int_delay_info rx_int_delay; 5266c8d4b16SJack F Vogel struct em_int_delay_info rx_abs_int_delay; 5274dc07530SLuigi Rizzo struct em_int_delay_info tx_itr; 528a69ed8dfSJack F Vogel 5298cfa0ad2SJack F Vogel /* Misc stats maintained by the driver */ 5308cfa0ad2SJack F Vogel unsigned long dropped_pkts; 531e12a9f25SMarius Strobl unsigned long link_irq; 5328cfa0ad2SJack F Vogel unsigned long rx_overruns; 5338ec87fc5SJack F Vogel unsigned long watchdog_events; 5348cfa0ad2SJack F Vogel 5358cfa0ad2SJack F Vogel struct e1000_hw_stats stats; 536d8c2808fSSean Bruno u16 vf_ifp; 5378cfa0ad2SJack F Vogel }; 5388cfa0ad2SJack F Vogel 5398ec87fc5SJack F Vogel /******************************************************************************** 5408cfa0ad2SJack F Vogel * vendor_info_array 5418cfa0ad2SJack F Vogel * 5428cfa0ad2SJack F Vogel * This array contains the list of Subvendor/Subdevice IDs on which the driver 5438cfa0ad2SJack F Vogel * should load. 5448cfa0ad2SJack F Vogel * 5458ec87fc5SJack F Vogel ********************************************************************************/ 5468cfa0ad2SJack F Vogel typedef struct _em_vendor_info_t { 5478cfa0ad2SJack F Vogel unsigned int vendor_id; 5488cfa0ad2SJack F Vogel unsigned int device_id; 5498cfa0ad2SJack F Vogel unsigned int subvendor_id; 5508cfa0ad2SJack F Vogel unsigned int subdevice_id; 5518cfa0ad2SJack F Vogel unsigned int index; 5528cfa0ad2SJack F Vogel } em_vendor_info_t; 5538cfa0ad2SJack F Vogel 554dc926051SKevin Bowling void em_dump_rs(struct e1000_softc *); 555e61e0b91SJack F Vogel 556b834dceaSSean Bruno #define EM_RSSRK_SIZE 4 557b834dceaSSean Bruno #define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \ 558b834dceaSSean Bruno key[(i) * EM_RSSRK_SIZE + 1] << 8 | \ 559b834dceaSSean Bruno key[(i) * EM_RSSRK_SIZE + 2] << 16 | \ 560b834dceaSSean Bruno key[(i) * EM_RSSRK_SIZE + 3] << 24) 5618cfa0ad2SJack F Vogel #endif /* _EM_H_DEFINED_ */ 562