1d37cece2SSean Bruno /*- 2d37cece2SSean Bruno * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org> 3d37cece2SSean Bruno * All rights reserved. 4d37cece2SSean Bruno * 5d37cece2SSean Bruno * Redistribution and use in source and binary forms, with or without 6d37cece2SSean Bruno * modification, are permitted provided that the following conditions 7d37cece2SSean Bruno * are met: 8d37cece2SSean Bruno * 1. Redistributions of source code must retain the above copyright 9d37cece2SSean Bruno * notice, this list of conditions and the following disclaimer. 10d37cece2SSean Bruno * 2. Redistributions in binary form must reproduce the above copyright 11d37cece2SSean Bruno * notice, this list of conditions and the following disclaimer in the 12d37cece2SSean Bruno * documentation and/or other materials provided with the distribution. 13d37cece2SSean Bruno * 14d37cece2SSean Bruno * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15d37cece2SSean Bruno * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16d37cece2SSean Bruno * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17d37cece2SSean Bruno * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18d37cece2SSean Bruno * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19d37cece2SSean Bruno * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20d37cece2SSean Bruno * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21d37cece2SSean Bruno * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22d37cece2SSean Bruno * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23d37cece2SSean Bruno * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24d37cece2SSean Bruno * SUCH DAMAGE. 25d37cece2SSean Bruno */ 26d37cece2SSean Bruno 278cfa0ad2SJack F Vogel /*$FreeBSD$*/ 28f2d6ace4SSean Bruno #include "opt_ddb.h" 29f2d6ace4SSean Bruno #include "opt_inet.h" 30f2d6ace4SSean Bruno #include "opt_inet6.h" 31f2d6ace4SSean Bruno 32f2d6ace4SSean Bruno #ifdef HAVE_KERNEL_OPTION_HEADERS 33f2d6ace4SSean Bruno #include "opt_device_polling.h" 34f2d6ace4SSean Bruno #endif 35f2d6ace4SSean Bruno 36f2d6ace4SSean Bruno #include <sys/param.h> 37f2d6ace4SSean Bruno #include <sys/systm.h> 38f2d6ace4SSean Bruno #ifdef DDB 39f2d6ace4SSean Bruno #include <sys/types.h> 40f2d6ace4SSean Bruno #include <ddb/ddb.h> 41f2d6ace4SSean Bruno #endif 42f2d6ace4SSean Bruno #if __FreeBSD_version >= 800000 43f2d6ace4SSean Bruno #include <sys/buf_ring.h> 44f2d6ace4SSean Bruno #endif 45f2d6ace4SSean Bruno #include <sys/bus.h> 46f2d6ace4SSean Bruno #include <sys/endian.h> 47f2d6ace4SSean Bruno #include <sys/kernel.h> 48f2d6ace4SSean Bruno #include <sys/kthread.h> 49f2d6ace4SSean Bruno #include <sys/malloc.h> 50f2d6ace4SSean Bruno #include <sys/mbuf.h> 51f2d6ace4SSean Bruno #include <sys/module.h> 52f2d6ace4SSean Bruno #include <sys/rman.h> 53f2d6ace4SSean Bruno #include <sys/smp.h> 54f2d6ace4SSean Bruno #include <sys/socket.h> 55f2d6ace4SSean Bruno #include <sys/sockio.h> 56f2d6ace4SSean Bruno #include <sys/sysctl.h> 57f2d6ace4SSean Bruno #include <sys/taskqueue.h> 58f2d6ace4SSean Bruno #include <sys/eventhandler.h> 59f2d6ace4SSean Bruno #include <machine/bus.h> 60f2d6ace4SSean Bruno #include <machine/resource.h> 61f2d6ace4SSean Bruno 62f2d6ace4SSean Bruno #include <net/bpf.h> 63f2d6ace4SSean Bruno #include <net/ethernet.h> 64f2d6ace4SSean Bruno #include <net/if.h> 65f2d6ace4SSean Bruno #include <net/if_var.h> 66f2d6ace4SSean Bruno #include <net/if_arp.h> 67f2d6ace4SSean Bruno #include <net/if_dl.h> 68f2d6ace4SSean Bruno #include <net/if_media.h> 69f2d6ace4SSean Bruno #include <net/iflib.h> 70f2d6ace4SSean Bruno 71f2d6ace4SSean Bruno #include <net/if_types.h> 72f2d6ace4SSean Bruno #include <net/if_vlan_var.h> 73f2d6ace4SSean Bruno 74f2d6ace4SSean Bruno #include <netinet/in_systm.h> 75f2d6ace4SSean Bruno #include <netinet/in.h> 76f2d6ace4SSean Bruno #include <netinet/if_ether.h> 77f2d6ace4SSean Bruno #include <netinet/ip.h> 78f2d6ace4SSean Bruno #include <netinet/ip6.h> 79f2d6ace4SSean Bruno #include <netinet/tcp.h> 80f2d6ace4SSean Bruno #include <netinet/udp.h> 81f2d6ace4SSean Bruno 82f2d6ace4SSean Bruno #include <machine/in_cksum.h> 83f2d6ace4SSean Bruno #include <dev/led/led.h> 84f2d6ace4SSean Bruno #include <dev/pci/pcivar.h> 85f2d6ace4SSean Bruno #include <dev/pci/pcireg.h> 86f2d6ace4SSean Bruno 87f2d6ace4SSean Bruno #include "e1000_api.h" 88f2d6ace4SSean Bruno #include "e1000_82571.h" 89f2d6ace4SSean Bruno #include "ifdi_if.h" 908cfa0ad2SJack F Vogel 918cfa0ad2SJack F Vogel 928cfa0ad2SJack F Vogel #ifndef _EM_H_DEFINED_ 938cfa0ad2SJack F Vogel #define _EM_H_DEFINED_ 948cfa0ad2SJack F Vogel 959d81738fSJack F Vogel 968cfa0ad2SJack F Vogel /* Tunables */ 978cfa0ad2SJack F Vogel 988cfa0ad2SJack F Vogel /* 998cfa0ad2SJack F Vogel * EM_TXD: Maximum number of Transmit Descriptors 1008cfa0ad2SJack F Vogel * Valid Range: 80-256 for 82542 and 82543-based adapters 1018cfa0ad2SJack F Vogel * 80-4096 for others 1028cfa0ad2SJack F Vogel * Default Value: 256 1038cfa0ad2SJack F Vogel * This value is the number of transmit descriptors allocated by the driver. 1048cfa0ad2SJack F Vogel * Increasing this value allows the driver to queue more transmits. Each 1058cfa0ad2SJack F Vogel * descriptor is 16 bytes. 1068cfa0ad2SJack F Vogel * Since TDLEN should be multiple of 128bytes, the number of transmit 1078cfa0ad2SJack F Vogel * desscriptors should meet the following condition. 1088cfa0ad2SJack F Vogel * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 1098cfa0ad2SJack F Vogel */ 110f2d6ace4SSean Bruno #define EM_MIN_TXD 128 1118cfa0ad2SJack F Vogel #define EM_MAX_TXD 4096 112a69ed8dfSJack F Vogel #define EM_DEFAULT_TXD 1024 113f2d6ace4SSean Bruno #define EM_DEFAULT_MULTI_TXD 4096 1148cfa0ad2SJack F Vogel 1158cfa0ad2SJack F Vogel /* 1168cfa0ad2SJack F Vogel * EM_RXD - Maximum number of receive Descriptors 1178cfa0ad2SJack F Vogel * Valid Range: 80-256 for 82542 and 82543-based adapters 1188cfa0ad2SJack F Vogel * 80-4096 for others 1198cfa0ad2SJack F Vogel * Default Value: 256 1208cfa0ad2SJack F Vogel * This value is the number of receive descriptors allocated by the driver. 1218cfa0ad2SJack F Vogel * Increasing this value allows the driver to buffer more incoming packets. 1228cfa0ad2SJack F Vogel * Each descriptor is 16 bytes. A receive buffer is also allocated for each 1238cfa0ad2SJack F Vogel * descriptor. The maximum MTU size is 16110. 1248cfa0ad2SJack F Vogel * Since TDLEN should be multiple of 128bytes, the number of transmit 1258cfa0ad2SJack F Vogel * desscriptors should meet the following condition. 1268cfa0ad2SJack F Vogel * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 1278cfa0ad2SJack F Vogel */ 128f2d6ace4SSean Bruno #define EM_MIN_RXD 128 1298cfa0ad2SJack F Vogel #define EM_MAX_RXD 4096 130a69ed8dfSJack F Vogel #define EM_DEFAULT_RXD 1024 131f2d6ace4SSean Bruno #define EM_DEFAULT_MULTI_RXD 4096 1328cfa0ad2SJack F Vogel 1338cfa0ad2SJack F Vogel /* 1348cfa0ad2SJack F Vogel * EM_TIDV - Transmit Interrupt Delay Value 1358cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1368cfa0ad2SJack F Vogel * Default Value: 64 1378cfa0ad2SJack F Vogel * This value delays the generation of transmit interrupts in units of 1388cfa0ad2SJack F Vogel * 1.024 microseconds. Transmit interrupt reduction can improve CPU 1398cfa0ad2SJack F Vogel * efficiency if properly tuned for specific network traffic. If the 1408cfa0ad2SJack F Vogel * system is reporting dropped transmits, this value may be set too high 1418cfa0ad2SJack F Vogel * causing the driver to run out of available transmit descriptors. 1428cfa0ad2SJack F Vogel */ 1438cfa0ad2SJack F Vogel #define EM_TIDV 64 1448cfa0ad2SJack F Vogel 1458cfa0ad2SJack F Vogel /* 1468cfa0ad2SJack F Vogel * EM_TADV - Transmit Absolute Interrupt Delay Value 1478cfa0ad2SJack F Vogel * (Not valid for 82542/82543/82544) 1488cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1498cfa0ad2SJack F Vogel * Default Value: 64 1508cfa0ad2SJack F Vogel * This value, in units of 1.024 microseconds, limits the delay in which a 1518cfa0ad2SJack F Vogel * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 1528cfa0ad2SJack F Vogel * this value ensures that an interrupt is generated after the initial 1538cfa0ad2SJack F Vogel * packet is sent on the wire within the set amount of time. Proper tuning, 1548cfa0ad2SJack F Vogel * along with EM_TIDV, may improve traffic throughput in specific 1558cfa0ad2SJack F Vogel * network conditions. 1568cfa0ad2SJack F Vogel */ 1578cfa0ad2SJack F Vogel #define EM_TADV 64 1588cfa0ad2SJack F Vogel 1598cfa0ad2SJack F Vogel /* 1608cfa0ad2SJack F Vogel * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 1618cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1628cfa0ad2SJack F Vogel * Default Value: 0 1638cfa0ad2SJack F Vogel * This value delays the generation of receive interrupts in units of 1.024 1648cfa0ad2SJack F Vogel * microseconds. Receive interrupt reduction can improve CPU efficiency if 1658cfa0ad2SJack F Vogel * properly tuned for specific network traffic. Increasing this value adds 1668cfa0ad2SJack F Vogel * extra latency to frame reception and can end up decreasing the throughput 1678cfa0ad2SJack F Vogel * of TCP traffic. If the system is reporting dropped receives, this value 1688cfa0ad2SJack F Vogel * may be set too high, causing the driver to run out of available receive 1698cfa0ad2SJack F Vogel * descriptors. 1708cfa0ad2SJack F Vogel * 1718cfa0ad2SJack F Vogel * CAUTION: When setting EM_RDTR to a value other than 0, adapters 1728cfa0ad2SJack F Vogel * may hang (stop transmitting) under certain network conditions. 1738cfa0ad2SJack F Vogel * If this occurs a WATCHDOG message is logged in the system 1748cfa0ad2SJack F Vogel * event log. In addition, the controller is automatically reset, 1758cfa0ad2SJack F Vogel * restoring the network connection. To eliminate the potential 1768cfa0ad2SJack F Vogel * for the hang ensure that EM_RDTR is set to 0. 1778cfa0ad2SJack F Vogel */ 1788cfa0ad2SJack F Vogel #define EM_RDTR 0 1798cfa0ad2SJack F Vogel 1808cfa0ad2SJack F Vogel /* 1818cfa0ad2SJack F Vogel * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 1828cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1838cfa0ad2SJack F Vogel * Default Value: 64 1848cfa0ad2SJack F Vogel * This value, in units of 1.024 microseconds, limits the delay in which a 1858cfa0ad2SJack F Vogel * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 1868cfa0ad2SJack F Vogel * this value ensures that an interrupt is generated after the initial 1878cfa0ad2SJack F Vogel * packet is received within the set amount of time. Proper tuning, 1888cfa0ad2SJack F Vogel * along with EM_RDTR, may improve traffic throughput in specific network 1898cfa0ad2SJack F Vogel * conditions. 1908cfa0ad2SJack F Vogel */ 1918cfa0ad2SJack F Vogel #define EM_RADV 64 1928cfa0ad2SJack F Vogel 1938cfa0ad2SJack F Vogel /* 1948cfa0ad2SJack F Vogel * This parameter controls whether or not autonegotation is enabled. 1958cfa0ad2SJack F Vogel * 0 - Disable autonegotiation 1968cfa0ad2SJack F Vogel * 1 - Enable autonegotiation 1978cfa0ad2SJack F Vogel */ 1988cfa0ad2SJack F Vogel #define DO_AUTO_NEG 1 1998cfa0ad2SJack F Vogel 2008cfa0ad2SJack F Vogel /* 2018cfa0ad2SJack F Vogel * This parameter control whether or not the driver will wait for 2028cfa0ad2SJack F Vogel * autonegotiation to complete. 2038cfa0ad2SJack F Vogel * 1 - Wait for autonegotiation to complete 2048cfa0ad2SJack F Vogel * 0 - Don't wait for autonegotiation to complete 2058cfa0ad2SJack F Vogel */ 2068cfa0ad2SJack F Vogel #define WAIT_FOR_AUTO_NEG_DEFAULT 0 2078cfa0ad2SJack F Vogel 2088cfa0ad2SJack F Vogel /* Tunables -- End */ 2098cfa0ad2SJack F Vogel 2108cfa0ad2SJack F Vogel #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 2118cfa0ad2SJack F Vogel ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 2128cfa0ad2SJack F Vogel ADVERTISE_1000_FULL) 2138cfa0ad2SJack F Vogel 2148cfa0ad2SJack F Vogel #define AUTO_ALL_MODES 0 2158cfa0ad2SJack F Vogel 2168cfa0ad2SJack F Vogel /* PHY master/slave setting */ 2178cfa0ad2SJack F Vogel #define EM_MASTER_SLAVE e1000_ms_hw_default 2188cfa0ad2SJack F Vogel 2198cfa0ad2SJack F Vogel /* 2208cfa0ad2SJack F Vogel * Micellaneous constants 2218cfa0ad2SJack F Vogel */ 2228cfa0ad2SJack F Vogel #define EM_VENDOR_ID 0x8086 2238cfa0ad2SJack F Vogel #define EM_FLASH 0x0014 2248cfa0ad2SJack F Vogel 2258cfa0ad2SJack F Vogel #define EM_JUMBO_PBA 0x00000028 2268cfa0ad2SJack F Vogel #define EM_DEFAULT_PBA 0x00000030 2278cfa0ad2SJack F Vogel #define EM_SMARTSPEED_DOWNSHIFT 3 2288cfa0ad2SJack F Vogel #define EM_SMARTSPEED_MAX 15 2298ec87fc5SJack F Vogel #define EM_MAX_LOOP 10 2308cfa0ad2SJack F Vogel 2318cfa0ad2SJack F Vogel #define MAX_NUM_MULTICAST_ADDRESSES 128 2328cfa0ad2SJack F Vogel #define PCI_ANY_ID (~0U) 2338cfa0ad2SJack F Vogel #define ETHER_ALIGN 2 2348cfa0ad2SJack F Vogel #define EM_FC_PAUSE_TIME 0x0680 2358cfa0ad2SJack F Vogel #define EM_EEPROM_APME 0x400; 2364edd8523SJack F Vogel #define EM_82544_APME 0x0004; 2378cfa0ad2SJack F Vogel 238b7a728aaSSean Bruno /* 239b7a728aaSSean Bruno * Driver state logic for the detection of a hung state 240b7a728aaSSean Bruno * in hardware. Set TX_HUNG whenever a TX packet is used 241b7a728aaSSean Bruno * (data is sent) and clear it when txeof() is invoked if 242b7a728aaSSean Bruno * any descriptors from the ring are cleaned/reclaimed. 243b7a728aaSSean Bruno * Increment internal counter if no descriptors are cleaned 244b7a728aaSSean Bruno * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, 245b7a728aaSSean Bruno * reset adapter. 246b7a728aaSSean Bruno */ 247b7a728aaSSean Bruno #define EM_TX_IDLE 0x00000000 248b7a728aaSSean Bruno #define EM_TX_BUSY 0x00000001 249b7a728aaSSean Bruno #define EM_TX_HUNG 0x80000000 250b7a728aaSSean Bruno #define EM_TX_MAXTRIES 10 2517deff7f9SJack F Vogel 252c80429ceSEric Joyner #define PCICFG_DESC_RING_STATUS 0xe4 253c80429ceSEric Joyner #define FLUSH_DESC_REQUIRED 0x100 254c80429ceSEric Joyner 255f2d6ace4SSean Bruno 256f2d6ace4SSean Bruno #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 257f2d6ace4SSean Bruno ((hw->mac.type <= e1000_82576) ? 16 : 8)) 258f2d6ace4SSean Bruno #define IGB_RX_HTHRESH 8 259f2d6ace4SSean Bruno #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 260f2d6ace4SSean Bruno (adapter->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4) 261f2d6ace4SSean Bruno 262f2d6ace4SSean Bruno #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 263f2d6ace4SSean Bruno #define IGB_TX_HTHRESH 1 264f2d6ace4SSean Bruno #define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 265f2d6ace4SSean Bruno (adapter->intr_type == IFLIB_INTR_MSIX) ? 1 : 16) 266f2d6ace4SSean Bruno 2678cfa0ad2SJack F Vogel /* 2688cfa0ad2SJack F Vogel * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 2698cfa0ad2SJack F Vogel * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 2708cfa0ad2SJack F Vogel * also optimize cache line size effect. H/W supports up to cache line size 128. 2718cfa0ad2SJack F Vogel */ 2728cfa0ad2SJack F Vogel #define EM_DBA_ALIGN 128 2738cfa0ad2SJack F Vogel 27423c9098bSSean Bruno /* 27523c9098bSSean Bruno * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 27623c9098bSSean Bruno */ 27723c9098bSSean Bruno #define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ 27823c9098bSSean Bruno #define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 27923c9098bSSean Bruno #define TARC_MQ_FIX (1 << 23) | \ 28023c9098bSSean Bruno (1 << 24) | \ 28123c9098bSSean Bruno (1 << 25) /* Handle errata in MQ mode */ 28223c9098bSSean Bruno #define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ 2838cfa0ad2SJack F Vogel 2848cfa0ad2SJack F Vogel /* PCI Config defines */ 2858cfa0ad2SJack F Vogel #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 2868cfa0ad2SJack F Vogel #define EM_BAR_TYPE_MASK 0x00000001 2878cfa0ad2SJack F Vogel #define EM_BAR_TYPE_MMEM 0x00000000 288f2d6ace4SSean Bruno #define EM_BAR_TYPE_IO 0x00000001 2898cfa0ad2SJack F Vogel #define EM_BAR_TYPE_FLASH 0x0014 2908cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 2918cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE_MASK 0x00000006 2928cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE_32BIT 0x00000000 2938cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE_64BIT 0x00000004 2948cfa0ad2SJack F Vogel #define EM_MSIX_BAR 3 /* On 82575 */ 2958cfa0ad2SJack F Vogel 296fd33ce41SJack F Vogel /* More backward compatibility */ 297fd33ce41SJack F Vogel #if __FreeBSD_version < 900000 2981fd3c44fSJack F Vogel #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 2991fd3c44fSJack F Vogel #endif 3001fd3c44fSJack F Vogel 3018cfa0ad2SJack F Vogel /* Defines for printing debug information */ 3028cfa0ad2SJack F Vogel #define DEBUG_INIT 0 3038cfa0ad2SJack F Vogel #define DEBUG_IOCTL 0 3048cfa0ad2SJack F Vogel #define DEBUG_HW 0 3058cfa0ad2SJack F Vogel 3068cfa0ad2SJack F Vogel #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 3078cfa0ad2SJack F Vogel #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 3088cfa0ad2SJack F Vogel #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 3098cfa0ad2SJack F Vogel #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 3108cfa0ad2SJack F Vogel #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 3118cfa0ad2SJack F Vogel #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 3128cfa0ad2SJack F Vogel #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 3138cfa0ad2SJack F Vogel #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 3148cfa0ad2SJack F Vogel #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 3158cfa0ad2SJack F Vogel 3160a01ff4dSMarius Strobl #define EM_MAX_SCATTER 40 3179d81738fSJack F Vogel #define EM_VFTA_SIZE 128 3188cfa0ad2SJack F Vogel #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 3198cfa0ad2SJack F Vogel #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 3208cfa0ad2SJack F Vogel #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 3218ec87fc5SJack F Vogel #define EM_MSIX_LINK 0x01000000 /* For 82574 use */ 3228cfa0ad2SJack F Vogel #define ETH_ZLEN 60 3238cfa0ad2SJack F Vogel #define ETH_ADDR_LEN 6 32482379056SSean Bruno #define EM_CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 32582379056SSean Bruno #define IGB_CSUM_OFFLOAD 0x0E0F /* Offload bits in mbuf flag */ 3268cfa0ad2SJack F Vogel 327f2d6ace4SSean Bruno #define IGB_PKTTYPE_MASK 0x0000FFF0 328f2d6ace4SSean Bruno #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 329f2d6ace4SSean Bruno 3308cfa0ad2SJack F Vogel /* 3318cfa0ad2SJack F Vogel * 82574 has a nonstandard address for EIAC 3328cfa0ad2SJack F Vogel * and since its only used in MSIX, and in 3338cfa0ad2SJack F Vogel * the em driver only 82574 uses MSIX we can 3348cfa0ad2SJack F Vogel * solve it just using this define. 3358cfa0ad2SJack F Vogel */ 3368cfa0ad2SJack F Vogel #define EM_EIAC 0x000DC 33723c9098bSSean Bruno /* 33823c9098bSSean Bruno * 82574 only reports 3 MSI-X vectors by default; 33923c9098bSSean Bruno * defines assisting with making it report 5 are 34023c9098bSSean Bruno * located here. 34123c9098bSSean Bruno */ 34223c9098bSSean Bruno #define EM_NVM_PCIE_CTRL 0x1B 34323c9098bSSean Bruno #define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) 34423c9098bSSean Bruno #define EM_NVM_MSIX_N_SHIFT 7 3458cfa0ad2SJack F Vogel 3469d81738fSJack F Vogel struct adapter; 3479d81738fSJack F Vogel 3489d81738fSJack F Vogel struct em_int_delay_info { 3499d81738fSJack F Vogel struct adapter *adapter; /* Back-pointer to the adapter struct */ 3509d81738fSJack F Vogel int offset; /* Register offset to read/write */ 3519d81738fSJack F Vogel int value; /* Current value in usecs */ 3529d81738fSJack F Vogel }; 3539d81738fSJack F Vogel 3548ec87fc5SJack F Vogel /* 3558ec87fc5SJack F Vogel * The transmit ring, one per tx queue 3568ec87fc5SJack F Vogel */ 3578ec87fc5SJack F Vogel struct tx_ring { 3588ec87fc5SJack F Vogel struct adapter *adapter; 359f2d6ace4SSean Bruno struct em_tx_queue *que; 3608ec87fc5SJack F Vogel u32 me; 361b7a728aaSSean Bruno int busy; 3628ec87fc5SJack F Vogel struct e1000_tx_desc *tx_base; 363f2d6ace4SSean Bruno uint64_t tx_paddr; 364b834dceaSSean Bruno struct em_txbuffer *tx_buffers; 3658ec87fc5SJack F Vogel u32 tx_tso; /* last tx was tso */ 366f2d6ace4SSean Bruno 3678ec87fc5SJack F Vogel /* Interrupt resources */ 3688ec87fc5SJack F Vogel void *tag; 3698ec87fc5SJack F Vogel struct resource *res; 370eaa9db2bSJack F Vogel unsigned long tx_irq; 371eaa9db2bSJack F Vogel unsigned long no_desc_avail; 372f2d6ace4SSean Bruno 373f2d6ace4SSean Bruno /* Saved csum offloading context information */ 374f2d6ace4SSean Bruno int csum_flags; 375f2d6ace4SSean Bruno int csum_lhlen; 376f2d6ace4SSean Bruno int csum_iphlen; 377f2d6ace4SSean Bruno 378f2d6ace4SSean Bruno int csum_thlen; 379f2d6ace4SSean Bruno int csum_mss; 380f2d6ace4SSean Bruno int csum_pktlen; 381f2d6ace4SSean Bruno 382f2d6ace4SSean Bruno uint32_t csum_txd_upper; 383f2d6ace4SSean Bruno uint32_t csum_txd_lower; /* last field */ 3848ec87fc5SJack F Vogel }; 3858ec87fc5SJack F Vogel 3868ec87fc5SJack F Vogel /* 3878ec87fc5SJack F Vogel * The Receive ring, one per rx queue 3888ec87fc5SJack F Vogel */ 3898ec87fc5SJack F Vogel struct rx_ring { 3908ec87fc5SJack F Vogel struct adapter *adapter; 391f2d6ace4SSean Bruno struct em_rx_queue *que; 3928ec87fc5SJack F Vogel u32 me; 3938ec87fc5SJack F Vogel u32 payload; 394b834dceaSSean Bruno union e1000_rx_desc_extended *rx_base; 395f2d6ace4SSean Bruno uint64_t rx_paddr; 3968ec87fc5SJack F Vogel 3978ec87fc5SJack F Vogel /* Interrupt resources */ 3988ec87fc5SJack F Vogel void *tag; 3998ec87fc5SJack F Vogel struct resource *res; 400d9f1a5aaSJack F Vogel bool discard; 4018ec87fc5SJack F Vogel 4028ec87fc5SJack F Vogel /* Soft stats */ 403eaa9db2bSJack F Vogel unsigned long rx_irq; 404d9f1a5aaSJack F Vogel unsigned long rx_discarded; 405eaa9db2bSJack F Vogel unsigned long rx_packets; 406eaa9db2bSJack F Vogel unsigned long rx_bytes; 4078ec87fc5SJack F Vogel }; 4088ec87fc5SJack F Vogel 409f2d6ace4SSean Bruno struct em_tx_queue { 410f2d6ace4SSean Bruno struct adapter *adapter; 411f2d6ace4SSean Bruno u32 msix; 412f2d6ace4SSean Bruno u32 eims; /* This queue's EIMS bit */ 413f2d6ace4SSean Bruno u32 me; 414f2d6ace4SSean Bruno struct tx_ring txr; 415f2d6ace4SSean Bruno }; 416f2d6ace4SSean Bruno 417f2d6ace4SSean Bruno struct em_rx_queue { 418f2d6ace4SSean Bruno struct adapter *adapter; 419f2d6ace4SSean Bruno u32 me; 420f2d6ace4SSean Bruno u32 msix; 421f2d6ace4SSean Bruno u32 eims; 422f2d6ace4SSean Bruno struct rx_ring rxr; 423f2d6ace4SSean Bruno u64 irqs; 424f2d6ace4SSean Bruno struct if_irq que_irq; 425f2d6ace4SSean Bruno }; 4268ec87fc5SJack F Vogel 4278ec87fc5SJack F Vogel /* Our adapter structure */ 4288ec87fc5SJack F Vogel struct adapter { 429f2d6ace4SSean Bruno struct ifnet *ifp; 4306c8d4b16SJack F Vogel struct e1000_hw hw; 4318cfa0ad2SJack F Vogel 432f2d6ace4SSean Bruno if_softc_ctx_t shared; 433f2d6ace4SSean Bruno if_ctx_t ctx; 434f2d6ace4SSean Bruno #define tx_num_queues shared->isc_ntxqsets 435f2d6ace4SSean Bruno #define rx_num_queues shared->isc_nrxqsets 436f2d6ace4SSean Bruno #define intr_type shared->isc_intr 4376c8d4b16SJack F Vogel /* FreeBSD operating-system-specific structures. */ 4386c8d4b16SJack F Vogel struct e1000_osdep osdep; 439*5a9c6582SSean Bruno device_t dev; 44079c7b719SMarius Strobl struct cdev *led_dev; 4418cfa0ad2SJack F Vogel 442f2d6ace4SSean Bruno struct em_tx_queue *tx_queues; 443f2d6ace4SSean Bruno struct em_rx_queue *rx_queues; 444f2d6ace4SSean Bruno struct if_irq irq; 445f2d6ace4SSean Bruno 4466c8d4b16SJack F Vogel struct resource *memory; 4476c8d4b16SJack F Vogel struct resource *flash; 448f2d6ace4SSean Bruno struct resource *ioport; 449f2d6ace4SSean Bruno int io_rid; 4506c8d4b16SJack F Vogel 4518ec87fc5SJack F Vogel struct resource *res; 4528ec87fc5SJack F Vogel void *tag; 4538ec87fc5SJack F Vogel u32 linkvec; 4548ec87fc5SJack F Vogel u32 ivars; 4556c8d4b16SJack F Vogel 456f2d6ace4SSean Bruno struct ifmedia *media; 4578ec87fc5SJack F Vogel int msix; 4586c8d4b16SJack F Vogel int if_flags; 4596c8d4b16SJack F Vogel int min_frame_size; 4606c8d4b16SJack F Vogel int em_insert_vlan_header; 4618ec87fc5SJack F Vogel u32 ims; 4628ec87fc5SJack F Vogel bool in_detach; 4636c8d4b16SJack F Vogel 4646c8d4b16SJack F Vogel /* Task for FAST handling */ 465f2d6ace4SSean Bruno struct grouptask link_task; 4668ec87fc5SJack F Vogel 4678ec87fc5SJack F Vogel u16 num_vlans; 4688ec87fc5SJack F Vogel u32 txd_cmd; 4698ec87fc5SJack F Vogel 470f2d6ace4SSean Bruno u32 tx_process_limit; 4718ec87fc5SJack F Vogel u32 rx_process_limit; 4727deff7f9SJack F Vogel u32 rx_mbuf_sz; 4736c8d4b16SJack F Vogel 4746c8d4b16SJack F Vogel /* Management and WOL features */ 4756c8d4b16SJack F Vogel u32 wol; 4766c8d4b16SJack F Vogel bool has_manage; 4776c8d4b16SJack F Vogel bool has_amt; 4786c8d4b16SJack F Vogel 479dd20cce1SPyun YongHyeon /* Multicast array memory */ 480dd20cce1SPyun YongHyeon u8 *mta; 481d9f1a5aaSJack F Vogel 4827deff7f9SJack F Vogel /* 4837deff7f9SJack F Vogel ** Shadow VFTA table, this is needed because 4847deff7f9SJack F Vogel ** the real vlan filter table gets cleared during 4857deff7f9SJack F Vogel ** a soft reset and the driver needs to be able 4867deff7f9SJack F Vogel ** to repopulate it. 4877deff7f9SJack F Vogel */ 4887deff7f9SJack F Vogel u32 shadow_vfta[EM_VFTA_SIZE]; 4897deff7f9SJack F Vogel 4907deff7f9SJack F Vogel /* Info about the interface */ 491fd33ce41SJack F Vogel u16 link_active; 492fd33ce41SJack F Vogel u16 fc; 4937deff7f9SJack F Vogel u16 link_speed; 4947deff7f9SJack F Vogel u16 link_duplex; 4957deff7f9SJack F Vogel u32 smartspeed; 496f2d6ace4SSean Bruno u32 dmac; 497f2d6ace4SSean Bruno int link_mask; 498f2d6ace4SSean Bruno 499f2d6ace4SSean Bruno u64 que_mask; 500f2d6ace4SSean Bruno 5017deff7f9SJack F Vogel 5026c8d4b16SJack F Vogel struct em_int_delay_info tx_int_delay; 5036c8d4b16SJack F Vogel struct em_int_delay_info tx_abs_int_delay; 5046c8d4b16SJack F Vogel struct em_int_delay_info rx_int_delay; 5056c8d4b16SJack F Vogel struct em_int_delay_info rx_abs_int_delay; 5064dc07530SLuigi Rizzo struct em_int_delay_info tx_itr; 507a69ed8dfSJack F Vogel 5088cfa0ad2SJack F Vogel /* Misc stats maintained by the driver */ 5098cfa0ad2SJack F Vogel unsigned long dropped_pkts; 510e12a9f25SMarius Strobl unsigned long link_irq; 511e12a9f25SMarius Strobl unsigned long mbuf_defrag_failed; 5128cfa0ad2SJack F Vogel unsigned long no_tx_dma_setup; 513e12a9f25SMarius Strobl unsigned long no_tx_map_avail; 5148cfa0ad2SJack F Vogel unsigned long rx_overruns; 5158ec87fc5SJack F Vogel unsigned long watchdog_events; 5168cfa0ad2SJack F Vogel 5178cfa0ad2SJack F Vogel struct e1000_hw_stats stats; 5188cfa0ad2SJack F Vogel }; 5198cfa0ad2SJack F Vogel 5208ec87fc5SJack F Vogel /******************************************************************************** 5218cfa0ad2SJack F Vogel * vendor_info_array 5228cfa0ad2SJack F Vogel * 5238cfa0ad2SJack F Vogel * This array contains the list of Subvendor/Subdevice IDs on which the driver 5248cfa0ad2SJack F Vogel * should load. 5258cfa0ad2SJack F Vogel * 5268ec87fc5SJack F Vogel ********************************************************************************/ 5278cfa0ad2SJack F Vogel typedef struct _em_vendor_info_t { 5288cfa0ad2SJack F Vogel unsigned int vendor_id; 5298cfa0ad2SJack F Vogel unsigned int device_id; 5308cfa0ad2SJack F Vogel unsigned int subvendor_id; 5318cfa0ad2SJack F Vogel unsigned int subdevice_id; 5328cfa0ad2SJack F Vogel unsigned int index; 5338cfa0ad2SJack F Vogel } em_vendor_info_t; 5348cfa0ad2SJack F Vogel 535b834dceaSSean Bruno struct em_txbuffer { 536f2d6ace4SSean Bruno int eop; 5378cfa0ad2SJack F Vogel }; 5388cfa0ad2SJack F Vogel 539e61e0b91SJack F Vogel 5408cfa0ad2SJack F Vogel #define EM_CORE_LOCK_INIT(_sc, _name) \ 5418cfa0ad2SJack F Vogel mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 5428cfa0ad2SJack F Vogel #define EM_TX_LOCK_INIT(_sc, _name) \ 5438cfa0ad2SJack F Vogel mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 5448cfa0ad2SJack F Vogel #define EM_RX_LOCK_INIT(_sc, _name) \ 5458cfa0ad2SJack F Vogel mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 5468cfa0ad2SJack F Vogel #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 5478cfa0ad2SJack F Vogel #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 5488cfa0ad2SJack F Vogel #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 5498cfa0ad2SJack F Vogel #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 5508cfa0ad2SJack F Vogel #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 551f2502470SKip Macy #define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 5528cfa0ad2SJack F Vogel #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 5538cfa0ad2SJack F Vogel #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 5548cfa0ad2SJack F Vogel #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 5558cfa0ad2SJack F Vogel #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 5568cfa0ad2SJack F Vogel #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 5578cfa0ad2SJack F Vogel #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 55891ce5735SJack F Vogel #define EM_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 5598cfa0ad2SJack F Vogel 560b834dceaSSean Bruno #define EM_RSSRK_SIZE 4 561b834dceaSSean Bruno #define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \ 562b834dceaSSean Bruno key[(i) * EM_RSSRK_SIZE + 1] << 8 | \ 563b834dceaSSean Bruno key[(i) * EM_RSSRK_SIZE + 2] << 16 | \ 564b834dceaSSean Bruno key[(i) * EM_RSSRK_SIZE + 3] << 24) 5658cfa0ad2SJack F Vogel #endif /* _EM_H_DEFINED_ */ 566