1d37cece2SSean Bruno /*- 27282444bSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause 37282444bSPedro F. Giffuni * 47021bf05SStephen Hurd * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5d37cece2SSean Bruno * All rights reserved. 6d37cece2SSean Bruno * 7d37cece2SSean Bruno * Redistribution and use in source and binary forms, with or without 8d37cece2SSean Bruno * modification, are permitted provided that the following conditions 9d37cece2SSean Bruno * are met: 10d37cece2SSean Bruno * 1. Redistributions of source code must retain the above copyright 11d37cece2SSean Bruno * notice, this list of conditions and the following disclaimer. 12d37cece2SSean Bruno * 2. Redistributions in binary form must reproduce the above copyright 13d37cece2SSean Bruno * notice, this list of conditions and the following disclaimer in the 14d37cece2SSean Bruno * documentation and/or other materials provided with the distribution. 15d37cece2SSean Bruno * 16d37cece2SSean Bruno * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17d37cece2SSean Bruno * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18d37cece2SSean Bruno * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19d37cece2SSean Bruno * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20d37cece2SSean Bruno * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21d37cece2SSean Bruno * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22d37cece2SSean Bruno * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23d37cece2SSean Bruno * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24d37cece2SSean Bruno * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25d37cece2SSean Bruno * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26d37cece2SSean Bruno * SUCH DAMAGE. 27d37cece2SSean Bruno */ 28d37cece2SSean Bruno 298cfa0ad2SJack F Vogel /*$FreeBSD$*/ 30dc926051SKevin Bowling 31dc926051SKevin Bowling #ifndef _EM_H_DEFINED_ 32dc926051SKevin Bowling #define _EM_H_DEFINED_ 33dc926051SKevin Bowling 34f2d6ace4SSean Bruno #include "opt_ddb.h" 35f2d6ace4SSean Bruno #include "opt_inet.h" 36f2d6ace4SSean Bruno #include "opt_inet6.h" 37467515a4SEric Joyner #include "opt_rss.h" 38f2d6ace4SSean Bruno 39f2d6ace4SSean Bruno #ifdef HAVE_KERNEL_OPTION_HEADERS 40f2d6ace4SSean Bruno #include "opt_device_polling.h" 41f2d6ace4SSean Bruno #endif 42f2d6ace4SSean Bruno 43f2d6ace4SSean Bruno #include <sys/param.h> 44f2d6ace4SSean Bruno #include <sys/systm.h> 45f2d6ace4SSean Bruno #ifdef DDB 46f2d6ace4SSean Bruno #include <sys/types.h> 47f2d6ace4SSean Bruno #include <ddb/ddb.h> 48f2d6ace4SSean Bruno #endif 49f2d6ace4SSean Bruno #include <sys/buf_ring.h> 50f2d6ace4SSean Bruno #include <sys/bus.h> 51f2d6ace4SSean Bruno #include <sys/endian.h> 52f2d6ace4SSean Bruno #include <sys/kernel.h> 53f2d6ace4SSean Bruno #include <sys/kthread.h> 54f2d6ace4SSean Bruno #include <sys/malloc.h> 55f2d6ace4SSean Bruno #include <sys/mbuf.h> 56f2d6ace4SSean Bruno #include <sys/module.h> 57f2d6ace4SSean Bruno #include <sys/rman.h> 58f2d6ace4SSean Bruno #include <sys/smp.h> 59f2d6ace4SSean Bruno #include <sys/socket.h> 60f2d6ace4SSean Bruno #include <sys/sockio.h> 61f2d6ace4SSean Bruno #include <sys/sysctl.h> 62f2d6ace4SSean Bruno #include <sys/taskqueue.h> 63f2d6ace4SSean Bruno #include <sys/eventhandler.h> 64f2d6ace4SSean Bruno #include <machine/bus.h> 65f2d6ace4SSean Bruno #include <machine/resource.h> 66f2d6ace4SSean Bruno 67f2d6ace4SSean Bruno #include <net/bpf.h> 68f2d6ace4SSean Bruno #include <net/ethernet.h> 69f2d6ace4SSean Bruno #include <net/if.h> 70f2d6ace4SSean Bruno #include <net/if_var.h> 71f2d6ace4SSean Bruno #include <net/if_arp.h> 72f2d6ace4SSean Bruno #include <net/if_dl.h> 73f2d6ace4SSean Bruno #include <net/if_media.h> 74f2d6ace4SSean Bruno #include <net/iflib.h> 75467515a4SEric Joyner #ifdef RSS 76467515a4SEric Joyner #include <net/rss_config.h> 77467515a4SEric Joyner #include <netinet/in_rss.h> 78467515a4SEric Joyner #endif 79f2d6ace4SSean Bruno 80f2d6ace4SSean Bruno #include <net/if_types.h> 81f2d6ace4SSean Bruno #include <net/if_vlan_var.h> 82f2d6ace4SSean Bruno 83f2d6ace4SSean Bruno #include <netinet/in_systm.h> 84f2d6ace4SSean Bruno #include <netinet/in.h> 85f2d6ace4SSean Bruno #include <netinet/if_ether.h> 86f2d6ace4SSean Bruno #include <netinet/ip.h> 87f2d6ace4SSean Bruno #include <netinet/ip6.h> 88f2d6ace4SSean Bruno #include <netinet/tcp.h> 89f2d6ace4SSean Bruno #include <netinet/udp.h> 90f2d6ace4SSean Bruno 91f2d6ace4SSean Bruno #include <machine/in_cksum.h> 92f2d6ace4SSean Bruno #include <dev/led/led.h> 93f2d6ace4SSean Bruno #include <dev/pci/pcivar.h> 94f2d6ace4SSean Bruno #include <dev/pci/pcireg.h> 95f2d6ace4SSean Bruno 96f2d6ace4SSean Bruno #include "e1000_api.h" 97f2d6ace4SSean Bruno #include "e1000_82571.h" 98f2d6ace4SSean Bruno #include "ifdi_if.h" 998cfa0ad2SJack F Vogel 1008cfa0ad2SJack F Vogel /* Tunables */ 1018cfa0ad2SJack F Vogel 1028cfa0ad2SJack F Vogel /* 1037d0d6484SSean Bruno * EM_MAX_TXD: Maximum number of Transmit Descriptors 1048cfa0ad2SJack F Vogel * Valid Range: 80-256 for 82542 and 82543-based adapters 1058cfa0ad2SJack F Vogel * 80-4096 for others 1067d0d6484SSean Bruno * Default Value: 1024 1078cfa0ad2SJack F Vogel * This value is the number of transmit descriptors allocated by the driver. 1088cfa0ad2SJack F Vogel * Increasing this value allows the driver to queue more transmits. Each 1098cfa0ad2SJack F Vogel * descriptor is 16 bytes. 1108cfa0ad2SJack F Vogel * Since TDLEN should be multiple of 128bytes, the number of transmit 1118cfa0ad2SJack F Vogel * desscriptors should meet the following condition. 1128cfa0ad2SJack F Vogel * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 1138cfa0ad2SJack F Vogel */ 114f2d6ace4SSean Bruno #define EM_MIN_TXD 128 1158cfa0ad2SJack F Vogel #define EM_MAX_TXD 4096 116a69ed8dfSJack F Vogel #define EM_DEFAULT_TXD 1024 117f2d6ace4SSean Bruno #define EM_DEFAULT_MULTI_TXD 4096 1187d0d6484SSean Bruno #define IGB_MAX_TXD 4096 1198cfa0ad2SJack F Vogel 1208cfa0ad2SJack F Vogel /* 1217d0d6484SSean Bruno * EM_MAX_RXD - Maximum number of receive Descriptors 1228cfa0ad2SJack F Vogel * Valid Range: 80-256 for 82542 and 82543-based adapters 1238cfa0ad2SJack F Vogel * 80-4096 for others 1247d0d6484SSean Bruno * Default Value: 1024 1258cfa0ad2SJack F Vogel * This value is the number of receive descriptors allocated by the driver. 1268cfa0ad2SJack F Vogel * Increasing this value allows the driver to buffer more incoming packets. 1278cfa0ad2SJack F Vogel * Each descriptor is 16 bytes. A receive buffer is also allocated for each 1288cfa0ad2SJack F Vogel * descriptor. The maximum MTU size is 16110. 1298cfa0ad2SJack F Vogel * Since TDLEN should be multiple of 128bytes, the number of transmit 1308cfa0ad2SJack F Vogel * desscriptors should meet the following condition. 1318cfa0ad2SJack F Vogel * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 1328cfa0ad2SJack F Vogel */ 133f2d6ace4SSean Bruno #define EM_MIN_RXD 128 1348cfa0ad2SJack F Vogel #define EM_MAX_RXD 4096 135a69ed8dfSJack F Vogel #define EM_DEFAULT_RXD 1024 136f2d6ace4SSean Bruno #define EM_DEFAULT_MULTI_RXD 4096 1377d0d6484SSean Bruno #define IGB_MAX_RXD 4096 1388cfa0ad2SJack F Vogel 1398cfa0ad2SJack F Vogel /* 1408cfa0ad2SJack F Vogel * EM_TIDV - Transmit Interrupt Delay Value 1418cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1428cfa0ad2SJack F Vogel * Default Value: 64 1438cfa0ad2SJack F Vogel * This value delays the generation of transmit interrupts in units of 1448cfa0ad2SJack F Vogel * 1.024 microseconds. Transmit interrupt reduction can improve CPU 1458cfa0ad2SJack F Vogel * efficiency if properly tuned for specific network traffic. If the 1468cfa0ad2SJack F Vogel * system is reporting dropped transmits, this value may be set too high 1478cfa0ad2SJack F Vogel * causing the driver to run out of available transmit descriptors. 1488cfa0ad2SJack F Vogel */ 1498cfa0ad2SJack F Vogel #define EM_TIDV 64 1508cfa0ad2SJack F Vogel 1518cfa0ad2SJack F Vogel /* 1528cfa0ad2SJack F Vogel * EM_TADV - Transmit Absolute Interrupt Delay Value 1538cfa0ad2SJack F Vogel * (Not valid for 82542/82543/82544) 1548cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1558cfa0ad2SJack F Vogel * Default Value: 64 1568cfa0ad2SJack F Vogel * This value, in units of 1.024 microseconds, limits the delay in which a 1578cfa0ad2SJack F Vogel * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 1588cfa0ad2SJack F Vogel * this value ensures that an interrupt is generated after the initial 1598cfa0ad2SJack F Vogel * packet is sent on the wire within the set amount of time. Proper tuning, 1608cfa0ad2SJack F Vogel * along with EM_TIDV, may improve traffic throughput in specific 1618cfa0ad2SJack F Vogel * network conditions. 1628cfa0ad2SJack F Vogel */ 1638cfa0ad2SJack F Vogel #define EM_TADV 64 1648cfa0ad2SJack F Vogel 1658cfa0ad2SJack F Vogel /* 1668cfa0ad2SJack F Vogel * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 1678cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1688cfa0ad2SJack F Vogel * Default Value: 0 1698cfa0ad2SJack F Vogel * This value delays the generation of receive interrupts in units of 1.024 1708cfa0ad2SJack F Vogel * microseconds. Receive interrupt reduction can improve CPU efficiency if 1718cfa0ad2SJack F Vogel * properly tuned for specific network traffic. Increasing this value adds 1728cfa0ad2SJack F Vogel * extra latency to frame reception and can end up decreasing the throughput 1738cfa0ad2SJack F Vogel * of TCP traffic. If the system is reporting dropped receives, this value 1748cfa0ad2SJack F Vogel * may be set too high, causing the driver to run out of available receive 1758cfa0ad2SJack F Vogel * descriptors. 1768cfa0ad2SJack F Vogel * 1778cfa0ad2SJack F Vogel * CAUTION: When setting EM_RDTR to a value other than 0, adapters 1788cfa0ad2SJack F Vogel * may hang (stop transmitting) under certain network conditions. 1798cfa0ad2SJack F Vogel * If this occurs a WATCHDOG message is logged in the system 1808cfa0ad2SJack F Vogel * event log. In addition, the controller is automatically reset, 1818cfa0ad2SJack F Vogel * restoring the network connection. To eliminate the potential 1828cfa0ad2SJack F Vogel * for the hang ensure that EM_RDTR is set to 0. 1838cfa0ad2SJack F Vogel */ 1848cfa0ad2SJack F Vogel #define EM_RDTR 0 1858cfa0ad2SJack F Vogel 1868cfa0ad2SJack F Vogel /* 1878cfa0ad2SJack F Vogel * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 1888cfa0ad2SJack F Vogel * Valid Range: 0-65535 (0=off) 1898cfa0ad2SJack F Vogel * Default Value: 64 1908cfa0ad2SJack F Vogel * This value, in units of 1.024 microseconds, limits the delay in which a 1918cfa0ad2SJack F Vogel * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 1928cfa0ad2SJack F Vogel * this value ensures that an interrupt is generated after the initial 1938cfa0ad2SJack F Vogel * packet is received within the set amount of time. Proper tuning, 1948cfa0ad2SJack F Vogel * along with EM_RDTR, may improve traffic throughput in specific network 1958cfa0ad2SJack F Vogel * conditions. 1968cfa0ad2SJack F Vogel */ 1978cfa0ad2SJack F Vogel #define EM_RADV 64 1988cfa0ad2SJack F Vogel 1998cfa0ad2SJack F Vogel /* 200*237a6663SGordon Bergling * This parameter controls whether or not autonegotiation is enabled. 2018cfa0ad2SJack F Vogel * 0 - Disable autonegotiation 2028cfa0ad2SJack F Vogel * 1 - Enable autonegotiation 2038cfa0ad2SJack F Vogel */ 2048cfa0ad2SJack F Vogel #define DO_AUTO_NEG 1 2058cfa0ad2SJack F Vogel 2068cfa0ad2SJack F Vogel /* 2078cfa0ad2SJack F Vogel * This parameter control whether or not the driver will wait for 2088cfa0ad2SJack F Vogel * autonegotiation to complete. 2098cfa0ad2SJack F Vogel * 1 - Wait for autonegotiation to complete 2108cfa0ad2SJack F Vogel * 0 - Don't wait for autonegotiation to complete 2118cfa0ad2SJack F Vogel */ 2128cfa0ad2SJack F Vogel #define WAIT_FOR_AUTO_NEG_DEFAULT 0 2138cfa0ad2SJack F Vogel 2148cfa0ad2SJack F Vogel /* Tunables -- End */ 2158cfa0ad2SJack F Vogel 2168cfa0ad2SJack F Vogel #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 2178cfa0ad2SJack F Vogel ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 2188cfa0ad2SJack F Vogel ADVERTISE_1000_FULL) 2198cfa0ad2SJack F Vogel 2208cfa0ad2SJack F Vogel #define AUTO_ALL_MODES 0 2218cfa0ad2SJack F Vogel 2228cfa0ad2SJack F Vogel /* PHY master/slave setting */ 2238cfa0ad2SJack F Vogel #define EM_MASTER_SLAVE e1000_ms_hw_default 2248cfa0ad2SJack F Vogel 2258cfa0ad2SJack F Vogel /* 226dc926051SKevin Bowling * Miscellaneous constants 2278cfa0ad2SJack F Vogel */ 2288cfa0ad2SJack F Vogel #define EM_VENDOR_ID 0x8086 2298cfa0ad2SJack F Vogel #define EM_FLASH 0x0014 2308cfa0ad2SJack F Vogel 2318cfa0ad2SJack F Vogel #define EM_JUMBO_PBA 0x00000028 2328cfa0ad2SJack F Vogel #define EM_DEFAULT_PBA 0x00000030 2338cfa0ad2SJack F Vogel #define EM_SMARTSPEED_DOWNSHIFT 3 2348cfa0ad2SJack F Vogel #define EM_SMARTSPEED_MAX 15 2358ec87fc5SJack F Vogel #define EM_MAX_LOOP 10 2368cfa0ad2SJack F Vogel 2378cfa0ad2SJack F Vogel #define MAX_NUM_MULTICAST_ADDRESSES 128 2388cfa0ad2SJack F Vogel #define PCI_ANY_ID (~0U) 2398cfa0ad2SJack F Vogel #define ETHER_ALIGN 2 2408cfa0ad2SJack F Vogel #define EM_FC_PAUSE_TIME 0x0680 2418cfa0ad2SJack F Vogel #define EM_EEPROM_APME 0x400; 2424edd8523SJack F Vogel #define EM_82544_APME 0x0004; 2438cfa0ad2SJack F Vogel 244d8c2808fSSean Bruno /* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 245d8c2808fSSean Bruno #define IGB_MEDIA_RESET (1 << 0) 246d8c2808fSSean Bruno 247d8c2808fSSean Bruno /* Define the starting Interrupt rate per Queue */ 248d8c2808fSSean Bruno #define IGB_INTS_PER_SEC 8000 249d8c2808fSSean Bruno #define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 250d8c2808fSSean Bruno 251d8c2808fSSean Bruno #define IGB_LINK_ITR 2000 252d8c2808fSSean Bruno #define I210_LINK_DELAY 1000 253d8c2808fSSean Bruno 254d8c2808fSSean Bruno #define IGB_TXPBSIZE 20408 255d8c2808fSSean Bruno #define IGB_HDR_BUF 128 256d8c2808fSSean Bruno #define IGB_PKTTYPE_MASK 0x0000FFF0 257d8c2808fSSean Bruno #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 258d8c2808fSSean Bruno 259b7a728aaSSean Bruno /* 260b7a728aaSSean Bruno * Driver state logic for the detection of a hung state 261b7a728aaSSean Bruno * in hardware. Set TX_HUNG whenever a TX packet is used 262b7a728aaSSean Bruno * (data is sent) and clear it when txeof() is invoked if 263b7a728aaSSean Bruno * any descriptors from the ring are cleaned/reclaimed. 264b7a728aaSSean Bruno * Increment internal counter if no descriptors are cleaned 265b7a728aaSSean Bruno * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, 266b7a728aaSSean Bruno * reset adapter. 267b7a728aaSSean Bruno */ 268b7a728aaSSean Bruno #define EM_TX_IDLE 0x00000000 269b7a728aaSSean Bruno #define EM_TX_BUSY 0x00000001 270b7a728aaSSean Bruno #define EM_TX_HUNG 0x80000000 271b7a728aaSSean Bruno #define EM_TX_MAXTRIES 10 2727deff7f9SJack F Vogel 273c80429ceSEric Joyner #define PCICFG_DESC_RING_STATUS 0xe4 274c80429ceSEric Joyner #define FLUSH_DESC_REQUIRED 0x100 275c80429ceSEric Joyner 276f2d6ace4SSean Bruno 277f2d6ace4SSean Bruno #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 278f2d6ace4SSean Bruno ((hw->mac.type <= e1000_82576) ? 16 : 8)) 279f2d6ace4SSean Bruno #define IGB_RX_HTHRESH 8 280f2d6ace4SSean Bruno #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 281dc926051SKevin Bowling (sc->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4) 282f2d6ace4SSean Bruno 283f2d6ace4SSean Bruno #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 284f2d6ace4SSean Bruno #define IGB_TX_HTHRESH 1 285f2d6ace4SSean Bruno #define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 286dc926051SKevin Bowling sc->intr_type == IFLIB_INTR_MSIX) ? 1 : 16) 287f2d6ace4SSean Bruno 2888cfa0ad2SJack F Vogel /* 2898cfa0ad2SJack F Vogel * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 2908cfa0ad2SJack F Vogel * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 2918cfa0ad2SJack F Vogel * also optimize cache line size effect. H/W supports up to cache line size 128. 2928cfa0ad2SJack F Vogel */ 2938cfa0ad2SJack F Vogel #define EM_DBA_ALIGN 128 2948cfa0ad2SJack F Vogel 29523c9098bSSean Bruno /* 29623c9098bSSean Bruno * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 29723c9098bSSean Bruno */ 29823c9098bSSean Bruno #define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ 29923c9098bSSean Bruno #define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 30023c9098bSSean Bruno #define TARC_MQ_FIX (1 << 23) | \ 30123c9098bSSean Bruno (1 << 24) | \ 30223c9098bSSean Bruno (1 << 25) /* Handle errata in MQ mode */ 30323c9098bSSean Bruno #define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ 3048cfa0ad2SJack F Vogel 3058cfa0ad2SJack F Vogel /* PCI Config defines */ 3068cfa0ad2SJack F Vogel #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 3078cfa0ad2SJack F Vogel #define EM_BAR_TYPE_MASK 0x00000001 3088cfa0ad2SJack F Vogel #define EM_BAR_TYPE_MMEM 0x00000000 309f2d6ace4SSean Bruno #define EM_BAR_TYPE_IO 0x00000001 3108cfa0ad2SJack F Vogel #define EM_BAR_TYPE_FLASH 0x0014 3118cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 3128cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE_MASK 0x00000006 3138cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE_32BIT 0x00000000 3148cfa0ad2SJack F Vogel #define EM_BAR_MEM_TYPE_64BIT 0x00000004 3158cfa0ad2SJack F Vogel 3168cfa0ad2SJack F Vogel /* Defines for printing debug information */ 3178cfa0ad2SJack F Vogel #define DEBUG_INIT 0 3188cfa0ad2SJack F Vogel #define DEBUG_IOCTL 0 3198cfa0ad2SJack F Vogel #define DEBUG_HW 0 3208cfa0ad2SJack F Vogel 3218cfa0ad2SJack F Vogel #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 3228cfa0ad2SJack F Vogel #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 3238cfa0ad2SJack F Vogel #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 3248cfa0ad2SJack F Vogel #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 3258cfa0ad2SJack F Vogel #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 3268cfa0ad2SJack F Vogel #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 3278cfa0ad2SJack F Vogel #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 3288cfa0ad2SJack F Vogel #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 3298cfa0ad2SJack F Vogel #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 3308cfa0ad2SJack F Vogel 3310a01ff4dSMarius Strobl #define EM_MAX_SCATTER 40 3329d81738fSJack F Vogel #define EM_VFTA_SIZE 128 3337f87c040SMarius Strobl #define EM_TSO_SIZE 65535 3348cfa0ad2SJack F Vogel #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 3358cfa0ad2SJack F Vogel #define ETH_ZLEN 60 3360544676bSStephen Hurd #define EM_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP) /* Offload bits in mbuf flag */ 3370544676bSStephen Hurd #define IGB_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 3380544676bSStephen Hurd CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ 3390544676bSStephen Hurd CSUM_IP6_SCTP) /* Offload bits in mbuf flag */ 3400544676bSStephen Hurd 341f2d6ace4SSean Bruno #define IGB_PKTTYPE_MASK 0x0000FFF0 342f2d6ace4SSean Bruno #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 343f2d6ace4SSean Bruno 3448cfa0ad2SJack F Vogel /* 3458cfa0ad2SJack F Vogel * 82574 has a nonstandard address for EIAC 346b97de13aSMarius Strobl * and since its only used in MSI-X, and in 347b97de13aSMarius Strobl * the em driver only 82574 uses MSI-X we can 3488cfa0ad2SJack F Vogel * solve it just using this define. 3498cfa0ad2SJack F Vogel */ 3508cfa0ad2SJack F Vogel #define EM_EIAC 0x000DC 35123c9098bSSean Bruno /* 35223c9098bSSean Bruno * 82574 only reports 3 MSI-X vectors by default; 35323c9098bSSean Bruno * defines assisting with making it report 5 are 35423c9098bSSean Bruno * located here. 35523c9098bSSean Bruno */ 35623c9098bSSean Bruno #define EM_NVM_PCIE_CTRL 0x1B 35723c9098bSSean Bruno #define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) 35823c9098bSSean Bruno #define EM_NVM_MSIX_N_SHIFT 7 3598cfa0ad2SJack F Vogel 360dc926051SKevin Bowling struct e1000_softc; 3619d81738fSJack F Vogel 3629d81738fSJack F Vogel struct em_int_delay_info { 363dc926051SKevin Bowling struct e1000_softc *sc; /* Back-pointer to the sc struct */ 3649d81738fSJack F Vogel int offset; /* Register offset to read/write */ 3659d81738fSJack F Vogel int value; /* Current value in usecs */ 3669d81738fSJack F Vogel }; 3679d81738fSJack F Vogel 3688ec87fc5SJack F Vogel /* 3698ec87fc5SJack F Vogel * The transmit ring, one per tx queue 3708ec87fc5SJack F Vogel */ 3718ec87fc5SJack F Vogel struct tx_ring { 372dc926051SKevin Bowling struct e1000_softc *sc; 3738ec87fc5SJack F Vogel struct e1000_tx_desc *tx_base; 374f2d6ace4SSean Bruno uint64_t tx_paddr; 37595246abbSSean Bruno qidx_t *tx_rsq; 37695246abbSSean Bruno bool tx_tso; /* last tx was tso */ 37795246abbSSean Bruno uint8_t me; 37895246abbSSean Bruno qidx_t tx_rs_cidx; 37995246abbSSean Bruno qidx_t tx_rs_pidx; 38095246abbSSean Bruno qidx_t tx_cidx_processed; 3818ec87fc5SJack F Vogel /* Interrupt resources */ 3828ec87fc5SJack F Vogel void *tag; 3838ec87fc5SJack F Vogel struct resource *res; 384eaa9db2bSJack F Vogel unsigned long tx_irq; 385f2d6ace4SSean Bruno 386f2d6ace4SSean Bruno /* Saved csum offloading context information */ 387f2d6ace4SSean Bruno int csum_flags; 388f2d6ace4SSean Bruno int csum_lhlen; 389f2d6ace4SSean Bruno int csum_iphlen; 390f2d6ace4SSean Bruno 391f2d6ace4SSean Bruno int csum_thlen; 392f2d6ace4SSean Bruno int csum_mss; 393f2d6ace4SSean Bruno int csum_pktlen; 394f2d6ace4SSean Bruno 395f2d6ace4SSean Bruno uint32_t csum_txd_upper; 396f2d6ace4SSean Bruno uint32_t csum_txd_lower; /* last field */ 3978ec87fc5SJack F Vogel }; 3988ec87fc5SJack F Vogel 3998ec87fc5SJack F Vogel /* 4008ec87fc5SJack F Vogel * The Receive ring, one per rx queue 4018ec87fc5SJack F Vogel */ 4028ec87fc5SJack F Vogel struct rx_ring { 403dc926051SKevin Bowling struct e1000_softc *sc; 404f2d6ace4SSean Bruno struct em_rx_queue *que; 4058ec87fc5SJack F Vogel u32 me; 4068ec87fc5SJack F Vogel u32 payload; 407b834dceaSSean Bruno union e1000_rx_desc_extended *rx_base; 408f2d6ace4SSean Bruno uint64_t rx_paddr; 4098ec87fc5SJack F Vogel 4108ec87fc5SJack F Vogel /* Interrupt resources */ 4118ec87fc5SJack F Vogel void *tag; 4128ec87fc5SJack F Vogel struct resource *res; 413d9f1a5aaSJack F Vogel bool discard; 4148ec87fc5SJack F Vogel 4158ec87fc5SJack F Vogel /* Soft stats */ 416eaa9db2bSJack F Vogel unsigned long rx_irq; 417d9f1a5aaSJack F Vogel unsigned long rx_discarded; 418eaa9db2bSJack F Vogel unsigned long rx_packets; 419eaa9db2bSJack F Vogel unsigned long rx_bytes; 4208ec87fc5SJack F Vogel }; 4218ec87fc5SJack F Vogel 422f2d6ace4SSean Bruno struct em_tx_queue { 423dc926051SKevin Bowling struct e1000_softc *sc; 424f2d6ace4SSean Bruno u32 msix; 425f2d6ace4SSean Bruno u32 eims; /* This queue's EIMS bit */ 426f2d6ace4SSean Bruno u32 me; 427f2d6ace4SSean Bruno struct tx_ring txr; 428f2d6ace4SSean Bruno }; 429f2d6ace4SSean Bruno 430f2d6ace4SSean Bruno struct em_rx_queue { 431dc926051SKevin Bowling struct e1000_softc *sc; 432f2d6ace4SSean Bruno u32 me; 433f2d6ace4SSean Bruno u32 msix; 434f2d6ace4SSean Bruno u32 eims; 435f2d6ace4SSean Bruno struct rx_ring rxr; 436f2d6ace4SSean Bruno u64 irqs; 437f2d6ace4SSean Bruno struct if_irq que_irq; 438f2d6ace4SSean Bruno }; 4398ec87fc5SJack F Vogel 440dc926051SKevin Bowling /* Our softc structure */ 441dc926051SKevin Bowling struct e1000_softc { 4426c8d4b16SJack F Vogel struct e1000_hw hw; 4438cfa0ad2SJack F Vogel 444f2d6ace4SSean Bruno if_softc_ctx_t shared; 445f2d6ace4SSean Bruno if_ctx_t ctx; 446f2d6ace4SSean Bruno #define tx_num_queues shared->isc_ntxqsets 447f2d6ace4SSean Bruno #define rx_num_queues shared->isc_nrxqsets 448f2d6ace4SSean Bruno #define intr_type shared->isc_intr 4496c8d4b16SJack F Vogel /* FreeBSD operating-system-specific structures. */ 4506c8d4b16SJack F Vogel struct e1000_osdep osdep; 4515a9c6582SSean Bruno device_t dev; 45279c7b719SMarius Strobl struct cdev *led_dev; 4538cfa0ad2SJack F Vogel 454f2d6ace4SSean Bruno struct em_tx_queue *tx_queues; 455f2d6ace4SSean Bruno struct em_rx_queue *rx_queues; 456f2d6ace4SSean Bruno struct if_irq irq; 457f2d6ace4SSean Bruno 4586c8d4b16SJack F Vogel struct resource *memory; 4596c8d4b16SJack F Vogel struct resource *flash; 460f2d6ace4SSean Bruno struct resource *ioport; 4616c8d4b16SJack F Vogel 4628ec87fc5SJack F Vogel struct resource *res; 4638ec87fc5SJack F Vogel void *tag; 4648ec87fc5SJack F Vogel u32 linkvec; 4658ec87fc5SJack F Vogel u32 ivars; 4666c8d4b16SJack F Vogel 467f2d6ace4SSean Bruno struct ifmedia *media; 4688ec87fc5SJack F Vogel int msix; 4696c8d4b16SJack F Vogel int if_flags; 4706c8d4b16SJack F Vogel int em_insert_vlan_header; 4718ec87fc5SJack F Vogel u32 ims; 4728ec87fc5SJack F Vogel bool in_detach; 4736c8d4b16SJack F Vogel 474d8c2808fSSean Bruno u32 flags; 4756c8d4b16SJack F Vogel /* Task for FAST handling */ 476f2d6ace4SSean Bruno struct grouptask link_task; 4778ec87fc5SJack F Vogel 4788ec87fc5SJack F Vogel u16 num_vlans; 4798ec87fc5SJack F Vogel u32 txd_cmd; 4808ec87fc5SJack F Vogel 481f2d6ace4SSean Bruno u32 tx_process_limit; 4828ec87fc5SJack F Vogel u32 rx_process_limit; 4837deff7f9SJack F Vogel u32 rx_mbuf_sz; 4846c8d4b16SJack F Vogel 4856c8d4b16SJack F Vogel /* Management and WOL features */ 4866c8d4b16SJack F Vogel u32 wol; 4876c8d4b16SJack F Vogel bool has_manage; 4886c8d4b16SJack F Vogel bool has_amt; 4896c8d4b16SJack F Vogel 490dd20cce1SPyun YongHyeon /* Multicast array memory */ 491dd20cce1SPyun YongHyeon u8 *mta; 492d9f1a5aaSJack F Vogel 4937deff7f9SJack F Vogel /* 4947deff7f9SJack F Vogel ** Shadow VFTA table, this is needed because 4957deff7f9SJack F Vogel ** the real vlan filter table gets cleared during 4967deff7f9SJack F Vogel ** a soft reset and the driver needs to be able 4977deff7f9SJack F Vogel ** to repopulate it. 4987deff7f9SJack F Vogel */ 4997deff7f9SJack F Vogel u32 shadow_vfta[EM_VFTA_SIZE]; 5007deff7f9SJack F Vogel 5017deff7f9SJack F Vogel /* Info about the interface */ 502fd33ce41SJack F Vogel u16 link_active; 503fd33ce41SJack F Vogel u16 fc; 5047deff7f9SJack F Vogel u16 link_speed; 5057deff7f9SJack F Vogel u16 link_duplex; 5067deff7f9SJack F Vogel u32 smartspeed; 507f2d6ace4SSean Bruno u32 dmac; 508f2d6ace4SSean Bruno int link_mask; 509f2d6ace4SSean Bruno 510f2d6ace4SSean Bruno u64 que_mask; 511f2d6ace4SSean Bruno 512293663f4SKevin Bowling /* We need to store this at attach due to e1000 hw/sw locking model */ 513293663f4SKevin Bowling struct e1000_fw_version fw_ver; 514293663f4SKevin Bowling 5156c8d4b16SJack F Vogel struct em_int_delay_info tx_int_delay; 5166c8d4b16SJack F Vogel struct em_int_delay_info tx_abs_int_delay; 5176c8d4b16SJack F Vogel struct em_int_delay_info rx_int_delay; 5186c8d4b16SJack F Vogel struct em_int_delay_info rx_abs_int_delay; 5194dc07530SLuigi Rizzo struct em_int_delay_info tx_itr; 520a69ed8dfSJack F Vogel 5218cfa0ad2SJack F Vogel /* Misc stats maintained by the driver */ 5228cfa0ad2SJack F Vogel unsigned long dropped_pkts; 523e12a9f25SMarius Strobl unsigned long link_irq; 5248cfa0ad2SJack F Vogel unsigned long rx_overruns; 5258ec87fc5SJack F Vogel unsigned long watchdog_events; 5268cfa0ad2SJack F Vogel 5278cfa0ad2SJack F Vogel struct e1000_hw_stats stats; 528d8c2808fSSean Bruno u16 vf_ifp; 5298cfa0ad2SJack F Vogel }; 5308cfa0ad2SJack F Vogel 5318ec87fc5SJack F Vogel /******************************************************************************** 5328cfa0ad2SJack F Vogel * vendor_info_array 5338cfa0ad2SJack F Vogel * 5348cfa0ad2SJack F Vogel * This array contains the list of Subvendor/Subdevice IDs on which the driver 5358cfa0ad2SJack F Vogel * should load. 5368cfa0ad2SJack F Vogel * 5378ec87fc5SJack F Vogel ********************************************************************************/ 5388cfa0ad2SJack F Vogel typedef struct _em_vendor_info_t { 5398cfa0ad2SJack F Vogel unsigned int vendor_id; 5408cfa0ad2SJack F Vogel unsigned int device_id; 5418cfa0ad2SJack F Vogel unsigned int subvendor_id; 5428cfa0ad2SJack F Vogel unsigned int subdevice_id; 5438cfa0ad2SJack F Vogel unsigned int index; 5448cfa0ad2SJack F Vogel } em_vendor_info_t; 5458cfa0ad2SJack F Vogel 546dc926051SKevin Bowling void em_dump_rs(struct e1000_softc *); 547e61e0b91SJack F Vogel 548b834dceaSSean Bruno #define EM_RSSRK_SIZE 4 549b834dceaSSean Bruno #define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \ 550b834dceaSSean Bruno key[(i) * EM_RSSRK_SIZE + 1] << 8 | \ 551b834dceaSSean Bruno key[(i) * EM_RSSRK_SIZE + 2] << 16 | \ 552b834dceaSSean Bruno key[(i) * EM_RSSRK_SIZE + 3] << 24) 5538cfa0ad2SJack F Vogel #endif /* _EM_H_DEFINED_ */ 554