1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) - lem-class legacy devices */ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 98 99 /* Intel(R) - em-class devices */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 197 /* required last entry */ 198 PVID_END 199 }; 200 201 static pci_vendor_info_t igb_vendor_info_array[] = 202 { 203 /* Intel(R) - igb-class devices */ 204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 238 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 239 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 240 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 242 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 244 /* required last entry */ 245 PVID_END 246 }; 247 248 /********************************************************************* 249 * Function prototypes 250 *********************************************************************/ 251 static void *em_register(device_t dev); 252 static void *igb_register(device_t dev); 253 static int em_if_attach_pre(if_ctx_t ctx); 254 static int em_if_attach_post(if_ctx_t ctx); 255 static int em_if_detach(if_ctx_t ctx); 256 static int em_if_shutdown(if_ctx_t ctx); 257 static int em_if_suspend(if_ctx_t ctx); 258 static int em_if_resume(if_ctx_t ctx); 259 260 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 261 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 262 static void em_if_queues_free(if_ctx_t ctx); 263 264 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 265 static void em_if_init(if_ctx_t ctx); 266 static void em_if_stop(if_ctx_t ctx); 267 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 268 static int em_if_media_change(if_ctx_t ctx); 269 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 270 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 271 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 272 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 273 static void em_if_watchdog_reset(if_ctx_t ctx); 274 static bool em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 275 276 static void em_identify_hardware(if_ctx_t ctx); 277 static int em_allocate_pci_resources(if_ctx_t ctx); 278 static void em_free_pci_resources(if_ctx_t ctx); 279 static void em_reset(if_ctx_t ctx); 280 static int em_setup_interface(if_ctx_t ctx); 281 static int em_setup_msix(if_ctx_t ctx); 282 283 static void em_initialize_transmit_unit(if_ctx_t ctx); 284 static void em_initialize_receive_unit(if_ctx_t ctx); 285 286 static void em_if_intr_enable(if_ctx_t ctx); 287 static void em_if_intr_disable(if_ctx_t ctx); 288 static void igb_if_intr_enable(if_ctx_t ctx); 289 static void igb_if_intr_disable(if_ctx_t ctx); 290 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 291 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 292 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 293 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 294 static void em_if_multi_set(if_ctx_t ctx); 295 static void em_if_update_admin_status(if_ctx_t ctx); 296 static void em_if_debug(if_ctx_t ctx); 297 static void em_update_stats_counters(struct adapter *); 298 static void em_add_hw_stats(struct adapter *adapter); 299 static int em_if_set_promisc(if_ctx_t ctx, int flags); 300 static bool em_if_vlan_filter_capable(struct adapter *); 301 static bool em_if_vlan_filter_used(struct adapter *); 302 static void em_if_vlan_filter_enable(struct adapter *); 303 static void em_if_vlan_filter_disable(struct adapter *); 304 static void em_if_vlan_filter_write(struct adapter *); 305 static void em_setup_vlan_hw_support(struct adapter *); 306 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 307 static void em_print_nvm_info(struct adapter *); 308 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 309 static int em_get_rs(SYSCTL_HANDLER_ARGS); 310 static void em_print_debug_info(struct adapter *); 311 static int em_is_valid_ether_addr(u8 *); 312 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 313 static void em_add_int_delay_sysctl(struct adapter *, const char *, 314 const char *, struct em_int_delay_info *, int, int); 315 /* Management and WOL Support */ 316 static void em_init_manageability(struct adapter *); 317 static void em_release_manageability(struct adapter *); 318 static void em_get_hw_control(struct adapter *); 319 static void em_release_hw_control(struct adapter *); 320 static void em_get_wakeup(if_ctx_t ctx); 321 static void em_enable_wakeup(if_ctx_t ctx); 322 static int em_enable_phy_wakeup(struct adapter *); 323 static void em_disable_aspm(struct adapter *); 324 325 int em_intr(void *arg); 326 327 /* MSI-X handlers */ 328 static int em_if_msix_intr_assign(if_ctx_t, int); 329 static int em_msix_link(void *); 330 static void em_handle_link(void *context); 331 332 static void em_enable_vectors_82574(if_ctx_t); 333 334 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 335 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 336 static void em_if_led_func(if_ctx_t ctx, int onoff); 337 338 static int em_get_regs(SYSCTL_HANDLER_ARGS); 339 340 static void lem_smartspeed(struct adapter *adapter); 341 static void igb_configure_queues(struct adapter *adapter); 342 343 344 /********************************************************************* 345 * FreeBSD Device Interface Entry Points 346 *********************************************************************/ 347 static device_method_t em_methods[] = { 348 /* Device interface */ 349 DEVMETHOD(device_register, em_register), 350 DEVMETHOD(device_probe, iflib_device_probe), 351 DEVMETHOD(device_attach, iflib_device_attach), 352 DEVMETHOD(device_detach, iflib_device_detach), 353 DEVMETHOD(device_shutdown, iflib_device_shutdown), 354 DEVMETHOD(device_suspend, iflib_device_suspend), 355 DEVMETHOD(device_resume, iflib_device_resume), 356 DEVMETHOD_END 357 }; 358 359 static device_method_t igb_methods[] = { 360 /* Device interface */ 361 DEVMETHOD(device_register, igb_register), 362 DEVMETHOD(device_probe, iflib_device_probe), 363 DEVMETHOD(device_attach, iflib_device_attach), 364 DEVMETHOD(device_detach, iflib_device_detach), 365 DEVMETHOD(device_shutdown, iflib_device_shutdown), 366 DEVMETHOD(device_suspend, iflib_device_suspend), 367 DEVMETHOD(device_resume, iflib_device_resume), 368 DEVMETHOD_END 369 }; 370 371 372 static driver_t em_driver = { 373 "em", em_methods, sizeof(struct adapter), 374 }; 375 376 static devclass_t em_devclass; 377 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 378 379 MODULE_DEPEND(em, pci, 1, 1, 1); 380 MODULE_DEPEND(em, ether, 1, 1, 1); 381 MODULE_DEPEND(em, iflib, 1, 1, 1); 382 383 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 384 385 static driver_t igb_driver = { 386 "igb", igb_methods, sizeof(struct adapter), 387 }; 388 389 static devclass_t igb_devclass; 390 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 391 392 MODULE_DEPEND(igb, pci, 1, 1, 1); 393 MODULE_DEPEND(igb, ether, 1, 1, 1); 394 MODULE_DEPEND(igb, iflib, 1, 1, 1); 395 396 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 397 398 static device_method_t em_if_methods[] = { 399 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 400 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 401 DEVMETHOD(ifdi_detach, em_if_detach), 402 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 403 DEVMETHOD(ifdi_suspend, em_if_suspend), 404 DEVMETHOD(ifdi_resume, em_if_resume), 405 DEVMETHOD(ifdi_init, em_if_init), 406 DEVMETHOD(ifdi_stop, em_if_stop), 407 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 408 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 409 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 410 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 411 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 412 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 413 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 414 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 415 DEVMETHOD(ifdi_media_status, em_if_media_status), 416 DEVMETHOD(ifdi_media_change, em_if_media_change), 417 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 418 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 419 DEVMETHOD(ifdi_timer, em_if_timer), 420 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 421 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 422 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 423 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 424 DEVMETHOD(ifdi_led_func, em_if_led_func), 425 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 426 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 427 DEVMETHOD(ifdi_debug, em_if_debug), 428 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 429 DEVMETHOD_END 430 }; 431 432 static driver_t em_if_driver = { 433 "em_if", em_if_methods, sizeof(struct adapter) 434 }; 435 436 static device_method_t igb_if_methods[] = { 437 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 438 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 439 DEVMETHOD(ifdi_detach, em_if_detach), 440 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 441 DEVMETHOD(ifdi_suspend, em_if_suspend), 442 DEVMETHOD(ifdi_resume, em_if_resume), 443 DEVMETHOD(ifdi_init, em_if_init), 444 DEVMETHOD(ifdi_stop, em_if_stop), 445 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 446 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 447 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 448 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 449 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 450 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 451 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 452 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 453 DEVMETHOD(ifdi_media_status, em_if_media_status), 454 DEVMETHOD(ifdi_media_change, em_if_media_change), 455 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 456 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 457 DEVMETHOD(ifdi_timer, em_if_timer), 458 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 459 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 460 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 461 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 462 DEVMETHOD(ifdi_led_func, em_if_led_func), 463 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 464 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 465 DEVMETHOD(ifdi_debug, em_if_debug), 466 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 467 DEVMETHOD_END 468 }; 469 470 static driver_t igb_if_driver = { 471 "igb_if", igb_if_methods, sizeof(struct adapter) 472 }; 473 474 /********************************************************************* 475 * Tunable default values. 476 *********************************************************************/ 477 478 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 479 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 480 481 #define MAX_INTS_PER_SEC 8000 482 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 483 484 /* Allow common code without TSO */ 485 #ifndef CSUM_TSO 486 #define CSUM_TSO 0 487 #endif 488 489 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 490 "EM driver parameters"); 491 492 static int em_disable_crc_stripping = 0; 493 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 494 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 495 496 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 497 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 498 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 499 0, "Default transmit interrupt delay in usecs"); 500 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 501 0, "Default receive interrupt delay in usecs"); 502 503 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 504 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 505 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 506 &em_tx_abs_int_delay_dflt, 0, 507 "Default transmit interrupt delay limit in usecs"); 508 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 509 &em_rx_abs_int_delay_dflt, 0, 510 "Default receive interrupt delay limit in usecs"); 511 512 static int em_smart_pwr_down = FALSE; 513 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 514 0, "Set to true to leave smart power down enabled on newer adapters"); 515 516 /* Controls whether promiscuous also shows bad packets */ 517 static int em_debug_sbp = FALSE; 518 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 519 "Show bad packets in promiscuous mode"); 520 521 /* How many packets rxeof tries to clean at a time */ 522 static int em_rx_process_limit = 100; 523 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 524 &em_rx_process_limit, 0, 525 "Maximum number of received packets to process " 526 "at a time, -1 means unlimited"); 527 528 /* Energy efficient ethernet - default to OFF */ 529 static int eee_setting = 1; 530 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 531 "Enable Energy Efficient Ethernet"); 532 533 /* 534 ** Tuneable Interrupt rate 535 */ 536 static int em_max_interrupt_rate = 8000; 537 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 538 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 539 540 541 542 /* Global used in WOL setup with multiport cards */ 543 static int global_quad_port_a = 0; 544 545 extern struct if_txrx igb_txrx; 546 extern struct if_txrx em_txrx; 547 extern struct if_txrx lem_txrx; 548 549 static struct if_shared_ctx em_sctx_init = { 550 .isc_magic = IFLIB_MAGIC, 551 .isc_q_align = PAGE_SIZE, 552 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 553 .isc_tx_maxsegsize = PAGE_SIZE, 554 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 555 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 556 .isc_rx_maxsize = MJUM9BYTES, 557 .isc_rx_nsegments = 1, 558 .isc_rx_maxsegsize = MJUM9BYTES, 559 .isc_nfl = 1, 560 .isc_nrxqs = 1, 561 .isc_ntxqs = 1, 562 .isc_admin_intrcnt = 1, 563 .isc_vendor_info = em_vendor_info_array, 564 .isc_driver_version = em_driver_version, 565 .isc_driver = &em_if_driver, 566 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 567 568 .isc_nrxd_min = {EM_MIN_RXD}, 569 .isc_ntxd_min = {EM_MIN_TXD}, 570 .isc_nrxd_max = {EM_MAX_RXD}, 571 .isc_ntxd_max = {EM_MAX_TXD}, 572 .isc_nrxd_default = {EM_DEFAULT_RXD}, 573 .isc_ntxd_default = {EM_DEFAULT_TXD}, 574 }; 575 576 static struct if_shared_ctx igb_sctx_init = { 577 .isc_magic = IFLIB_MAGIC, 578 .isc_q_align = PAGE_SIZE, 579 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 580 .isc_tx_maxsegsize = PAGE_SIZE, 581 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 582 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 583 .isc_rx_maxsize = MJUM9BYTES, 584 .isc_rx_nsegments = 1, 585 .isc_rx_maxsegsize = MJUM9BYTES, 586 .isc_nfl = 1, 587 .isc_nrxqs = 1, 588 .isc_ntxqs = 1, 589 .isc_admin_intrcnt = 1, 590 .isc_vendor_info = igb_vendor_info_array, 591 .isc_driver_version = em_driver_version, 592 .isc_driver = &igb_if_driver, 593 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 594 595 .isc_nrxd_min = {EM_MIN_RXD}, 596 .isc_ntxd_min = {EM_MIN_TXD}, 597 .isc_nrxd_max = {IGB_MAX_RXD}, 598 .isc_ntxd_max = {IGB_MAX_TXD}, 599 .isc_nrxd_default = {EM_DEFAULT_RXD}, 600 .isc_ntxd_default = {EM_DEFAULT_TXD}, 601 }; 602 603 /***************************************************************** 604 * 605 * Dump Registers 606 * 607 ****************************************************************/ 608 #define IGB_REGS_LEN 739 609 610 static int em_get_regs(SYSCTL_HANDLER_ARGS) 611 { 612 struct adapter *adapter = (struct adapter *)arg1; 613 struct e1000_hw *hw = &adapter->hw; 614 struct sbuf *sb; 615 u32 *regs_buff; 616 int rc; 617 618 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 619 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 620 621 rc = sysctl_wire_old_buffer(req, 0); 622 MPASS(rc == 0); 623 if (rc != 0) { 624 free(regs_buff, M_DEVBUF); 625 return (rc); 626 } 627 628 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 629 MPASS(sb != NULL); 630 if (sb == NULL) { 631 free(regs_buff, M_DEVBUF); 632 return (ENOMEM); 633 } 634 635 /* General Registers */ 636 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 637 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 638 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 639 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 640 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 641 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 642 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 643 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 644 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 645 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 646 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 647 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 648 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 649 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 650 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 651 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 652 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 653 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 654 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 655 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 656 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 657 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 658 659 sbuf_printf(sb, "General Registers\n"); 660 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 661 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 662 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 663 664 sbuf_printf(sb, "Interrupt Registers\n"); 665 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 666 667 sbuf_printf(sb, "RX Registers\n"); 668 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 669 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 670 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 671 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 672 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 673 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 674 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 675 676 sbuf_printf(sb, "TX Registers\n"); 677 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 678 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 679 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 680 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 681 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 682 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 683 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 684 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 685 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 686 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 687 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 688 689 free(regs_buff, M_DEVBUF); 690 691 #ifdef DUMP_DESCS 692 { 693 if_softc_ctx_t scctx = adapter->shared; 694 struct rx_ring *rxr = &rx_que->rxr; 695 struct tx_ring *txr = &tx_que->txr; 696 int ntxd = scctx->isc_ntxd[0]; 697 int nrxd = scctx->isc_nrxd[0]; 698 int j; 699 700 for (j = 0; j < nrxd; j++) { 701 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 702 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 703 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 704 } 705 706 for (j = 0; j < min(ntxd, 256); j++) { 707 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 708 709 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 710 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 711 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 712 713 } 714 } 715 #endif 716 717 rc = sbuf_finish(sb); 718 sbuf_delete(sb); 719 return(rc); 720 } 721 722 static void * 723 em_register(device_t dev) 724 { 725 return (&em_sctx_init); 726 } 727 728 static void * 729 igb_register(device_t dev) 730 { 731 return (&igb_sctx_init); 732 } 733 734 static int 735 em_set_num_queues(if_ctx_t ctx) 736 { 737 struct adapter *adapter = iflib_get_softc(ctx); 738 int maxqueues; 739 740 /* Sanity check based on HW */ 741 switch (adapter->hw.mac.type) { 742 case e1000_82576: 743 case e1000_82580: 744 case e1000_i350: 745 case e1000_i354: 746 maxqueues = 8; 747 break; 748 case e1000_i210: 749 case e1000_82575: 750 maxqueues = 4; 751 break; 752 case e1000_i211: 753 case e1000_82574: 754 maxqueues = 2; 755 break; 756 default: 757 maxqueues = 1; 758 break; 759 } 760 761 return (maxqueues); 762 } 763 764 #define LEM_CAPS \ 765 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 766 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 767 768 #define EM_CAPS \ 769 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 770 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 771 IFCAP_LRO | IFCAP_VLAN_HWTSO 772 773 #define IGB_CAPS \ 774 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 775 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 776 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 777 IFCAP_TSO6 778 779 /********************************************************************* 780 * Device initialization routine 781 * 782 * The attach entry point is called when the driver is being loaded. 783 * This routine identifies the type of hardware, allocates all resources 784 * and initializes the hardware. 785 * 786 * return 0 on success, positive on failure 787 *********************************************************************/ 788 static int 789 em_if_attach_pre(if_ctx_t ctx) 790 { 791 struct adapter *adapter; 792 if_softc_ctx_t scctx; 793 device_t dev; 794 struct e1000_hw *hw; 795 int error = 0; 796 797 INIT_DEBUGOUT("em_if_attach_pre: begin"); 798 dev = iflib_get_dev(ctx); 799 adapter = iflib_get_softc(ctx); 800 801 adapter->ctx = adapter->osdep.ctx = ctx; 802 adapter->dev = adapter->osdep.dev = dev; 803 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 804 adapter->media = iflib_get_media(ctx); 805 hw = &adapter->hw; 806 807 adapter->tx_process_limit = scctx->isc_ntxd[0]; 808 809 /* SYSCTL stuff */ 810 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 811 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 812 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 813 adapter, 0, em_sysctl_nvm_info, "I", "NVM Information"); 814 815 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 817 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 818 adapter, 0, em_sysctl_debug_info, "I", "Debug Information"); 819 820 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 821 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 822 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 823 adapter, 0, em_set_flowcntl, "I", "Flow Control"); 824 825 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 826 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 827 OID_AUTO, "reg_dump", 828 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 829 em_get_regs, "A", "Dump Registers"); 830 831 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 832 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 833 OID_AUTO, "rs_dump", 834 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 835 em_get_rs, "I", "Dump RS indexes"); 836 837 /* Determine hardware and mac info */ 838 em_identify_hardware(ctx); 839 840 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 841 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 842 if (bootverbose) 843 device_printf(dev, "attach_pre capping queues at %d\n", 844 scctx->isc_ntxqsets_max); 845 846 if (hw->mac.type >= igb_mac_min) { 847 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 848 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 849 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 850 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 851 scctx->isc_txrx = &igb_txrx; 852 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 853 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 854 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 855 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 856 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 857 CSUM_IP6_TCP | CSUM_IP6_UDP; 858 if (hw->mac.type != e1000_82575) 859 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 860 /* 861 ** Some new devices, as with ixgbe, now may 862 ** use a different BAR, so we need to keep 863 ** track of which is used. 864 */ 865 scctx->isc_msix_bar = pci_msix_table_bar(dev); 866 } else if (hw->mac.type >= em_mac_min) { 867 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 868 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 869 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 870 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 871 scctx->isc_txrx = &em_txrx; 872 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 873 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 874 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 875 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 876 /* 877 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 878 * by default as we don't have workarounds for all associated 879 * silicon errata. E. g., with several MACs such as 82573E, 880 * TSO only works at Gigabit speed and otherwise can cause the 881 * hardware to hang (which also would be next to impossible to 882 * work around given that already queued TSO-using descriptors 883 * would need to be flushed and vlan(4) reconfigured at runtime 884 * in case of a link speed change). Moreover, MACs like 82579 885 * still can hang at Gigabit even with all publicly documented 886 * TSO workarounds implemented. Generally, the penality of 887 * these workarounds is rather high and may involve copying 888 * mbuf data around so advantages of TSO lapse. Still, TSO may 889 * work for a few MACs of this class - at least when sticking 890 * with Gigabit - in which case users may enable TSO manually. 891 */ 892 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 893 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 894 /* 895 * We support MSI-X with 82574 only, but indicate to iflib(4) 896 * that it shall give MSI at least a try with other devices. 897 */ 898 if (hw->mac.type == e1000_82574) { 899 scctx->isc_msix_bar = pci_msix_table_bar(dev);; 900 } else { 901 scctx->isc_msix_bar = -1; 902 scctx->isc_disable_msix = 1; 903 } 904 } else { 905 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 906 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 907 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 908 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 909 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 910 scctx->isc_txrx = &lem_txrx; 911 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 912 if (hw->mac.type < e1000_82543) 913 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 914 /* 82541ER doesn't do HW tagging */ 915 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 916 scctx->isc_capenable &= ~IFCAP_VLAN_HWTAGGING; 917 /* INTx only */ 918 scctx->isc_msix_bar = 0; 919 } 920 921 /* Setup PCI resources */ 922 if (em_allocate_pci_resources(ctx)) { 923 device_printf(dev, "Allocation of PCI resources failed\n"); 924 error = ENXIO; 925 goto err_pci; 926 } 927 928 /* 929 ** For ICH8 and family we need to 930 ** map the flash memory, and this 931 ** must happen after the MAC is 932 ** identified 933 */ 934 if ((hw->mac.type == e1000_ich8lan) || 935 (hw->mac.type == e1000_ich9lan) || 936 (hw->mac.type == e1000_ich10lan) || 937 (hw->mac.type == e1000_pchlan) || 938 (hw->mac.type == e1000_pch2lan) || 939 (hw->mac.type == e1000_pch_lpt)) { 940 int rid = EM_BAR_TYPE_FLASH; 941 adapter->flash = bus_alloc_resource_any(dev, 942 SYS_RES_MEMORY, &rid, RF_ACTIVE); 943 if (adapter->flash == NULL) { 944 device_printf(dev, "Mapping of Flash failed\n"); 945 error = ENXIO; 946 goto err_pci; 947 } 948 /* This is used in the shared code */ 949 hw->flash_address = (u8 *)adapter->flash; 950 adapter->osdep.flash_bus_space_tag = 951 rman_get_bustag(adapter->flash); 952 adapter->osdep.flash_bus_space_handle = 953 rman_get_bushandle(adapter->flash); 954 } 955 /* 956 ** In the new SPT device flash is not a 957 ** separate BAR, rather it is also in BAR0, 958 ** so use the same tag and an offset handle for the 959 ** FLASH read/write macros in the shared code. 960 */ 961 else if (hw->mac.type >= e1000_pch_spt) { 962 adapter->osdep.flash_bus_space_tag = 963 adapter->osdep.mem_bus_space_tag; 964 adapter->osdep.flash_bus_space_handle = 965 adapter->osdep.mem_bus_space_handle 966 + E1000_FLASH_BASE_ADDR; 967 } 968 969 /* Do Shared Code initialization */ 970 error = e1000_setup_init_funcs(hw, TRUE); 971 if (error) { 972 device_printf(dev, "Setup of Shared code failed, error %d\n", 973 error); 974 error = ENXIO; 975 goto err_pci; 976 } 977 978 em_setup_msix(ctx); 979 e1000_get_bus_info(hw); 980 981 /* Set up some sysctls for the tunable interrupt delays */ 982 em_add_int_delay_sysctl(adapter, "rx_int_delay", 983 "receive interrupt delay in usecs", &adapter->rx_int_delay, 984 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 985 em_add_int_delay_sysctl(adapter, "tx_int_delay", 986 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 987 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 988 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 989 "receive interrupt delay limit in usecs", 990 &adapter->rx_abs_int_delay, 991 E1000_REGISTER(hw, E1000_RADV), 992 em_rx_abs_int_delay_dflt); 993 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 994 "transmit interrupt delay limit in usecs", 995 &adapter->tx_abs_int_delay, 996 E1000_REGISTER(hw, E1000_TADV), 997 em_tx_abs_int_delay_dflt); 998 em_add_int_delay_sysctl(adapter, "itr", 999 "interrupt delay limit in usecs/4", 1000 &adapter->tx_itr, 1001 E1000_REGISTER(hw, E1000_ITR), 1002 DEFAULT_ITR); 1003 1004 hw->mac.autoneg = DO_AUTO_NEG; 1005 hw->phy.autoneg_wait_to_complete = FALSE; 1006 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1007 1008 if (hw->mac.type < em_mac_min) { 1009 e1000_init_script_state_82541(hw, TRUE); 1010 e1000_set_tbi_compatibility_82543(hw, TRUE); 1011 } 1012 /* Copper options */ 1013 if (hw->phy.media_type == e1000_media_type_copper) { 1014 hw->phy.mdix = AUTO_ALL_MODES; 1015 hw->phy.disable_polarity_correction = FALSE; 1016 hw->phy.ms_type = EM_MASTER_SLAVE; 1017 } 1018 1019 /* 1020 * Set the frame limits assuming 1021 * standard ethernet sized frames. 1022 */ 1023 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1024 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1025 1026 /* 1027 * This controls when hardware reports transmit completion 1028 * status. 1029 */ 1030 hw->mac.report_tx_early = 1; 1031 1032 /* Allocate multicast array memory. */ 1033 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1034 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1035 if (adapter->mta == NULL) { 1036 device_printf(dev, "Can not allocate multicast setup array\n"); 1037 error = ENOMEM; 1038 goto err_late; 1039 } 1040 1041 /* Check SOL/IDER usage */ 1042 if (e1000_check_reset_block(hw)) 1043 device_printf(dev, "PHY reset is blocked" 1044 " due to SOL/IDER session.\n"); 1045 1046 /* Sysctl for setting Energy Efficient Ethernet */ 1047 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1048 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1049 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1050 OID_AUTO, "eee_control", 1051 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1052 adapter, 0, em_sysctl_eee, "I", 1053 "Disable Energy Efficient Ethernet"); 1054 1055 /* 1056 ** Start from a known state, this is 1057 ** important in reading the nvm and 1058 ** mac from that. 1059 */ 1060 e1000_reset_hw(hw); 1061 1062 /* Make sure we have a good EEPROM before we read from it */ 1063 if (e1000_validate_nvm_checksum(hw) < 0) { 1064 /* 1065 ** Some PCI-E parts fail the first check due to 1066 ** the link being in sleep state, call it again, 1067 ** if it fails a second time its a real issue. 1068 */ 1069 if (e1000_validate_nvm_checksum(hw) < 0) { 1070 device_printf(dev, 1071 "The EEPROM Checksum Is Not Valid\n"); 1072 error = EIO; 1073 goto err_late; 1074 } 1075 } 1076 1077 /* Copy the permanent MAC address out of the EEPROM */ 1078 if (e1000_read_mac_addr(hw) < 0) { 1079 device_printf(dev, "EEPROM read error while reading MAC" 1080 " address\n"); 1081 error = EIO; 1082 goto err_late; 1083 } 1084 1085 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1086 if (adapter->vf_ifp) { 1087 ether_gen_addr(iflib_get_ifp(ctx), 1088 (struct ether_addr *)hw->mac.addr); 1089 } else { 1090 device_printf(dev, "Invalid MAC address\n"); 1091 error = EIO; 1092 goto err_late; 1093 } 1094 } 1095 1096 /* 1097 * Get Wake-on-Lan and Management info for later use 1098 */ 1099 em_get_wakeup(ctx); 1100 1101 /* Enable only WOL MAGIC by default */ 1102 scctx->isc_capenable &= ~IFCAP_WOL; 1103 if (adapter->wol != 0) 1104 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1105 1106 iflib_set_mac(ctx, hw->mac.addr); 1107 1108 return (0); 1109 1110 err_late: 1111 em_release_hw_control(adapter); 1112 err_pci: 1113 em_free_pci_resources(ctx); 1114 free(adapter->mta, M_DEVBUF); 1115 1116 return (error); 1117 } 1118 1119 static int 1120 em_if_attach_post(if_ctx_t ctx) 1121 { 1122 struct adapter *adapter = iflib_get_softc(ctx); 1123 struct e1000_hw *hw = &adapter->hw; 1124 int error = 0; 1125 1126 /* Setup OS specific network interface */ 1127 error = em_setup_interface(ctx); 1128 if (error != 0) { 1129 device_printf(adapter->dev, "Interface setup failed: %d\n", error); 1130 goto err_late; 1131 } 1132 1133 em_reset(ctx); 1134 1135 /* Initialize statistics */ 1136 em_update_stats_counters(adapter); 1137 hw->mac.get_link_status = 1; 1138 em_if_update_admin_status(ctx); 1139 em_add_hw_stats(adapter); 1140 1141 /* Non-AMT based hardware can now take control from firmware */ 1142 if (adapter->has_manage && !adapter->has_amt) 1143 em_get_hw_control(adapter); 1144 1145 INIT_DEBUGOUT("em_if_attach_post: end"); 1146 1147 return (0); 1148 1149 err_late: 1150 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1151 return (error); 1152 } 1153 1154 /********************************************************************* 1155 * Device removal routine 1156 * 1157 * The detach entry point is called when the driver is being removed. 1158 * This routine stops the adapter and deallocates all the resources 1159 * that were allocated for driver operation. 1160 * 1161 * return 0 on success, positive on failure 1162 *********************************************************************/ 1163 static int 1164 em_if_detach(if_ctx_t ctx) 1165 { 1166 struct adapter *adapter = iflib_get_softc(ctx); 1167 1168 INIT_DEBUGOUT("em_if_detach: begin"); 1169 1170 e1000_phy_hw_reset(&adapter->hw); 1171 1172 em_release_manageability(adapter); 1173 em_release_hw_control(adapter); 1174 em_free_pci_resources(ctx); 1175 free(adapter->mta, M_DEVBUF); 1176 adapter->mta = NULL; 1177 1178 return (0); 1179 } 1180 1181 /********************************************************************* 1182 * 1183 * Shutdown entry point 1184 * 1185 **********************************************************************/ 1186 1187 static int 1188 em_if_shutdown(if_ctx_t ctx) 1189 { 1190 return em_if_suspend(ctx); 1191 } 1192 1193 /* 1194 * Suspend/resume device methods. 1195 */ 1196 static int 1197 em_if_suspend(if_ctx_t ctx) 1198 { 1199 struct adapter *adapter = iflib_get_softc(ctx); 1200 1201 em_release_manageability(adapter); 1202 em_release_hw_control(adapter); 1203 em_enable_wakeup(ctx); 1204 return (0); 1205 } 1206 1207 static int 1208 em_if_resume(if_ctx_t ctx) 1209 { 1210 struct adapter *adapter = iflib_get_softc(ctx); 1211 1212 if (adapter->hw.mac.type == e1000_pch2lan) 1213 e1000_resume_workarounds_pchlan(&adapter->hw); 1214 em_if_init(ctx); 1215 em_init_manageability(adapter); 1216 1217 return(0); 1218 } 1219 1220 static int 1221 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1222 { 1223 int max_frame_size; 1224 struct adapter *adapter = iflib_get_softc(ctx); 1225 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1226 1227 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1228 1229 switch (adapter->hw.mac.type) { 1230 case e1000_82571: 1231 case e1000_82572: 1232 case e1000_ich9lan: 1233 case e1000_ich10lan: 1234 case e1000_pch2lan: 1235 case e1000_pch_lpt: 1236 case e1000_pch_spt: 1237 case e1000_pch_cnp: 1238 case e1000_pch_tgp: 1239 case e1000_pch_adp: 1240 case e1000_pch_mtp: 1241 case e1000_82574: 1242 case e1000_82583: 1243 case e1000_80003es2lan: 1244 /* 9K Jumbo Frame size */ 1245 max_frame_size = 9234; 1246 break; 1247 case e1000_pchlan: 1248 max_frame_size = 4096; 1249 break; 1250 case e1000_82542: 1251 case e1000_ich8lan: 1252 /* Adapters that do not support jumbo frames */ 1253 max_frame_size = ETHER_MAX_LEN; 1254 break; 1255 default: 1256 if (adapter->hw.mac.type >= igb_mac_min) 1257 max_frame_size = 9234; 1258 else /* lem */ 1259 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1260 } 1261 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1262 return (EINVAL); 1263 } 1264 1265 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1266 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1267 return (0); 1268 } 1269 1270 /********************************************************************* 1271 * Init entry point 1272 * 1273 * This routine is used in two ways. It is used by the stack as 1274 * init entry point in network interface structure. It is also used 1275 * by the driver as a hw/sw initialization routine to get to a 1276 * consistent state. 1277 * 1278 **********************************************************************/ 1279 static void 1280 em_if_init(if_ctx_t ctx) 1281 { 1282 struct adapter *adapter = iflib_get_softc(ctx); 1283 if_softc_ctx_t scctx = adapter->shared; 1284 struct ifnet *ifp = iflib_get_ifp(ctx); 1285 struct em_tx_queue *tx_que; 1286 int i; 1287 1288 INIT_DEBUGOUT("em_if_init: begin"); 1289 1290 /* Get the latest mac address, User can use a LAA */ 1291 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1292 ETHER_ADDR_LEN); 1293 1294 /* Put the address into the Receive Address Array */ 1295 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1296 1297 /* 1298 * With the 82571 adapter, RAR[0] may be overwritten 1299 * when the other port is reset, we make a duplicate 1300 * in RAR[14] for that eventuality, this assures 1301 * the interface continues to function. 1302 */ 1303 if (adapter->hw.mac.type == e1000_82571) { 1304 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1305 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1306 E1000_RAR_ENTRIES - 1); 1307 } 1308 1309 1310 /* Initialize the hardware */ 1311 em_reset(ctx); 1312 em_if_update_admin_status(ctx); 1313 1314 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1315 struct tx_ring *txr = &tx_que->txr; 1316 1317 txr->tx_rs_cidx = txr->tx_rs_pidx; 1318 1319 /* Initialize the last processed descriptor to be the end of 1320 * the ring, rather than the start, so that we avoid an 1321 * off-by-one error when calculating how many descriptors are 1322 * done in the credits_update function. 1323 */ 1324 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1325 } 1326 1327 /* Setup VLAN support, basic and offload if available */ 1328 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1329 1330 /* Clear bad data from Rx FIFOs */ 1331 if (adapter->hw.mac.type >= igb_mac_min) 1332 e1000_rx_fifo_flush_82575(&adapter->hw); 1333 1334 /* Configure for OS presence */ 1335 em_init_manageability(adapter); 1336 1337 /* Prepare transmit descriptors and buffers */ 1338 em_initialize_transmit_unit(ctx); 1339 1340 /* Setup Multicast table */ 1341 em_if_multi_set(ctx); 1342 1343 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1344 em_initialize_receive_unit(ctx); 1345 1346 /* Set up VLAN support and filter */ 1347 em_setup_vlan_hw_support(adapter); 1348 1349 /* Don't lose promiscuous settings */ 1350 em_if_set_promisc(ctx, if_getflags(ifp)); 1351 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1352 1353 /* MSI-X configuration for 82574 */ 1354 if (adapter->hw.mac.type == e1000_82574) { 1355 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1356 1357 tmp |= E1000_CTRL_EXT_PBA_CLR; 1358 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1359 /* Set the IVAR - interrupt vector routing. */ 1360 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1361 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1362 igb_configure_queues(adapter); 1363 1364 /* this clears any pending interrupts */ 1365 E1000_READ_REG(&adapter->hw, E1000_ICR); 1366 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1367 1368 /* AMT based hardware can now take control from firmware */ 1369 if (adapter->has_manage && adapter->has_amt) 1370 em_get_hw_control(adapter); 1371 1372 /* Set Energy Efficient Ethernet */ 1373 if (adapter->hw.mac.type >= igb_mac_min && 1374 adapter->hw.phy.media_type == e1000_media_type_copper) { 1375 if (adapter->hw.mac.type == e1000_i354) 1376 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1377 else 1378 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1379 } 1380 } 1381 1382 /********************************************************************* 1383 * 1384 * Fast Legacy/MSI Combined Interrupt Service routine 1385 * 1386 *********************************************************************/ 1387 int 1388 em_intr(void *arg) 1389 { 1390 struct adapter *adapter = arg; 1391 if_ctx_t ctx = adapter->ctx; 1392 u32 reg_icr; 1393 1394 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1395 1396 /* Hot eject? */ 1397 if (reg_icr == 0xffffffff) 1398 return FILTER_STRAY; 1399 1400 /* Definitely not our interrupt. */ 1401 if (reg_icr == 0x0) 1402 return FILTER_STRAY; 1403 1404 /* 1405 * Starting with the 82571 chip, bit 31 should be used to 1406 * determine whether the interrupt belongs to us. 1407 */ 1408 if (adapter->hw.mac.type >= e1000_82571 && 1409 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1410 return FILTER_STRAY; 1411 1412 /* 1413 * Only MSI-X interrupts have one-shot behavior by taking advantage 1414 * of the EIAC register. Thus, explicitly disable interrupts. This 1415 * also works around the MSI message reordering errata on certain 1416 * systems. 1417 */ 1418 IFDI_INTR_DISABLE(ctx); 1419 1420 /* Link status change */ 1421 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1422 em_handle_link(ctx); 1423 1424 if (reg_icr & E1000_ICR_RXO) 1425 adapter->rx_overruns++; 1426 1427 return (FILTER_SCHEDULE_THREAD); 1428 } 1429 1430 static int 1431 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1432 { 1433 struct adapter *adapter = iflib_get_softc(ctx); 1434 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1435 1436 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1437 return (0); 1438 } 1439 1440 static int 1441 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1442 { 1443 struct adapter *adapter = iflib_get_softc(ctx); 1444 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1445 1446 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1447 return (0); 1448 } 1449 1450 static int 1451 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1452 { 1453 struct adapter *adapter = iflib_get_softc(ctx); 1454 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1455 1456 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1457 return (0); 1458 } 1459 1460 static int 1461 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1462 { 1463 struct adapter *adapter = iflib_get_softc(ctx); 1464 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1465 1466 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1467 return (0); 1468 } 1469 1470 /********************************************************************* 1471 * 1472 * MSI-X RX Interrupt Service routine 1473 * 1474 **********************************************************************/ 1475 static int 1476 em_msix_que(void *arg) 1477 { 1478 struct em_rx_queue *que = arg; 1479 1480 ++que->irqs; 1481 1482 return (FILTER_SCHEDULE_THREAD); 1483 } 1484 1485 /********************************************************************* 1486 * 1487 * MSI-X Link Fast Interrupt Service routine 1488 * 1489 **********************************************************************/ 1490 static int 1491 em_msix_link(void *arg) 1492 { 1493 struct adapter *adapter = arg; 1494 u32 reg_icr; 1495 bool notlink = false; 1496 1497 ++adapter->link_irq; 1498 MPASS(adapter->hw.back != NULL); 1499 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1500 1501 if (reg_icr & E1000_ICR_RXO) 1502 adapter->rx_overruns++; 1503 1504 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1505 em_handle_link(adapter->ctx); 1506 else 1507 notlink = true; 1508 1509 /* Re-arm for other/spurious interrupts */ 1510 if (notlink && adapter->hw.mac.type >= igb_mac_min) { 1511 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1512 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1513 } else if (adapter->hw.mac.type == e1000_82574) { 1514 if (notlink) 1515 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC | 1516 E1000_IMS_OTHER); 1517 /* 1518 * Because we must read the ICR for this interrupt it may 1519 * clear other causes using autoclear, for this reason we 1520 * simply create a soft interrupt for all these vectors. 1521 */ 1522 if (reg_icr) 1523 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims); 1524 } 1525 1526 return (FILTER_HANDLED); 1527 } 1528 1529 static void 1530 em_handle_link(void *context) 1531 { 1532 if_ctx_t ctx = context; 1533 struct adapter *adapter = iflib_get_softc(ctx); 1534 1535 adapter->hw.mac.get_link_status = 1; 1536 iflib_admin_intr_deferred(ctx); 1537 } 1538 1539 /********************************************************************* 1540 * 1541 * Media Ioctl callback 1542 * 1543 * This routine is called whenever the user queries the status of 1544 * the interface using ifconfig. 1545 * 1546 **********************************************************************/ 1547 static void 1548 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1549 { 1550 struct adapter *adapter = iflib_get_softc(ctx); 1551 u_char fiber_type = IFM_1000_SX; 1552 1553 INIT_DEBUGOUT("em_if_media_status: begin"); 1554 1555 iflib_admin_intr_deferred(ctx); 1556 1557 ifmr->ifm_status = IFM_AVALID; 1558 ifmr->ifm_active = IFM_ETHER; 1559 1560 if (!adapter->link_active) { 1561 return; 1562 } 1563 1564 ifmr->ifm_status |= IFM_ACTIVE; 1565 1566 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1567 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1568 if (adapter->hw.mac.type == e1000_82545) 1569 fiber_type = IFM_1000_LX; 1570 ifmr->ifm_active |= fiber_type | IFM_FDX; 1571 } else { 1572 switch (adapter->link_speed) { 1573 case 10: 1574 ifmr->ifm_active |= IFM_10_T; 1575 break; 1576 case 100: 1577 ifmr->ifm_active |= IFM_100_TX; 1578 break; 1579 case 1000: 1580 ifmr->ifm_active |= IFM_1000_T; 1581 break; 1582 } 1583 if (adapter->link_duplex == FULL_DUPLEX) 1584 ifmr->ifm_active |= IFM_FDX; 1585 else 1586 ifmr->ifm_active |= IFM_HDX; 1587 } 1588 } 1589 1590 /********************************************************************* 1591 * 1592 * Media Ioctl callback 1593 * 1594 * This routine is called when the user changes speed/duplex using 1595 * media/mediopt option with ifconfig. 1596 * 1597 **********************************************************************/ 1598 static int 1599 em_if_media_change(if_ctx_t ctx) 1600 { 1601 struct adapter *adapter = iflib_get_softc(ctx); 1602 struct ifmedia *ifm = iflib_get_media(ctx); 1603 1604 INIT_DEBUGOUT("em_if_media_change: begin"); 1605 1606 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1607 return (EINVAL); 1608 1609 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1610 case IFM_AUTO: 1611 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1612 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1613 break; 1614 case IFM_1000_LX: 1615 case IFM_1000_SX: 1616 case IFM_1000_T: 1617 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1618 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1619 break; 1620 case IFM_100_TX: 1621 adapter->hw.mac.autoneg = FALSE; 1622 adapter->hw.phy.autoneg_advertised = 0; 1623 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1624 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1625 else 1626 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1627 break; 1628 case IFM_10_T: 1629 adapter->hw.mac.autoneg = FALSE; 1630 adapter->hw.phy.autoneg_advertised = 0; 1631 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1632 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1633 else 1634 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1635 break; 1636 default: 1637 device_printf(adapter->dev, "Unsupported media type\n"); 1638 } 1639 1640 em_if_init(ctx); 1641 1642 return (0); 1643 } 1644 1645 static int 1646 em_if_set_promisc(if_ctx_t ctx, int flags) 1647 { 1648 struct adapter *adapter = iflib_get_softc(ctx); 1649 struct ifnet *ifp = iflib_get_ifp(ctx); 1650 u32 reg_rctl; 1651 int mcnt = 0; 1652 1653 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1654 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1655 if (flags & IFF_ALLMULTI) 1656 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1657 else 1658 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1659 1660 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1661 reg_rctl &= (~E1000_RCTL_MPE); 1662 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1663 1664 if (flags & IFF_PROMISC) { 1665 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1666 em_if_vlan_filter_disable(adapter); 1667 /* Turn this on if you want to see bad packets */ 1668 if (em_debug_sbp) 1669 reg_rctl |= E1000_RCTL_SBP; 1670 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1671 } else { 1672 if (flags & IFF_ALLMULTI) { 1673 reg_rctl |= E1000_RCTL_MPE; 1674 reg_rctl &= ~E1000_RCTL_UPE; 1675 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1676 } 1677 if (em_if_vlan_filter_used(adapter)) 1678 em_if_vlan_filter_enable(adapter); 1679 } 1680 return (0); 1681 } 1682 1683 static u_int 1684 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1685 { 1686 u8 *mta = arg; 1687 1688 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1689 return (0); 1690 1691 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1692 1693 return (1); 1694 } 1695 1696 /********************************************************************* 1697 * Multicast Update 1698 * 1699 * This routine is called whenever multicast address list is updated. 1700 * 1701 **********************************************************************/ 1702 static void 1703 em_if_multi_set(if_ctx_t ctx) 1704 { 1705 struct adapter *adapter = iflib_get_softc(ctx); 1706 struct ifnet *ifp = iflib_get_ifp(ctx); 1707 u8 *mta; /* Multicast array memory */ 1708 u32 reg_rctl = 0; 1709 int mcnt = 0; 1710 1711 IOCTL_DEBUGOUT("em_set_multi: begin"); 1712 1713 mta = adapter->mta; 1714 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1715 1716 if (adapter->hw.mac.type == e1000_82542 && 1717 adapter->hw.revision_id == E1000_REVISION_2) { 1718 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1719 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1720 e1000_pci_clear_mwi(&adapter->hw); 1721 reg_rctl |= E1000_RCTL_RST; 1722 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1723 msec_delay(5); 1724 } 1725 1726 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1727 1728 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1729 1730 if (if_getflags(ifp) & IFF_PROMISC) 1731 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1732 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1733 if_getflags(ifp) & IFF_ALLMULTI) { 1734 reg_rctl |= E1000_RCTL_MPE; 1735 reg_rctl &= ~E1000_RCTL_UPE; 1736 } else 1737 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1738 1739 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1740 1741 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1742 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1743 1744 if (adapter->hw.mac.type == e1000_82542 && 1745 adapter->hw.revision_id == E1000_REVISION_2) { 1746 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1747 reg_rctl &= ~E1000_RCTL_RST; 1748 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1749 msec_delay(5); 1750 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1751 e1000_pci_set_mwi(&adapter->hw); 1752 } 1753 } 1754 1755 /********************************************************************* 1756 * Timer routine 1757 * 1758 * This routine schedules em_if_update_admin_status() to check for 1759 * link status and to gather statistics as well as to perform some 1760 * controller-specific hardware patting. 1761 * 1762 **********************************************************************/ 1763 static void 1764 em_if_timer(if_ctx_t ctx, uint16_t qid) 1765 { 1766 1767 if (qid != 0) 1768 return; 1769 1770 iflib_admin_intr_deferred(ctx); 1771 } 1772 1773 static void 1774 em_if_update_admin_status(if_ctx_t ctx) 1775 { 1776 struct adapter *adapter = iflib_get_softc(ctx); 1777 struct e1000_hw *hw = &adapter->hw; 1778 device_t dev = iflib_get_dev(ctx); 1779 u32 link_check, thstat, ctrl; 1780 1781 link_check = thstat = ctrl = 0; 1782 /* Get the cached link value or read phy for real */ 1783 switch (hw->phy.media_type) { 1784 case e1000_media_type_copper: 1785 if (hw->mac.get_link_status) { 1786 if (hw->mac.type == e1000_pch_spt) 1787 msec_delay(50); 1788 /* Do the work to read phy */ 1789 e1000_check_for_link(hw); 1790 link_check = !hw->mac.get_link_status; 1791 if (link_check) /* ESB2 fix */ 1792 e1000_cfg_on_link_up(hw); 1793 } else { 1794 link_check = TRUE; 1795 } 1796 break; 1797 case e1000_media_type_fiber: 1798 e1000_check_for_link(hw); 1799 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1800 E1000_STATUS_LU); 1801 break; 1802 case e1000_media_type_internal_serdes: 1803 e1000_check_for_link(hw); 1804 link_check = hw->mac.serdes_has_link; 1805 break; 1806 /* VF device is type_unknown */ 1807 case e1000_media_type_unknown: 1808 e1000_check_for_link(hw); 1809 link_check = !hw->mac.get_link_status; 1810 /* FALLTHROUGH */ 1811 default: 1812 break; 1813 } 1814 1815 /* Check for thermal downshift or shutdown */ 1816 if (hw->mac.type == e1000_i350) { 1817 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1818 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1819 } 1820 1821 /* Now check for a transition */ 1822 if (link_check && (adapter->link_active == 0)) { 1823 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1824 &adapter->link_duplex); 1825 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1826 if ((adapter->link_speed != SPEED_1000) && 1827 ((hw->mac.type == e1000_82571) || 1828 (hw->mac.type == e1000_82572))) { 1829 int tarc0; 1830 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1831 tarc0 &= ~TARC_SPEED_MODE_BIT; 1832 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1833 } 1834 if (bootverbose) 1835 device_printf(dev, "Link is up %d Mbps %s\n", 1836 adapter->link_speed, 1837 ((adapter->link_duplex == FULL_DUPLEX) ? 1838 "Full Duplex" : "Half Duplex")); 1839 adapter->link_active = 1; 1840 adapter->smartspeed = 0; 1841 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1842 E1000_CTRL_EXT_LINK_MODE_GMII && 1843 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1844 device_printf(dev, "Link: thermal downshift\n"); 1845 /* Delay Link Up for Phy update */ 1846 if (((hw->mac.type == e1000_i210) || 1847 (hw->mac.type == e1000_i211)) && 1848 (hw->phy.id == I210_I_PHY_ID)) 1849 msec_delay(I210_LINK_DELAY); 1850 /* Reset if the media type changed. */ 1851 if (hw->dev_spec._82575.media_changed && 1852 hw->mac.type >= igb_mac_min) { 1853 hw->dev_spec._82575.media_changed = false; 1854 adapter->flags |= IGB_MEDIA_RESET; 1855 em_reset(ctx); 1856 } 1857 iflib_link_state_change(ctx, LINK_STATE_UP, 1858 IF_Mbps(adapter->link_speed)); 1859 } else if (!link_check && (adapter->link_active == 1)) { 1860 adapter->link_speed = 0; 1861 adapter->link_duplex = 0; 1862 adapter->link_active = 0; 1863 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1864 } 1865 em_update_stats_counters(adapter); 1866 1867 /* Reset LAA into RAR[0] on 82571 */ 1868 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1869 e1000_rar_set(hw, hw->mac.addr, 0); 1870 1871 if (hw->mac.type < em_mac_min) 1872 lem_smartspeed(adapter); 1873 else if (hw->mac.type >= igb_mac_min && 1874 adapter->intr_type == IFLIB_INTR_MSIX) { 1875 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1876 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1877 } else if (hw->mac.type == e1000_82574 && 1878 adapter->intr_type == IFLIB_INTR_MSIX) 1879 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_OTHER); 1880 } 1881 1882 static void 1883 em_if_watchdog_reset(if_ctx_t ctx) 1884 { 1885 struct adapter *adapter = iflib_get_softc(ctx); 1886 1887 /* 1888 * Just count the event; iflib(4) will already trigger a 1889 * sufficient reset of the controller. 1890 */ 1891 adapter->watchdog_events++; 1892 } 1893 1894 /********************************************************************* 1895 * 1896 * This routine disables all traffic on the adapter by issuing a 1897 * global reset on the MAC. 1898 * 1899 **********************************************************************/ 1900 static void 1901 em_if_stop(if_ctx_t ctx) 1902 { 1903 struct adapter *adapter = iflib_get_softc(ctx); 1904 1905 INIT_DEBUGOUT("em_if_stop: begin"); 1906 1907 e1000_reset_hw(&adapter->hw); 1908 if (adapter->hw.mac.type >= e1000_82544) 1909 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1910 1911 e1000_led_off(&adapter->hw); 1912 e1000_cleanup_led(&adapter->hw); 1913 } 1914 1915 /********************************************************************* 1916 * 1917 * Determine hardware revision. 1918 * 1919 **********************************************************************/ 1920 static void 1921 em_identify_hardware(if_ctx_t ctx) 1922 { 1923 device_t dev = iflib_get_dev(ctx); 1924 struct adapter *adapter = iflib_get_softc(ctx); 1925 1926 /* Make sure our PCI config space has the necessary stuff set */ 1927 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1928 1929 /* Save off the information about this board */ 1930 adapter->hw.vendor_id = pci_get_vendor(dev); 1931 adapter->hw.device_id = pci_get_device(dev); 1932 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1933 adapter->hw.subsystem_vendor_id = 1934 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1935 adapter->hw.subsystem_device_id = 1936 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1937 1938 /* Do Shared Code Init and Setup */ 1939 if (e1000_set_mac_type(&adapter->hw)) { 1940 device_printf(dev, "Setup init failure\n"); 1941 return; 1942 } 1943 1944 /* Are we a VF device? */ 1945 if ((adapter->hw.mac.type == e1000_vfadapt) || 1946 (adapter->hw.mac.type == e1000_vfadapt_i350)) 1947 adapter->vf_ifp = 1; 1948 else 1949 adapter->vf_ifp = 0; 1950 } 1951 1952 static int 1953 em_allocate_pci_resources(if_ctx_t ctx) 1954 { 1955 struct adapter *adapter = iflib_get_softc(ctx); 1956 device_t dev = iflib_get_dev(ctx); 1957 int rid, val; 1958 1959 rid = PCIR_BAR(0); 1960 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1961 &rid, RF_ACTIVE); 1962 if (adapter->memory == NULL) { 1963 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1964 return (ENXIO); 1965 } 1966 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1967 adapter->osdep.mem_bus_space_handle = 1968 rman_get_bushandle(adapter->memory); 1969 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1970 1971 /* Only older adapters use IO mapping */ 1972 if (adapter->hw.mac.type < em_mac_min && 1973 adapter->hw.mac.type > e1000_82543) { 1974 /* Figure our where our IO BAR is ? */ 1975 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1976 val = pci_read_config(dev, rid, 4); 1977 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1978 break; 1979 } 1980 rid += 4; 1981 /* check for 64bit BAR */ 1982 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1983 rid += 4; 1984 } 1985 if (rid >= PCIR_CIS) { 1986 device_printf(dev, "Unable to locate IO BAR\n"); 1987 return (ENXIO); 1988 } 1989 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1990 &rid, RF_ACTIVE); 1991 if (adapter->ioport == NULL) { 1992 device_printf(dev, "Unable to allocate bus resource: " 1993 "ioport\n"); 1994 return (ENXIO); 1995 } 1996 adapter->hw.io_base = 0; 1997 adapter->osdep.io_bus_space_tag = 1998 rman_get_bustag(adapter->ioport); 1999 adapter->osdep.io_bus_space_handle = 2000 rman_get_bushandle(adapter->ioport); 2001 } 2002 2003 adapter->hw.back = &adapter->osdep; 2004 2005 return (0); 2006 } 2007 2008 /********************************************************************* 2009 * 2010 * Set up the MSI-X Interrupt handlers 2011 * 2012 **********************************************************************/ 2013 static int 2014 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2015 { 2016 struct adapter *adapter = iflib_get_softc(ctx); 2017 struct em_rx_queue *rx_que = adapter->rx_queues; 2018 struct em_tx_queue *tx_que = adapter->tx_queues; 2019 int error, rid, i, vector = 0, rx_vectors; 2020 char buf[16]; 2021 2022 /* First set up ring resources */ 2023 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 2024 rid = vector + 1; 2025 snprintf(buf, sizeof(buf), "rxq%d", i); 2026 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2027 if (error) { 2028 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2029 adapter->rx_num_queues = i + 1; 2030 goto fail; 2031 } 2032 2033 rx_que->msix = vector; 2034 2035 /* 2036 * Set the bit to enable interrupt 2037 * in E1000_IMS -- bits 20 and 21 2038 * are for RX0 and RX1, note this has 2039 * NOTHING to do with the MSI-X vector 2040 */ 2041 if (adapter->hw.mac.type == e1000_82574) { 2042 rx_que->eims = 1 << (20 + i); 2043 adapter->ims |= rx_que->eims; 2044 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 2045 } else if (adapter->hw.mac.type == e1000_82575) 2046 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2047 else 2048 rx_que->eims = 1 << vector; 2049 } 2050 rx_vectors = vector; 2051 2052 vector = 0; 2053 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 2054 snprintf(buf, sizeof(buf), "txq%d", i); 2055 tx_que = &adapter->tx_queues[i]; 2056 iflib_softirq_alloc_generic(ctx, 2057 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 2058 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2059 2060 tx_que->msix = (vector % adapter->rx_num_queues); 2061 2062 /* 2063 * Set the bit to enable interrupt 2064 * in E1000_IMS -- bits 22 and 23 2065 * are for TX0 and TX1, note this has 2066 * NOTHING to do with the MSI-X vector 2067 */ 2068 if (adapter->hw.mac.type == e1000_82574) { 2069 tx_que->eims = 1 << (22 + i); 2070 adapter->ims |= tx_que->eims; 2071 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2072 } else if (adapter->hw.mac.type == e1000_82575) { 2073 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2074 } else { 2075 tx_que->eims = 1 << i; 2076 } 2077 } 2078 2079 /* Link interrupt */ 2080 rid = rx_vectors + 1; 2081 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2082 2083 if (error) { 2084 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2085 goto fail; 2086 } 2087 adapter->linkvec = rx_vectors; 2088 if (adapter->hw.mac.type < igb_mac_min) { 2089 adapter->ivars |= (8 | rx_vectors) << 16; 2090 adapter->ivars |= 0x80000000; 2091 /* Enable the "Other" interrupt type for link status change */ 2092 adapter->ims |= E1000_IMS_OTHER; 2093 } 2094 2095 return (0); 2096 fail: 2097 iflib_irq_free(ctx, &adapter->irq); 2098 rx_que = adapter->rx_queues; 2099 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2100 iflib_irq_free(ctx, &rx_que->que_irq); 2101 return (error); 2102 } 2103 2104 static void 2105 igb_configure_queues(struct adapter *adapter) 2106 { 2107 struct e1000_hw *hw = &adapter->hw; 2108 struct em_rx_queue *rx_que; 2109 struct em_tx_queue *tx_que; 2110 u32 tmp, ivar = 0, newitr = 0; 2111 2112 /* First turn on RSS capability */ 2113 if (hw->mac.type != e1000_82575) 2114 E1000_WRITE_REG(hw, E1000_GPIE, 2115 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2116 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2117 2118 /* Turn on MSI-X */ 2119 switch (hw->mac.type) { 2120 case e1000_82580: 2121 case e1000_i350: 2122 case e1000_i354: 2123 case e1000_i210: 2124 case e1000_i211: 2125 case e1000_vfadapt: 2126 case e1000_vfadapt_i350: 2127 /* RX entries */ 2128 for (int i = 0; i < adapter->rx_num_queues; i++) { 2129 u32 index = i >> 1; 2130 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2131 rx_que = &adapter->rx_queues[i]; 2132 if (i & 1) { 2133 ivar &= 0xFF00FFFF; 2134 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2135 } else { 2136 ivar &= 0xFFFFFF00; 2137 ivar |= rx_que->msix | E1000_IVAR_VALID; 2138 } 2139 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2140 } 2141 /* TX entries */ 2142 for (int i = 0; i < adapter->tx_num_queues; i++) { 2143 u32 index = i >> 1; 2144 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2145 tx_que = &adapter->tx_queues[i]; 2146 if (i & 1) { 2147 ivar &= 0x00FFFFFF; 2148 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2149 } else { 2150 ivar &= 0xFFFF00FF; 2151 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2152 } 2153 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2154 adapter->que_mask |= tx_que->eims; 2155 } 2156 2157 /* And for the link interrupt */ 2158 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2159 adapter->link_mask = 1 << adapter->linkvec; 2160 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2161 break; 2162 case e1000_82576: 2163 /* RX entries */ 2164 for (int i = 0; i < adapter->rx_num_queues; i++) { 2165 u32 index = i & 0x7; /* Each IVAR has two entries */ 2166 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2167 rx_que = &adapter->rx_queues[i]; 2168 if (i < 8) { 2169 ivar &= 0xFFFFFF00; 2170 ivar |= rx_que->msix | E1000_IVAR_VALID; 2171 } else { 2172 ivar &= 0xFF00FFFF; 2173 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2174 } 2175 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2176 adapter->que_mask |= rx_que->eims; 2177 } 2178 /* TX entries */ 2179 for (int i = 0; i < adapter->tx_num_queues; i++) { 2180 u32 index = i & 0x7; /* Each IVAR has two entries */ 2181 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2182 tx_que = &adapter->tx_queues[i]; 2183 if (i < 8) { 2184 ivar &= 0xFFFF00FF; 2185 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2186 } else { 2187 ivar &= 0x00FFFFFF; 2188 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2189 } 2190 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2191 adapter->que_mask |= tx_que->eims; 2192 } 2193 2194 /* And for the link interrupt */ 2195 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2196 adapter->link_mask = 1 << adapter->linkvec; 2197 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2198 break; 2199 2200 case e1000_82575: 2201 /* enable MSI-X support*/ 2202 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2203 tmp |= E1000_CTRL_EXT_PBA_CLR; 2204 /* Auto-Mask interrupts upon ICR read. */ 2205 tmp |= E1000_CTRL_EXT_EIAME; 2206 tmp |= E1000_CTRL_EXT_IRCA; 2207 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2208 2209 /* Queues */ 2210 for (int i = 0; i < adapter->rx_num_queues; i++) { 2211 rx_que = &adapter->rx_queues[i]; 2212 tmp = E1000_EICR_RX_QUEUE0 << i; 2213 tmp |= E1000_EICR_TX_QUEUE0 << i; 2214 rx_que->eims = tmp; 2215 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2216 i, rx_que->eims); 2217 adapter->que_mask |= rx_que->eims; 2218 } 2219 2220 /* Link */ 2221 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2222 E1000_EIMS_OTHER); 2223 adapter->link_mask |= E1000_EIMS_OTHER; 2224 default: 2225 break; 2226 } 2227 2228 /* Set the starting interrupt rate */ 2229 if (em_max_interrupt_rate > 0) 2230 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2231 2232 if (hw->mac.type == e1000_82575) 2233 newitr |= newitr << 16; 2234 else 2235 newitr |= E1000_EITR_CNT_IGNR; 2236 2237 for (int i = 0; i < adapter->rx_num_queues; i++) { 2238 rx_que = &adapter->rx_queues[i]; 2239 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2240 } 2241 2242 return; 2243 } 2244 2245 static void 2246 em_free_pci_resources(if_ctx_t ctx) 2247 { 2248 struct adapter *adapter = iflib_get_softc(ctx); 2249 struct em_rx_queue *que = adapter->rx_queues; 2250 device_t dev = iflib_get_dev(ctx); 2251 2252 /* Release all MSI-X queue resources */ 2253 if (adapter->intr_type == IFLIB_INTR_MSIX) 2254 iflib_irq_free(ctx, &adapter->irq); 2255 2256 if (que != NULL) { 2257 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2258 iflib_irq_free(ctx, &que->que_irq); 2259 } 2260 } 2261 2262 if (adapter->memory != NULL) { 2263 bus_release_resource(dev, SYS_RES_MEMORY, 2264 rman_get_rid(adapter->memory), adapter->memory); 2265 adapter->memory = NULL; 2266 } 2267 2268 if (adapter->flash != NULL) { 2269 bus_release_resource(dev, SYS_RES_MEMORY, 2270 rman_get_rid(adapter->flash), adapter->flash); 2271 adapter->flash = NULL; 2272 } 2273 2274 if (adapter->ioport != NULL) { 2275 bus_release_resource(dev, SYS_RES_IOPORT, 2276 rman_get_rid(adapter->ioport), adapter->ioport); 2277 adapter->ioport = NULL; 2278 } 2279 } 2280 2281 /* Set up MSI or MSI-X */ 2282 static int 2283 em_setup_msix(if_ctx_t ctx) 2284 { 2285 struct adapter *adapter = iflib_get_softc(ctx); 2286 2287 if (adapter->hw.mac.type == e1000_82574) { 2288 em_enable_vectors_82574(ctx); 2289 } 2290 return (0); 2291 } 2292 2293 /********************************************************************* 2294 * 2295 * Workaround for SmartSpeed on 82541 and 82547 controllers 2296 * 2297 **********************************************************************/ 2298 static void 2299 lem_smartspeed(struct adapter *adapter) 2300 { 2301 u16 phy_tmp; 2302 2303 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2304 adapter->hw.mac.autoneg == 0 || 2305 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2306 return; 2307 2308 if (adapter->smartspeed == 0) { 2309 /* If Master/Slave config fault is asserted twice, 2310 * we assume back-to-back */ 2311 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2312 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2313 return; 2314 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2315 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2316 e1000_read_phy_reg(&adapter->hw, 2317 PHY_1000T_CTRL, &phy_tmp); 2318 if(phy_tmp & CR_1000T_MS_ENABLE) { 2319 phy_tmp &= ~CR_1000T_MS_ENABLE; 2320 e1000_write_phy_reg(&adapter->hw, 2321 PHY_1000T_CTRL, phy_tmp); 2322 adapter->smartspeed++; 2323 if(adapter->hw.mac.autoneg && 2324 !e1000_copper_link_autoneg(&adapter->hw) && 2325 !e1000_read_phy_reg(&adapter->hw, 2326 PHY_CONTROL, &phy_tmp)) { 2327 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2328 MII_CR_RESTART_AUTO_NEG); 2329 e1000_write_phy_reg(&adapter->hw, 2330 PHY_CONTROL, phy_tmp); 2331 } 2332 } 2333 } 2334 return; 2335 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2336 /* If still no link, perhaps using 2/3 pair cable */ 2337 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2338 phy_tmp |= CR_1000T_MS_ENABLE; 2339 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2340 if(adapter->hw.mac.autoneg && 2341 !e1000_copper_link_autoneg(&adapter->hw) && 2342 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2343 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2344 MII_CR_RESTART_AUTO_NEG); 2345 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2346 } 2347 } 2348 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2349 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2350 adapter->smartspeed = 0; 2351 } 2352 2353 /********************************************************************* 2354 * 2355 * Initialize the DMA Coalescing feature 2356 * 2357 **********************************************************************/ 2358 static void 2359 igb_init_dmac(struct adapter *adapter, u32 pba) 2360 { 2361 device_t dev = adapter->dev; 2362 struct e1000_hw *hw = &adapter->hw; 2363 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2364 u16 hwm; 2365 u16 max_frame_size; 2366 2367 if (hw->mac.type == e1000_i211) 2368 return; 2369 2370 max_frame_size = adapter->shared->isc_max_frame_size; 2371 if (hw->mac.type > e1000_82580) { 2372 2373 if (adapter->dmac == 0) { /* Disabling it */ 2374 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2375 return; 2376 } else 2377 device_printf(dev, "DMA Coalescing enabled\n"); 2378 2379 /* Set starting threshold */ 2380 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2381 2382 hwm = 64 * pba - max_frame_size / 16; 2383 if (hwm < 64 * (pba - 6)) 2384 hwm = 64 * (pba - 6); 2385 reg = E1000_READ_REG(hw, E1000_FCRTC); 2386 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2387 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2388 & E1000_FCRTC_RTH_COAL_MASK); 2389 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2390 2391 2392 dmac = pba - max_frame_size / 512; 2393 if (dmac < pba - 10) 2394 dmac = pba - 10; 2395 reg = E1000_READ_REG(hw, E1000_DMACR); 2396 reg &= ~E1000_DMACR_DMACTHR_MASK; 2397 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2398 & E1000_DMACR_DMACTHR_MASK); 2399 2400 /* transition to L0x or L1 if available..*/ 2401 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2402 2403 /* Check if status is 2.5Gb backplane connection 2404 * before configuration of watchdog timer, which is 2405 * in msec values in 12.8usec intervals 2406 * watchdog timer= msec values in 32usec intervals 2407 * for non 2.5Gb connection 2408 */ 2409 if (hw->mac.type == e1000_i354) { 2410 int status = E1000_READ_REG(hw, E1000_STATUS); 2411 if ((status & E1000_STATUS_2P5_SKU) && 2412 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2413 reg |= ((adapter->dmac * 5) >> 6); 2414 else 2415 reg |= (adapter->dmac >> 5); 2416 } else { 2417 reg |= (adapter->dmac >> 5); 2418 } 2419 2420 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2421 2422 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2423 2424 /* Set the interval before transition */ 2425 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2426 if (hw->mac.type == e1000_i350) 2427 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2428 /* 2429 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2430 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2431 */ 2432 if (hw->mac.type == e1000_i354) { 2433 int status = E1000_READ_REG(hw, E1000_STATUS); 2434 if ((status & E1000_STATUS_2P5_SKU) && 2435 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2436 reg |= 0xA; 2437 else 2438 reg |= 0x4; 2439 } else { 2440 reg |= 0x4; 2441 } 2442 2443 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2444 2445 /* free space in tx packet buffer to wake from DMA coal */ 2446 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2447 (2 * max_frame_size)) >> 6); 2448 2449 /* make low power state decision controlled by DMA coal */ 2450 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2451 reg &= ~E1000_PCIEMISC_LX_DECISION; 2452 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2453 2454 } else if (hw->mac.type == e1000_82580) { 2455 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2456 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2457 reg & ~E1000_PCIEMISC_LX_DECISION); 2458 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2459 } 2460 } 2461 2462 /********************************************************************* 2463 * 2464 * Initialize the hardware to a configuration as specified by the 2465 * adapter structure. 2466 * 2467 **********************************************************************/ 2468 static void 2469 em_reset(if_ctx_t ctx) 2470 { 2471 device_t dev = iflib_get_dev(ctx); 2472 struct adapter *adapter = iflib_get_softc(ctx); 2473 struct ifnet *ifp = iflib_get_ifp(ctx); 2474 struct e1000_hw *hw = &adapter->hw; 2475 u16 rx_buffer_size; 2476 u32 pba; 2477 2478 INIT_DEBUGOUT("em_reset: begin"); 2479 /* Let the firmware know the OS is in control */ 2480 em_get_hw_control(adapter); 2481 2482 /* Set up smart power down as default off on newer adapters. */ 2483 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2484 hw->mac.type == e1000_82572)) { 2485 u16 phy_tmp = 0; 2486 2487 /* Speed up time to link by disabling smart power down. */ 2488 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2489 phy_tmp &= ~IGP02E1000_PM_SPD; 2490 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2491 } 2492 2493 /* 2494 * Packet Buffer Allocation (PBA) 2495 * Writing PBA sets the receive portion of the buffer 2496 * the remainder is used for the transmit buffer. 2497 */ 2498 switch (hw->mac.type) { 2499 /* 82547: Total Packet Buffer is 40K */ 2500 case e1000_82547: 2501 case e1000_82547_rev_2: 2502 if (hw->mac.max_frame_size > 8192) 2503 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2504 else 2505 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2506 break; 2507 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2508 case e1000_82571: 2509 case e1000_82572: 2510 case e1000_80003es2lan: 2511 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2512 break; 2513 /* 82573: Total Packet Buffer is 32K */ 2514 case e1000_82573: 2515 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2516 break; 2517 case e1000_82574: 2518 case e1000_82583: 2519 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2520 break; 2521 case e1000_ich8lan: 2522 pba = E1000_PBA_8K; 2523 break; 2524 case e1000_ich9lan: 2525 case e1000_ich10lan: 2526 /* Boost Receive side for jumbo frames */ 2527 if (hw->mac.max_frame_size > 4096) 2528 pba = E1000_PBA_14K; 2529 else 2530 pba = E1000_PBA_10K; 2531 break; 2532 case e1000_pchlan: 2533 case e1000_pch2lan: 2534 case e1000_pch_lpt: 2535 case e1000_pch_spt: 2536 case e1000_pch_cnp: 2537 case e1000_pch_tgp: 2538 case e1000_pch_adp: 2539 case e1000_pch_mtp: 2540 pba = E1000_PBA_26K; 2541 break; 2542 case e1000_82575: 2543 pba = E1000_PBA_32K; 2544 break; 2545 case e1000_82576: 2546 case e1000_vfadapt: 2547 pba = E1000_READ_REG(hw, E1000_RXPBS); 2548 pba &= E1000_RXPBS_SIZE_MASK_82576; 2549 break; 2550 case e1000_82580: 2551 case e1000_i350: 2552 case e1000_i354: 2553 case e1000_vfadapt_i350: 2554 pba = E1000_READ_REG(hw, E1000_RXPBS); 2555 pba = e1000_rxpbs_adjust_82580(pba); 2556 break; 2557 case e1000_i210: 2558 case e1000_i211: 2559 pba = E1000_PBA_34K; 2560 break; 2561 default: 2562 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2563 if (hw->mac.max_frame_size > 8192) 2564 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2565 else 2566 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2567 } 2568 2569 /* Special needs in case of Jumbo frames */ 2570 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2571 u32 tx_space, min_tx, min_rx; 2572 pba = E1000_READ_REG(hw, E1000_PBA); 2573 tx_space = pba >> 16; 2574 pba &= 0xffff; 2575 min_tx = (hw->mac.max_frame_size + 2576 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2577 min_tx = roundup2(min_tx, 1024); 2578 min_tx >>= 10; 2579 min_rx = hw->mac.max_frame_size; 2580 min_rx = roundup2(min_rx, 1024); 2581 min_rx >>= 10; 2582 if (tx_space < min_tx && 2583 ((min_tx - tx_space) < pba)) { 2584 pba = pba - (min_tx - tx_space); 2585 /* 2586 * if short on rx space, rx wins 2587 * and must trump tx adjustment 2588 */ 2589 if (pba < min_rx) 2590 pba = min_rx; 2591 } 2592 E1000_WRITE_REG(hw, E1000_PBA, pba); 2593 } 2594 2595 if (hw->mac.type < igb_mac_min) 2596 E1000_WRITE_REG(hw, E1000_PBA, pba); 2597 2598 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2599 2600 /* 2601 * These parameters control the automatic generation (Tx) and 2602 * response (Rx) to Ethernet PAUSE frames. 2603 * - High water mark should allow for at least two frames to be 2604 * received after sending an XOFF. 2605 * - Low water mark works best when it is very near the high water mark. 2606 * This allows the receiver to restart by sending XON when it has 2607 * drained a bit. Here we use an arbitrary value of 1500 which will 2608 * restart after one full frame is pulled from the buffer. There 2609 * could be several smaller frames in the buffer and if so they will 2610 * not trigger the XON until their total number reduces the buffer 2611 * by 1500. 2612 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2613 */ 2614 rx_buffer_size = (pba & 0xffff) << 10; 2615 hw->fc.high_water = rx_buffer_size - 2616 roundup2(hw->mac.max_frame_size, 1024); 2617 hw->fc.low_water = hw->fc.high_water - 1500; 2618 2619 if (adapter->fc) /* locally set flow control value? */ 2620 hw->fc.requested_mode = adapter->fc; 2621 else 2622 hw->fc.requested_mode = e1000_fc_full; 2623 2624 if (hw->mac.type == e1000_80003es2lan) 2625 hw->fc.pause_time = 0xFFFF; 2626 else 2627 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2628 2629 hw->fc.send_xon = TRUE; 2630 2631 /* Device specific overrides/settings */ 2632 switch (hw->mac.type) { 2633 case e1000_pchlan: 2634 /* Workaround: no TX flow ctrl for PCH */ 2635 hw->fc.requested_mode = e1000_fc_rx_pause; 2636 hw->fc.pause_time = 0xFFFF; /* override */ 2637 if (if_getmtu(ifp) > ETHERMTU) { 2638 hw->fc.high_water = 0x3500; 2639 hw->fc.low_water = 0x1500; 2640 } else { 2641 hw->fc.high_water = 0x5000; 2642 hw->fc.low_water = 0x3000; 2643 } 2644 hw->fc.refresh_time = 0x1000; 2645 break; 2646 case e1000_pch2lan: 2647 case e1000_pch_lpt: 2648 case e1000_pch_spt: 2649 case e1000_pch_cnp: 2650 case e1000_pch_tgp: 2651 case e1000_pch_adp: 2652 case e1000_pch_mtp: 2653 hw->fc.high_water = 0x5C20; 2654 hw->fc.low_water = 0x5048; 2655 hw->fc.pause_time = 0x0650; 2656 hw->fc.refresh_time = 0x0400; 2657 /* Jumbos need adjusted PBA */ 2658 if (if_getmtu(ifp) > ETHERMTU) 2659 E1000_WRITE_REG(hw, E1000_PBA, 12); 2660 else 2661 E1000_WRITE_REG(hw, E1000_PBA, 26); 2662 break; 2663 case e1000_82575: 2664 case e1000_82576: 2665 /* 8-byte granularity */ 2666 hw->fc.low_water = hw->fc.high_water - 8; 2667 break; 2668 case e1000_82580: 2669 case e1000_i350: 2670 case e1000_i354: 2671 case e1000_i210: 2672 case e1000_i211: 2673 case e1000_vfadapt: 2674 case e1000_vfadapt_i350: 2675 /* 16-byte granularity */ 2676 hw->fc.low_water = hw->fc.high_water - 16; 2677 break; 2678 case e1000_ich9lan: 2679 case e1000_ich10lan: 2680 if (if_getmtu(ifp) > ETHERMTU) { 2681 hw->fc.high_water = 0x2800; 2682 hw->fc.low_water = hw->fc.high_water - 8; 2683 break; 2684 } 2685 /* FALLTHROUGH */ 2686 default: 2687 if (hw->mac.type == e1000_80003es2lan) 2688 hw->fc.pause_time = 0xFFFF; 2689 break; 2690 } 2691 2692 /* Issue a global reset */ 2693 e1000_reset_hw(hw); 2694 if (hw->mac.type >= igb_mac_min) { 2695 E1000_WRITE_REG(hw, E1000_WUC, 0); 2696 } else { 2697 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2698 em_disable_aspm(adapter); 2699 } 2700 if (adapter->flags & IGB_MEDIA_RESET) { 2701 e1000_setup_init_funcs(hw, TRUE); 2702 e1000_get_bus_info(hw); 2703 adapter->flags &= ~IGB_MEDIA_RESET; 2704 } 2705 /* and a re-init */ 2706 if (e1000_init_hw(hw) < 0) { 2707 device_printf(dev, "Hardware Initialization Failed\n"); 2708 return; 2709 } 2710 if (hw->mac.type >= igb_mac_min) 2711 igb_init_dmac(adapter, pba); 2712 2713 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2714 e1000_get_phy_info(hw); 2715 e1000_check_for_link(hw); 2716 } 2717 2718 /* 2719 * Initialise the RSS mapping for NICs that support multiple transmit/ 2720 * receive rings. 2721 */ 2722 2723 #define RSSKEYLEN 10 2724 static void 2725 em_initialize_rss_mapping(struct adapter *adapter) 2726 { 2727 uint8_t rss_key[4 * RSSKEYLEN]; 2728 uint32_t reta = 0; 2729 struct e1000_hw *hw = &adapter->hw; 2730 int i; 2731 2732 /* 2733 * Configure RSS key 2734 */ 2735 arc4rand(rss_key, sizeof(rss_key), 0); 2736 for (i = 0; i < RSSKEYLEN; ++i) { 2737 uint32_t rssrk = 0; 2738 2739 rssrk = EM_RSSRK_VAL(rss_key, i); 2740 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2741 } 2742 2743 /* 2744 * Configure RSS redirect table in following fashion: 2745 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2746 */ 2747 for (i = 0; i < sizeof(reta); ++i) { 2748 uint32_t q; 2749 2750 q = (i % adapter->rx_num_queues) << 7; 2751 reta |= q << (8 * i); 2752 } 2753 2754 for (i = 0; i < 32; ++i) 2755 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2756 2757 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2758 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2759 E1000_MRQC_RSS_FIELD_IPV4 | 2760 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2761 E1000_MRQC_RSS_FIELD_IPV6_EX | 2762 E1000_MRQC_RSS_FIELD_IPV6); 2763 } 2764 2765 static void 2766 igb_initialize_rss_mapping(struct adapter *adapter) 2767 { 2768 struct e1000_hw *hw = &adapter->hw; 2769 int i; 2770 int queue_id; 2771 u32 reta; 2772 u32 rss_key[10], mrqc, shift = 0; 2773 2774 /* XXX? */ 2775 if (hw->mac.type == e1000_82575) 2776 shift = 6; 2777 2778 /* 2779 * The redirection table controls which destination 2780 * queue each bucket redirects traffic to. 2781 * Each DWORD represents four queues, with the LSB 2782 * being the first queue in the DWORD. 2783 * 2784 * This just allocates buckets to queues using round-robin 2785 * allocation. 2786 * 2787 * NOTE: It Just Happens to line up with the default 2788 * RSS allocation method. 2789 */ 2790 2791 /* Warning FM follows */ 2792 reta = 0; 2793 for (i = 0; i < 128; i++) { 2794 #ifdef RSS 2795 queue_id = rss_get_indirection_to_bucket(i); 2796 /* 2797 * If we have more queues than buckets, we'll 2798 * end up mapping buckets to a subset of the 2799 * queues. 2800 * 2801 * If we have more buckets than queues, we'll 2802 * end up instead assigning multiple buckets 2803 * to queues. 2804 * 2805 * Both are suboptimal, but we need to handle 2806 * the case so we don't go out of bounds 2807 * indexing arrays and such. 2808 */ 2809 queue_id = queue_id % adapter->rx_num_queues; 2810 #else 2811 queue_id = (i % adapter->rx_num_queues); 2812 #endif 2813 /* Adjust if required */ 2814 queue_id = queue_id << shift; 2815 2816 /* 2817 * The low 8 bits are for hash value (n+0); 2818 * The next 8 bits are for hash value (n+1), etc. 2819 */ 2820 reta = reta >> 8; 2821 reta = reta | ( ((uint32_t) queue_id) << 24); 2822 if ((i & 3) == 3) { 2823 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2824 reta = 0; 2825 } 2826 } 2827 2828 /* Now fill in hash table */ 2829 2830 /* 2831 * MRQC: Multiple Receive Queues Command 2832 * Set queuing to RSS control, number depends on the device. 2833 */ 2834 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2835 2836 #ifdef RSS 2837 /* XXX ew typecasting */ 2838 rss_getkey((uint8_t *) &rss_key); 2839 #else 2840 arc4rand(&rss_key, sizeof(rss_key), 0); 2841 #endif 2842 for (i = 0; i < 10; i++) 2843 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2844 2845 /* 2846 * Configure the RSS fields to hash upon. 2847 */ 2848 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2849 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2850 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2851 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2852 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2853 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2854 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2855 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2856 2857 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2858 } 2859 2860 /********************************************************************* 2861 * 2862 * Setup networking device structure and register interface media. 2863 * 2864 **********************************************************************/ 2865 static int 2866 em_setup_interface(if_ctx_t ctx) 2867 { 2868 struct ifnet *ifp = iflib_get_ifp(ctx); 2869 struct adapter *adapter = iflib_get_softc(ctx); 2870 if_softc_ctx_t scctx = adapter->shared; 2871 2872 INIT_DEBUGOUT("em_setup_interface: begin"); 2873 2874 /* Single Queue */ 2875 if (adapter->tx_num_queues == 1) { 2876 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2877 if_setsendqready(ifp); 2878 } 2879 2880 /* 2881 * Specify the media types supported by this adapter and register 2882 * callbacks to update media and link information 2883 */ 2884 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2885 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2886 u_char fiber_type = IFM_1000_SX; /* default type */ 2887 2888 if (adapter->hw.mac.type == e1000_82545) 2889 fiber_type = IFM_1000_LX; 2890 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2891 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2892 } else { 2893 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2894 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2895 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2896 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2897 if (adapter->hw.phy.type != e1000_phy_ife) { 2898 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2899 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2900 } 2901 } 2902 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2903 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2904 return (0); 2905 } 2906 2907 static int 2908 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2909 { 2910 struct adapter *adapter = iflib_get_softc(ctx); 2911 if_softc_ctx_t scctx = adapter->shared; 2912 int error = E1000_SUCCESS; 2913 struct em_tx_queue *que; 2914 int i, j; 2915 2916 MPASS(adapter->tx_num_queues > 0); 2917 MPASS(adapter->tx_num_queues == ntxqsets); 2918 2919 /* First allocate the top level queue structs */ 2920 if (!(adapter->tx_queues = 2921 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2922 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2923 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2924 return(ENOMEM); 2925 } 2926 2927 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2928 /* Set up some basics */ 2929 2930 struct tx_ring *txr = &que->txr; 2931 txr->adapter = que->adapter = adapter; 2932 que->me = txr->me = i; 2933 2934 /* Allocate report status array */ 2935 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2936 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2937 error = ENOMEM; 2938 goto fail; 2939 } 2940 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2941 txr->tx_rsq[j] = QIDX_INVALID; 2942 /* get the virtual and physical address of the hardware queues */ 2943 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2944 txr->tx_paddr = paddrs[i*ntxqs]; 2945 } 2946 2947 if (bootverbose) 2948 device_printf(iflib_get_dev(ctx), 2949 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2950 return (0); 2951 fail: 2952 em_if_queues_free(ctx); 2953 return (error); 2954 } 2955 2956 static int 2957 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2958 { 2959 struct adapter *adapter = iflib_get_softc(ctx); 2960 int error = E1000_SUCCESS; 2961 struct em_rx_queue *que; 2962 int i; 2963 2964 MPASS(adapter->rx_num_queues > 0); 2965 MPASS(adapter->rx_num_queues == nrxqsets); 2966 2967 /* First allocate the top level queue structs */ 2968 if (!(adapter->rx_queues = 2969 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2970 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2971 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2972 error = ENOMEM; 2973 goto fail; 2974 } 2975 2976 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2977 /* Set up some basics */ 2978 struct rx_ring *rxr = &que->rxr; 2979 rxr->adapter = que->adapter = adapter; 2980 rxr->que = que; 2981 que->me = rxr->me = i; 2982 2983 /* get the virtual and physical address of the hardware queues */ 2984 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2985 rxr->rx_paddr = paddrs[i*nrxqs]; 2986 } 2987 2988 if (bootverbose) 2989 device_printf(iflib_get_dev(ctx), 2990 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2991 2992 return (0); 2993 fail: 2994 em_if_queues_free(ctx); 2995 return (error); 2996 } 2997 2998 static void 2999 em_if_queues_free(if_ctx_t ctx) 3000 { 3001 struct adapter *adapter = iflib_get_softc(ctx); 3002 struct em_tx_queue *tx_que = adapter->tx_queues; 3003 struct em_rx_queue *rx_que = adapter->rx_queues; 3004 3005 if (tx_que != NULL) { 3006 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 3007 struct tx_ring *txr = &tx_que->txr; 3008 if (txr->tx_rsq == NULL) 3009 break; 3010 3011 free(txr->tx_rsq, M_DEVBUF); 3012 txr->tx_rsq = NULL; 3013 } 3014 free(adapter->tx_queues, M_DEVBUF); 3015 adapter->tx_queues = NULL; 3016 } 3017 3018 if (rx_que != NULL) { 3019 free(adapter->rx_queues, M_DEVBUF); 3020 adapter->rx_queues = NULL; 3021 } 3022 } 3023 3024 /********************************************************************* 3025 * 3026 * Enable transmit unit. 3027 * 3028 **********************************************************************/ 3029 static void 3030 em_initialize_transmit_unit(if_ctx_t ctx) 3031 { 3032 struct adapter *adapter = iflib_get_softc(ctx); 3033 if_softc_ctx_t scctx = adapter->shared; 3034 struct em_tx_queue *que; 3035 struct tx_ring *txr; 3036 struct e1000_hw *hw = &adapter->hw; 3037 u32 tctl, txdctl = 0, tarc, tipg = 0; 3038 3039 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3040 3041 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 3042 u64 bus_addr; 3043 caddr_t offp, endp; 3044 3045 que = &adapter->tx_queues[i]; 3046 txr = &que->txr; 3047 bus_addr = txr->tx_paddr; 3048 3049 /* Clear checksum offload context. */ 3050 offp = (caddr_t)&txr->csum_flags; 3051 endp = (caddr_t)(txr + 1); 3052 bzero(offp, endp - offp); 3053 3054 /* Base and Len of TX Ring */ 3055 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3056 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3057 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3058 (u32)(bus_addr >> 32)); 3059 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3060 (u32)bus_addr); 3061 /* Init the HEAD/TAIL indices */ 3062 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3063 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3064 3065 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3066 E1000_READ_REG(hw, E1000_TDBAL(i)), 3067 E1000_READ_REG(hw, E1000_TDLEN(i))); 3068 3069 txdctl = 0; /* clear txdctl */ 3070 txdctl |= 0x1f; /* PTHRESH */ 3071 txdctl |= 1 << 8; /* HTHRESH */ 3072 txdctl |= 1 << 16;/* WTHRESH */ 3073 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3074 txdctl |= E1000_TXDCTL_GRAN; 3075 txdctl |= 1 << 25; /* LWTHRESH */ 3076 3077 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3078 } 3079 3080 /* Set the default values for the Tx Inter Packet Gap timer */ 3081 switch (hw->mac.type) { 3082 case e1000_80003es2lan: 3083 tipg = DEFAULT_82543_TIPG_IPGR1; 3084 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3085 E1000_TIPG_IPGR2_SHIFT; 3086 break; 3087 case e1000_82542: 3088 tipg = DEFAULT_82542_TIPG_IPGT; 3089 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3090 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3091 break; 3092 default: 3093 if (hw->phy.media_type == e1000_media_type_fiber || 3094 hw->phy.media_type == e1000_media_type_internal_serdes) 3095 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3096 else 3097 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3098 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3099 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3100 } 3101 3102 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3103 E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value); 3104 3105 if(hw->mac.type >= e1000_82540) 3106 E1000_WRITE_REG(hw, E1000_TADV, 3107 adapter->tx_abs_int_delay.value); 3108 3109 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3110 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3111 tarc |= TARC_SPEED_MODE_BIT; 3112 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3113 } else if (hw->mac.type == e1000_80003es2lan) { 3114 /* errata: program both queues to unweighted RR */ 3115 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3116 tarc |= 1; 3117 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3118 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3119 tarc |= 1; 3120 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3121 } else if (hw->mac.type == e1000_82574) { 3122 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3123 tarc |= TARC_ERRATA_BIT; 3124 if ( adapter->tx_num_queues > 1) { 3125 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3126 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3127 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3128 } else 3129 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3130 } 3131 3132 if (adapter->tx_int_delay.value > 0) 3133 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3134 3135 /* Program the Transmit Control Register */ 3136 tctl = E1000_READ_REG(hw, E1000_TCTL); 3137 tctl &= ~E1000_TCTL_CT; 3138 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3139 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3140 3141 if (hw->mac.type >= e1000_82571) 3142 tctl |= E1000_TCTL_MULR; 3143 3144 /* This write will effectively turn on the transmit unit. */ 3145 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3146 3147 /* SPT and KBL errata workarounds */ 3148 if (hw->mac.type == e1000_pch_spt) { 3149 u32 reg; 3150 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3151 reg |= E1000_RCTL_RDMTS_HEX; 3152 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3153 /* i218-i219 Specification Update 1.5.4.5 */ 3154 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3155 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3156 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3157 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3158 } 3159 } 3160 3161 /********************************************************************* 3162 * 3163 * Enable receive unit. 3164 * 3165 **********************************************************************/ 3166 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3167 3168 static void 3169 em_initialize_receive_unit(if_ctx_t ctx) 3170 { 3171 struct adapter *adapter = iflib_get_softc(ctx); 3172 if_softc_ctx_t scctx = adapter->shared; 3173 struct ifnet *ifp = iflib_get_ifp(ctx); 3174 struct e1000_hw *hw = &adapter->hw; 3175 struct em_rx_queue *que; 3176 int i; 3177 uint32_t rctl, rxcsum; 3178 3179 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3180 3181 /* 3182 * Make sure receives are disabled while setting 3183 * up the descriptor ring 3184 */ 3185 rctl = E1000_READ_REG(hw, E1000_RCTL); 3186 /* Do not disable if ever enabled on this hardware */ 3187 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3188 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3189 3190 /* Setup the Receive Control Register */ 3191 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3192 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3193 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3194 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3195 3196 /* Do not store bad packets */ 3197 rctl &= ~E1000_RCTL_SBP; 3198 3199 /* Enable Long Packet receive */ 3200 if (if_getmtu(ifp) > ETHERMTU) 3201 rctl |= E1000_RCTL_LPE; 3202 else 3203 rctl &= ~E1000_RCTL_LPE; 3204 3205 /* Strip the CRC */ 3206 if (!em_disable_crc_stripping) 3207 rctl |= E1000_RCTL_SECRC; 3208 3209 if (hw->mac.type >= e1000_82540) { 3210 E1000_WRITE_REG(hw, E1000_RADV, 3211 adapter->rx_abs_int_delay.value); 3212 3213 /* 3214 * Set the interrupt throttling rate. Value is calculated 3215 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3216 */ 3217 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3218 } 3219 E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value); 3220 3221 if (hw->mac.type >= em_mac_min) { 3222 uint32_t rfctl; 3223 /* Use extended rx descriptor formats */ 3224 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3225 rfctl |= E1000_RFCTL_EXTEN; 3226 3227 /* 3228 * When using MSI-X interrupts we need to throttle 3229 * using the EITR register (82574 only) 3230 */ 3231 if (hw->mac.type == e1000_82574) { 3232 for (int i = 0; i < 4; i++) 3233 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3234 DEFAULT_ITR); 3235 /* Disable accelerated acknowledge */ 3236 rfctl |= E1000_RFCTL_ACK_DIS; 3237 } 3238 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3239 } 3240 3241 /* Set up L3 and L4 csum Rx descriptor offloads */ 3242 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3243 if (scctx->isc_capenable & IFCAP_RXCSUM) { 3244 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3245 if (hw->mac.type > e1000_82575) 3246 rxcsum |= E1000_RXCSUM_CRCOFL; 3247 else if (hw->mac.type < em_mac_min && 3248 scctx->isc_capenable & IFCAP_HWCSUM_IPV6) 3249 rxcsum |= E1000_RXCSUM_IPV6OFL; 3250 } else { 3251 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3252 if (hw->mac.type > e1000_82575) 3253 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3254 else if (hw->mac.type < em_mac_min) 3255 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3256 } 3257 3258 if (adapter->rx_num_queues > 1) { 3259 /* RSS hash needed in the Rx descriptor */ 3260 rxcsum |= E1000_RXCSUM_PCSD; 3261 3262 if (hw->mac.type >= igb_mac_min) 3263 igb_initialize_rss_mapping(adapter); 3264 else 3265 em_initialize_rss_mapping(adapter); 3266 } 3267 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3268 3269 /* 3270 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3271 * long latencies are observed, like Lenovo X60. This 3272 * change eliminates the problem, but since having positive 3273 * values in RDTR is a known source of problems on other 3274 * platforms another solution is being sought. 3275 */ 3276 if (hw->mac.type == e1000_82573) 3277 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3278 3279 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3280 struct rx_ring *rxr = &que->rxr; 3281 /* Setup the Base and Length of the Rx Descriptor Ring */ 3282 u64 bus_addr = rxr->rx_paddr; 3283 #if 0 3284 u32 rdt = adapter->rx_num_queues -1; /* default */ 3285 #endif 3286 3287 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3288 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3289 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3290 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3291 /* Setup the Head and Tail Descriptor Pointers */ 3292 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3293 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3294 } 3295 3296 /* 3297 * Set PTHRESH for improved jumbo performance 3298 * According to 10.2.5.11 of Intel 82574 Datasheet, 3299 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3300 * Only write to RXDCTL(1) if there is a need for different 3301 * settings. 3302 */ 3303 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3304 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3305 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3306 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3307 } else if (hw->mac.type == e1000_82574) { 3308 for (int i = 0; i < adapter->rx_num_queues; i++) { 3309 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3310 rxdctl |= 0x20; /* PTHRESH */ 3311 rxdctl |= 4 << 8; /* HTHRESH */ 3312 rxdctl |= 4 << 16;/* WTHRESH */ 3313 rxdctl |= 1 << 24; /* Switch to granularity */ 3314 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3315 } 3316 } else if (hw->mac.type >= igb_mac_min) { 3317 u32 psize, srrctl = 0; 3318 3319 if (if_getmtu(ifp) > ETHERMTU) { 3320 psize = scctx->isc_max_frame_size; 3321 /* are we on a vlan? */ 3322 if (ifp->if_vlantrunk != NULL) 3323 psize += VLAN_TAG_SIZE; 3324 3325 if (adapter->vf_ifp) 3326 e1000_rlpml_set_vf(hw, psize); 3327 else 3328 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3329 } 3330 3331 /* Set maximum packet buffer len */ 3332 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3333 E1000_SRRCTL_BSIZEPKT_SHIFT; 3334 3335 /* 3336 * If TX flow control is disabled and there's >1 queue defined, 3337 * enable DROP. 3338 * 3339 * This drops frames rather than hanging the RX MAC for all queues. 3340 */ 3341 if ((adapter->rx_num_queues > 1) && 3342 (adapter->fc == e1000_fc_none || 3343 adapter->fc == e1000_fc_rx_pause)) { 3344 srrctl |= E1000_SRRCTL_DROP_EN; 3345 } 3346 /* Setup the Base and Length of the Rx Descriptor Rings */ 3347 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3348 struct rx_ring *rxr = &que->rxr; 3349 u64 bus_addr = rxr->rx_paddr; 3350 u32 rxdctl; 3351 3352 #ifdef notyet 3353 /* Configure for header split? -- ignore for now */ 3354 rxr->hdr_split = igb_header_split; 3355 #else 3356 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3357 #endif 3358 3359 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3360 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3361 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3362 (uint32_t)(bus_addr >> 32)); 3363 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3364 (uint32_t)bus_addr); 3365 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3366 /* Enable this Queue */ 3367 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3368 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3369 rxdctl &= 0xFFF00000; 3370 rxdctl |= IGB_RX_PTHRESH; 3371 rxdctl |= IGB_RX_HTHRESH << 8; 3372 rxdctl |= IGB_RX_WTHRESH << 16; 3373 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3374 } 3375 } else if (hw->mac.type >= e1000_pch2lan) { 3376 if (if_getmtu(ifp) > ETHERMTU) 3377 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3378 else 3379 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3380 } 3381 3382 /* Make sure VLAN Filters are off */ 3383 rctl &= ~E1000_RCTL_VFE; 3384 3385 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3386 if (hw->mac.type < igb_mac_min) { 3387 if (adapter->rx_mbuf_sz > 2048 && adapter->rx_mbuf_sz <= 4096) 3388 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3389 else if (adapter->rx_mbuf_sz > 4096 && adapter->rx_mbuf_sz <= 8192) 3390 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3391 else if (adapter->rx_mbuf_sz > 8192) 3392 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3393 else { 3394 rctl |= E1000_RCTL_SZ_2048; 3395 rctl &= ~E1000_RCTL_BSEX; 3396 } 3397 } else 3398 rctl |= E1000_RCTL_SZ_2048; 3399 3400 /* 3401 * rctl bits 11:10 are as follows 3402 * lem: reserved 3403 * em: DTYPE 3404 * igb: reserved 3405 * and should be 00 on all of the above 3406 */ 3407 rctl &= ~0x00000C00; 3408 3409 /* Write out the settings */ 3410 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3411 3412 return; 3413 } 3414 3415 static void 3416 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3417 { 3418 struct adapter *adapter = iflib_get_softc(ctx); 3419 u32 index, bit; 3420 3421 index = (vtag >> 5) & 0x7F; 3422 bit = vtag & 0x1F; 3423 adapter->shadow_vfta[index] |= (1 << bit); 3424 ++adapter->num_vlans; 3425 em_if_vlan_filter_write(adapter); 3426 } 3427 3428 static void 3429 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3430 { 3431 struct adapter *adapter = iflib_get_softc(ctx); 3432 u32 index, bit; 3433 3434 index = (vtag >> 5) & 0x7F; 3435 bit = vtag & 0x1F; 3436 adapter->shadow_vfta[index] &= ~(1 << bit); 3437 --adapter->num_vlans; 3438 em_if_vlan_filter_write(adapter); 3439 } 3440 3441 static bool 3442 em_if_vlan_filter_capable(struct adapter *adapter) 3443 { 3444 if_softc_ctx_t scctx = adapter->shared; 3445 3446 if ((scctx->isc_capenable & IFCAP_VLAN_HWFILTER) && 3447 !em_disable_crc_stripping) 3448 return (true); 3449 3450 return (false); 3451 } 3452 3453 static bool 3454 em_if_vlan_filter_used(struct adapter *adapter) 3455 { 3456 if (!em_if_vlan_filter_capable(adapter)) 3457 return (false); 3458 3459 for (int i = 0; i < EM_VFTA_SIZE; i++) 3460 if (adapter->shadow_vfta[i] != 0) 3461 return (true); 3462 3463 return (false); 3464 } 3465 3466 static void 3467 em_if_vlan_filter_enable(struct adapter *adapter) 3468 { 3469 struct e1000_hw *hw = &adapter->hw; 3470 u32 reg; 3471 3472 reg = E1000_READ_REG(hw, E1000_RCTL); 3473 reg &= ~E1000_RCTL_CFIEN; 3474 reg |= E1000_RCTL_VFE; 3475 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3476 } 3477 3478 static void 3479 em_if_vlan_filter_disable(struct adapter *adapter) 3480 { 3481 struct e1000_hw *hw = &adapter->hw; 3482 u32 reg; 3483 3484 reg = E1000_READ_REG(hw, E1000_RCTL); 3485 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3486 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3487 } 3488 3489 static void 3490 em_if_vlan_filter_write(struct adapter *adapter) 3491 { 3492 struct e1000_hw *hw = &adapter->hw; 3493 3494 if (adapter->vf_ifp) 3495 return; 3496 3497 /* Disable interrupts for lem-class devices during the filter change */ 3498 if (hw->mac.type < em_mac_min) 3499 em_if_intr_disable(adapter->ctx); 3500 3501 for (int i = 0; i < EM_VFTA_SIZE; i++) 3502 if (adapter->shadow_vfta[i] != 0) { 3503 /* XXXKB: incomplete VF support, we return early above */ 3504 if (adapter->vf_ifp) 3505 e1000_vfta_set_vf(hw, adapter->shadow_vfta[i], TRUE); 3506 else 3507 e1000_write_vfta(hw, i, adapter->shadow_vfta[i]); 3508 } 3509 3510 /* Re-enable interrupts for lem-class devices */ 3511 if (hw->mac.type < em_mac_min) 3512 em_if_intr_enable(adapter->ctx); 3513 } 3514 3515 static void 3516 em_setup_vlan_hw_support(struct adapter *adapter) 3517 { 3518 if_softc_ctx_t scctx = adapter->shared; 3519 struct e1000_hw *hw = &adapter->hw; 3520 u32 reg; 3521 3522 /* XXXKB: Return early if we are a VF until VF decap and filter management 3523 * is ready and tested. 3524 */ 3525 if (adapter->vf_ifp) 3526 return; 3527 3528 if (scctx->isc_capenable & IFCAP_VLAN_HWTAGGING && 3529 !em_disable_crc_stripping) { 3530 reg = E1000_READ_REG(hw, E1000_CTRL); 3531 reg |= E1000_CTRL_VME; 3532 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3533 } else { 3534 reg = E1000_READ_REG(hw, E1000_CTRL); 3535 reg &= ~E1000_CTRL_VME; 3536 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3537 } 3538 3539 /* If we aren't doing HW filtering, we're done */ 3540 if (!em_if_vlan_filter_capable(adapter)) { 3541 em_if_vlan_filter_disable(adapter); 3542 return; 3543 } 3544 3545 /* 3546 * A soft reset zero's out the VFTA, so 3547 * we need to repopulate it now. 3548 */ 3549 em_if_vlan_filter_write(adapter); 3550 3551 /* Enable the Filter Table */ 3552 em_if_vlan_filter_enable(adapter); 3553 } 3554 3555 static void 3556 em_if_intr_enable(if_ctx_t ctx) 3557 { 3558 struct adapter *adapter = iflib_get_softc(ctx); 3559 struct e1000_hw *hw = &adapter->hw; 3560 u32 ims_mask = IMS_ENABLE_MASK; 3561 3562 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3563 E1000_WRITE_REG(hw, EM_EIAC, adapter->ims); 3564 ims_mask |= adapter->ims; 3565 } 3566 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3567 E1000_WRITE_FLUSH(hw); 3568 } 3569 3570 static void 3571 em_if_intr_disable(if_ctx_t ctx) 3572 { 3573 struct adapter *adapter = iflib_get_softc(ctx); 3574 struct e1000_hw *hw = &adapter->hw; 3575 3576 if (adapter->intr_type == IFLIB_INTR_MSIX) 3577 E1000_WRITE_REG(hw, EM_EIAC, 0); 3578 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3579 E1000_WRITE_FLUSH(hw); 3580 } 3581 3582 static void 3583 igb_if_intr_enable(if_ctx_t ctx) 3584 { 3585 struct adapter *adapter = iflib_get_softc(ctx); 3586 struct e1000_hw *hw = &adapter->hw; 3587 u32 mask; 3588 3589 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3590 mask = (adapter->que_mask | adapter->link_mask); 3591 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3592 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3593 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3594 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3595 } else 3596 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3597 E1000_WRITE_FLUSH(hw); 3598 } 3599 3600 static void 3601 igb_if_intr_disable(if_ctx_t ctx) 3602 { 3603 struct adapter *adapter = iflib_get_softc(ctx); 3604 struct e1000_hw *hw = &adapter->hw; 3605 3606 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3607 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3608 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3609 } 3610 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3611 E1000_WRITE_FLUSH(hw); 3612 } 3613 3614 /* 3615 * Bit of a misnomer, what this really means is 3616 * to enable OS management of the system... aka 3617 * to disable special hardware management features 3618 */ 3619 static void 3620 em_init_manageability(struct adapter *adapter) 3621 { 3622 /* A shared code workaround */ 3623 #define E1000_82542_MANC2H E1000_MANC2H 3624 if (adapter->has_manage) { 3625 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3626 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3627 3628 /* disable hardware interception of ARP */ 3629 manc &= ~(E1000_MANC_ARP_EN); 3630 3631 /* enable receiving management packets to the host */ 3632 manc |= E1000_MANC_EN_MNG2HOST; 3633 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3634 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3635 manc2h |= E1000_MNG2HOST_PORT_623; 3636 manc2h |= E1000_MNG2HOST_PORT_664; 3637 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3638 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3639 } 3640 } 3641 3642 /* 3643 * Give control back to hardware management 3644 * controller if there is one. 3645 */ 3646 static void 3647 em_release_manageability(struct adapter *adapter) 3648 { 3649 if (adapter->has_manage) { 3650 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3651 3652 /* re-enable hardware interception of ARP */ 3653 manc |= E1000_MANC_ARP_EN; 3654 manc &= ~E1000_MANC_EN_MNG2HOST; 3655 3656 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3657 } 3658 } 3659 3660 /* 3661 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3662 * For ASF and Pass Through versions of f/w this means 3663 * that the driver is loaded. For AMT version type f/w 3664 * this means that the network i/f is open. 3665 */ 3666 static void 3667 em_get_hw_control(struct adapter *adapter) 3668 { 3669 u32 ctrl_ext, swsm; 3670 3671 if (adapter->vf_ifp) 3672 return; 3673 3674 if (adapter->hw.mac.type == e1000_82573) { 3675 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3676 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3677 swsm | E1000_SWSM_DRV_LOAD); 3678 return; 3679 } 3680 /* else */ 3681 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3682 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3683 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3684 } 3685 3686 /* 3687 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3688 * For ASF and Pass Through versions of f/w this means that 3689 * the driver is no longer loaded. For AMT versions of the 3690 * f/w this means that the network i/f is closed. 3691 */ 3692 static void 3693 em_release_hw_control(struct adapter *adapter) 3694 { 3695 u32 ctrl_ext, swsm; 3696 3697 if (!adapter->has_manage) 3698 return; 3699 3700 if (adapter->hw.mac.type == e1000_82573) { 3701 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3702 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3703 swsm & ~E1000_SWSM_DRV_LOAD); 3704 return; 3705 } 3706 /* else */ 3707 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3708 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3709 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3710 return; 3711 } 3712 3713 static int 3714 em_is_valid_ether_addr(u8 *addr) 3715 { 3716 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3717 3718 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3719 return (FALSE); 3720 } 3721 3722 return (TRUE); 3723 } 3724 3725 /* 3726 ** Parse the interface capabilities with regard 3727 ** to both system management and wake-on-lan for 3728 ** later use. 3729 */ 3730 static void 3731 em_get_wakeup(if_ctx_t ctx) 3732 { 3733 struct adapter *adapter = iflib_get_softc(ctx); 3734 device_t dev = iflib_get_dev(ctx); 3735 u16 eeprom_data = 0, device_id, apme_mask; 3736 3737 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3738 apme_mask = EM_EEPROM_APME; 3739 3740 switch (adapter->hw.mac.type) { 3741 case e1000_82542: 3742 case e1000_82543: 3743 break; 3744 case e1000_82544: 3745 e1000_read_nvm(&adapter->hw, 3746 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3747 apme_mask = EM_82544_APME; 3748 break; 3749 case e1000_82546: 3750 case e1000_82546_rev_3: 3751 if (adapter->hw.bus.func == 1) { 3752 e1000_read_nvm(&adapter->hw, 3753 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3754 break; 3755 } else 3756 e1000_read_nvm(&adapter->hw, 3757 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3758 break; 3759 case e1000_82573: 3760 case e1000_82583: 3761 adapter->has_amt = TRUE; 3762 /* FALLTHROUGH */ 3763 case e1000_82571: 3764 case e1000_82572: 3765 case e1000_80003es2lan: 3766 if (adapter->hw.bus.func == 1) { 3767 e1000_read_nvm(&adapter->hw, 3768 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3769 break; 3770 } else 3771 e1000_read_nvm(&adapter->hw, 3772 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3773 break; 3774 case e1000_ich8lan: 3775 case e1000_ich9lan: 3776 case e1000_ich10lan: 3777 case e1000_pchlan: 3778 case e1000_pch2lan: 3779 case e1000_pch_lpt: 3780 case e1000_pch_spt: 3781 case e1000_82575: /* listing all igb devices */ 3782 case e1000_82576: 3783 case e1000_82580: 3784 case e1000_i350: 3785 case e1000_i354: 3786 case e1000_i210: 3787 case e1000_i211: 3788 case e1000_vfadapt: 3789 case e1000_vfadapt_i350: 3790 apme_mask = E1000_WUC_APME; 3791 adapter->has_amt = TRUE; 3792 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3793 break; 3794 default: 3795 e1000_read_nvm(&adapter->hw, 3796 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3797 break; 3798 } 3799 if (eeprom_data & apme_mask) 3800 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3801 /* 3802 * We have the eeprom settings, now apply the special cases 3803 * where the eeprom may be wrong or the board won't support 3804 * wake on lan on a particular port 3805 */ 3806 device_id = pci_get_device(dev); 3807 switch (device_id) { 3808 case E1000_DEV_ID_82546GB_PCIE: 3809 adapter->wol = 0; 3810 break; 3811 case E1000_DEV_ID_82546EB_FIBER: 3812 case E1000_DEV_ID_82546GB_FIBER: 3813 /* Wake events only supported on port A for dual fiber 3814 * regardless of eeprom setting */ 3815 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3816 E1000_STATUS_FUNC_1) 3817 adapter->wol = 0; 3818 break; 3819 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3820 /* if quad port adapter, disable WoL on all but port A */ 3821 if (global_quad_port_a != 0) 3822 adapter->wol = 0; 3823 /* Reset for multiple quad port adapters */ 3824 if (++global_quad_port_a == 4) 3825 global_quad_port_a = 0; 3826 break; 3827 case E1000_DEV_ID_82571EB_FIBER: 3828 /* Wake events only supported on port A for dual fiber 3829 * regardless of eeprom setting */ 3830 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3831 E1000_STATUS_FUNC_1) 3832 adapter->wol = 0; 3833 break; 3834 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3835 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3836 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3837 /* if quad port adapter, disable WoL on all but port A */ 3838 if (global_quad_port_a != 0) 3839 adapter->wol = 0; 3840 /* Reset for multiple quad port adapters */ 3841 if (++global_quad_port_a == 4) 3842 global_quad_port_a = 0; 3843 break; 3844 } 3845 return; 3846 } 3847 3848 3849 /* 3850 * Enable PCI Wake On Lan capability 3851 */ 3852 static void 3853 em_enable_wakeup(if_ctx_t ctx) 3854 { 3855 struct adapter *adapter = iflib_get_softc(ctx); 3856 device_t dev = iflib_get_dev(ctx); 3857 if_t ifp = iflib_get_ifp(ctx); 3858 int error = 0; 3859 u32 pmc, ctrl, ctrl_ext, rctl; 3860 u16 status; 3861 3862 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3863 return; 3864 3865 /* 3866 * Determine type of Wakeup: note that wol 3867 * is set with all bits on by default. 3868 */ 3869 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3870 adapter->wol &= ~E1000_WUFC_MAG; 3871 3872 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3873 adapter->wol &= ~E1000_WUFC_EX; 3874 3875 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3876 adapter->wol &= ~E1000_WUFC_MC; 3877 else { 3878 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3879 rctl |= E1000_RCTL_MPE; 3880 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3881 } 3882 3883 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) { 3884 if (adapter->hw.mac.type >= e1000_pch_lpt) { 3885 e1000_enable_ulp_lpt_lp(&adapter->hw, TRUE); 3886 } 3887 goto pme; 3888 } 3889 3890 /* Advertise the wakeup capability */ 3891 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3892 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3893 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3894 3895 /* Keep the laser running on Fiber adapters */ 3896 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3897 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3898 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3899 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3900 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3901 } 3902 3903 if ((adapter->hw.mac.type == e1000_ich8lan) || 3904 (adapter->hw.mac.type == e1000_pchlan) || 3905 (adapter->hw.mac.type == e1000_ich9lan) || 3906 (adapter->hw.mac.type == e1000_ich10lan)) 3907 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3908 3909 if ( adapter->hw.mac.type >= e1000_pchlan) { 3910 error = em_enable_phy_wakeup(adapter); 3911 if (error) 3912 goto pme; 3913 } else { 3914 /* Enable wakeup by the MAC */ 3915 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3916 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3917 } 3918 3919 if (adapter->hw.phy.type == e1000_phy_igp_3) 3920 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3921 3922 pme: 3923 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3924 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3925 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3926 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3927 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3928 3929 return; 3930 } 3931 3932 /* 3933 * WOL in the newer chipset interfaces (pchlan) 3934 * require thing to be copied into the phy 3935 */ 3936 static int 3937 em_enable_phy_wakeup(struct adapter *adapter) 3938 { 3939 struct e1000_hw *hw = &adapter->hw; 3940 u32 mreg, ret = 0; 3941 u16 preg; 3942 3943 /* copy MAC RARs to PHY RARs */ 3944 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3945 3946 /* copy MAC MTA to PHY MTA */ 3947 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3948 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3949 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3950 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3951 (u16)((mreg >> 16) & 0xFFFF)); 3952 } 3953 3954 /* configure PHY Rx Control register */ 3955 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3956 mreg = E1000_READ_REG(hw, E1000_RCTL); 3957 if (mreg & E1000_RCTL_UPE) 3958 preg |= BM_RCTL_UPE; 3959 if (mreg & E1000_RCTL_MPE) 3960 preg |= BM_RCTL_MPE; 3961 preg &= ~(BM_RCTL_MO_MASK); 3962 if (mreg & E1000_RCTL_MO_3) 3963 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3964 << BM_RCTL_MO_SHIFT); 3965 if (mreg & E1000_RCTL_BAM) 3966 preg |= BM_RCTL_BAM; 3967 if (mreg & E1000_RCTL_PMCF) 3968 preg |= BM_RCTL_PMCF; 3969 mreg = E1000_READ_REG(hw, E1000_CTRL); 3970 if (mreg & E1000_CTRL_RFCE) 3971 preg |= BM_RCTL_RFCE; 3972 e1000_write_phy_reg(hw, BM_RCTL, preg); 3973 3974 /* enable PHY wakeup in MAC register */ 3975 E1000_WRITE_REG(hw, E1000_WUC, 3976 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3977 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3978 3979 /* configure and enable PHY wakeup in PHY registers */ 3980 e1000_write_phy_reg(hw, BM_WUFC, adapter->wol); 3981 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3982 3983 /* activate PHY wakeup */ 3984 ret = hw->phy.ops.acquire(hw); 3985 if (ret) { 3986 printf("Could not acquire PHY\n"); 3987 return ret; 3988 } 3989 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3990 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3991 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3992 if (ret) { 3993 printf("Could not read PHY page 769\n"); 3994 goto out; 3995 } 3996 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3997 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3998 if (ret) 3999 printf("Could not set PHY Host Wakeup bit\n"); 4000 out: 4001 hw->phy.ops.release(hw); 4002 4003 return ret; 4004 } 4005 4006 static void 4007 em_if_led_func(if_ctx_t ctx, int onoff) 4008 { 4009 struct adapter *adapter = iflib_get_softc(ctx); 4010 4011 if (onoff) { 4012 e1000_setup_led(&adapter->hw); 4013 e1000_led_on(&adapter->hw); 4014 } else { 4015 e1000_led_off(&adapter->hw); 4016 e1000_cleanup_led(&adapter->hw); 4017 } 4018 } 4019 4020 /* 4021 * Disable the L0S and L1 LINK states 4022 */ 4023 static void 4024 em_disable_aspm(struct adapter *adapter) 4025 { 4026 int base, reg; 4027 u16 link_cap,link_ctrl; 4028 device_t dev = adapter->dev; 4029 4030 switch (adapter->hw.mac.type) { 4031 case e1000_82573: 4032 case e1000_82574: 4033 case e1000_82583: 4034 break; 4035 default: 4036 return; 4037 } 4038 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4039 return; 4040 reg = base + PCIER_LINK_CAP; 4041 link_cap = pci_read_config(dev, reg, 2); 4042 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4043 return; 4044 reg = base + PCIER_LINK_CTL; 4045 link_ctrl = pci_read_config(dev, reg, 2); 4046 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4047 pci_write_config(dev, reg, link_ctrl, 2); 4048 return; 4049 } 4050 4051 /********************************************************************** 4052 * 4053 * Update the board statistics counters. 4054 * 4055 **********************************************************************/ 4056 static void 4057 em_update_stats_counters(struct adapter *adapter) 4058 { 4059 u64 prev_xoffrxc = adapter->stats.xoffrxc; 4060 4061 if(adapter->hw.phy.media_type == e1000_media_type_copper || 4062 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4063 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 4064 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 4065 } 4066 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 4067 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 4068 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 4069 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 4070 4071 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 4072 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 4073 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 4074 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 4075 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 4076 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 4077 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 4078 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 4079 /* 4080 ** For watchdog management we need to know if we have been 4081 ** paused during the last interval, so capture that here. 4082 */ 4083 if (adapter->stats.xoffrxc != prev_xoffrxc) 4084 adapter->shared->isc_pause_frames = 1; 4085 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4086 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4087 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4088 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4089 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4090 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4091 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4092 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4093 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 4094 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 4095 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 4096 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 4097 4098 /* For the 64-bit byte counters the low dword must be read first. */ 4099 /* Both registers clear on the read of the high dword */ 4100 4101 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 4102 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 4103 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 4104 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 4105 4106 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 4107 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 4108 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 4109 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 4110 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 4111 4112 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 4113 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 4114 4115 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 4116 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 4117 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 4118 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 4119 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 4120 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 4121 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 4122 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 4123 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 4124 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 4125 4126 /* Interrupt Counts */ 4127 4128 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 4129 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 4130 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 4131 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 4132 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 4133 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 4134 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 4135 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 4136 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 4137 4138 if (adapter->hw.mac.type >= e1000_82543) { 4139 adapter->stats.algnerrc += 4140 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4141 adapter->stats.rxerrc += 4142 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4143 adapter->stats.tncrs += 4144 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4145 adapter->stats.cexterr += 4146 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4147 adapter->stats.tsctc += 4148 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4149 adapter->stats.tsctfc += 4150 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4151 } 4152 } 4153 4154 static uint64_t 4155 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4156 { 4157 struct adapter *adapter = iflib_get_softc(ctx); 4158 struct ifnet *ifp = iflib_get_ifp(ctx); 4159 4160 switch (cnt) { 4161 case IFCOUNTER_COLLISIONS: 4162 return (adapter->stats.colc); 4163 case IFCOUNTER_IERRORS: 4164 return (adapter->dropped_pkts + adapter->stats.rxerrc + 4165 adapter->stats.crcerrs + adapter->stats.algnerrc + 4166 adapter->stats.ruc + adapter->stats.roc + 4167 adapter->stats.mpc + adapter->stats.cexterr); 4168 case IFCOUNTER_OERRORS: 4169 return (adapter->stats.ecol + adapter->stats.latecol + 4170 adapter->watchdog_events); 4171 default: 4172 return (if_get_counter_default(ifp, cnt)); 4173 } 4174 } 4175 4176 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4177 * @ctx: iflib context 4178 * @event: event code to check 4179 * 4180 * Defaults to returning true for unknown events. 4181 * 4182 * @returns true if iflib needs to reinit the interface 4183 */ 4184 static bool 4185 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4186 { 4187 switch (event) { 4188 case IFLIB_RESTART_VLAN_CONFIG: 4189 return (false); 4190 default: 4191 return (true); 4192 } 4193 } 4194 4195 /* Export a single 32-bit register via a read-only sysctl. */ 4196 static int 4197 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4198 { 4199 struct adapter *adapter; 4200 u_int val; 4201 4202 adapter = oidp->oid_arg1; 4203 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 4204 return (sysctl_handle_int(oidp, &val, 0, req)); 4205 } 4206 4207 /* 4208 * Add sysctl variables, one per statistic, to the system. 4209 */ 4210 static void 4211 em_add_hw_stats(struct adapter *adapter) 4212 { 4213 device_t dev = iflib_get_dev(adapter->ctx); 4214 struct em_tx_queue *tx_que = adapter->tx_queues; 4215 struct em_rx_queue *rx_que = adapter->rx_queues; 4216 4217 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4218 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4219 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4220 struct e1000_hw_stats *stats = &adapter->stats; 4221 4222 struct sysctl_oid *stat_node, *queue_node, *int_node; 4223 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4224 4225 #define QUEUE_NAME_LEN 32 4226 char namebuf[QUEUE_NAME_LEN]; 4227 4228 /* Driver Statistics */ 4229 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4230 CTLFLAG_RD, &adapter->dropped_pkts, 4231 "Driver dropped packets"); 4232 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4233 CTLFLAG_RD, &adapter->link_irq, 4234 "Link MSI-X IRQ Handled"); 4235 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4236 CTLFLAG_RD, &adapter->rx_overruns, 4237 "RX overruns"); 4238 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4239 CTLFLAG_RD, &adapter->watchdog_events, 4240 "Watchdog timeouts"); 4241 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4242 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4243 adapter, E1000_CTRL, em_sysctl_reg_handler, "IU", 4244 "Device Control Register"); 4245 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4246 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4247 adapter, E1000_RCTL, em_sysctl_reg_handler, "IU", 4248 "Receiver Control Register"); 4249 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4250 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4251 "Flow Control High Watermark"); 4252 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4253 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4254 "Flow Control Low Watermark"); 4255 4256 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4257 struct tx_ring *txr = &tx_que->txr; 4258 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4259 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4260 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4261 queue_list = SYSCTL_CHILDREN(queue_node); 4262 4263 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4264 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4265 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4266 "Transmit Descriptor Head"); 4267 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4268 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4269 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4270 "Transmit Descriptor Tail"); 4271 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4272 CTLFLAG_RD, &txr->tx_irq, 4273 "Queue MSI-X Transmit Interrupts"); 4274 } 4275 4276 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4277 struct rx_ring *rxr = &rx_que->rxr; 4278 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4279 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4280 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4281 queue_list = SYSCTL_CHILDREN(queue_node); 4282 4283 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4284 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4285 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4286 "Receive Descriptor Head"); 4287 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4288 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4289 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4290 "Receive Descriptor Tail"); 4291 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4292 CTLFLAG_RD, &rxr->rx_irq, 4293 "Queue MSI-X Receive Interrupts"); 4294 } 4295 4296 /* MAC stats get their own sub node */ 4297 4298 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4299 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4300 stat_list = SYSCTL_CHILDREN(stat_node); 4301 4302 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4303 CTLFLAG_RD, &stats->ecol, 4304 "Excessive collisions"); 4305 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4306 CTLFLAG_RD, &stats->scc, 4307 "Single collisions"); 4308 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4309 CTLFLAG_RD, &stats->mcc, 4310 "Multiple collisions"); 4311 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4312 CTLFLAG_RD, &stats->latecol, 4313 "Late collisions"); 4314 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4315 CTLFLAG_RD, &stats->colc, 4316 "Collision Count"); 4317 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4318 CTLFLAG_RD, &adapter->stats.symerrs, 4319 "Symbol Errors"); 4320 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4321 CTLFLAG_RD, &adapter->stats.sec, 4322 "Sequence Errors"); 4323 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4324 CTLFLAG_RD, &adapter->stats.dc, 4325 "Defer Count"); 4326 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4327 CTLFLAG_RD, &adapter->stats.mpc, 4328 "Missed Packets"); 4329 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4330 CTLFLAG_RD, &adapter->stats.rnbc, 4331 "Receive No Buffers"); 4332 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4333 CTLFLAG_RD, &adapter->stats.ruc, 4334 "Receive Undersize"); 4335 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4336 CTLFLAG_RD, &adapter->stats.rfc, 4337 "Fragmented Packets Received "); 4338 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4339 CTLFLAG_RD, &adapter->stats.roc, 4340 "Oversized Packets Received"); 4341 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4342 CTLFLAG_RD, &adapter->stats.rjc, 4343 "Recevied Jabber"); 4344 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4345 CTLFLAG_RD, &adapter->stats.rxerrc, 4346 "Receive Errors"); 4347 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4348 CTLFLAG_RD, &adapter->stats.crcerrs, 4349 "CRC errors"); 4350 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4351 CTLFLAG_RD, &adapter->stats.algnerrc, 4352 "Alignment Errors"); 4353 /* On 82575 these are collision counts */ 4354 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4355 CTLFLAG_RD, &adapter->stats.cexterr, 4356 "Collision/Carrier extension errors"); 4357 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4358 CTLFLAG_RD, &adapter->stats.xonrxc, 4359 "XON Received"); 4360 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4361 CTLFLAG_RD, &adapter->stats.xontxc, 4362 "XON Transmitted"); 4363 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4364 CTLFLAG_RD, &adapter->stats.xoffrxc, 4365 "XOFF Received"); 4366 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4367 CTLFLAG_RD, &adapter->stats.xofftxc, 4368 "XOFF Transmitted"); 4369 4370 /* Packet Reception Stats */ 4371 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4372 CTLFLAG_RD, &adapter->stats.tpr, 4373 "Total Packets Received "); 4374 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4375 CTLFLAG_RD, &adapter->stats.gprc, 4376 "Good Packets Received"); 4377 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4378 CTLFLAG_RD, &adapter->stats.bprc, 4379 "Broadcast Packets Received"); 4380 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4381 CTLFLAG_RD, &adapter->stats.mprc, 4382 "Multicast Packets Received"); 4383 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4384 CTLFLAG_RD, &adapter->stats.prc64, 4385 "64 byte frames received "); 4386 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4387 CTLFLAG_RD, &adapter->stats.prc127, 4388 "65-127 byte frames received"); 4389 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4390 CTLFLAG_RD, &adapter->stats.prc255, 4391 "128-255 byte frames received"); 4392 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4393 CTLFLAG_RD, &adapter->stats.prc511, 4394 "256-511 byte frames received"); 4395 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4396 CTLFLAG_RD, &adapter->stats.prc1023, 4397 "512-1023 byte frames received"); 4398 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4399 CTLFLAG_RD, &adapter->stats.prc1522, 4400 "1023-1522 byte frames received"); 4401 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4402 CTLFLAG_RD, &adapter->stats.gorc, 4403 "Good Octets Received"); 4404 4405 /* Packet Transmission Stats */ 4406 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4407 CTLFLAG_RD, &adapter->stats.gotc, 4408 "Good Octets Transmitted"); 4409 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4410 CTLFLAG_RD, &adapter->stats.tpt, 4411 "Total Packets Transmitted"); 4412 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4413 CTLFLAG_RD, &adapter->stats.gptc, 4414 "Good Packets Transmitted"); 4415 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4416 CTLFLAG_RD, &adapter->stats.bptc, 4417 "Broadcast Packets Transmitted"); 4418 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4419 CTLFLAG_RD, &adapter->stats.mptc, 4420 "Multicast Packets Transmitted"); 4421 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4422 CTLFLAG_RD, &adapter->stats.ptc64, 4423 "64 byte frames transmitted "); 4424 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4425 CTLFLAG_RD, &adapter->stats.ptc127, 4426 "65-127 byte frames transmitted"); 4427 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4428 CTLFLAG_RD, &adapter->stats.ptc255, 4429 "128-255 byte frames transmitted"); 4430 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4431 CTLFLAG_RD, &adapter->stats.ptc511, 4432 "256-511 byte frames transmitted"); 4433 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4434 CTLFLAG_RD, &adapter->stats.ptc1023, 4435 "512-1023 byte frames transmitted"); 4436 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4437 CTLFLAG_RD, &adapter->stats.ptc1522, 4438 "1024-1522 byte frames transmitted"); 4439 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4440 CTLFLAG_RD, &adapter->stats.tsctc, 4441 "TSO Contexts Transmitted"); 4442 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4443 CTLFLAG_RD, &adapter->stats.tsctfc, 4444 "TSO Contexts Failed"); 4445 4446 4447 /* Interrupt Stats */ 4448 4449 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4450 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4451 int_list = SYSCTL_CHILDREN(int_node); 4452 4453 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4454 CTLFLAG_RD, &adapter->stats.iac, 4455 "Interrupt Assertion Count"); 4456 4457 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4458 CTLFLAG_RD, &adapter->stats.icrxptc, 4459 "Interrupt Cause Rx Pkt Timer Expire Count"); 4460 4461 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4462 CTLFLAG_RD, &adapter->stats.icrxatc, 4463 "Interrupt Cause Rx Abs Timer Expire Count"); 4464 4465 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4466 CTLFLAG_RD, &adapter->stats.ictxptc, 4467 "Interrupt Cause Tx Pkt Timer Expire Count"); 4468 4469 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4470 CTLFLAG_RD, &adapter->stats.ictxatc, 4471 "Interrupt Cause Tx Abs Timer Expire Count"); 4472 4473 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4474 CTLFLAG_RD, &adapter->stats.ictxqec, 4475 "Interrupt Cause Tx Queue Empty Count"); 4476 4477 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4478 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4479 "Interrupt Cause Tx Queue Min Thresh Count"); 4480 4481 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4482 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4483 "Interrupt Cause Rx Desc Min Thresh Count"); 4484 4485 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4486 CTLFLAG_RD, &adapter->stats.icrxoc, 4487 "Interrupt Cause Receiver Overrun Count"); 4488 } 4489 4490 /********************************************************************** 4491 * 4492 * This routine provides a way to dump out the adapter eeprom, 4493 * often a useful debug/service tool. This only dumps the first 4494 * 32 words, stuff that matters is in that extent. 4495 * 4496 **********************************************************************/ 4497 static int 4498 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4499 { 4500 struct adapter *adapter = (struct adapter *)arg1; 4501 int error; 4502 int result; 4503 4504 result = -1; 4505 error = sysctl_handle_int(oidp, &result, 0, req); 4506 4507 if (error || !req->newptr) 4508 return (error); 4509 4510 /* 4511 * This value will cause a hex dump of the 4512 * first 32 16-bit words of the EEPROM to 4513 * the screen. 4514 */ 4515 if (result == 1) 4516 em_print_nvm_info(adapter); 4517 4518 return (error); 4519 } 4520 4521 static void 4522 em_print_nvm_info(struct adapter *adapter) 4523 { 4524 u16 eeprom_data; 4525 int i, j, row = 0; 4526 4527 /* Its a bit crude, but it gets the job done */ 4528 printf("\nInterface EEPROM Dump:\n"); 4529 printf("Offset\n0x0000 "); 4530 for (i = 0, j = 0; i < 32; i++, j++) { 4531 if (j == 8) { /* Make the offset block */ 4532 j = 0; ++row; 4533 printf("\n0x00%x0 ",row); 4534 } 4535 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4536 printf("%04x ", eeprom_data); 4537 } 4538 printf("\n"); 4539 } 4540 4541 static int 4542 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4543 { 4544 struct em_int_delay_info *info; 4545 struct adapter *adapter; 4546 u32 regval; 4547 int error, usecs, ticks; 4548 4549 info = (struct em_int_delay_info *) arg1; 4550 usecs = info->value; 4551 error = sysctl_handle_int(oidp, &usecs, 0, req); 4552 if (error != 0 || req->newptr == NULL) 4553 return (error); 4554 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4555 return (EINVAL); 4556 info->value = usecs; 4557 ticks = EM_USECS_TO_TICKS(usecs); 4558 if (info->offset == E1000_ITR) /* units are 256ns here */ 4559 ticks *= 4; 4560 4561 adapter = info->adapter; 4562 4563 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4564 regval = (regval & ~0xffff) | (ticks & 0xffff); 4565 /* Handle a few special cases. */ 4566 switch (info->offset) { 4567 case E1000_RDTR: 4568 break; 4569 case E1000_TIDV: 4570 if (ticks == 0) { 4571 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4572 /* Don't write 0 into the TIDV register. */ 4573 regval++; 4574 } else 4575 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4576 break; 4577 } 4578 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4579 return (0); 4580 } 4581 4582 static void 4583 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4584 const char *description, struct em_int_delay_info *info, 4585 int offset, int value) 4586 { 4587 info->adapter = adapter; 4588 info->offset = offset; 4589 info->value = value; 4590 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4591 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4592 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4593 info, 0, em_sysctl_int_delay, "I", description); 4594 } 4595 4596 /* 4597 * Set flow control using sysctl: 4598 * Flow control values: 4599 * 0 - off 4600 * 1 - rx pause 4601 * 2 - tx pause 4602 * 3 - full 4603 */ 4604 static int 4605 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4606 { 4607 int error; 4608 static int input = 3; /* default is full */ 4609 struct adapter *adapter = (struct adapter *) arg1; 4610 4611 error = sysctl_handle_int(oidp, &input, 0, req); 4612 4613 if ((error) || (req->newptr == NULL)) 4614 return (error); 4615 4616 if (input == adapter->fc) /* no change? */ 4617 return (error); 4618 4619 switch (input) { 4620 case e1000_fc_rx_pause: 4621 case e1000_fc_tx_pause: 4622 case e1000_fc_full: 4623 case e1000_fc_none: 4624 adapter->hw.fc.requested_mode = input; 4625 adapter->fc = input; 4626 break; 4627 default: 4628 /* Do nothing */ 4629 return (error); 4630 } 4631 4632 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4633 e1000_force_mac_fc(&adapter->hw); 4634 return (error); 4635 } 4636 4637 /* 4638 * Manage Energy Efficient Ethernet: 4639 * Control values: 4640 * 0/1 - enabled/disabled 4641 */ 4642 static int 4643 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4644 { 4645 struct adapter *adapter = (struct adapter *) arg1; 4646 int error, value; 4647 4648 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4649 error = sysctl_handle_int(oidp, &value, 0, req); 4650 if (error || req->newptr == NULL) 4651 return (error); 4652 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4653 em_if_init(adapter->ctx); 4654 4655 return (0); 4656 } 4657 4658 static int 4659 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4660 { 4661 struct adapter *adapter; 4662 int error; 4663 int result; 4664 4665 result = -1; 4666 error = sysctl_handle_int(oidp, &result, 0, req); 4667 4668 if (error || !req->newptr) 4669 return (error); 4670 4671 if (result == 1) { 4672 adapter = (struct adapter *) arg1; 4673 em_print_debug_info(adapter); 4674 } 4675 4676 return (error); 4677 } 4678 4679 static int 4680 em_get_rs(SYSCTL_HANDLER_ARGS) 4681 { 4682 struct adapter *adapter = (struct adapter *) arg1; 4683 int error; 4684 int result; 4685 4686 result = 0; 4687 error = sysctl_handle_int(oidp, &result, 0, req); 4688 4689 if (error || !req->newptr || result != 1) 4690 return (error); 4691 em_dump_rs(adapter); 4692 4693 return (error); 4694 } 4695 4696 static void 4697 em_if_debug(if_ctx_t ctx) 4698 { 4699 em_dump_rs(iflib_get_softc(ctx)); 4700 } 4701 4702 /* 4703 * This routine is meant to be fluid, add whatever is 4704 * needed for debugging a problem. -jfv 4705 */ 4706 static void 4707 em_print_debug_info(struct adapter *adapter) 4708 { 4709 device_t dev = iflib_get_dev(adapter->ctx); 4710 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4711 struct tx_ring *txr = &adapter->tx_queues->txr; 4712 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4713 4714 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4715 printf("Interface is RUNNING "); 4716 else 4717 printf("Interface is NOT RUNNING\n"); 4718 4719 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4720 printf("and INACTIVE\n"); 4721 else 4722 printf("and ACTIVE\n"); 4723 4724 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4725 device_printf(dev, "TX Queue %d ------\n", i); 4726 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4727 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4728 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4729 4730 } 4731 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4732 device_printf(dev, "RX Queue %d ------\n", j); 4733 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4734 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4735 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4736 } 4737 } 4738 4739 /* 4740 * 82574 only: 4741 * Write a new value to the EEPROM increasing the number of MSI-X 4742 * vectors from 3 to 5, for proper multiqueue support. 4743 */ 4744 static void 4745 em_enable_vectors_82574(if_ctx_t ctx) 4746 { 4747 struct adapter *adapter = iflib_get_softc(ctx); 4748 struct e1000_hw *hw = &adapter->hw; 4749 device_t dev = iflib_get_dev(ctx); 4750 u16 edata; 4751 4752 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4753 if (bootverbose) 4754 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4755 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4756 device_printf(dev, "Writing to eeprom: increasing " 4757 "reported MSI-X vectors from 3 to 5...\n"); 4758 edata &= ~(EM_NVM_MSIX_N_MASK); 4759 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4760 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4761 e1000_update_nvm_checksum(hw); 4762 device_printf(dev, "Writing to eeprom: done\n"); 4763 } 4764 } 4765