1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) - lem-class legacy devices */ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 98 99 /* Intel(R) - em-class devices */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 197 /* required last entry */ 198 PVID_END 199 }; 200 201 static pci_vendor_info_t igb_vendor_info_array[] = 202 { 203 /* Intel(R) - igb-class devices */ 204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 238 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 239 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 240 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 242 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 244 /* required last entry */ 245 PVID_END 246 }; 247 248 /********************************************************************* 249 * Function prototypes 250 *********************************************************************/ 251 static void *em_register(device_t); 252 static void *igb_register(device_t); 253 static int em_if_attach_pre(if_ctx_t); 254 static int em_if_attach_post(if_ctx_t); 255 static int em_if_detach(if_ctx_t); 256 static int em_if_shutdown(if_ctx_t); 257 static int em_if_suspend(if_ctx_t); 258 static int em_if_resume(if_ctx_t); 259 260 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 261 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 262 static void em_if_queues_free(if_ctx_t); 263 264 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 265 static void em_if_init(if_ctx_t); 266 static void em_if_stop(if_ctx_t); 267 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 268 static int em_if_media_change(if_ctx_t); 269 static int em_if_mtu_set(if_ctx_t, uint32_t); 270 static void em_if_timer(if_ctx_t, uint16_t); 271 static void em_if_vlan_register(if_ctx_t, u16); 272 static void em_if_vlan_unregister(if_ctx_t, u16); 273 static void em_if_watchdog_reset(if_ctx_t); 274 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 275 276 static void em_identify_hardware(if_ctx_t); 277 static int em_allocate_pci_resources(if_ctx_t); 278 static void em_free_pci_resources(if_ctx_t); 279 static void em_reset(if_ctx_t); 280 static int em_setup_interface(if_ctx_t); 281 static int em_setup_msix(if_ctx_t); 282 283 static void em_initialize_transmit_unit(if_ctx_t); 284 static void em_initialize_receive_unit(if_ctx_t); 285 286 static void em_if_intr_enable(if_ctx_t); 287 static void em_if_intr_disable(if_ctx_t); 288 static void igb_if_intr_enable(if_ctx_t); 289 static void igb_if_intr_disable(if_ctx_t); 290 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 291 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 292 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 293 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 294 static void em_if_multi_set(if_ctx_t); 295 static void em_if_update_admin_status(if_ctx_t); 296 static void em_if_debug(if_ctx_t); 297 static void em_update_stats_counters(struct e1000_softc *); 298 static void em_add_hw_stats(struct e1000_softc *); 299 static int em_if_set_promisc(if_ctx_t, int); 300 static bool em_if_vlan_filter_capable(if_ctx_t); 301 static bool em_if_vlan_filter_used(if_ctx_t); 302 static void em_if_vlan_filter_enable(struct e1000_softc *); 303 static void em_if_vlan_filter_disable(struct e1000_softc *); 304 static void em_if_vlan_filter_write(struct e1000_softc *); 305 static void em_setup_vlan_hw_support(if_ctx_t ctx); 306 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 307 static void em_print_nvm_info(struct e1000_softc *); 308 static void em_fw_version_locked(if_ctx_t); 309 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 310 static void em_print_fw_version(struct e1000_softc *); 311 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 312 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 313 static int em_get_rs(SYSCTL_HANDLER_ARGS); 314 static void em_print_debug_info(struct e1000_softc *); 315 static int em_is_valid_ether_addr(u8 *); 316 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 317 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 318 const char *, struct em_int_delay_info *, int, int); 319 /* Management and WOL Support */ 320 static void em_init_manageability(struct e1000_softc *); 321 static void em_release_manageability(struct e1000_softc *); 322 static void em_get_hw_control(struct e1000_softc *); 323 static void em_release_hw_control(struct e1000_softc *); 324 static void em_get_wakeup(if_ctx_t); 325 static void em_enable_wakeup(if_ctx_t); 326 static int em_enable_phy_wakeup(struct e1000_softc *); 327 static void em_disable_aspm(struct e1000_softc *); 328 329 int em_intr(void *); 330 331 /* MSI-X handlers */ 332 static int em_if_msix_intr_assign(if_ctx_t, int); 333 static int em_msix_link(void *); 334 static void em_handle_link(void *); 335 336 static void em_enable_vectors_82574(if_ctx_t); 337 338 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 339 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 340 static void em_if_led_func(if_ctx_t, int); 341 342 static int em_get_regs(SYSCTL_HANDLER_ARGS); 343 344 static void lem_smartspeed(struct e1000_softc *); 345 static void igb_configure_queues(struct e1000_softc *); 346 347 348 /********************************************************************* 349 * FreeBSD Device Interface Entry Points 350 *********************************************************************/ 351 static device_method_t em_methods[] = { 352 /* Device interface */ 353 DEVMETHOD(device_register, em_register), 354 DEVMETHOD(device_probe, iflib_device_probe), 355 DEVMETHOD(device_attach, iflib_device_attach), 356 DEVMETHOD(device_detach, iflib_device_detach), 357 DEVMETHOD(device_shutdown, iflib_device_shutdown), 358 DEVMETHOD(device_suspend, iflib_device_suspend), 359 DEVMETHOD(device_resume, iflib_device_resume), 360 DEVMETHOD_END 361 }; 362 363 static device_method_t igb_methods[] = { 364 /* Device interface */ 365 DEVMETHOD(device_register, igb_register), 366 DEVMETHOD(device_probe, iflib_device_probe), 367 DEVMETHOD(device_attach, iflib_device_attach), 368 DEVMETHOD(device_detach, iflib_device_detach), 369 DEVMETHOD(device_shutdown, iflib_device_shutdown), 370 DEVMETHOD(device_suspend, iflib_device_suspend), 371 DEVMETHOD(device_resume, iflib_device_resume), 372 DEVMETHOD_END 373 }; 374 375 376 static driver_t em_driver = { 377 "em", em_methods, sizeof(struct e1000_softc), 378 }; 379 380 static devclass_t em_devclass; 381 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 382 383 MODULE_DEPEND(em, pci, 1, 1, 1); 384 MODULE_DEPEND(em, ether, 1, 1, 1); 385 MODULE_DEPEND(em, iflib, 1, 1, 1); 386 387 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 388 389 static driver_t igb_driver = { 390 "igb", igb_methods, sizeof(struct e1000_softc), 391 }; 392 393 static devclass_t igb_devclass; 394 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 395 396 MODULE_DEPEND(igb, pci, 1, 1, 1); 397 MODULE_DEPEND(igb, ether, 1, 1, 1); 398 MODULE_DEPEND(igb, iflib, 1, 1, 1); 399 400 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 401 402 static device_method_t em_if_methods[] = { 403 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 404 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 405 DEVMETHOD(ifdi_detach, em_if_detach), 406 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 407 DEVMETHOD(ifdi_suspend, em_if_suspend), 408 DEVMETHOD(ifdi_resume, em_if_resume), 409 DEVMETHOD(ifdi_init, em_if_init), 410 DEVMETHOD(ifdi_stop, em_if_stop), 411 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 412 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 413 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 414 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 415 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 416 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 417 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 418 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 419 DEVMETHOD(ifdi_media_status, em_if_media_status), 420 DEVMETHOD(ifdi_media_change, em_if_media_change), 421 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 422 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 423 DEVMETHOD(ifdi_timer, em_if_timer), 424 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 425 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 426 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 427 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 428 DEVMETHOD(ifdi_led_func, em_if_led_func), 429 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 430 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 431 DEVMETHOD(ifdi_debug, em_if_debug), 432 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 433 DEVMETHOD_END 434 }; 435 436 static driver_t em_if_driver = { 437 "em_if", em_if_methods, sizeof(struct e1000_softc) 438 }; 439 440 static device_method_t igb_if_methods[] = { 441 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 442 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 443 DEVMETHOD(ifdi_detach, em_if_detach), 444 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 445 DEVMETHOD(ifdi_suspend, em_if_suspend), 446 DEVMETHOD(ifdi_resume, em_if_resume), 447 DEVMETHOD(ifdi_init, em_if_init), 448 DEVMETHOD(ifdi_stop, em_if_stop), 449 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 450 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 451 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 452 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 453 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 454 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 455 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 456 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 457 DEVMETHOD(ifdi_media_status, em_if_media_status), 458 DEVMETHOD(ifdi_media_change, em_if_media_change), 459 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 460 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 461 DEVMETHOD(ifdi_timer, em_if_timer), 462 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 463 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 464 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 465 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 466 DEVMETHOD(ifdi_led_func, em_if_led_func), 467 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 468 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 469 DEVMETHOD(ifdi_debug, em_if_debug), 470 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 471 DEVMETHOD_END 472 }; 473 474 static driver_t igb_if_driver = { 475 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 476 }; 477 478 /********************************************************************* 479 * Tunable default values. 480 *********************************************************************/ 481 482 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 483 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 484 485 #define MAX_INTS_PER_SEC 8000 486 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 487 488 /* Allow common code without TSO */ 489 #ifndef CSUM_TSO 490 #define CSUM_TSO 0 491 #endif 492 493 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 494 "EM driver parameters"); 495 496 static int em_disable_crc_stripping = 0; 497 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 498 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 499 500 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 501 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 502 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 503 0, "Default transmit interrupt delay in usecs"); 504 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 505 0, "Default receive interrupt delay in usecs"); 506 507 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 508 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 509 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 510 &em_tx_abs_int_delay_dflt, 0, 511 "Default transmit interrupt delay limit in usecs"); 512 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 513 &em_rx_abs_int_delay_dflt, 0, 514 "Default receive interrupt delay limit in usecs"); 515 516 static int em_smart_pwr_down = false; 517 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 518 0, "Set to true to leave smart power down enabled on newer adapters"); 519 520 /* Controls whether promiscuous also shows bad packets */ 521 static int em_debug_sbp = false; 522 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 523 "Show bad packets in promiscuous mode"); 524 525 /* How many packets rxeof tries to clean at a time */ 526 static int em_rx_process_limit = 100; 527 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 528 &em_rx_process_limit, 0, 529 "Maximum number of received packets to process " 530 "at a time, -1 means unlimited"); 531 532 /* Energy efficient ethernet - default to OFF */ 533 static int eee_setting = 1; 534 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 535 "Enable Energy Efficient Ethernet"); 536 537 /* 538 ** Tuneable Interrupt rate 539 */ 540 static int em_max_interrupt_rate = 8000; 541 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 542 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 543 544 545 546 /* Global used in WOL setup with multiport cards */ 547 static int global_quad_port_a = 0; 548 549 extern struct if_txrx igb_txrx; 550 extern struct if_txrx em_txrx; 551 extern struct if_txrx lem_txrx; 552 553 static struct if_shared_ctx em_sctx_init = { 554 .isc_magic = IFLIB_MAGIC, 555 .isc_q_align = PAGE_SIZE, 556 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 557 .isc_tx_maxsegsize = PAGE_SIZE, 558 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 559 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 560 .isc_rx_maxsize = MJUM9BYTES, 561 .isc_rx_nsegments = 1, 562 .isc_rx_maxsegsize = MJUM9BYTES, 563 .isc_nfl = 1, 564 .isc_nrxqs = 1, 565 .isc_ntxqs = 1, 566 .isc_admin_intrcnt = 1, 567 .isc_vendor_info = em_vendor_info_array, 568 .isc_driver_version = em_driver_version, 569 .isc_driver = &em_if_driver, 570 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 571 572 .isc_nrxd_min = {EM_MIN_RXD}, 573 .isc_ntxd_min = {EM_MIN_TXD}, 574 .isc_nrxd_max = {EM_MAX_RXD}, 575 .isc_ntxd_max = {EM_MAX_TXD}, 576 .isc_nrxd_default = {EM_DEFAULT_RXD}, 577 .isc_ntxd_default = {EM_DEFAULT_TXD}, 578 }; 579 580 static struct if_shared_ctx igb_sctx_init = { 581 .isc_magic = IFLIB_MAGIC, 582 .isc_q_align = PAGE_SIZE, 583 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 584 .isc_tx_maxsegsize = PAGE_SIZE, 585 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 586 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 587 .isc_rx_maxsize = MJUM9BYTES, 588 .isc_rx_nsegments = 1, 589 .isc_rx_maxsegsize = MJUM9BYTES, 590 .isc_nfl = 1, 591 .isc_nrxqs = 1, 592 .isc_ntxqs = 1, 593 .isc_admin_intrcnt = 1, 594 .isc_vendor_info = igb_vendor_info_array, 595 .isc_driver_version = em_driver_version, 596 .isc_driver = &igb_if_driver, 597 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 598 599 .isc_nrxd_min = {EM_MIN_RXD}, 600 .isc_ntxd_min = {EM_MIN_TXD}, 601 .isc_nrxd_max = {IGB_MAX_RXD}, 602 .isc_ntxd_max = {IGB_MAX_TXD}, 603 .isc_nrxd_default = {EM_DEFAULT_RXD}, 604 .isc_ntxd_default = {EM_DEFAULT_TXD}, 605 }; 606 607 /***************************************************************** 608 * 609 * Dump Registers 610 * 611 ****************************************************************/ 612 #define IGB_REGS_LEN 739 613 614 static int em_get_regs(SYSCTL_HANDLER_ARGS) 615 { 616 struct e1000_softc *sc = (struct e1000_softc *)arg1; 617 struct e1000_hw *hw = &sc->hw; 618 struct sbuf *sb; 619 u32 *regs_buff; 620 int rc; 621 622 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 623 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 624 625 rc = sysctl_wire_old_buffer(req, 0); 626 MPASS(rc == 0); 627 if (rc != 0) { 628 free(regs_buff, M_DEVBUF); 629 return (rc); 630 } 631 632 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 633 MPASS(sb != NULL); 634 if (sb == NULL) { 635 free(regs_buff, M_DEVBUF); 636 return (ENOMEM); 637 } 638 639 /* General Registers */ 640 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 641 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 642 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 643 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 644 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 645 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 646 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 647 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 648 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 649 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 650 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 651 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 652 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 653 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 654 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 655 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 656 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 657 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 658 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 659 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 660 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 661 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 662 663 sbuf_printf(sb, "General Registers\n"); 664 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 665 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 666 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 667 668 sbuf_printf(sb, "Interrupt Registers\n"); 669 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 670 671 sbuf_printf(sb, "RX Registers\n"); 672 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 673 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 674 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 675 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 676 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 677 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 678 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 679 680 sbuf_printf(sb, "TX Registers\n"); 681 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 682 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 683 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 684 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 685 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 686 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 687 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 688 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 689 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 690 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 691 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 692 693 free(regs_buff, M_DEVBUF); 694 695 #ifdef DUMP_DESCS 696 { 697 if_softc_ctx_t scctx = sc->shared; 698 struct rx_ring *rxr = &rx_que->rxr; 699 struct tx_ring *txr = &tx_que->txr; 700 int ntxd = scctx->isc_ntxd[0]; 701 int nrxd = scctx->isc_nrxd[0]; 702 int j; 703 704 for (j = 0; j < nrxd; j++) { 705 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 706 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 707 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 708 } 709 710 for (j = 0; j < min(ntxd, 256); j++) { 711 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 712 713 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 714 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 715 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 716 717 } 718 } 719 #endif 720 721 rc = sbuf_finish(sb); 722 sbuf_delete(sb); 723 return(rc); 724 } 725 726 static void * 727 em_register(device_t dev) 728 { 729 return (&em_sctx_init); 730 } 731 732 static void * 733 igb_register(device_t dev) 734 { 735 return (&igb_sctx_init); 736 } 737 738 static int 739 em_set_num_queues(if_ctx_t ctx) 740 { 741 struct e1000_softc *sc = iflib_get_softc(ctx); 742 int maxqueues; 743 744 /* Sanity check based on HW */ 745 switch (sc->hw.mac.type) { 746 case e1000_82576: 747 case e1000_82580: 748 case e1000_i350: 749 case e1000_i354: 750 maxqueues = 8; 751 break; 752 case e1000_i210: 753 case e1000_82575: 754 maxqueues = 4; 755 break; 756 case e1000_i211: 757 case e1000_82574: 758 maxqueues = 2; 759 break; 760 default: 761 maxqueues = 1; 762 break; 763 } 764 765 return (maxqueues); 766 } 767 768 #define LEM_CAPS \ 769 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 770 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 771 772 #define EM_CAPS \ 773 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 774 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 775 IFCAP_LRO | IFCAP_VLAN_HWTSO 776 777 #define IGB_CAPS \ 778 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 779 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 780 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 781 IFCAP_TSO6 782 783 /********************************************************************* 784 * Device initialization routine 785 * 786 * The attach entry point is called when the driver is being loaded. 787 * This routine identifies the type of hardware, allocates all resources 788 * and initializes the hardware. 789 * 790 * return 0 on success, positive on failure 791 *********************************************************************/ 792 static int 793 em_if_attach_pre(if_ctx_t ctx) 794 { 795 struct e1000_softc *sc; 796 if_softc_ctx_t scctx; 797 device_t dev; 798 struct e1000_hw *hw; 799 struct sysctl_oid_list *child; 800 struct sysctl_ctx_list *ctx_list; 801 int error = 0; 802 803 INIT_DEBUGOUT("em_if_attach_pre: begin"); 804 dev = iflib_get_dev(ctx); 805 sc = iflib_get_softc(ctx); 806 807 sc->ctx = sc->osdep.ctx = ctx; 808 sc->dev = sc->osdep.dev = dev; 809 scctx = sc->shared = iflib_get_softc_ctx(ctx); 810 sc->media = iflib_get_media(ctx); 811 hw = &sc->hw; 812 813 sc->tx_process_limit = scctx->isc_ntxd[0]; 814 815 /* Determine hardware and mac info */ 816 em_identify_hardware(ctx); 817 818 /* SYSCTL stuff */ 819 ctx_list = device_get_sysctl_ctx(dev); 820 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 821 822 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 823 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 824 em_sysctl_nvm_info, "I", "NVM Information"); 825 826 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 827 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 828 em_sysctl_print_fw_version, "A", 829 "Prints FW/NVM Versions"); 830 831 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 832 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 833 em_sysctl_debug_info, "I", "Debug Information"); 834 835 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 836 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 837 em_set_flowcntl, "I", "Flow Control"); 838 839 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 840 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 841 em_get_regs, "A", "Dump Registers"); 842 843 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 844 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 845 em_get_rs, "I", "Dump RS indexes"); 846 847 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 848 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 849 if (bootverbose) 850 device_printf(dev, "attach_pre capping queues at %d\n", 851 scctx->isc_ntxqsets_max); 852 853 if (hw->mac.type >= igb_mac_min) { 854 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 855 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 856 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 857 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 858 scctx->isc_txrx = &igb_txrx; 859 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 860 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 861 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 862 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 863 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 864 CSUM_IP6_TCP | CSUM_IP6_UDP; 865 if (hw->mac.type != e1000_82575) 866 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 867 /* 868 ** Some new devices, as with ixgbe, now may 869 ** use a different BAR, so we need to keep 870 ** track of which is used. 871 */ 872 scctx->isc_msix_bar = pci_msix_table_bar(dev); 873 } else if (hw->mac.type >= em_mac_min) { 874 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 875 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 876 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 877 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 878 scctx->isc_txrx = &em_txrx; 879 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 880 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 881 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 882 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 883 /* 884 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 885 * by default as we don't have workarounds for all associated 886 * silicon errata. E. g., with several MACs such as 82573E, 887 * TSO only works at Gigabit speed and otherwise can cause the 888 * hardware to hang (which also would be next to impossible to 889 * work around given that already queued TSO-using descriptors 890 * would need to be flushed and vlan(4) reconfigured at runtime 891 * in case of a link speed change). Moreover, MACs like 82579 892 * still can hang at Gigabit even with all publicly documented 893 * TSO workarounds implemented. Generally, the penality of 894 * these workarounds is rather high and may involve copying 895 * mbuf data around so advantages of TSO lapse. Still, TSO may 896 * work for a few MACs of this class - at least when sticking 897 * with Gigabit - in which case users may enable TSO manually. 898 */ 899 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 900 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 901 /* 902 * We support MSI-X with 82574 only, but indicate to iflib(4) 903 * that it shall give MSI at least a try with other devices. 904 */ 905 if (hw->mac.type == e1000_82574) { 906 scctx->isc_msix_bar = pci_msix_table_bar(dev);; 907 } else { 908 scctx->isc_msix_bar = -1; 909 scctx->isc_disable_msix = 1; 910 } 911 } else { 912 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 913 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 914 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 915 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 916 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 917 scctx->isc_txrx = &lem_txrx; 918 scctx->isc_capabilities = LEM_CAPS; 919 if (hw->mac.type < e1000_82543) 920 scctx->isc_capabilities &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 921 /* 82541ER doesn't do HW tagging */ 922 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 923 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 924 /* INTx only */ 925 scctx->isc_msix_bar = 0; 926 scctx->isc_capenable = scctx->isc_capabilities; 927 } 928 929 /* Setup PCI resources */ 930 if (em_allocate_pci_resources(ctx)) { 931 device_printf(dev, "Allocation of PCI resources failed\n"); 932 error = ENXIO; 933 goto err_pci; 934 } 935 936 /* 937 ** For ICH8 and family we need to 938 ** map the flash memory, and this 939 ** must happen after the MAC is 940 ** identified 941 */ 942 if ((hw->mac.type == e1000_ich8lan) || 943 (hw->mac.type == e1000_ich9lan) || 944 (hw->mac.type == e1000_ich10lan) || 945 (hw->mac.type == e1000_pchlan) || 946 (hw->mac.type == e1000_pch2lan) || 947 (hw->mac.type == e1000_pch_lpt)) { 948 int rid = EM_BAR_TYPE_FLASH; 949 sc->flash = bus_alloc_resource_any(dev, 950 SYS_RES_MEMORY, &rid, RF_ACTIVE); 951 if (sc->flash == NULL) { 952 device_printf(dev, "Mapping of Flash failed\n"); 953 error = ENXIO; 954 goto err_pci; 955 } 956 /* This is used in the shared code */ 957 hw->flash_address = (u8 *)sc->flash; 958 sc->osdep.flash_bus_space_tag = 959 rman_get_bustag(sc->flash); 960 sc->osdep.flash_bus_space_handle = 961 rman_get_bushandle(sc->flash); 962 } 963 /* 964 ** In the new SPT device flash is not a 965 ** separate BAR, rather it is also in BAR0, 966 ** so use the same tag and an offset handle for the 967 ** FLASH read/write macros in the shared code. 968 */ 969 else if (hw->mac.type >= e1000_pch_spt) { 970 sc->osdep.flash_bus_space_tag = 971 sc->osdep.mem_bus_space_tag; 972 sc->osdep.flash_bus_space_handle = 973 sc->osdep.mem_bus_space_handle 974 + E1000_FLASH_BASE_ADDR; 975 } 976 977 /* Do Shared Code initialization */ 978 error = e1000_setup_init_funcs(hw, true); 979 if (error) { 980 device_printf(dev, "Setup of Shared code failed, error %d\n", 981 error); 982 error = ENXIO; 983 goto err_pci; 984 } 985 986 em_setup_msix(ctx); 987 e1000_get_bus_info(hw); 988 989 /* Set up some sysctls for the tunable interrupt delays */ 990 em_add_int_delay_sysctl(sc, "rx_int_delay", 991 "receive interrupt delay in usecs", &sc->rx_int_delay, 992 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 993 em_add_int_delay_sysctl(sc, "tx_int_delay", 994 "transmit interrupt delay in usecs", &sc->tx_int_delay, 995 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 996 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 997 "receive interrupt delay limit in usecs", 998 &sc->rx_abs_int_delay, 999 E1000_REGISTER(hw, E1000_RADV), 1000 em_rx_abs_int_delay_dflt); 1001 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1002 "transmit interrupt delay limit in usecs", 1003 &sc->tx_abs_int_delay, 1004 E1000_REGISTER(hw, E1000_TADV), 1005 em_tx_abs_int_delay_dflt); 1006 em_add_int_delay_sysctl(sc, "itr", 1007 "interrupt delay limit in usecs/4", 1008 &sc->tx_itr, 1009 E1000_REGISTER(hw, E1000_ITR), 1010 DEFAULT_ITR); 1011 1012 hw->mac.autoneg = DO_AUTO_NEG; 1013 hw->phy.autoneg_wait_to_complete = false; 1014 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1015 1016 if (hw->mac.type < em_mac_min) { 1017 e1000_init_script_state_82541(hw, true); 1018 e1000_set_tbi_compatibility_82543(hw, true); 1019 } 1020 /* Copper options */ 1021 if (hw->phy.media_type == e1000_media_type_copper) { 1022 hw->phy.mdix = AUTO_ALL_MODES; 1023 hw->phy.disable_polarity_correction = false; 1024 hw->phy.ms_type = EM_MASTER_SLAVE; 1025 } 1026 1027 /* 1028 * Set the frame limits assuming 1029 * standard ethernet sized frames. 1030 */ 1031 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1032 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1033 1034 /* 1035 * This controls when hardware reports transmit completion 1036 * status. 1037 */ 1038 hw->mac.report_tx_early = 1; 1039 1040 /* Allocate multicast array memory. */ 1041 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1042 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1043 if (sc->mta == NULL) { 1044 device_printf(dev, "Can not allocate multicast setup array\n"); 1045 error = ENOMEM; 1046 goto err_late; 1047 } 1048 1049 /* Check SOL/IDER usage */ 1050 if (e1000_check_reset_block(hw)) 1051 device_printf(dev, "PHY reset is blocked" 1052 " due to SOL/IDER session.\n"); 1053 1054 /* Sysctl for setting Energy Efficient Ethernet */ 1055 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1056 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1057 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1058 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1059 1060 /* 1061 ** Start from a known state, this is 1062 ** important in reading the nvm and 1063 ** mac from that. 1064 */ 1065 e1000_reset_hw(hw); 1066 1067 /* Make sure we have a good EEPROM before we read from it */ 1068 if (e1000_validate_nvm_checksum(hw) < 0) { 1069 /* 1070 ** Some PCI-E parts fail the first check due to 1071 ** the link being in sleep state, call it again, 1072 ** if it fails a second time its a real issue. 1073 */ 1074 if (e1000_validate_nvm_checksum(hw) < 0) { 1075 device_printf(dev, 1076 "The EEPROM Checksum Is Not Valid\n"); 1077 error = EIO; 1078 goto err_late; 1079 } 1080 } 1081 1082 /* Copy the permanent MAC address out of the EEPROM */ 1083 if (e1000_read_mac_addr(hw) < 0) { 1084 device_printf(dev, "EEPROM read error while reading MAC" 1085 " address\n"); 1086 error = EIO; 1087 goto err_late; 1088 } 1089 1090 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1091 if (sc->vf_ifp) { 1092 ether_gen_addr(iflib_get_ifp(ctx), 1093 (struct ether_addr *)hw->mac.addr); 1094 } else { 1095 device_printf(dev, "Invalid MAC address\n"); 1096 error = EIO; 1097 goto err_late; 1098 } 1099 } 1100 1101 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1102 em_fw_version_locked(ctx); 1103 1104 em_print_fw_version(sc); 1105 1106 /* Disable ULP support */ 1107 e1000_disable_ulp_lpt_lp(hw, true); 1108 1109 /* 1110 * Get Wake-on-Lan and Management info for later use 1111 */ 1112 em_get_wakeup(ctx); 1113 1114 /* Enable only WOL MAGIC by default */ 1115 scctx->isc_capenable &= ~IFCAP_WOL; 1116 if (sc->wol != 0) 1117 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1118 1119 iflib_set_mac(ctx, hw->mac.addr); 1120 1121 return (0); 1122 1123 err_late: 1124 em_release_hw_control(sc); 1125 err_pci: 1126 em_free_pci_resources(ctx); 1127 free(sc->mta, M_DEVBUF); 1128 1129 return (error); 1130 } 1131 1132 static int 1133 em_if_attach_post(if_ctx_t ctx) 1134 { 1135 struct e1000_softc *sc = iflib_get_softc(ctx); 1136 struct e1000_hw *hw = &sc->hw; 1137 int error = 0; 1138 1139 /* Setup OS specific network interface */ 1140 error = em_setup_interface(ctx); 1141 if (error != 0) { 1142 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1143 goto err_late; 1144 } 1145 1146 em_reset(ctx); 1147 1148 /* Initialize statistics */ 1149 em_update_stats_counters(sc); 1150 hw->mac.get_link_status = 1; 1151 em_if_update_admin_status(ctx); 1152 em_add_hw_stats(sc); 1153 1154 /* Non-AMT based hardware can now take control from firmware */ 1155 if (sc->has_manage && !sc->has_amt) 1156 em_get_hw_control(sc); 1157 1158 INIT_DEBUGOUT("em_if_attach_post: end"); 1159 1160 return (0); 1161 1162 err_late: 1163 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1164 return (error); 1165 } 1166 1167 /********************************************************************* 1168 * Device removal routine 1169 * 1170 * The detach entry point is called when the driver is being removed. 1171 * This routine stops the adapter and deallocates all the resources 1172 * that were allocated for driver operation. 1173 * 1174 * return 0 on success, positive on failure 1175 *********************************************************************/ 1176 static int 1177 em_if_detach(if_ctx_t ctx) 1178 { 1179 struct e1000_softc *sc = iflib_get_softc(ctx); 1180 1181 INIT_DEBUGOUT("em_if_detach: begin"); 1182 1183 e1000_phy_hw_reset(&sc->hw); 1184 1185 em_release_manageability(sc); 1186 em_release_hw_control(sc); 1187 em_free_pci_resources(ctx); 1188 free(sc->mta, M_DEVBUF); 1189 sc->mta = NULL; 1190 1191 return (0); 1192 } 1193 1194 /********************************************************************* 1195 * 1196 * Shutdown entry point 1197 * 1198 **********************************************************************/ 1199 1200 static int 1201 em_if_shutdown(if_ctx_t ctx) 1202 { 1203 return em_if_suspend(ctx); 1204 } 1205 1206 /* 1207 * Suspend/resume device methods. 1208 */ 1209 static int 1210 em_if_suspend(if_ctx_t ctx) 1211 { 1212 struct e1000_softc *sc = iflib_get_softc(ctx); 1213 1214 em_release_manageability(sc); 1215 em_release_hw_control(sc); 1216 em_enable_wakeup(ctx); 1217 return (0); 1218 } 1219 1220 static int 1221 em_if_resume(if_ctx_t ctx) 1222 { 1223 struct e1000_softc *sc = iflib_get_softc(ctx); 1224 1225 if (sc->hw.mac.type == e1000_pch2lan) 1226 e1000_resume_workarounds_pchlan(&sc->hw); 1227 em_if_init(ctx); 1228 em_init_manageability(sc); 1229 1230 return(0); 1231 } 1232 1233 static int 1234 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1235 { 1236 int max_frame_size; 1237 struct e1000_softc *sc = iflib_get_softc(ctx); 1238 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1239 1240 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1241 1242 switch (sc->hw.mac.type) { 1243 case e1000_82571: 1244 case e1000_82572: 1245 case e1000_ich9lan: 1246 case e1000_ich10lan: 1247 case e1000_pch2lan: 1248 case e1000_pch_lpt: 1249 case e1000_pch_spt: 1250 case e1000_pch_cnp: 1251 case e1000_pch_tgp: 1252 case e1000_pch_adp: 1253 case e1000_pch_mtp: 1254 case e1000_82574: 1255 case e1000_82583: 1256 case e1000_80003es2lan: 1257 /* 9K Jumbo Frame size */ 1258 max_frame_size = 9234; 1259 break; 1260 case e1000_pchlan: 1261 max_frame_size = 4096; 1262 break; 1263 case e1000_82542: 1264 case e1000_ich8lan: 1265 /* Adapters that do not support jumbo frames */ 1266 max_frame_size = ETHER_MAX_LEN; 1267 break; 1268 default: 1269 if (sc->hw.mac.type >= igb_mac_min) 1270 max_frame_size = 9234; 1271 else /* lem */ 1272 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1273 } 1274 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1275 return (EINVAL); 1276 } 1277 1278 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1279 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1280 return (0); 1281 } 1282 1283 /********************************************************************* 1284 * Init entry point 1285 * 1286 * This routine is used in two ways. It is used by the stack as 1287 * init entry point in network interface structure. It is also used 1288 * by the driver as a hw/sw initialization routine to get to a 1289 * consistent state. 1290 * 1291 **********************************************************************/ 1292 static void 1293 em_if_init(if_ctx_t ctx) 1294 { 1295 struct e1000_softc *sc = iflib_get_softc(ctx); 1296 if_softc_ctx_t scctx = sc->shared; 1297 struct ifnet *ifp = iflib_get_ifp(ctx); 1298 struct em_tx_queue *tx_que; 1299 int i; 1300 1301 INIT_DEBUGOUT("em_if_init: begin"); 1302 1303 /* Get the latest mac address, User can use a LAA */ 1304 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1305 ETHER_ADDR_LEN); 1306 1307 /* Put the address into the Receive Address Array */ 1308 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1309 1310 /* 1311 * With the 82571 adapter, RAR[0] may be overwritten 1312 * when the other port is reset, we make a duplicate 1313 * in RAR[14] for that eventuality, this assures 1314 * the interface continues to function. 1315 */ 1316 if (sc->hw.mac.type == e1000_82571) { 1317 e1000_set_laa_state_82571(&sc->hw, true); 1318 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1319 E1000_RAR_ENTRIES - 1); 1320 } 1321 1322 1323 /* Initialize the hardware */ 1324 em_reset(ctx); 1325 em_if_update_admin_status(ctx); 1326 1327 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1328 struct tx_ring *txr = &tx_que->txr; 1329 1330 txr->tx_rs_cidx = txr->tx_rs_pidx; 1331 1332 /* Initialize the last processed descriptor to be the end of 1333 * the ring, rather than the start, so that we avoid an 1334 * off-by-one error when calculating how many descriptors are 1335 * done in the credits_update function. 1336 */ 1337 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1338 } 1339 1340 /* Setup VLAN support, basic and offload if available */ 1341 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1342 1343 /* Clear bad data from Rx FIFOs */ 1344 if (sc->hw.mac.type >= igb_mac_min) 1345 e1000_rx_fifo_flush_base(&sc->hw); 1346 1347 /* Configure for OS presence */ 1348 em_init_manageability(sc); 1349 1350 /* Prepare transmit descriptors and buffers */ 1351 em_initialize_transmit_unit(ctx); 1352 1353 /* Setup Multicast table */ 1354 em_if_multi_set(ctx); 1355 1356 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1357 em_initialize_receive_unit(ctx); 1358 1359 /* Set up VLAN support and filter */ 1360 em_setup_vlan_hw_support(ctx); 1361 1362 /* Don't lose promiscuous settings */ 1363 em_if_set_promisc(ctx, if_getflags(ifp)); 1364 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1365 1366 /* MSI-X configuration for 82574 */ 1367 if (sc->hw.mac.type == e1000_82574) { 1368 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1369 1370 tmp |= E1000_CTRL_EXT_PBA_CLR; 1371 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1372 /* Set the IVAR - interrupt vector routing. */ 1373 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1374 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1375 igb_configure_queues(sc); 1376 1377 /* this clears any pending interrupts */ 1378 E1000_READ_REG(&sc->hw, E1000_ICR); 1379 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1380 1381 /* AMT based hardware can now take control from firmware */ 1382 if (sc->has_manage && sc->has_amt) 1383 em_get_hw_control(sc); 1384 1385 /* Set Energy Efficient Ethernet */ 1386 if (sc->hw.mac.type >= igb_mac_min && 1387 sc->hw.phy.media_type == e1000_media_type_copper) { 1388 if (sc->hw.mac.type == e1000_i354) 1389 e1000_set_eee_i354(&sc->hw, true, true); 1390 else 1391 e1000_set_eee_i350(&sc->hw, true, true); 1392 } 1393 } 1394 1395 /********************************************************************* 1396 * 1397 * Fast Legacy/MSI Combined Interrupt Service routine 1398 * 1399 *********************************************************************/ 1400 int 1401 em_intr(void *arg) 1402 { 1403 struct e1000_softc *sc = arg; 1404 if_ctx_t ctx = sc->ctx; 1405 u32 reg_icr; 1406 1407 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1408 1409 /* Hot eject? */ 1410 if (reg_icr == 0xffffffff) 1411 return FILTER_STRAY; 1412 1413 /* Definitely not our interrupt. */ 1414 if (reg_icr == 0x0) 1415 return FILTER_STRAY; 1416 1417 /* 1418 * Starting with the 82571 chip, bit 31 should be used to 1419 * determine whether the interrupt belongs to us. 1420 */ 1421 if (sc->hw.mac.type >= e1000_82571 && 1422 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1423 return FILTER_STRAY; 1424 1425 /* 1426 * Only MSI-X interrupts have one-shot behavior by taking advantage 1427 * of the EIAC register. Thus, explicitly disable interrupts. This 1428 * also works around the MSI message reordering errata on certain 1429 * systems. 1430 */ 1431 IFDI_INTR_DISABLE(ctx); 1432 1433 /* Link status change */ 1434 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1435 em_handle_link(ctx); 1436 1437 if (reg_icr & E1000_ICR_RXO) 1438 sc->rx_overruns++; 1439 1440 return (FILTER_SCHEDULE_THREAD); 1441 } 1442 1443 static int 1444 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1445 { 1446 struct e1000_softc *sc = iflib_get_softc(ctx); 1447 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1448 1449 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1450 return (0); 1451 } 1452 1453 static int 1454 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1455 { 1456 struct e1000_softc *sc = iflib_get_softc(ctx); 1457 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1458 1459 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1460 return (0); 1461 } 1462 1463 static int 1464 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1465 { 1466 struct e1000_softc *sc = iflib_get_softc(ctx); 1467 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1468 1469 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1470 return (0); 1471 } 1472 1473 static int 1474 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1475 { 1476 struct e1000_softc *sc = iflib_get_softc(ctx); 1477 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1478 1479 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1480 return (0); 1481 } 1482 1483 /********************************************************************* 1484 * 1485 * MSI-X RX Interrupt Service routine 1486 * 1487 **********************************************************************/ 1488 static int 1489 em_msix_que(void *arg) 1490 { 1491 struct em_rx_queue *que = arg; 1492 1493 ++que->irqs; 1494 1495 return (FILTER_SCHEDULE_THREAD); 1496 } 1497 1498 /********************************************************************* 1499 * 1500 * MSI-X Link Fast Interrupt Service routine 1501 * 1502 **********************************************************************/ 1503 static int 1504 em_msix_link(void *arg) 1505 { 1506 struct e1000_softc *sc = arg; 1507 u32 reg_icr; 1508 1509 ++sc->link_irq; 1510 MPASS(sc->hw.back != NULL); 1511 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1512 1513 if (reg_icr & E1000_ICR_RXO) 1514 sc->rx_overruns++; 1515 1516 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1517 em_handle_link(sc->ctx); 1518 1519 /* Re-arm unconditionally */ 1520 if (sc->hw.mac.type >= igb_mac_min) { 1521 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1522 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1523 } else if (sc->hw.mac.type == e1000_82574) { 1524 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1525 E1000_IMS_OTHER); 1526 /* 1527 * Because we must read the ICR for this interrupt it may 1528 * clear other causes using autoclear, for this reason we 1529 * simply create a soft interrupt for all these vectors. 1530 */ 1531 if (reg_icr) 1532 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1533 } else 1534 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1535 1536 return (FILTER_HANDLED); 1537 } 1538 1539 static void 1540 em_handle_link(void *context) 1541 { 1542 if_ctx_t ctx = context; 1543 struct e1000_softc *sc = iflib_get_softc(ctx); 1544 1545 sc->hw.mac.get_link_status = 1; 1546 iflib_admin_intr_deferred(ctx); 1547 } 1548 1549 /********************************************************************* 1550 * 1551 * Media Ioctl callback 1552 * 1553 * This routine is called whenever the user queries the status of 1554 * the interface using ifconfig. 1555 * 1556 **********************************************************************/ 1557 static void 1558 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1559 { 1560 struct e1000_softc *sc = iflib_get_softc(ctx); 1561 u_char fiber_type = IFM_1000_SX; 1562 1563 INIT_DEBUGOUT("em_if_media_status: begin"); 1564 1565 iflib_admin_intr_deferred(ctx); 1566 1567 ifmr->ifm_status = IFM_AVALID; 1568 ifmr->ifm_active = IFM_ETHER; 1569 1570 if (!sc->link_active) { 1571 return; 1572 } 1573 1574 ifmr->ifm_status |= IFM_ACTIVE; 1575 1576 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1577 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1578 if (sc->hw.mac.type == e1000_82545) 1579 fiber_type = IFM_1000_LX; 1580 ifmr->ifm_active |= fiber_type | IFM_FDX; 1581 } else { 1582 switch (sc->link_speed) { 1583 case 10: 1584 ifmr->ifm_active |= IFM_10_T; 1585 break; 1586 case 100: 1587 ifmr->ifm_active |= IFM_100_TX; 1588 break; 1589 case 1000: 1590 ifmr->ifm_active |= IFM_1000_T; 1591 break; 1592 } 1593 if (sc->link_duplex == FULL_DUPLEX) 1594 ifmr->ifm_active |= IFM_FDX; 1595 else 1596 ifmr->ifm_active |= IFM_HDX; 1597 } 1598 } 1599 1600 /********************************************************************* 1601 * 1602 * Media Ioctl callback 1603 * 1604 * This routine is called when the user changes speed/duplex using 1605 * media/mediopt option with ifconfig. 1606 * 1607 **********************************************************************/ 1608 static int 1609 em_if_media_change(if_ctx_t ctx) 1610 { 1611 struct e1000_softc *sc = iflib_get_softc(ctx); 1612 struct ifmedia *ifm = iflib_get_media(ctx); 1613 1614 INIT_DEBUGOUT("em_if_media_change: begin"); 1615 1616 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1617 return (EINVAL); 1618 1619 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1620 case IFM_AUTO: 1621 sc->hw.mac.autoneg = DO_AUTO_NEG; 1622 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1623 break; 1624 case IFM_1000_LX: 1625 case IFM_1000_SX: 1626 case IFM_1000_T: 1627 sc->hw.mac.autoneg = DO_AUTO_NEG; 1628 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1629 break; 1630 case IFM_100_TX: 1631 sc->hw.mac.autoneg = DO_AUTO_NEG; 1632 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 1633 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1634 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1635 } else { 1636 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1637 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1638 } 1639 break; 1640 case IFM_10_T: 1641 sc->hw.mac.autoneg = DO_AUTO_NEG; 1642 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 1643 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1644 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1645 } else { 1646 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1647 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1648 } 1649 break; 1650 default: 1651 device_printf(sc->dev, "Unsupported media type\n"); 1652 } 1653 1654 em_if_init(ctx); 1655 1656 return (0); 1657 } 1658 1659 static int 1660 em_if_set_promisc(if_ctx_t ctx, int flags) 1661 { 1662 struct e1000_softc *sc = iflib_get_softc(ctx); 1663 struct ifnet *ifp = iflib_get_ifp(ctx); 1664 u32 reg_rctl; 1665 int mcnt = 0; 1666 1667 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1668 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1669 if (flags & IFF_ALLMULTI) 1670 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1671 else 1672 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1673 1674 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1675 reg_rctl &= (~E1000_RCTL_MPE); 1676 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1677 1678 if (flags & IFF_PROMISC) { 1679 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1680 em_if_vlan_filter_disable(sc); 1681 /* Turn this on if you want to see bad packets */ 1682 if (em_debug_sbp) 1683 reg_rctl |= E1000_RCTL_SBP; 1684 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1685 } else { 1686 if (flags & IFF_ALLMULTI) { 1687 reg_rctl |= E1000_RCTL_MPE; 1688 reg_rctl &= ~E1000_RCTL_UPE; 1689 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1690 } 1691 if (em_if_vlan_filter_used(ctx)) 1692 em_if_vlan_filter_enable(sc); 1693 } 1694 return (0); 1695 } 1696 1697 static u_int 1698 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1699 { 1700 u8 *mta = arg; 1701 1702 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1703 return (0); 1704 1705 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1706 1707 return (1); 1708 } 1709 1710 /********************************************************************* 1711 * Multicast Update 1712 * 1713 * This routine is called whenever multicast address list is updated. 1714 * 1715 **********************************************************************/ 1716 static void 1717 em_if_multi_set(if_ctx_t ctx) 1718 { 1719 struct e1000_softc *sc = iflib_get_softc(ctx); 1720 struct ifnet *ifp = iflib_get_ifp(ctx); 1721 u8 *mta; /* Multicast array memory */ 1722 u32 reg_rctl = 0; 1723 int mcnt = 0; 1724 1725 IOCTL_DEBUGOUT("em_set_multi: begin"); 1726 1727 mta = sc->mta; 1728 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1729 1730 if (sc->hw.mac.type == e1000_82542 && 1731 sc->hw.revision_id == E1000_REVISION_2) { 1732 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1733 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1734 e1000_pci_clear_mwi(&sc->hw); 1735 reg_rctl |= E1000_RCTL_RST; 1736 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1737 msec_delay(5); 1738 } 1739 1740 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1741 1742 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1743 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1744 1745 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1746 1747 if (if_getflags(ifp) & IFF_PROMISC) 1748 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1749 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1750 if_getflags(ifp) & IFF_ALLMULTI) { 1751 reg_rctl |= E1000_RCTL_MPE; 1752 reg_rctl &= ~E1000_RCTL_UPE; 1753 } else 1754 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1755 1756 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1757 1758 if (sc->hw.mac.type == e1000_82542 && 1759 sc->hw.revision_id == E1000_REVISION_2) { 1760 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1761 reg_rctl &= ~E1000_RCTL_RST; 1762 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1763 msec_delay(5); 1764 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1765 e1000_pci_set_mwi(&sc->hw); 1766 } 1767 } 1768 1769 /********************************************************************* 1770 * Timer routine 1771 * 1772 * This routine schedules em_if_update_admin_status() to check for 1773 * link status and to gather statistics as well as to perform some 1774 * controller-specific hardware patting. 1775 * 1776 **********************************************************************/ 1777 static void 1778 em_if_timer(if_ctx_t ctx, uint16_t qid) 1779 { 1780 1781 if (qid != 0) 1782 return; 1783 1784 iflib_admin_intr_deferred(ctx); 1785 } 1786 1787 static void 1788 em_if_update_admin_status(if_ctx_t ctx) 1789 { 1790 struct e1000_softc *sc = iflib_get_softc(ctx); 1791 struct e1000_hw *hw = &sc->hw; 1792 device_t dev = iflib_get_dev(ctx); 1793 u32 link_check, thstat, ctrl; 1794 1795 link_check = thstat = ctrl = 0; 1796 /* Get the cached link value or read phy for real */ 1797 switch (hw->phy.media_type) { 1798 case e1000_media_type_copper: 1799 if (hw->mac.get_link_status) { 1800 if (hw->mac.type == e1000_pch_spt) 1801 msec_delay(50); 1802 /* Do the work to read phy */ 1803 e1000_check_for_link(hw); 1804 link_check = !hw->mac.get_link_status; 1805 if (link_check) /* ESB2 fix */ 1806 e1000_cfg_on_link_up(hw); 1807 } else { 1808 link_check = true; 1809 } 1810 break; 1811 case e1000_media_type_fiber: 1812 e1000_check_for_link(hw); 1813 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1814 E1000_STATUS_LU); 1815 break; 1816 case e1000_media_type_internal_serdes: 1817 e1000_check_for_link(hw); 1818 link_check = hw->mac.serdes_has_link; 1819 break; 1820 /* VF device is type_unknown */ 1821 case e1000_media_type_unknown: 1822 e1000_check_for_link(hw); 1823 link_check = !hw->mac.get_link_status; 1824 /* FALLTHROUGH */ 1825 default: 1826 break; 1827 } 1828 1829 /* Check for thermal downshift or shutdown */ 1830 if (hw->mac.type == e1000_i350) { 1831 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1832 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1833 } 1834 1835 /* Now check for a transition */ 1836 if (link_check && (sc->link_active == 0)) { 1837 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1838 &sc->link_duplex); 1839 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1840 if ((sc->link_speed != SPEED_1000) && 1841 ((hw->mac.type == e1000_82571) || 1842 (hw->mac.type == e1000_82572))) { 1843 int tarc0; 1844 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1845 tarc0 &= ~TARC_SPEED_MODE_BIT; 1846 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1847 } 1848 if (bootverbose) 1849 device_printf(dev, "Link is up %d Mbps %s\n", 1850 sc->link_speed, 1851 ((sc->link_duplex == FULL_DUPLEX) ? 1852 "Full Duplex" : "Half Duplex")); 1853 sc->link_active = 1; 1854 sc->smartspeed = 0; 1855 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1856 E1000_CTRL_EXT_LINK_MODE_GMII && 1857 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1858 device_printf(dev, "Link: thermal downshift\n"); 1859 /* Delay Link Up for Phy update */ 1860 if (((hw->mac.type == e1000_i210) || 1861 (hw->mac.type == e1000_i211)) && 1862 (hw->phy.id == I210_I_PHY_ID)) 1863 msec_delay(I210_LINK_DELAY); 1864 /* Reset if the media type changed. */ 1865 if (hw->dev_spec._82575.media_changed && 1866 hw->mac.type >= igb_mac_min) { 1867 hw->dev_spec._82575.media_changed = false; 1868 sc->flags |= IGB_MEDIA_RESET; 1869 em_reset(ctx); 1870 } 1871 iflib_link_state_change(ctx, LINK_STATE_UP, 1872 IF_Mbps(sc->link_speed)); 1873 } else if (!link_check && (sc->link_active == 1)) { 1874 sc->link_speed = 0; 1875 sc->link_duplex = 0; 1876 sc->link_active = 0; 1877 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1878 } 1879 em_update_stats_counters(sc); 1880 1881 /* Reset LAA into RAR[0] on 82571 */ 1882 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1883 e1000_rar_set(hw, hw->mac.addr, 0); 1884 1885 if (hw->mac.type < em_mac_min) 1886 lem_smartspeed(sc); 1887 } 1888 1889 static void 1890 em_if_watchdog_reset(if_ctx_t ctx) 1891 { 1892 struct e1000_softc *sc = iflib_get_softc(ctx); 1893 1894 /* 1895 * Just count the event; iflib(4) will already trigger a 1896 * sufficient reset of the controller. 1897 */ 1898 sc->watchdog_events++; 1899 } 1900 1901 /********************************************************************* 1902 * 1903 * This routine disables all traffic on the adapter by issuing a 1904 * global reset on the MAC. 1905 * 1906 **********************************************************************/ 1907 static void 1908 em_if_stop(if_ctx_t ctx) 1909 { 1910 struct e1000_softc *sc = iflib_get_softc(ctx); 1911 1912 INIT_DEBUGOUT("em_if_stop: begin"); 1913 1914 e1000_reset_hw(&sc->hw); 1915 if (sc->hw.mac.type >= e1000_82544) 1916 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1917 1918 e1000_led_off(&sc->hw); 1919 e1000_cleanup_led(&sc->hw); 1920 } 1921 1922 /********************************************************************* 1923 * 1924 * Determine hardware revision. 1925 * 1926 **********************************************************************/ 1927 static void 1928 em_identify_hardware(if_ctx_t ctx) 1929 { 1930 device_t dev = iflib_get_dev(ctx); 1931 struct e1000_softc *sc = iflib_get_softc(ctx); 1932 1933 /* Make sure our PCI config space has the necessary stuff set */ 1934 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1935 1936 /* Save off the information about this board */ 1937 sc->hw.vendor_id = pci_get_vendor(dev); 1938 sc->hw.device_id = pci_get_device(dev); 1939 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1940 sc->hw.subsystem_vendor_id = 1941 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1942 sc->hw.subsystem_device_id = 1943 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1944 1945 /* Do Shared Code Init and Setup */ 1946 if (e1000_set_mac_type(&sc->hw)) { 1947 device_printf(dev, "Setup init failure\n"); 1948 return; 1949 } 1950 1951 /* Are we a VF device? */ 1952 if ((sc->hw.mac.type == e1000_vfadapt) || 1953 (sc->hw.mac.type == e1000_vfadapt_i350)) 1954 sc->vf_ifp = 1; 1955 else 1956 sc->vf_ifp = 0; 1957 } 1958 1959 static int 1960 em_allocate_pci_resources(if_ctx_t ctx) 1961 { 1962 struct e1000_softc *sc = iflib_get_softc(ctx); 1963 device_t dev = iflib_get_dev(ctx); 1964 int rid, val; 1965 1966 rid = PCIR_BAR(0); 1967 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1968 &rid, RF_ACTIVE); 1969 if (sc->memory == NULL) { 1970 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1971 return (ENXIO); 1972 } 1973 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 1974 sc->osdep.mem_bus_space_handle = 1975 rman_get_bushandle(sc->memory); 1976 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 1977 1978 /* Only older adapters use IO mapping */ 1979 if (sc->hw.mac.type < em_mac_min && 1980 sc->hw.mac.type > e1000_82543) { 1981 /* Figure our where our IO BAR is ? */ 1982 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1983 val = pci_read_config(dev, rid, 4); 1984 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1985 break; 1986 } 1987 rid += 4; 1988 /* check for 64bit BAR */ 1989 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1990 rid += 4; 1991 } 1992 if (rid >= PCIR_CIS) { 1993 device_printf(dev, "Unable to locate IO BAR\n"); 1994 return (ENXIO); 1995 } 1996 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1997 &rid, RF_ACTIVE); 1998 if (sc->ioport == NULL) { 1999 device_printf(dev, "Unable to allocate bus resource: " 2000 "ioport\n"); 2001 return (ENXIO); 2002 } 2003 sc->hw.io_base = 0; 2004 sc->osdep.io_bus_space_tag = 2005 rman_get_bustag(sc->ioport); 2006 sc->osdep.io_bus_space_handle = 2007 rman_get_bushandle(sc->ioport); 2008 } 2009 2010 sc->hw.back = &sc->osdep; 2011 2012 return (0); 2013 } 2014 2015 /********************************************************************* 2016 * 2017 * Set up the MSI-X Interrupt handlers 2018 * 2019 **********************************************************************/ 2020 static int 2021 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2022 { 2023 struct e1000_softc *sc = iflib_get_softc(ctx); 2024 struct em_rx_queue *rx_que = sc->rx_queues; 2025 struct em_tx_queue *tx_que = sc->tx_queues; 2026 int error, rid, i, vector = 0, rx_vectors; 2027 char buf[16]; 2028 2029 /* First set up ring resources */ 2030 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2031 rid = vector + 1; 2032 snprintf(buf, sizeof(buf), "rxq%d", i); 2033 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2034 if (error) { 2035 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2036 sc->rx_num_queues = i + 1; 2037 goto fail; 2038 } 2039 2040 rx_que->msix = vector; 2041 2042 /* 2043 * Set the bit to enable interrupt 2044 * in E1000_IMS -- bits 20 and 21 2045 * are for RX0 and RX1, note this has 2046 * NOTHING to do with the MSI-X vector 2047 */ 2048 if (sc->hw.mac.type == e1000_82574) { 2049 rx_que->eims = 1 << (20 + i); 2050 sc->ims |= rx_que->eims; 2051 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2052 } else if (sc->hw.mac.type == e1000_82575) 2053 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2054 else 2055 rx_que->eims = 1 << vector; 2056 } 2057 rx_vectors = vector; 2058 2059 vector = 0; 2060 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2061 snprintf(buf, sizeof(buf), "txq%d", i); 2062 tx_que = &sc->tx_queues[i]; 2063 iflib_softirq_alloc_generic(ctx, 2064 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2065 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2066 2067 tx_que->msix = (vector % sc->rx_num_queues); 2068 2069 /* 2070 * Set the bit to enable interrupt 2071 * in E1000_IMS -- bits 22 and 23 2072 * are for TX0 and TX1, note this has 2073 * NOTHING to do with the MSI-X vector 2074 */ 2075 if (sc->hw.mac.type == e1000_82574) { 2076 tx_que->eims = 1 << (22 + i); 2077 sc->ims |= tx_que->eims; 2078 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2079 } else if (sc->hw.mac.type == e1000_82575) { 2080 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2081 } else { 2082 tx_que->eims = 1 << i; 2083 } 2084 } 2085 2086 /* Link interrupt */ 2087 rid = rx_vectors + 1; 2088 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2089 2090 if (error) { 2091 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2092 goto fail; 2093 } 2094 sc->linkvec = rx_vectors; 2095 if (sc->hw.mac.type < igb_mac_min) { 2096 sc->ivars |= (8 | rx_vectors) << 16; 2097 sc->ivars |= 0x80000000; 2098 /* Enable the "Other" interrupt type for link status change */ 2099 sc->ims |= E1000_IMS_OTHER; 2100 } 2101 2102 return (0); 2103 fail: 2104 iflib_irq_free(ctx, &sc->irq); 2105 rx_que = sc->rx_queues; 2106 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2107 iflib_irq_free(ctx, &rx_que->que_irq); 2108 return (error); 2109 } 2110 2111 static void 2112 igb_configure_queues(struct e1000_softc *sc) 2113 { 2114 struct e1000_hw *hw = &sc->hw; 2115 struct em_rx_queue *rx_que; 2116 struct em_tx_queue *tx_que; 2117 u32 tmp, ivar = 0, newitr = 0; 2118 2119 /* First turn on RSS capability */ 2120 if (hw->mac.type != e1000_82575) 2121 E1000_WRITE_REG(hw, E1000_GPIE, 2122 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2123 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2124 2125 /* Turn on MSI-X */ 2126 switch (hw->mac.type) { 2127 case e1000_82580: 2128 case e1000_i350: 2129 case e1000_i354: 2130 case e1000_i210: 2131 case e1000_i211: 2132 case e1000_vfadapt: 2133 case e1000_vfadapt_i350: 2134 /* RX entries */ 2135 for (int i = 0; i < sc->rx_num_queues; i++) { 2136 u32 index = i >> 1; 2137 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2138 rx_que = &sc->rx_queues[i]; 2139 if (i & 1) { 2140 ivar &= 0xFF00FFFF; 2141 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2142 } else { 2143 ivar &= 0xFFFFFF00; 2144 ivar |= rx_que->msix | E1000_IVAR_VALID; 2145 } 2146 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2147 } 2148 /* TX entries */ 2149 for (int i = 0; i < sc->tx_num_queues; i++) { 2150 u32 index = i >> 1; 2151 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2152 tx_que = &sc->tx_queues[i]; 2153 if (i & 1) { 2154 ivar &= 0x00FFFFFF; 2155 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2156 } else { 2157 ivar &= 0xFFFF00FF; 2158 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2159 } 2160 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2161 sc->que_mask |= tx_que->eims; 2162 } 2163 2164 /* And for the link interrupt */ 2165 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2166 sc->link_mask = 1 << sc->linkvec; 2167 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2168 break; 2169 case e1000_82576: 2170 /* RX entries */ 2171 for (int i = 0; i < sc->rx_num_queues; i++) { 2172 u32 index = i & 0x7; /* Each IVAR has two entries */ 2173 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2174 rx_que = &sc->rx_queues[i]; 2175 if (i < 8) { 2176 ivar &= 0xFFFFFF00; 2177 ivar |= rx_que->msix | E1000_IVAR_VALID; 2178 } else { 2179 ivar &= 0xFF00FFFF; 2180 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2181 } 2182 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2183 sc->que_mask |= rx_que->eims; 2184 } 2185 /* TX entries */ 2186 for (int i = 0; i < sc->tx_num_queues; i++) { 2187 u32 index = i & 0x7; /* Each IVAR has two entries */ 2188 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2189 tx_que = &sc->tx_queues[i]; 2190 if (i < 8) { 2191 ivar &= 0xFFFF00FF; 2192 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2193 } else { 2194 ivar &= 0x00FFFFFF; 2195 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2196 } 2197 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2198 sc->que_mask |= tx_que->eims; 2199 } 2200 2201 /* And for the link interrupt */ 2202 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2203 sc->link_mask = 1 << sc->linkvec; 2204 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2205 break; 2206 2207 case e1000_82575: 2208 /* enable MSI-X support*/ 2209 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2210 tmp |= E1000_CTRL_EXT_PBA_CLR; 2211 /* Auto-Mask interrupts upon ICR read. */ 2212 tmp |= E1000_CTRL_EXT_EIAME; 2213 tmp |= E1000_CTRL_EXT_IRCA; 2214 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2215 2216 /* Queues */ 2217 for (int i = 0; i < sc->rx_num_queues; i++) { 2218 rx_que = &sc->rx_queues[i]; 2219 tmp = E1000_EICR_RX_QUEUE0 << i; 2220 tmp |= E1000_EICR_TX_QUEUE0 << i; 2221 rx_que->eims = tmp; 2222 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2223 i, rx_que->eims); 2224 sc->que_mask |= rx_que->eims; 2225 } 2226 2227 /* Link */ 2228 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2229 E1000_EIMS_OTHER); 2230 sc->link_mask |= E1000_EIMS_OTHER; 2231 default: 2232 break; 2233 } 2234 2235 /* Set the starting interrupt rate */ 2236 if (em_max_interrupt_rate > 0) 2237 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2238 2239 if (hw->mac.type == e1000_82575) 2240 newitr |= newitr << 16; 2241 else 2242 newitr |= E1000_EITR_CNT_IGNR; 2243 2244 for (int i = 0; i < sc->rx_num_queues; i++) { 2245 rx_que = &sc->rx_queues[i]; 2246 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2247 } 2248 2249 return; 2250 } 2251 2252 static void 2253 em_free_pci_resources(if_ctx_t ctx) 2254 { 2255 struct e1000_softc *sc = iflib_get_softc(ctx); 2256 struct em_rx_queue *que = sc->rx_queues; 2257 device_t dev = iflib_get_dev(ctx); 2258 2259 /* Release all MSI-X queue resources */ 2260 if (sc->intr_type == IFLIB_INTR_MSIX) 2261 iflib_irq_free(ctx, &sc->irq); 2262 2263 if (que != NULL) { 2264 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2265 iflib_irq_free(ctx, &que->que_irq); 2266 } 2267 } 2268 2269 if (sc->memory != NULL) { 2270 bus_release_resource(dev, SYS_RES_MEMORY, 2271 rman_get_rid(sc->memory), sc->memory); 2272 sc->memory = NULL; 2273 } 2274 2275 if (sc->flash != NULL) { 2276 bus_release_resource(dev, SYS_RES_MEMORY, 2277 rman_get_rid(sc->flash), sc->flash); 2278 sc->flash = NULL; 2279 } 2280 2281 if (sc->ioport != NULL) { 2282 bus_release_resource(dev, SYS_RES_IOPORT, 2283 rman_get_rid(sc->ioport), sc->ioport); 2284 sc->ioport = NULL; 2285 } 2286 } 2287 2288 /* Set up MSI or MSI-X */ 2289 static int 2290 em_setup_msix(if_ctx_t ctx) 2291 { 2292 struct e1000_softc *sc = iflib_get_softc(ctx); 2293 2294 if (sc->hw.mac.type == e1000_82574) { 2295 em_enable_vectors_82574(ctx); 2296 } 2297 return (0); 2298 } 2299 2300 /********************************************************************* 2301 * 2302 * Workaround for SmartSpeed on 82541 and 82547 controllers 2303 * 2304 **********************************************************************/ 2305 static void 2306 lem_smartspeed(struct e1000_softc *sc) 2307 { 2308 u16 phy_tmp; 2309 2310 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2311 sc->hw.mac.autoneg == 0 || 2312 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2313 return; 2314 2315 if (sc->smartspeed == 0) { 2316 /* If Master/Slave config fault is asserted twice, 2317 * we assume back-to-back */ 2318 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2319 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2320 return; 2321 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2322 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2323 e1000_read_phy_reg(&sc->hw, 2324 PHY_1000T_CTRL, &phy_tmp); 2325 if(phy_tmp & CR_1000T_MS_ENABLE) { 2326 phy_tmp &= ~CR_1000T_MS_ENABLE; 2327 e1000_write_phy_reg(&sc->hw, 2328 PHY_1000T_CTRL, phy_tmp); 2329 sc->smartspeed++; 2330 if(sc->hw.mac.autoneg && 2331 !e1000_copper_link_autoneg(&sc->hw) && 2332 !e1000_read_phy_reg(&sc->hw, 2333 PHY_CONTROL, &phy_tmp)) { 2334 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2335 MII_CR_RESTART_AUTO_NEG); 2336 e1000_write_phy_reg(&sc->hw, 2337 PHY_CONTROL, phy_tmp); 2338 } 2339 } 2340 } 2341 return; 2342 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2343 /* If still no link, perhaps using 2/3 pair cable */ 2344 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2345 phy_tmp |= CR_1000T_MS_ENABLE; 2346 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2347 if(sc->hw.mac.autoneg && 2348 !e1000_copper_link_autoneg(&sc->hw) && 2349 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2350 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2351 MII_CR_RESTART_AUTO_NEG); 2352 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2353 } 2354 } 2355 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2356 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2357 sc->smartspeed = 0; 2358 } 2359 2360 /********************************************************************* 2361 * 2362 * Initialize the DMA Coalescing feature 2363 * 2364 **********************************************************************/ 2365 static void 2366 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2367 { 2368 device_t dev = sc->dev; 2369 struct e1000_hw *hw = &sc->hw; 2370 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2371 u16 hwm; 2372 u16 max_frame_size; 2373 2374 if (hw->mac.type == e1000_i211) 2375 return; 2376 2377 max_frame_size = sc->shared->isc_max_frame_size; 2378 if (hw->mac.type > e1000_82580) { 2379 2380 if (sc->dmac == 0) { /* Disabling it */ 2381 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2382 return; 2383 } else 2384 device_printf(dev, "DMA Coalescing enabled\n"); 2385 2386 /* Set starting threshold */ 2387 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2388 2389 hwm = 64 * pba - max_frame_size / 16; 2390 if (hwm < 64 * (pba - 6)) 2391 hwm = 64 * (pba - 6); 2392 reg = E1000_READ_REG(hw, E1000_FCRTC); 2393 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2394 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2395 & E1000_FCRTC_RTH_COAL_MASK); 2396 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2397 2398 2399 dmac = pba - max_frame_size / 512; 2400 if (dmac < pba - 10) 2401 dmac = pba - 10; 2402 reg = E1000_READ_REG(hw, E1000_DMACR); 2403 reg &= ~E1000_DMACR_DMACTHR_MASK; 2404 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2405 & E1000_DMACR_DMACTHR_MASK); 2406 2407 /* transition to L0x or L1 if available..*/ 2408 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2409 2410 /* Check if status is 2.5Gb backplane connection 2411 * before configuration of watchdog timer, which is 2412 * in msec values in 12.8usec intervals 2413 * watchdog timer= msec values in 32usec intervals 2414 * for non 2.5Gb connection 2415 */ 2416 if (hw->mac.type == e1000_i354) { 2417 int status = E1000_READ_REG(hw, E1000_STATUS); 2418 if ((status & E1000_STATUS_2P5_SKU) && 2419 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2420 reg |= ((sc->dmac * 5) >> 6); 2421 else 2422 reg |= (sc->dmac >> 5); 2423 } else { 2424 reg |= (sc->dmac >> 5); 2425 } 2426 2427 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2428 2429 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2430 2431 /* Set the interval before transition */ 2432 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2433 if (hw->mac.type == e1000_i350) 2434 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2435 /* 2436 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2437 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2438 */ 2439 if (hw->mac.type == e1000_i354) { 2440 int status = E1000_READ_REG(hw, E1000_STATUS); 2441 if ((status & E1000_STATUS_2P5_SKU) && 2442 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2443 reg |= 0xA; 2444 else 2445 reg |= 0x4; 2446 } else { 2447 reg |= 0x4; 2448 } 2449 2450 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2451 2452 /* free space in tx packet buffer to wake from DMA coal */ 2453 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2454 (2 * max_frame_size)) >> 6); 2455 2456 /* make low power state decision controlled by DMA coal */ 2457 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2458 reg &= ~E1000_PCIEMISC_LX_DECISION; 2459 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2460 2461 } else if (hw->mac.type == e1000_82580) { 2462 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2463 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2464 reg & ~E1000_PCIEMISC_LX_DECISION); 2465 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2466 } 2467 } 2468 2469 /********************************************************************* 2470 * 2471 * Initialize the hardware to a configuration as specified by the 2472 * sc structure. 2473 * 2474 **********************************************************************/ 2475 static void 2476 em_reset(if_ctx_t ctx) 2477 { 2478 device_t dev = iflib_get_dev(ctx); 2479 struct e1000_softc *sc = iflib_get_softc(ctx); 2480 struct ifnet *ifp = iflib_get_ifp(ctx); 2481 struct e1000_hw *hw = &sc->hw; 2482 u16 rx_buffer_size; 2483 u32 pba; 2484 2485 INIT_DEBUGOUT("em_reset: begin"); 2486 /* Let the firmware know the OS is in control */ 2487 em_get_hw_control(sc); 2488 2489 /* Set up smart power down as default off on newer adapters. */ 2490 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2491 hw->mac.type == e1000_82572)) { 2492 u16 phy_tmp = 0; 2493 2494 /* Speed up time to link by disabling smart power down. */ 2495 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2496 phy_tmp &= ~IGP02E1000_PM_SPD; 2497 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2498 } 2499 2500 /* 2501 * Packet Buffer Allocation (PBA) 2502 * Writing PBA sets the receive portion of the buffer 2503 * the remainder is used for the transmit buffer. 2504 */ 2505 switch (hw->mac.type) { 2506 /* 82547: Total Packet Buffer is 40K */ 2507 case e1000_82547: 2508 case e1000_82547_rev_2: 2509 if (hw->mac.max_frame_size > 8192) 2510 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2511 else 2512 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2513 break; 2514 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2515 case e1000_82571: 2516 case e1000_82572: 2517 case e1000_80003es2lan: 2518 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2519 break; 2520 /* 82573: Total Packet Buffer is 32K */ 2521 case e1000_82573: 2522 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2523 break; 2524 case e1000_82574: 2525 case e1000_82583: 2526 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2527 break; 2528 case e1000_ich8lan: 2529 pba = E1000_PBA_8K; 2530 break; 2531 case e1000_ich9lan: 2532 case e1000_ich10lan: 2533 /* Boost Receive side for jumbo frames */ 2534 if (hw->mac.max_frame_size > 4096) 2535 pba = E1000_PBA_14K; 2536 else 2537 pba = E1000_PBA_10K; 2538 break; 2539 case e1000_pchlan: 2540 case e1000_pch2lan: 2541 case e1000_pch_lpt: 2542 case e1000_pch_spt: 2543 case e1000_pch_cnp: 2544 case e1000_pch_tgp: 2545 case e1000_pch_adp: 2546 case e1000_pch_mtp: 2547 pba = E1000_PBA_26K; 2548 break; 2549 case e1000_82575: 2550 pba = E1000_PBA_32K; 2551 break; 2552 case e1000_82576: 2553 case e1000_vfadapt: 2554 pba = E1000_READ_REG(hw, E1000_RXPBS); 2555 pba &= E1000_RXPBS_SIZE_MASK_82576; 2556 break; 2557 case e1000_82580: 2558 case e1000_i350: 2559 case e1000_i354: 2560 case e1000_vfadapt_i350: 2561 pba = E1000_READ_REG(hw, E1000_RXPBS); 2562 pba = e1000_rxpbs_adjust_82580(pba); 2563 break; 2564 case e1000_i210: 2565 case e1000_i211: 2566 pba = E1000_PBA_34K; 2567 break; 2568 default: 2569 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2570 if (hw->mac.max_frame_size > 8192) 2571 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2572 else 2573 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2574 } 2575 2576 /* Special needs in case of Jumbo frames */ 2577 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2578 u32 tx_space, min_tx, min_rx; 2579 pba = E1000_READ_REG(hw, E1000_PBA); 2580 tx_space = pba >> 16; 2581 pba &= 0xffff; 2582 min_tx = (hw->mac.max_frame_size + 2583 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2584 min_tx = roundup2(min_tx, 1024); 2585 min_tx >>= 10; 2586 min_rx = hw->mac.max_frame_size; 2587 min_rx = roundup2(min_rx, 1024); 2588 min_rx >>= 10; 2589 if (tx_space < min_tx && 2590 ((min_tx - tx_space) < pba)) { 2591 pba = pba - (min_tx - tx_space); 2592 /* 2593 * if short on rx space, rx wins 2594 * and must trump tx adjustment 2595 */ 2596 if (pba < min_rx) 2597 pba = min_rx; 2598 } 2599 E1000_WRITE_REG(hw, E1000_PBA, pba); 2600 } 2601 2602 if (hw->mac.type < igb_mac_min) 2603 E1000_WRITE_REG(hw, E1000_PBA, pba); 2604 2605 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2606 2607 /* 2608 * These parameters control the automatic generation (Tx) and 2609 * response (Rx) to Ethernet PAUSE frames. 2610 * - High water mark should allow for at least two frames to be 2611 * received after sending an XOFF. 2612 * - Low water mark works best when it is very near the high water mark. 2613 * This allows the receiver to restart by sending XON when it has 2614 * drained a bit. Here we use an arbitrary value of 1500 which will 2615 * restart after one full frame is pulled from the buffer. There 2616 * could be several smaller frames in the buffer and if so they will 2617 * not trigger the XON until their total number reduces the buffer 2618 * by 1500. 2619 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2620 */ 2621 rx_buffer_size = (pba & 0xffff) << 10; 2622 hw->fc.high_water = rx_buffer_size - 2623 roundup2(hw->mac.max_frame_size, 1024); 2624 hw->fc.low_water = hw->fc.high_water - 1500; 2625 2626 if (sc->fc) /* locally set flow control value? */ 2627 hw->fc.requested_mode = sc->fc; 2628 else 2629 hw->fc.requested_mode = e1000_fc_full; 2630 2631 if (hw->mac.type == e1000_80003es2lan) 2632 hw->fc.pause_time = 0xFFFF; 2633 else 2634 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2635 2636 hw->fc.send_xon = true; 2637 2638 /* Device specific overrides/settings */ 2639 switch (hw->mac.type) { 2640 case e1000_pchlan: 2641 /* Workaround: no TX flow ctrl for PCH */ 2642 hw->fc.requested_mode = e1000_fc_rx_pause; 2643 hw->fc.pause_time = 0xFFFF; /* override */ 2644 if (if_getmtu(ifp) > ETHERMTU) { 2645 hw->fc.high_water = 0x3500; 2646 hw->fc.low_water = 0x1500; 2647 } else { 2648 hw->fc.high_water = 0x5000; 2649 hw->fc.low_water = 0x3000; 2650 } 2651 hw->fc.refresh_time = 0x1000; 2652 break; 2653 case e1000_pch2lan: 2654 case e1000_pch_lpt: 2655 case e1000_pch_spt: 2656 case e1000_pch_cnp: 2657 case e1000_pch_tgp: 2658 case e1000_pch_adp: 2659 case e1000_pch_mtp: 2660 hw->fc.high_water = 0x5C20; 2661 hw->fc.low_water = 0x5048; 2662 hw->fc.pause_time = 0x0650; 2663 hw->fc.refresh_time = 0x0400; 2664 /* Jumbos need adjusted PBA */ 2665 if (if_getmtu(ifp) > ETHERMTU) 2666 E1000_WRITE_REG(hw, E1000_PBA, 12); 2667 else 2668 E1000_WRITE_REG(hw, E1000_PBA, 26); 2669 break; 2670 case e1000_82575: 2671 case e1000_82576: 2672 /* 8-byte granularity */ 2673 hw->fc.low_water = hw->fc.high_water - 8; 2674 break; 2675 case e1000_82580: 2676 case e1000_i350: 2677 case e1000_i354: 2678 case e1000_i210: 2679 case e1000_i211: 2680 case e1000_vfadapt: 2681 case e1000_vfadapt_i350: 2682 /* 16-byte granularity */ 2683 hw->fc.low_water = hw->fc.high_water - 16; 2684 break; 2685 case e1000_ich9lan: 2686 case e1000_ich10lan: 2687 if (if_getmtu(ifp) > ETHERMTU) { 2688 hw->fc.high_water = 0x2800; 2689 hw->fc.low_water = hw->fc.high_water - 8; 2690 break; 2691 } 2692 /* FALLTHROUGH */ 2693 default: 2694 if (hw->mac.type == e1000_80003es2lan) 2695 hw->fc.pause_time = 0xFFFF; 2696 break; 2697 } 2698 2699 /* Issue a global reset */ 2700 e1000_reset_hw(hw); 2701 if (hw->mac.type >= igb_mac_min) { 2702 E1000_WRITE_REG(hw, E1000_WUC, 0); 2703 } else { 2704 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2705 em_disable_aspm(sc); 2706 } 2707 if (sc->flags & IGB_MEDIA_RESET) { 2708 e1000_setup_init_funcs(hw, true); 2709 e1000_get_bus_info(hw); 2710 sc->flags &= ~IGB_MEDIA_RESET; 2711 } 2712 /* and a re-init */ 2713 if (e1000_init_hw(hw) < 0) { 2714 device_printf(dev, "Hardware Initialization Failed\n"); 2715 return; 2716 } 2717 if (hw->mac.type >= igb_mac_min) 2718 igb_init_dmac(sc, pba); 2719 2720 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2721 e1000_get_phy_info(hw); 2722 e1000_check_for_link(hw); 2723 } 2724 2725 /* 2726 * Initialise the RSS mapping for NICs that support multiple transmit/ 2727 * receive rings. 2728 */ 2729 2730 #define RSSKEYLEN 10 2731 static void 2732 em_initialize_rss_mapping(struct e1000_softc *sc) 2733 { 2734 uint8_t rss_key[4 * RSSKEYLEN]; 2735 uint32_t reta = 0; 2736 struct e1000_hw *hw = &sc->hw; 2737 int i; 2738 2739 /* 2740 * Configure RSS key 2741 */ 2742 arc4rand(rss_key, sizeof(rss_key), 0); 2743 for (i = 0; i < RSSKEYLEN; ++i) { 2744 uint32_t rssrk = 0; 2745 2746 rssrk = EM_RSSRK_VAL(rss_key, i); 2747 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2748 } 2749 2750 /* 2751 * Configure RSS redirect table in following fashion: 2752 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2753 */ 2754 for (i = 0; i < sizeof(reta); ++i) { 2755 uint32_t q; 2756 2757 q = (i % sc->rx_num_queues) << 7; 2758 reta |= q << (8 * i); 2759 } 2760 2761 for (i = 0; i < 32; ++i) 2762 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2763 2764 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2765 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2766 E1000_MRQC_RSS_FIELD_IPV4 | 2767 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2768 E1000_MRQC_RSS_FIELD_IPV6_EX | 2769 E1000_MRQC_RSS_FIELD_IPV6); 2770 } 2771 2772 static void 2773 igb_initialize_rss_mapping(struct e1000_softc *sc) 2774 { 2775 struct e1000_hw *hw = &sc->hw; 2776 int i; 2777 int queue_id; 2778 u32 reta; 2779 u32 rss_key[10], mrqc, shift = 0; 2780 2781 /* XXX? */ 2782 if (hw->mac.type == e1000_82575) 2783 shift = 6; 2784 2785 /* 2786 * The redirection table controls which destination 2787 * queue each bucket redirects traffic to. 2788 * Each DWORD represents four queues, with the LSB 2789 * being the first queue in the DWORD. 2790 * 2791 * This just allocates buckets to queues using round-robin 2792 * allocation. 2793 * 2794 * NOTE: It Just Happens to line up with the default 2795 * RSS allocation method. 2796 */ 2797 2798 /* Warning FM follows */ 2799 reta = 0; 2800 for (i = 0; i < 128; i++) { 2801 #ifdef RSS 2802 queue_id = rss_get_indirection_to_bucket(i); 2803 /* 2804 * If we have more queues than buckets, we'll 2805 * end up mapping buckets to a subset of the 2806 * queues. 2807 * 2808 * If we have more buckets than queues, we'll 2809 * end up instead assigning multiple buckets 2810 * to queues. 2811 * 2812 * Both are suboptimal, but we need to handle 2813 * the case so we don't go out of bounds 2814 * indexing arrays and such. 2815 */ 2816 queue_id = queue_id % sc->rx_num_queues; 2817 #else 2818 queue_id = (i % sc->rx_num_queues); 2819 #endif 2820 /* Adjust if required */ 2821 queue_id = queue_id << shift; 2822 2823 /* 2824 * The low 8 bits are for hash value (n+0); 2825 * The next 8 bits are for hash value (n+1), etc. 2826 */ 2827 reta = reta >> 8; 2828 reta = reta | ( ((uint32_t) queue_id) << 24); 2829 if ((i & 3) == 3) { 2830 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2831 reta = 0; 2832 } 2833 } 2834 2835 /* Now fill in hash table */ 2836 2837 /* 2838 * MRQC: Multiple Receive Queues Command 2839 * Set queuing to RSS control, number depends on the device. 2840 */ 2841 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2842 2843 #ifdef RSS 2844 /* XXX ew typecasting */ 2845 rss_getkey((uint8_t *) &rss_key); 2846 #else 2847 arc4rand(&rss_key, sizeof(rss_key), 0); 2848 #endif 2849 for (i = 0; i < 10; i++) 2850 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2851 2852 /* 2853 * Configure the RSS fields to hash upon. 2854 */ 2855 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2856 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2857 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2858 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2859 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2860 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2861 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2862 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2863 2864 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2865 } 2866 2867 /********************************************************************* 2868 * 2869 * Setup networking device structure and register interface media. 2870 * 2871 **********************************************************************/ 2872 static int 2873 em_setup_interface(if_ctx_t ctx) 2874 { 2875 struct ifnet *ifp = iflib_get_ifp(ctx); 2876 struct e1000_softc *sc = iflib_get_softc(ctx); 2877 if_softc_ctx_t scctx = sc->shared; 2878 2879 INIT_DEBUGOUT("em_setup_interface: begin"); 2880 2881 /* Single Queue */ 2882 if (sc->tx_num_queues == 1) { 2883 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2884 if_setsendqready(ifp); 2885 } 2886 2887 /* 2888 * Specify the media types supported by this adapter and register 2889 * callbacks to update media and link information 2890 */ 2891 if (sc->hw.phy.media_type == e1000_media_type_fiber || 2892 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 2893 u_char fiber_type = IFM_1000_SX; /* default type */ 2894 2895 if (sc->hw.mac.type == e1000_82545) 2896 fiber_type = IFM_1000_LX; 2897 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2898 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 2899 } else { 2900 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2901 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2902 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2903 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2904 if (sc->hw.phy.type != e1000_phy_ife) { 2905 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2906 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2907 } 2908 } 2909 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2910 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 2911 return (0); 2912 } 2913 2914 static int 2915 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2916 { 2917 struct e1000_softc *sc = iflib_get_softc(ctx); 2918 if_softc_ctx_t scctx = sc->shared; 2919 int error = E1000_SUCCESS; 2920 struct em_tx_queue *que; 2921 int i, j; 2922 2923 MPASS(sc->tx_num_queues > 0); 2924 MPASS(sc->tx_num_queues == ntxqsets); 2925 2926 /* First allocate the top level queue structs */ 2927 if (!(sc->tx_queues = 2928 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2929 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2930 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2931 return(ENOMEM); 2932 } 2933 2934 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 2935 /* Set up some basics */ 2936 2937 struct tx_ring *txr = &que->txr; 2938 txr->sc = que->sc = sc; 2939 que->me = txr->me = i; 2940 2941 /* Allocate report status array */ 2942 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2943 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2944 error = ENOMEM; 2945 goto fail; 2946 } 2947 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2948 txr->tx_rsq[j] = QIDX_INVALID; 2949 /* get the virtual and physical address of the hardware queues */ 2950 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2951 txr->tx_paddr = paddrs[i*ntxqs]; 2952 } 2953 2954 if (bootverbose) 2955 device_printf(iflib_get_dev(ctx), 2956 "allocated for %d tx_queues\n", sc->tx_num_queues); 2957 return (0); 2958 fail: 2959 em_if_queues_free(ctx); 2960 return (error); 2961 } 2962 2963 static int 2964 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2965 { 2966 struct e1000_softc *sc = iflib_get_softc(ctx); 2967 int error = E1000_SUCCESS; 2968 struct em_rx_queue *que; 2969 int i; 2970 2971 MPASS(sc->rx_num_queues > 0); 2972 MPASS(sc->rx_num_queues == nrxqsets); 2973 2974 /* First allocate the top level queue structs */ 2975 if (!(sc->rx_queues = 2976 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2977 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2978 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2979 error = ENOMEM; 2980 goto fail; 2981 } 2982 2983 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 2984 /* Set up some basics */ 2985 struct rx_ring *rxr = &que->rxr; 2986 rxr->sc = que->sc = sc; 2987 rxr->que = que; 2988 que->me = rxr->me = i; 2989 2990 /* get the virtual and physical address of the hardware queues */ 2991 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2992 rxr->rx_paddr = paddrs[i*nrxqs]; 2993 } 2994 2995 if (bootverbose) 2996 device_printf(iflib_get_dev(ctx), 2997 "allocated for %d rx_queues\n", sc->rx_num_queues); 2998 2999 return (0); 3000 fail: 3001 em_if_queues_free(ctx); 3002 return (error); 3003 } 3004 3005 static void 3006 em_if_queues_free(if_ctx_t ctx) 3007 { 3008 struct e1000_softc *sc = iflib_get_softc(ctx); 3009 struct em_tx_queue *tx_que = sc->tx_queues; 3010 struct em_rx_queue *rx_que = sc->rx_queues; 3011 3012 if (tx_que != NULL) { 3013 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3014 struct tx_ring *txr = &tx_que->txr; 3015 if (txr->tx_rsq == NULL) 3016 break; 3017 3018 free(txr->tx_rsq, M_DEVBUF); 3019 txr->tx_rsq = NULL; 3020 } 3021 free(sc->tx_queues, M_DEVBUF); 3022 sc->tx_queues = NULL; 3023 } 3024 3025 if (rx_que != NULL) { 3026 free(sc->rx_queues, M_DEVBUF); 3027 sc->rx_queues = NULL; 3028 } 3029 } 3030 3031 /********************************************************************* 3032 * 3033 * Enable transmit unit. 3034 * 3035 **********************************************************************/ 3036 static void 3037 em_initialize_transmit_unit(if_ctx_t ctx) 3038 { 3039 struct e1000_softc *sc = iflib_get_softc(ctx); 3040 if_softc_ctx_t scctx = sc->shared; 3041 struct em_tx_queue *que; 3042 struct tx_ring *txr; 3043 struct e1000_hw *hw = &sc->hw; 3044 u32 tctl, txdctl = 0, tarc, tipg = 0; 3045 3046 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3047 3048 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3049 u64 bus_addr; 3050 caddr_t offp, endp; 3051 3052 que = &sc->tx_queues[i]; 3053 txr = &que->txr; 3054 bus_addr = txr->tx_paddr; 3055 3056 /* Clear checksum offload context. */ 3057 offp = (caddr_t)&txr->csum_flags; 3058 endp = (caddr_t)(txr + 1); 3059 bzero(offp, endp - offp); 3060 3061 /* Base and Len of TX Ring */ 3062 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3063 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3064 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3065 (u32)(bus_addr >> 32)); 3066 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3067 (u32)bus_addr); 3068 /* Init the HEAD/TAIL indices */ 3069 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3070 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3071 3072 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3073 E1000_READ_REG(hw, E1000_TDBAL(i)), 3074 E1000_READ_REG(hw, E1000_TDLEN(i))); 3075 3076 txdctl = 0; /* clear txdctl */ 3077 txdctl |= 0x1f; /* PTHRESH */ 3078 txdctl |= 1 << 8; /* HTHRESH */ 3079 txdctl |= 1 << 16;/* WTHRESH */ 3080 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3081 txdctl |= E1000_TXDCTL_GRAN; 3082 txdctl |= 1 << 25; /* LWTHRESH */ 3083 3084 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3085 } 3086 3087 /* Set the default values for the Tx Inter Packet Gap timer */ 3088 switch (hw->mac.type) { 3089 case e1000_80003es2lan: 3090 tipg = DEFAULT_82543_TIPG_IPGR1; 3091 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3092 E1000_TIPG_IPGR2_SHIFT; 3093 break; 3094 case e1000_82542: 3095 tipg = DEFAULT_82542_TIPG_IPGT; 3096 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3097 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3098 break; 3099 default: 3100 if (hw->phy.media_type == e1000_media_type_fiber || 3101 hw->phy.media_type == e1000_media_type_internal_serdes) 3102 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3103 else 3104 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3105 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3106 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3107 } 3108 3109 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3110 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3111 3112 if(hw->mac.type >= e1000_82540) 3113 E1000_WRITE_REG(hw, E1000_TADV, 3114 sc->tx_abs_int_delay.value); 3115 3116 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3117 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3118 tarc |= TARC_SPEED_MODE_BIT; 3119 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3120 } else if (hw->mac.type == e1000_80003es2lan) { 3121 /* errata: program both queues to unweighted RR */ 3122 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3123 tarc |= 1; 3124 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3125 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3126 tarc |= 1; 3127 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3128 } else if (hw->mac.type == e1000_82574) { 3129 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3130 tarc |= TARC_ERRATA_BIT; 3131 if ( sc->tx_num_queues > 1) { 3132 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3133 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3134 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3135 } else 3136 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3137 } 3138 3139 if (sc->tx_int_delay.value > 0) 3140 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3141 3142 /* Program the Transmit Control Register */ 3143 tctl = E1000_READ_REG(hw, E1000_TCTL); 3144 tctl &= ~E1000_TCTL_CT; 3145 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3146 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3147 3148 if (hw->mac.type >= e1000_82571) 3149 tctl |= E1000_TCTL_MULR; 3150 3151 /* This write will effectively turn on the transmit unit. */ 3152 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3153 3154 /* SPT and KBL errata workarounds */ 3155 if (hw->mac.type == e1000_pch_spt) { 3156 u32 reg; 3157 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3158 reg |= E1000_RCTL_RDMTS_HEX; 3159 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3160 /* i218-i219 Specification Update 1.5.4.5 */ 3161 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3162 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3163 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3164 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3165 } 3166 } 3167 3168 /********************************************************************* 3169 * 3170 * Enable receive unit. 3171 * 3172 **********************************************************************/ 3173 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3174 3175 static void 3176 em_initialize_receive_unit(if_ctx_t ctx) 3177 { 3178 struct e1000_softc *sc = iflib_get_softc(ctx); 3179 if_softc_ctx_t scctx = sc->shared; 3180 struct ifnet *ifp = iflib_get_ifp(ctx); 3181 struct e1000_hw *hw = &sc->hw; 3182 struct em_rx_queue *que; 3183 int i; 3184 uint32_t rctl, rxcsum; 3185 3186 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3187 3188 /* 3189 * Make sure receives are disabled while setting 3190 * up the descriptor ring 3191 */ 3192 rctl = E1000_READ_REG(hw, E1000_RCTL); 3193 /* Do not disable if ever enabled on this hardware */ 3194 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3195 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3196 3197 /* Setup the Receive Control Register */ 3198 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3199 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3200 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3201 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3202 3203 /* Do not store bad packets */ 3204 rctl &= ~E1000_RCTL_SBP; 3205 3206 /* Enable Long Packet receive */ 3207 if (if_getmtu(ifp) > ETHERMTU) 3208 rctl |= E1000_RCTL_LPE; 3209 else 3210 rctl &= ~E1000_RCTL_LPE; 3211 3212 /* Strip the CRC */ 3213 if (!em_disable_crc_stripping) 3214 rctl |= E1000_RCTL_SECRC; 3215 3216 if (hw->mac.type >= e1000_82540) { 3217 E1000_WRITE_REG(hw, E1000_RADV, 3218 sc->rx_abs_int_delay.value); 3219 3220 /* 3221 * Set the interrupt throttling rate. Value is calculated 3222 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3223 */ 3224 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3225 } 3226 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3227 3228 if (hw->mac.type >= em_mac_min) { 3229 uint32_t rfctl; 3230 /* Use extended rx descriptor formats */ 3231 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3232 rfctl |= E1000_RFCTL_EXTEN; 3233 3234 /* 3235 * When using MSI-X interrupts we need to throttle 3236 * using the EITR register (82574 only) 3237 */ 3238 if (hw->mac.type == e1000_82574) { 3239 for (int i = 0; i < 4; i++) 3240 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3241 DEFAULT_ITR); 3242 /* Disable accelerated acknowledge */ 3243 rfctl |= E1000_RFCTL_ACK_DIS; 3244 } 3245 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3246 } 3247 3248 /* Set up L3 and L4 csum Rx descriptor offloads */ 3249 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3250 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3251 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3252 if (hw->mac.type > e1000_82575) 3253 rxcsum |= E1000_RXCSUM_CRCOFL; 3254 else if (hw->mac.type < em_mac_min && 3255 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3256 rxcsum |= E1000_RXCSUM_IPV6OFL; 3257 } else { 3258 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3259 if (hw->mac.type > e1000_82575) 3260 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3261 else if (hw->mac.type < em_mac_min) 3262 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3263 } 3264 3265 if (sc->rx_num_queues > 1) { 3266 /* RSS hash needed in the Rx descriptor */ 3267 rxcsum |= E1000_RXCSUM_PCSD; 3268 3269 if (hw->mac.type >= igb_mac_min) 3270 igb_initialize_rss_mapping(sc); 3271 else 3272 em_initialize_rss_mapping(sc); 3273 } 3274 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3275 3276 /* 3277 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3278 * long latencies are observed, like Lenovo X60. This 3279 * change eliminates the problem, but since having positive 3280 * values in RDTR is a known source of problems on other 3281 * platforms another solution is being sought. 3282 */ 3283 if (hw->mac.type == e1000_82573) 3284 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3285 3286 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3287 struct rx_ring *rxr = &que->rxr; 3288 /* Setup the Base and Length of the Rx Descriptor Ring */ 3289 u64 bus_addr = rxr->rx_paddr; 3290 #if 0 3291 u32 rdt = sc->rx_num_queues -1; /* default */ 3292 #endif 3293 3294 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3295 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3296 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3297 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3298 /* Setup the Head and Tail Descriptor Pointers */ 3299 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3300 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3301 } 3302 3303 /* 3304 * Set PTHRESH for improved jumbo performance 3305 * According to 10.2.5.11 of Intel 82574 Datasheet, 3306 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3307 * Only write to RXDCTL(1) if there is a need for different 3308 * settings. 3309 */ 3310 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3311 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3312 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3313 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3314 } else if (hw->mac.type == e1000_82574) { 3315 for (int i = 0; i < sc->rx_num_queues; i++) { 3316 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3317 rxdctl |= 0x20; /* PTHRESH */ 3318 rxdctl |= 4 << 8; /* HTHRESH */ 3319 rxdctl |= 4 << 16;/* WTHRESH */ 3320 rxdctl |= 1 << 24; /* Switch to granularity */ 3321 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3322 } 3323 } else if (hw->mac.type >= igb_mac_min) { 3324 u32 psize, srrctl = 0; 3325 3326 if (if_getmtu(ifp) > ETHERMTU) { 3327 psize = scctx->isc_max_frame_size; 3328 /* are we on a vlan? */ 3329 if (ifp->if_vlantrunk != NULL) 3330 psize += VLAN_TAG_SIZE; 3331 3332 if (sc->vf_ifp) 3333 e1000_rlpml_set_vf(hw, psize); 3334 else 3335 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3336 } 3337 3338 /* Set maximum packet buffer len */ 3339 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3340 E1000_SRRCTL_BSIZEPKT_SHIFT; 3341 3342 /* 3343 * If TX flow control is disabled and there's >1 queue defined, 3344 * enable DROP. 3345 * 3346 * This drops frames rather than hanging the RX MAC for all queues. 3347 */ 3348 if ((sc->rx_num_queues > 1) && 3349 (sc->fc == e1000_fc_none || 3350 sc->fc == e1000_fc_rx_pause)) { 3351 srrctl |= E1000_SRRCTL_DROP_EN; 3352 } 3353 /* Setup the Base and Length of the Rx Descriptor Rings */ 3354 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3355 struct rx_ring *rxr = &que->rxr; 3356 u64 bus_addr = rxr->rx_paddr; 3357 u32 rxdctl; 3358 3359 #ifdef notyet 3360 /* Configure for header split? -- ignore for now */ 3361 rxr->hdr_split = igb_header_split; 3362 #else 3363 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3364 #endif 3365 3366 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3367 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3368 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3369 (uint32_t)(bus_addr >> 32)); 3370 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3371 (uint32_t)bus_addr); 3372 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3373 /* Enable this Queue */ 3374 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3375 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3376 rxdctl &= 0xFFF00000; 3377 rxdctl |= IGB_RX_PTHRESH; 3378 rxdctl |= IGB_RX_HTHRESH << 8; 3379 rxdctl |= IGB_RX_WTHRESH << 16; 3380 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3381 } 3382 } else if (hw->mac.type >= e1000_pch2lan) { 3383 if (if_getmtu(ifp) > ETHERMTU) 3384 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3385 else 3386 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3387 } 3388 3389 /* Make sure VLAN Filters are off */ 3390 rctl &= ~E1000_RCTL_VFE; 3391 3392 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3393 if (hw->mac.type < igb_mac_min) { 3394 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3395 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3396 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3397 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3398 else if (sc->rx_mbuf_sz > 8192) 3399 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3400 else { 3401 rctl |= E1000_RCTL_SZ_2048; 3402 rctl &= ~E1000_RCTL_BSEX; 3403 } 3404 } else 3405 rctl |= E1000_RCTL_SZ_2048; 3406 3407 /* 3408 * rctl bits 11:10 are as follows 3409 * lem: reserved 3410 * em: DTYPE 3411 * igb: reserved 3412 * and should be 00 on all of the above 3413 */ 3414 rctl &= ~0x00000C00; 3415 3416 /* Write out the settings */ 3417 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3418 3419 return; 3420 } 3421 3422 static void 3423 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3424 { 3425 struct e1000_softc *sc = iflib_get_softc(ctx); 3426 u32 index, bit; 3427 3428 index = (vtag >> 5) & 0x7F; 3429 bit = vtag & 0x1F; 3430 sc->shadow_vfta[index] |= (1 << bit); 3431 ++sc->num_vlans; 3432 em_if_vlan_filter_write(sc); 3433 } 3434 3435 static void 3436 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3437 { 3438 struct e1000_softc *sc = iflib_get_softc(ctx); 3439 u32 index, bit; 3440 3441 index = (vtag >> 5) & 0x7F; 3442 bit = vtag & 0x1F; 3443 sc->shadow_vfta[index] &= ~(1 << bit); 3444 --sc->num_vlans; 3445 em_if_vlan_filter_write(sc); 3446 } 3447 3448 static bool 3449 em_if_vlan_filter_capable(if_ctx_t ctx) 3450 { 3451 if_t ifp = iflib_get_ifp(ctx); 3452 3453 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3454 !em_disable_crc_stripping) 3455 return (true); 3456 3457 return (false); 3458 } 3459 3460 static bool 3461 em_if_vlan_filter_used(if_ctx_t ctx) 3462 { 3463 struct e1000_softc *sc = iflib_get_softc(ctx); 3464 3465 if (!em_if_vlan_filter_capable(ctx)) 3466 return (false); 3467 3468 for (int i = 0; i < EM_VFTA_SIZE; i++) 3469 if (sc->shadow_vfta[i] != 0) 3470 return (true); 3471 3472 return (false); 3473 } 3474 3475 static void 3476 em_if_vlan_filter_enable(struct e1000_softc *sc) 3477 { 3478 struct e1000_hw *hw = &sc->hw; 3479 u32 reg; 3480 3481 reg = E1000_READ_REG(hw, E1000_RCTL); 3482 reg &= ~E1000_RCTL_CFIEN; 3483 reg |= E1000_RCTL_VFE; 3484 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3485 } 3486 3487 static void 3488 em_if_vlan_filter_disable(struct e1000_softc *sc) 3489 { 3490 struct e1000_hw *hw = &sc->hw; 3491 u32 reg; 3492 3493 reg = E1000_READ_REG(hw, E1000_RCTL); 3494 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3495 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3496 } 3497 3498 static void 3499 em_if_vlan_filter_write(struct e1000_softc *sc) 3500 { 3501 struct e1000_hw *hw = &sc->hw; 3502 3503 if (sc->vf_ifp) 3504 return; 3505 3506 /* Disable interrupts for lem-class devices during the filter change */ 3507 if (hw->mac.type < em_mac_min) 3508 em_if_intr_disable(sc->ctx); 3509 3510 for (int i = 0; i < EM_VFTA_SIZE; i++) 3511 if (sc->shadow_vfta[i] != 0) { 3512 /* XXXKB: incomplete VF support, we return early above */ 3513 if (sc->vf_ifp) 3514 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3515 else 3516 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3517 } 3518 3519 /* Re-enable interrupts for lem-class devices */ 3520 if (hw->mac.type < em_mac_min) 3521 em_if_intr_enable(sc->ctx); 3522 } 3523 3524 static void 3525 em_setup_vlan_hw_support(if_ctx_t ctx) 3526 { 3527 struct e1000_softc *sc = iflib_get_softc(ctx); 3528 struct e1000_hw *hw = &sc->hw; 3529 struct ifnet *ifp = iflib_get_ifp(ctx); 3530 u32 reg; 3531 3532 /* XXXKB: Return early if we are a VF until VF decap and filter management 3533 * is ready and tested. 3534 */ 3535 if (sc->vf_ifp) 3536 return; 3537 3538 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3539 !em_disable_crc_stripping) { 3540 reg = E1000_READ_REG(hw, E1000_CTRL); 3541 reg |= E1000_CTRL_VME; 3542 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3543 } else { 3544 reg = E1000_READ_REG(hw, E1000_CTRL); 3545 reg &= ~E1000_CTRL_VME; 3546 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3547 } 3548 3549 /* If we aren't doing HW filtering, we're done */ 3550 if (!em_if_vlan_filter_capable(ctx)) { 3551 em_if_vlan_filter_disable(sc); 3552 return; 3553 } 3554 3555 /* 3556 * A soft reset zero's out the VFTA, so 3557 * we need to repopulate it now. 3558 */ 3559 em_if_vlan_filter_write(sc); 3560 3561 /* Enable the Filter Table */ 3562 em_if_vlan_filter_enable(sc); 3563 } 3564 3565 static void 3566 em_if_intr_enable(if_ctx_t ctx) 3567 { 3568 struct e1000_softc *sc = iflib_get_softc(ctx); 3569 struct e1000_hw *hw = &sc->hw; 3570 u32 ims_mask = IMS_ENABLE_MASK; 3571 3572 if (sc->intr_type == IFLIB_INTR_MSIX) { 3573 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3574 ims_mask |= sc->ims; 3575 } 3576 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3577 E1000_WRITE_FLUSH(hw); 3578 } 3579 3580 static void 3581 em_if_intr_disable(if_ctx_t ctx) 3582 { 3583 struct e1000_softc *sc = iflib_get_softc(ctx); 3584 struct e1000_hw *hw = &sc->hw; 3585 3586 if (sc->intr_type == IFLIB_INTR_MSIX) 3587 E1000_WRITE_REG(hw, EM_EIAC, 0); 3588 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3589 E1000_WRITE_FLUSH(hw); 3590 } 3591 3592 static void 3593 igb_if_intr_enable(if_ctx_t ctx) 3594 { 3595 struct e1000_softc *sc = iflib_get_softc(ctx); 3596 struct e1000_hw *hw = &sc->hw; 3597 u32 mask; 3598 3599 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3600 mask = (sc->que_mask | sc->link_mask); 3601 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3602 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3603 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3604 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3605 } else 3606 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3607 E1000_WRITE_FLUSH(hw); 3608 } 3609 3610 static void 3611 igb_if_intr_disable(if_ctx_t ctx) 3612 { 3613 struct e1000_softc *sc = iflib_get_softc(ctx); 3614 struct e1000_hw *hw = &sc->hw; 3615 3616 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3617 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3618 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3619 } 3620 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3621 E1000_WRITE_FLUSH(hw); 3622 } 3623 3624 /* 3625 * Bit of a misnomer, what this really means is 3626 * to enable OS management of the system... aka 3627 * to disable special hardware management features 3628 */ 3629 static void 3630 em_init_manageability(struct e1000_softc *sc) 3631 { 3632 /* A shared code workaround */ 3633 #define E1000_82542_MANC2H E1000_MANC2H 3634 if (sc->has_manage) { 3635 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3636 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3637 3638 /* disable hardware interception of ARP */ 3639 manc &= ~(E1000_MANC_ARP_EN); 3640 3641 /* enable receiving management packets to the host */ 3642 manc |= E1000_MANC_EN_MNG2HOST; 3643 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3644 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3645 manc2h |= E1000_MNG2HOST_PORT_623; 3646 manc2h |= E1000_MNG2HOST_PORT_664; 3647 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3648 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3649 } 3650 } 3651 3652 /* 3653 * Give control back to hardware management 3654 * controller if there is one. 3655 */ 3656 static void 3657 em_release_manageability(struct e1000_softc *sc) 3658 { 3659 if (sc->has_manage) { 3660 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3661 3662 /* re-enable hardware interception of ARP */ 3663 manc |= E1000_MANC_ARP_EN; 3664 manc &= ~E1000_MANC_EN_MNG2HOST; 3665 3666 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3667 } 3668 } 3669 3670 /* 3671 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3672 * For ASF and Pass Through versions of f/w this means 3673 * that the driver is loaded. For AMT version type f/w 3674 * this means that the network i/f is open. 3675 */ 3676 static void 3677 em_get_hw_control(struct e1000_softc *sc) 3678 { 3679 u32 ctrl_ext, swsm; 3680 3681 if (sc->vf_ifp) 3682 return; 3683 3684 if (sc->hw.mac.type == e1000_82573) { 3685 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3686 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3687 swsm | E1000_SWSM_DRV_LOAD); 3688 return; 3689 } 3690 /* else */ 3691 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3692 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3693 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3694 } 3695 3696 /* 3697 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3698 * For ASF and Pass Through versions of f/w this means that 3699 * the driver is no longer loaded. For AMT versions of the 3700 * f/w this means that the network i/f is closed. 3701 */ 3702 static void 3703 em_release_hw_control(struct e1000_softc *sc) 3704 { 3705 u32 ctrl_ext, swsm; 3706 3707 if (!sc->has_manage) 3708 return; 3709 3710 if (sc->hw.mac.type == e1000_82573) { 3711 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3712 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3713 swsm & ~E1000_SWSM_DRV_LOAD); 3714 return; 3715 } 3716 /* else */ 3717 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3718 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3719 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3720 return; 3721 } 3722 3723 static int 3724 em_is_valid_ether_addr(u8 *addr) 3725 { 3726 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3727 3728 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3729 return (false); 3730 } 3731 3732 return (true); 3733 } 3734 3735 /* 3736 ** Parse the interface capabilities with regard 3737 ** to both system management and wake-on-lan for 3738 ** later use. 3739 */ 3740 static void 3741 em_get_wakeup(if_ctx_t ctx) 3742 { 3743 struct e1000_softc *sc = iflib_get_softc(ctx); 3744 device_t dev = iflib_get_dev(ctx); 3745 u16 eeprom_data = 0, device_id, apme_mask; 3746 3747 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3748 apme_mask = EM_EEPROM_APME; 3749 3750 switch (sc->hw.mac.type) { 3751 case e1000_82542: 3752 case e1000_82543: 3753 break; 3754 case e1000_82544: 3755 e1000_read_nvm(&sc->hw, 3756 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3757 apme_mask = EM_82544_APME; 3758 break; 3759 case e1000_82546: 3760 case e1000_82546_rev_3: 3761 if (sc->hw.bus.func == 1) { 3762 e1000_read_nvm(&sc->hw, 3763 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3764 break; 3765 } else 3766 e1000_read_nvm(&sc->hw, 3767 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3768 break; 3769 case e1000_82573: 3770 case e1000_82583: 3771 sc->has_amt = true; 3772 /* FALLTHROUGH */ 3773 case e1000_82571: 3774 case e1000_82572: 3775 case e1000_80003es2lan: 3776 if (sc->hw.bus.func == 1) { 3777 e1000_read_nvm(&sc->hw, 3778 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3779 break; 3780 } else 3781 e1000_read_nvm(&sc->hw, 3782 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3783 break; 3784 case e1000_ich8lan: 3785 case e1000_ich9lan: 3786 case e1000_ich10lan: 3787 case e1000_pchlan: 3788 case e1000_pch2lan: 3789 case e1000_pch_lpt: 3790 case e1000_pch_spt: 3791 case e1000_82575: /* listing all igb devices */ 3792 case e1000_82576: 3793 case e1000_82580: 3794 case e1000_i350: 3795 case e1000_i354: 3796 case e1000_i210: 3797 case e1000_i211: 3798 case e1000_vfadapt: 3799 case e1000_vfadapt_i350: 3800 apme_mask = E1000_WUC_APME; 3801 sc->has_amt = true; 3802 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 3803 break; 3804 default: 3805 e1000_read_nvm(&sc->hw, 3806 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3807 break; 3808 } 3809 if (eeprom_data & apme_mask) 3810 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3811 /* 3812 * We have the eeprom settings, now apply the special cases 3813 * where the eeprom may be wrong or the board won't support 3814 * wake on lan on a particular port 3815 */ 3816 device_id = pci_get_device(dev); 3817 switch (device_id) { 3818 case E1000_DEV_ID_82546GB_PCIE: 3819 sc->wol = 0; 3820 break; 3821 case E1000_DEV_ID_82546EB_FIBER: 3822 case E1000_DEV_ID_82546GB_FIBER: 3823 /* Wake events only supported on port A for dual fiber 3824 * regardless of eeprom setting */ 3825 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3826 E1000_STATUS_FUNC_1) 3827 sc->wol = 0; 3828 break; 3829 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3830 /* if quad port adapter, disable WoL on all but port A */ 3831 if (global_quad_port_a != 0) 3832 sc->wol = 0; 3833 /* Reset for multiple quad port adapters */ 3834 if (++global_quad_port_a == 4) 3835 global_quad_port_a = 0; 3836 break; 3837 case E1000_DEV_ID_82571EB_FIBER: 3838 /* Wake events only supported on port A for dual fiber 3839 * regardless of eeprom setting */ 3840 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3841 E1000_STATUS_FUNC_1) 3842 sc->wol = 0; 3843 break; 3844 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3845 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3846 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3847 /* if quad port adapter, disable WoL on all but port A */ 3848 if (global_quad_port_a != 0) 3849 sc->wol = 0; 3850 /* Reset for multiple quad port adapters */ 3851 if (++global_quad_port_a == 4) 3852 global_quad_port_a = 0; 3853 break; 3854 } 3855 return; 3856 } 3857 3858 3859 /* 3860 * Enable PCI Wake On Lan capability 3861 */ 3862 static void 3863 em_enable_wakeup(if_ctx_t ctx) 3864 { 3865 struct e1000_softc *sc = iflib_get_softc(ctx); 3866 device_t dev = iflib_get_dev(ctx); 3867 if_t ifp = iflib_get_ifp(ctx); 3868 int error = 0; 3869 u32 pmc, ctrl, ctrl_ext, rctl; 3870 u16 status; 3871 3872 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3873 return; 3874 3875 /* 3876 * Determine type of Wakeup: note that wol 3877 * is set with all bits on by default. 3878 */ 3879 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3880 sc->wol &= ~E1000_WUFC_MAG; 3881 3882 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3883 sc->wol &= ~E1000_WUFC_EX; 3884 3885 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3886 sc->wol &= ~E1000_WUFC_MC; 3887 else { 3888 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 3889 rctl |= E1000_RCTL_MPE; 3890 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 3891 } 3892 3893 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3894 goto pme; 3895 3896 /* Advertise the wakeup capability */ 3897 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 3898 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3899 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 3900 3901 /* Keep the laser running on Fiber adapters */ 3902 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3903 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3904 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3905 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3906 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 3907 } 3908 3909 if ((sc->hw.mac.type == e1000_ich8lan) || 3910 (sc->hw.mac.type == e1000_pchlan) || 3911 (sc->hw.mac.type == e1000_ich9lan) || 3912 (sc->hw.mac.type == e1000_ich10lan)) 3913 e1000_suspend_workarounds_ich8lan(&sc->hw); 3914 3915 if ( sc->hw.mac.type >= e1000_pchlan) { 3916 error = em_enable_phy_wakeup(sc); 3917 if (error) 3918 goto pme; 3919 } else { 3920 /* Enable wakeup by the MAC */ 3921 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 3922 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 3923 } 3924 3925 if (sc->hw.phy.type == e1000_phy_igp_3) 3926 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 3927 3928 pme: 3929 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3930 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3931 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3932 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3933 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3934 3935 return; 3936 } 3937 3938 /* 3939 * WOL in the newer chipset interfaces (pchlan) 3940 * require thing to be copied into the phy 3941 */ 3942 static int 3943 em_enable_phy_wakeup(struct e1000_softc *sc) 3944 { 3945 struct e1000_hw *hw = &sc->hw; 3946 u32 mreg, ret = 0; 3947 u16 preg; 3948 3949 /* copy MAC RARs to PHY RARs */ 3950 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3951 3952 /* copy MAC MTA to PHY MTA */ 3953 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3954 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3955 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3956 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3957 (u16)((mreg >> 16) & 0xFFFF)); 3958 } 3959 3960 /* configure PHY Rx Control register */ 3961 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3962 mreg = E1000_READ_REG(hw, E1000_RCTL); 3963 if (mreg & E1000_RCTL_UPE) 3964 preg |= BM_RCTL_UPE; 3965 if (mreg & E1000_RCTL_MPE) 3966 preg |= BM_RCTL_MPE; 3967 preg &= ~(BM_RCTL_MO_MASK); 3968 if (mreg & E1000_RCTL_MO_3) 3969 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3970 << BM_RCTL_MO_SHIFT); 3971 if (mreg & E1000_RCTL_BAM) 3972 preg |= BM_RCTL_BAM; 3973 if (mreg & E1000_RCTL_PMCF) 3974 preg |= BM_RCTL_PMCF; 3975 mreg = E1000_READ_REG(hw, E1000_CTRL); 3976 if (mreg & E1000_CTRL_RFCE) 3977 preg |= BM_RCTL_RFCE; 3978 e1000_write_phy_reg(hw, BM_RCTL, preg); 3979 3980 /* enable PHY wakeup in MAC register */ 3981 E1000_WRITE_REG(hw, E1000_WUC, 3982 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3983 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 3984 3985 /* configure and enable PHY wakeup in PHY registers */ 3986 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 3987 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3988 3989 /* activate PHY wakeup */ 3990 ret = hw->phy.ops.acquire(hw); 3991 if (ret) { 3992 printf("Could not acquire PHY\n"); 3993 return ret; 3994 } 3995 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3996 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3997 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3998 if (ret) { 3999 printf("Could not read PHY page 769\n"); 4000 goto out; 4001 } 4002 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4003 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4004 if (ret) 4005 printf("Could not set PHY Host Wakeup bit\n"); 4006 out: 4007 hw->phy.ops.release(hw); 4008 4009 return ret; 4010 } 4011 4012 static void 4013 em_if_led_func(if_ctx_t ctx, int onoff) 4014 { 4015 struct e1000_softc *sc = iflib_get_softc(ctx); 4016 4017 if (onoff) { 4018 e1000_setup_led(&sc->hw); 4019 e1000_led_on(&sc->hw); 4020 } else { 4021 e1000_led_off(&sc->hw); 4022 e1000_cleanup_led(&sc->hw); 4023 } 4024 } 4025 4026 /* 4027 * Disable the L0S and L1 LINK states 4028 */ 4029 static void 4030 em_disable_aspm(struct e1000_softc *sc) 4031 { 4032 int base, reg; 4033 u16 link_cap,link_ctrl; 4034 device_t dev = sc->dev; 4035 4036 switch (sc->hw.mac.type) { 4037 case e1000_82573: 4038 case e1000_82574: 4039 case e1000_82583: 4040 break; 4041 default: 4042 return; 4043 } 4044 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4045 return; 4046 reg = base + PCIER_LINK_CAP; 4047 link_cap = pci_read_config(dev, reg, 2); 4048 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4049 return; 4050 reg = base + PCIER_LINK_CTL; 4051 link_ctrl = pci_read_config(dev, reg, 2); 4052 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4053 pci_write_config(dev, reg, link_ctrl, 2); 4054 return; 4055 } 4056 4057 /********************************************************************** 4058 * 4059 * Update the board statistics counters. 4060 * 4061 **********************************************************************/ 4062 static void 4063 em_update_stats_counters(struct e1000_softc *sc) 4064 { 4065 u64 prev_xoffrxc = sc->stats.xoffrxc; 4066 4067 if(sc->hw.phy.media_type == e1000_media_type_copper || 4068 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4069 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4070 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4071 } 4072 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4073 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4074 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4075 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4076 4077 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4078 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4079 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4080 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4081 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4082 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4083 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4084 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4085 /* 4086 ** For watchdog management we need to know if we have been 4087 ** paused during the last interval, so capture that here. 4088 */ 4089 if (sc->stats.xoffrxc != prev_xoffrxc) 4090 sc->shared->isc_pause_frames = 1; 4091 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4092 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4093 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4094 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4095 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4096 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4097 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4098 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4099 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4100 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4101 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4102 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4103 4104 /* For the 64-bit byte counters the low dword must be read first. */ 4105 /* Both registers clear on the read of the high dword */ 4106 4107 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4108 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4109 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4110 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4111 4112 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4113 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4114 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4115 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4116 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4117 4118 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4119 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4120 4121 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4122 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4123 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4124 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4125 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4126 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4127 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4128 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4129 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4130 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4131 4132 /* Interrupt Counts */ 4133 4134 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4135 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4136 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4137 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4138 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4139 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4140 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4141 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4142 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4143 4144 if (sc->hw.mac.type >= e1000_82543) { 4145 sc->stats.algnerrc += 4146 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4147 sc->stats.rxerrc += 4148 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4149 sc->stats.tncrs += 4150 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4151 sc->stats.cexterr += 4152 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4153 sc->stats.tsctc += 4154 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4155 sc->stats.tsctfc += 4156 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4157 } 4158 } 4159 4160 static uint64_t 4161 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4162 { 4163 struct e1000_softc *sc = iflib_get_softc(ctx); 4164 struct ifnet *ifp = iflib_get_ifp(ctx); 4165 4166 switch (cnt) { 4167 case IFCOUNTER_COLLISIONS: 4168 return (sc->stats.colc); 4169 case IFCOUNTER_IERRORS: 4170 return (sc->dropped_pkts + sc->stats.rxerrc + 4171 sc->stats.crcerrs + sc->stats.algnerrc + 4172 sc->stats.ruc + sc->stats.roc + 4173 sc->stats.mpc + sc->stats.cexterr); 4174 case IFCOUNTER_OERRORS: 4175 return (sc->stats.ecol + sc->stats.latecol + 4176 sc->watchdog_events); 4177 default: 4178 return (if_get_counter_default(ifp, cnt)); 4179 } 4180 } 4181 4182 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4183 * @ctx: iflib context 4184 * @event: event code to check 4185 * 4186 * Defaults to returning true for unknown events. 4187 * 4188 * @returns true if iflib needs to reinit the interface 4189 */ 4190 static bool 4191 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4192 { 4193 switch (event) { 4194 case IFLIB_RESTART_VLAN_CONFIG: 4195 return (false); 4196 default: 4197 return (true); 4198 } 4199 } 4200 4201 /* Export a single 32-bit register via a read-only sysctl. */ 4202 static int 4203 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4204 { 4205 struct e1000_softc *sc; 4206 u_int val; 4207 4208 sc = oidp->oid_arg1; 4209 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4210 return (sysctl_handle_int(oidp, &val, 0, req)); 4211 } 4212 4213 /* 4214 * Add sysctl variables, one per statistic, to the system. 4215 */ 4216 static void 4217 em_add_hw_stats(struct e1000_softc *sc) 4218 { 4219 device_t dev = iflib_get_dev(sc->ctx); 4220 struct em_tx_queue *tx_que = sc->tx_queues; 4221 struct em_rx_queue *rx_que = sc->rx_queues; 4222 4223 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4224 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4225 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4226 struct e1000_hw_stats *stats = &sc->stats; 4227 4228 struct sysctl_oid *stat_node, *queue_node, *int_node; 4229 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4230 4231 #define QUEUE_NAME_LEN 32 4232 char namebuf[QUEUE_NAME_LEN]; 4233 4234 /* Driver Statistics */ 4235 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4236 CTLFLAG_RD, &sc->dropped_pkts, 4237 "Driver dropped packets"); 4238 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4239 CTLFLAG_RD, &sc->link_irq, 4240 "Link MSI-X IRQ Handled"); 4241 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4242 CTLFLAG_RD, &sc->rx_overruns, 4243 "RX overruns"); 4244 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4245 CTLFLAG_RD, &sc->watchdog_events, 4246 "Watchdog timeouts"); 4247 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4248 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4249 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4250 "Device Control Register"); 4251 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4252 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4253 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4254 "Receiver Control Register"); 4255 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4256 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4257 "Flow Control High Watermark"); 4258 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4259 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4260 "Flow Control Low Watermark"); 4261 4262 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4263 struct tx_ring *txr = &tx_que->txr; 4264 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4265 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4266 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4267 queue_list = SYSCTL_CHILDREN(queue_node); 4268 4269 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4270 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4271 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4272 "Transmit Descriptor Head"); 4273 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4274 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4275 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4276 "Transmit Descriptor Tail"); 4277 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4278 CTLFLAG_RD, &txr->tx_irq, 4279 "Queue MSI-X Transmit Interrupts"); 4280 } 4281 4282 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4283 struct rx_ring *rxr = &rx_que->rxr; 4284 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4285 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4286 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4287 queue_list = SYSCTL_CHILDREN(queue_node); 4288 4289 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4290 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4291 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4292 "Receive Descriptor Head"); 4293 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4294 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4295 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4296 "Receive Descriptor Tail"); 4297 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4298 CTLFLAG_RD, &rxr->rx_irq, 4299 "Queue MSI-X Receive Interrupts"); 4300 } 4301 4302 /* MAC stats get their own sub node */ 4303 4304 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4305 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4306 stat_list = SYSCTL_CHILDREN(stat_node); 4307 4308 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4309 CTLFLAG_RD, &stats->ecol, 4310 "Excessive collisions"); 4311 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4312 CTLFLAG_RD, &stats->scc, 4313 "Single collisions"); 4314 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4315 CTLFLAG_RD, &stats->mcc, 4316 "Multiple collisions"); 4317 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4318 CTLFLAG_RD, &stats->latecol, 4319 "Late collisions"); 4320 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4321 CTLFLAG_RD, &stats->colc, 4322 "Collision Count"); 4323 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4324 CTLFLAG_RD, &sc->stats.symerrs, 4325 "Symbol Errors"); 4326 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4327 CTLFLAG_RD, &sc->stats.sec, 4328 "Sequence Errors"); 4329 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4330 CTLFLAG_RD, &sc->stats.dc, 4331 "Defer Count"); 4332 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4333 CTLFLAG_RD, &sc->stats.mpc, 4334 "Missed Packets"); 4335 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4336 CTLFLAG_RD, &sc->stats.rnbc, 4337 "Receive No Buffers"); 4338 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4339 CTLFLAG_RD, &sc->stats.ruc, 4340 "Receive Undersize"); 4341 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4342 CTLFLAG_RD, &sc->stats.rfc, 4343 "Fragmented Packets Received "); 4344 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4345 CTLFLAG_RD, &sc->stats.roc, 4346 "Oversized Packets Received"); 4347 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4348 CTLFLAG_RD, &sc->stats.rjc, 4349 "Recevied Jabber"); 4350 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4351 CTLFLAG_RD, &sc->stats.rxerrc, 4352 "Receive Errors"); 4353 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4354 CTLFLAG_RD, &sc->stats.crcerrs, 4355 "CRC errors"); 4356 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4357 CTLFLAG_RD, &sc->stats.algnerrc, 4358 "Alignment Errors"); 4359 /* On 82575 these are collision counts */ 4360 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4361 CTLFLAG_RD, &sc->stats.cexterr, 4362 "Collision/Carrier extension errors"); 4363 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4364 CTLFLAG_RD, &sc->stats.xonrxc, 4365 "XON Received"); 4366 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4367 CTLFLAG_RD, &sc->stats.xontxc, 4368 "XON Transmitted"); 4369 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4370 CTLFLAG_RD, &sc->stats.xoffrxc, 4371 "XOFF Received"); 4372 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4373 CTLFLAG_RD, &sc->stats.xofftxc, 4374 "XOFF Transmitted"); 4375 4376 /* Packet Reception Stats */ 4377 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4378 CTLFLAG_RD, &sc->stats.tpr, 4379 "Total Packets Received "); 4380 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4381 CTLFLAG_RD, &sc->stats.gprc, 4382 "Good Packets Received"); 4383 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4384 CTLFLAG_RD, &sc->stats.bprc, 4385 "Broadcast Packets Received"); 4386 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4387 CTLFLAG_RD, &sc->stats.mprc, 4388 "Multicast Packets Received"); 4389 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4390 CTLFLAG_RD, &sc->stats.prc64, 4391 "64 byte frames received "); 4392 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4393 CTLFLAG_RD, &sc->stats.prc127, 4394 "65-127 byte frames received"); 4395 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4396 CTLFLAG_RD, &sc->stats.prc255, 4397 "128-255 byte frames received"); 4398 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4399 CTLFLAG_RD, &sc->stats.prc511, 4400 "256-511 byte frames received"); 4401 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4402 CTLFLAG_RD, &sc->stats.prc1023, 4403 "512-1023 byte frames received"); 4404 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4405 CTLFLAG_RD, &sc->stats.prc1522, 4406 "1023-1522 byte frames received"); 4407 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4408 CTLFLAG_RD, &sc->stats.gorc, 4409 "Good Octets Received"); 4410 4411 /* Packet Transmission Stats */ 4412 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4413 CTLFLAG_RD, &sc->stats.gotc, 4414 "Good Octets Transmitted"); 4415 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4416 CTLFLAG_RD, &sc->stats.tpt, 4417 "Total Packets Transmitted"); 4418 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4419 CTLFLAG_RD, &sc->stats.gptc, 4420 "Good Packets Transmitted"); 4421 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4422 CTLFLAG_RD, &sc->stats.bptc, 4423 "Broadcast Packets Transmitted"); 4424 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4425 CTLFLAG_RD, &sc->stats.mptc, 4426 "Multicast Packets Transmitted"); 4427 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4428 CTLFLAG_RD, &sc->stats.ptc64, 4429 "64 byte frames transmitted "); 4430 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4431 CTLFLAG_RD, &sc->stats.ptc127, 4432 "65-127 byte frames transmitted"); 4433 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4434 CTLFLAG_RD, &sc->stats.ptc255, 4435 "128-255 byte frames transmitted"); 4436 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4437 CTLFLAG_RD, &sc->stats.ptc511, 4438 "256-511 byte frames transmitted"); 4439 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4440 CTLFLAG_RD, &sc->stats.ptc1023, 4441 "512-1023 byte frames transmitted"); 4442 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4443 CTLFLAG_RD, &sc->stats.ptc1522, 4444 "1024-1522 byte frames transmitted"); 4445 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4446 CTLFLAG_RD, &sc->stats.tsctc, 4447 "TSO Contexts Transmitted"); 4448 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4449 CTLFLAG_RD, &sc->stats.tsctfc, 4450 "TSO Contexts Failed"); 4451 4452 4453 /* Interrupt Stats */ 4454 4455 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4456 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4457 int_list = SYSCTL_CHILDREN(int_node); 4458 4459 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4460 CTLFLAG_RD, &sc->stats.iac, 4461 "Interrupt Assertion Count"); 4462 4463 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4464 CTLFLAG_RD, &sc->stats.icrxptc, 4465 "Interrupt Cause Rx Pkt Timer Expire Count"); 4466 4467 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4468 CTLFLAG_RD, &sc->stats.icrxatc, 4469 "Interrupt Cause Rx Abs Timer Expire Count"); 4470 4471 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4472 CTLFLAG_RD, &sc->stats.ictxptc, 4473 "Interrupt Cause Tx Pkt Timer Expire Count"); 4474 4475 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4476 CTLFLAG_RD, &sc->stats.ictxatc, 4477 "Interrupt Cause Tx Abs Timer Expire Count"); 4478 4479 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4480 CTLFLAG_RD, &sc->stats.ictxqec, 4481 "Interrupt Cause Tx Queue Empty Count"); 4482 4483 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4484 CTLFLAG_RD, &sc->stats.ictxqmtc, 4485 "Interrupt Cause Tx Queue Min Thresh Count"); 4486 4487 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4488 CTLFLAG_RD, &sc->stats.icrxdmtc, 4489 "Interrupt Cause Rx Desc Min Thresh Count"); 4490 4491 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4492 CTLFLAG_RD, &sc->stats.icrxoc, 4493 "Interrupt Cause Receiver Overrun Count"); 4494 } 4495 4496 static void 4497 em_fw_version_locked(if_ctx_t ctx) 4498 { 4499 struct e1000_softc *sc = iflib_get_softc(ctx); 4500 struct e1000_hw *hw = &sc->hw; 4501 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4502 uint16_t eep = 0; 4503 4504 /* 4505 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4506 * NVM locking model, so we do it in em_if_attach_pre() and store the 4507 * info in the softc 4508 */ 4509 ASSERT_CTX_LOCK_HELD(hw); 4510 4511 *fw_ver = (struct e1000_fw_version){0}; 4512 4513 if (hw->mac.type >= igb_mac_min) { 4514 /* 4515 * Use the Shared Code for igb(4) 4516 */ 4517 e1000_get_fw_version(hw, fw_ver); 4518 } else { 4519 /* 4520 * Otherwise, EEPROM version should be present on (almost?) all 4521 * devices here 4522 */ 4523 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4524 INIT_DEBUGOUT("can't get EEPROM version"); 4525 return; 4526 } 4527 4528 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4529 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4530 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4531 } 4532 } 4533 4534 static void 4535 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4536 { 4537 const char *space = ""; 4538 4539 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4540 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4541 fw_ver->eep_minor, fw_ver->eep_build); 4542 space = " "; 4543 } 4544 4545 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4546 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4547 space, fw_ver->invm_major, fw_ver->invm_minor, 4548 fw_ver->invm_img_type); 4549 space = " "; 4550 } 4551 4552 if (fw_ver->or_valid) { 4553 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4554 space, fw_ver->or_major, fw_ver->or_build, 4555 fw_ver->or_patch); 4556 space = " "; 4557 } 4558 4559 if (fw_ver->etrack_id) 4560 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4561 } 4562 4563 static void 4564 em_print_fw_version(struct e1000_softc *sc ) 4565 { 4566 device_t dev = sc->dev; 4567 struct sbuf *buf; 4568 int error = 0; 4569 4570 buf = sbuf_new_auto(); 4571 if (!buf) { 4572 device_printf(dev, "Could not allocate sbuf for output.\n"); 4573 return; 4574 } 4575 4576 em_sbuf_fw_version(&sc->fw_ver, buf); 4577 4578 error = sbuf_finish(buf); 4579 if (error) 4580 device_printf(dev, "Error finishing sbuf: %d\n", error); 4581 else if (sbuf_len(buf)) 4582 device_printf(dev, "%s\n", sbuf_data(buf)); 4583 4584 sbuf_delete(buf); 4585 } 4586 4587 static int 4588 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4589 { 4590 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4591 device_t dev = sc->dev; 4592 struct sbuf *buf; 4593 int error = 0; 4594 4595 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4596 if (!buf) { 4597 device_printf(dev, "Could not allocate sbuf for output.\n"); 4598 return (ENOMEM); 4599 } 4600 4601 em_sbuf_fw_version(&sc->fw_ver, buf); 4602 4603 error = sbuf_finish(buf); 4604 if (error) 4605 device_printf(dev, "Error finishing sbuf: %d\n", error); 4606 4607 sbuf_delete(buf); 4608 4609 return (0); 4610 } 4611 4612 /********************************************************************** 4613 * 4614 * This routine provides a way to dump out the adapter eeprom, 4615 * often a useful debug/service tool. This only dumps the first 4616 * 32 words, stuff that matters is in that extent. 4617 * 4618 **********************************************************************/ 4619 static int 4620 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4621 { 4622 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4623 int error; 4624 int result; 4625 4626 result = -1; 4627 error = sysctl_handle_int(oidp, &result, 0, req); 4628 4629 if (error || !req->newptr) 4630 return (error); 4631 4632 /* 4633 * This value will cause a hex dump of the 4634 * first 32 16-bit words of the EEPROM to 4635 * the screen. 4636 */ 4637 if (result == 1) 4638 em_print_nvm_info(sc); 4639 4640 return (error); 4641 } 4642 4643 static void 4644 em_print_nvm_info(struct e1000_softc *sc) 4645 { 4646 struct e1000_hw *hw = &sc->hw; 4647 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4648 u16 eeprom_data; 4649 int i, j, row = 0; 4650 4651 /* Its a bit crude, but it gets the job done */ 4652 printf("\nInterface EEPROM Dump:\n"); 4653 printf("Offset\n0x0000 "); 4654 4655 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4656 sx_xlock(iflib_ctx_lock); 4657 ASSERT_CTX_LOCK_HELD(hw); 4658 for (i = 0, j = 0; i < 32; i++, j++) { 4659 if (j == 8) { /* Make the offset block */ 4660 j = 0; ++row; 4661 printf("\n0x00%x0 ",row); 4662 } 4663 e1000_read_nvm(hw, i, 1, &eeprom_data); 4664 printf("%04x ", eeprom_data); 4665 } 4666 sx_xunlock(iflib_ctx_lock); 4667 printf("\n"); 4668 } 4669 4670 static int 4671 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4672 { 4673 struct em_int_delay_info *info; 4674 struct e1000_softc *sc; 4675 u32 regval; 4676 int error, usecs, ticks; 4677 4678 info = (struct em_int_delay_info *) arg1; 4679 usecs = info->value; 4680 error = sysctl_handle_int(oidp, &usecs, 0, req); 4681 if (error != 0 || req->newptr == NULL) 4682 return (error); 4683 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4684 return (EINVAL); 4685 info->value = usecs; 4686 ticks = EM_USECS_TO_TICKS(usecs); 4687 if (info->offset == E1000_ITR) /* units are 256ns here */ 4688 ticks *= 4; 4689 4690 sc = info->sc; 4691 4692 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4693 regval = (regval & ~0xffff) | (ticks & 0xffff); 4694 /* Handle a few special cases. */ 4695 switch (info->offset) { 4696 case E1000_RDTR: 4697 break; 4698 case E1000_TIDV: 4699 if (ticks == 0) { 4700 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4701 /* Don't write 0 into the TIDV register. */ 4702 regval++; 4703 } else 4704 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4705 break; 4706 } 4707 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4708 return (0); 4709 } 4710 4711 static void 4712 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4713 const char *description, struct em_int_delay_info *info, 4714 int offset, int value) 4715 { 4716 info->sc = sc; 4717 info->offset = offset; 4718 info->value = value; 4719 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4720 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4721 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4722 info, 0, em_sysctl_int_delay, "I", description); 4723 } 4724 4725 /* 4726 * Set flow control using sysctl: 4727 * Flow control values: 4728 * 0 - off 4729 * 1 - rx pause 4730 * 2 - tx pause 4731 * 3 - full 4732 */ 4733 static int 4734 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4735 { 4736 int error; 4737 static int input = 3; /* default is full */ 4738 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4739 4740 error = sysctl_handle_int(oidp, &input, 0, req); 4741 4742 if ((error) || (req->newptr == NULL)) 4743 return (error); 4744 4745 if (input == sc->fc) /* no change? */ 4746 return (error); 4747 4748 switch (input) { 4749 case e1000_fc_rx_pause: 4750 case e1000_fc_tx_pause: 4751 case e1000_fc_full: 4752 case e1000_fc_none: 4753 sc->hw.fc.requested_mode = input; 4754 sc->fc = input; 4755 break; 4756 default: 4757 /* Do nothing */ 4758 return (error); 4759 } 4760 4761 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4762 e1000_force_mac_fc(&sc->hw); 4763 return (error); 4764 } 4765 4766 /* 4767 * Manage Energy Efficient Ethernet: 4768 * Control values: 4769 * 0/1 - enabled/disabled 4770 */ 4771 static int 4772 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4773 { 4774 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4775 int error, value; 4776 4777 value = sc->hw.dev_spec.ich8lan.eee_disable; 4778 error = sysctl_handle_int(oidp, &value, 0, req); 4779 if (error || req->newptr == NULL) 4780 return (error); 4781 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4782 em_if_init(sc->ctx); 4783 4784 return (0); 4785 } 4786 4787 static int 4788 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4789 { 4790 struct e1000_softc *sc; 4791 int error; 4792 int result; 4793 4794 result = -1; 4795 error = sysctl_handle_int(oidp, &result, 0, req); 4796 4797 if (error || !req->newptr) 4798 return (error); 4799 4800 if (result == 1) { 4801 sc = (struct e1000_softc *) arg1; 4802 em_print_debug_info(sc); 4803 } 4804 4805 return (error); 4806 } 4807 4808 static int 4809 em_get_rs(SYSCTL_HANDLER_ARGS) 4810 { 4811 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4812 int error; 4813 int result; 4814 4815 result = 0; 4816 error = sysctl_handle_int(oidp, &result, 0, req); 4817 4818 if (error || !req->newptr || result != 1) 4819 return (error); 4820 em_dump_rs(sc); 4821 4822 return (error); 4823 } 4824 4825 static void 4826 em_if_debug(if_ctx_t ctx) 4827 { 4828 em_dump_rs(iflib_get_softc(ctx)); 4829 } 4830 4831 /* 4832 * This routine is meant to be fluid, add whatever is 4833 * needed for debugging a problem. -jfv 4834 */ 4835 static void 4836 em_print_debug_info(struct e1000_softc *sc) 4837 { 4838 device_t dev = iflib_get_dev(sc->ctx); 4839 struct ifnet *ifp = iflib_get_ifp(sc->ctx); 4840 struct tx_ring *txr = &sc->tx_queues->txr; 4841 struct rx_ring *rxr = &sc->rx_queues->rxr; 4842 4843 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4844 printf("Interface is RUNNING "); 4845 else 4846 printf("Interface is NOT RUNNING\n"); 4847 4848 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4849 printf("and INACTIVE\n"); 4850 else 4851 printf("and ACTIVE\n"); 4852 4853 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 4854 device_printf(dev, "TX Queue %d ------\n", i); 4855 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4856 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 4857 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 4858 4859 } 4860 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 4861 device_printf(dev, "RX Queue %d ------\n", j); 4862 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4863 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 4864 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 4865 } 4866 } 4867 4868 /* 4869 * 82574 only: 4870 * Write a new value to the EEPROM increasing the number of MSI-X 4871 * vectors from 3 to 5, for proper multiqueue support. 4872 */ 4873 static void 4874 em_enable_vectors_82574(if_ctx_t ctx) 4875 { 4876 struct e1000_softc *sc = iflib_get_softc(ctx); 4877 struct e1000_hw *hw = &sc->hw; 4878 device_t dev = iflib_get_dev(ctx); 4879 u16 edata; 4880 4881 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4882 if (bootverbose) 4883 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4884 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4885 device_printf(dev, "Writing to eeprom: increasing " 4886 "reported MSI-X vectors from 3 to 5...\n"); 4887 edata &= ~(EM_NVM_MSIX_N_MASK); 4888 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4889 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4890 e1000_update_nvm_checksum(hw); 4891 device_printf(dev, "Writing to eeprom: done\n"); 4892 } 4893 } 4894