1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.7.8-fbsd"; 41 char igb_driver_version[] = "2.5.19-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 57 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 58 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 61 62 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 63 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 66 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 69 70 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 71 72 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 73 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 74 75 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 76 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 79 80 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 81 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 85 86 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 96 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 97 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 98 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 99 100 /* Intel(R) - em-class devices */ 101 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 109 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 114 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 117 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 140 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 213 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 214 /* required last entry */ 215 PVID_END 216 }; 217 218 static pci_vendor_info_t igb_vendor_info_array[] = 219 { 220 /* Intel(R) - igb-class devices */ 221 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 222 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 224 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 226 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 227 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 232 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 238 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 242 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 244 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 246 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 247 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 251 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 253 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 254 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 256 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 257 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 260 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 261 /* required last entry */ 262 PVID_END 263 }; 264 265 /********************************************************************* 266 * Function prototypes 267 *********************************************************************/ 268 static void *em_register(device_t); 269 static void *igb_register(device_t); 270 static int em_if_attach_pre(if_ctx_t); 271 static int em_if_attach_post(if_ctx_t); 272 static int em_if_detach(if_ctx_t); 273 static int em_if_shutdown(if_ctx_t); 274 static int em_if_suspend(if_ctx_t); 275 static int em_if_resume(if_ctx_t); 276 277 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 279 static void em_if_queues_free(if_ctx_t); 280 281 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 282 static void em_if_init(if_ctx_t); 283 static void em_if_stop(if_ctx_t); 284 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 285 static int em_if_media_change(if_ctx_t); 286 static int em_if_mtu_set(if_ctx_t, uint32_t); 287 static void em_if_timer(if_ctx_t, uint16_t); 288 static void em_if_vlan_register(if_ctx_t, u16); 289 static void em_if_vlan_unregister(if_ctx_t, u16); 290 static void em_if_watchdog_reset(if_ctx_t); 291 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 292 293 static void em_identify_hardware(if_ctx_t); 294 static int em_allocate_pci_resources(if_ctx_t); 295 static void em_free_pci_resources(if_ctx_t); 296 static void em_reset(if_ctx_t); 297 static int em_setup_interface(if_ctx_t); 298 static int em_setup_msix(if_ctx_t); 299 300 static void em_initialize_transmit_unit(if_ctx_t); 301 static void em_initialize_receive_unit(if_ctx_t); 302 303 static void em_if_intr_enable(if_ctx_t); 304 static void em_if_intr_disable(if_ctx_t); 305 static void igb_if_intr_enable(if_ctx_t); 306 static void igb_if_intr_disable(if_ctx_t); 307 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 310 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 311 static void em_if_multi_set(if_ctx_t); 312 static void em_if_update_admin_status(if_ctx_t); 313 static void em_if_debug(if_ctx_t); 314 static void em_update_stats_counters(struct e1000_softc *); 315 static void em_add_hw_stats(struct e1000_softc *); 316 static int em_if_set_promisc(if_ctx_t, int); 317 static bool em_if_vlan_filter_capable(if_ctx_t); 318 static bool em_if_vlan_filter_used(if_ctx_t); 319 static void em_if_vlan_filter_enable(struct e1000_softc *); 320 static void em_if_vlan_filter_disable(struct e1000_softc *); 321 static void em_if_vlan_filter_write(struct e1000_softc *); 322 static void em_setup_vlan_hw_support(if_ctx_t ctx); 323 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 324 static void em_print_nvm_info(struct e1000_softc *); 325 static void em_fw_version_locked(if_ctx_t); 326 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 327 static void em_print_fw_version(struct e1000_softc *); 328 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_get_rs(SYSCTL_HANDLER_ARGS); 331 static void em_print_debug_info(struct e1000_softc *); 332 static int em_is_valid_ether_addr(u8 *); 333 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 334 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 335 const char *, struct em_int_delay_info *, int, int); 336 /* Management and WOL Support */ 337 static void em_init_manageability(struct e1000_softc *); 338 static void em_release_manageability(struct e1000_softc *); 339 static void em_get_hw_control(struct e1000_softc *); 340 static void em_release_hw_control(struct e1000_softc *); 341 static void em_get_wakeup(if_ctx_t); 342 static void em_enable_wakeup(if_ctx_t); 343 static int em_enable_phy_wakeup(struct e1000_softc *); 344 static void em_disable_aspm(struct e1000_softc *); 345 346 int em_intr(void *); 347 348 /* MSI-X handlers */ 349 static int em_if_msix_intr_assign(if_ctx_t, int); 350 static int em_msix_link(void *); 351 static void em_handle_link(void *); 352 353 static void em_enable_vectors_82574(if_ctx_t); 354 355 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 356 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 357 static void em_if_led_func(if_ctx_t, int); 358 359 static int em_get_regs(SYSCTL_HANDLER_ARGS); 360 361 static void lem_smartspeed(struct e1000_softc *); 362 static void igb_configure_queues(struct e1000_softc *); 363 static void em_flush_desc_rings(struct e1000_softc *); 364 365 366 /********************************************************************* 367 * FreeBSD Device Interface Entry Points 368 *********************************************************************/ 369 static device_method_t em_methods[] = { 370 /* Device interface */ 371 DEVMETHOD(device_register, em_register), 372 DEVMETHOD(device_probe, iflib_device_probe), 373 DEVMETHOD(device_attach, iflib_device_attach), 374 DEVMETHOD(device_detach, iflib_device_detach), 375 DEVMETHOD(device_shutdown, iflib_device_shutdown), 376 DEVMETHOD(device_suspend, iflib_device_suspend), 377 DEVMETHOD(device_resume, iflib_device_resume), 378 DEVMETHOD_END 379 }; 380 381 static device_method_t igb_methods[] = { 382 /* Device interface */ 383 DEVMETHOD(device_register, igb_register), 384 DEVMETHOD(device_probe, iflib_device_probe), 385 DEVMETHOD(device_attach, iflib_device_attach), 386 DEVMETHOD(device_detach, iflib_device_detach), 387 DEVMETHOD(device_shutdown, iflib_device_shutdown), 388 DEVMETHOD(device_suspend, iflib_device_suspend), 389 DEVMETHOD(device_resume, iflib_device_resume), 390 DEVMETHOD_END 391 }; 392 393 394 static driver_t em_driver = { 395 "em", em_methods, sizeof(struct e1000_softc), 396 }; 397 398 DRIVER_MODULE(em, pci, em_driver, 0, 0); 399 400 MODULE_DEPEND(em, pci, 1, 1, 1); 401 MODULE_DEPEND(em, ether, 1, 1, 1); 402 MODULE_DEPEND(em, iflib, 1, 1, 1); 403 404 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 405 406 static driver_t igb_driver = { 407 "igb", igb_methods, sizeof(struct e1000_softc), 408 }; 409 410 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 411 412 MODULE_DEPEND(igb, pci, 1, 1, 1); 413 MODULE_DEPEND(igb, ether, 1, 1, 1); 414 MODULE_DEPEND(igb, iflib, 1, 1, 1); 415 416 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 417 418 static device_method_t em_if_methods[] = { 419 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 420 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 421 DEVMETHOD(ifdi_detach, em_if_detach), 422 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 423 DEVMETHOD(ifdi_suspend, em_if_suspend), 424 DEVMETHOD(ifdi_resume, em_if_resume), 425 DEVMETHOD(ifdi_init, em_if_init), 426 DEVMETHOD(ifdi_stop, em_if_stop), 427 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 428 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 429 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 430 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 431 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 432 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 433 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 434 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 435 DEVMETHOD(ifdi_media_status, em_if_media_status), 436 DEVMETHOD(ifdi_media_change, em_if_media_change), 437 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 438 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 439 DEVMETHOD(ifdi_timer, em_if_timer), 440 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 441 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 442 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 443 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 444 DEVMETHOD(ifdi_led_func, em_if_led_func), 445 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 446 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 447 DEVMETHOD(ifdi_debug, em_if_debug), 448 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 449 DEVMETHOD_END 450 }; 451 452 static driver_t em_if_driver = { 453 "em_if", em_if_methods, sizeof(struct e1000_softc) 454 }; 455 456 static device_method_t igb_if_methods[] = { 457 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 458 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 459 DEVMETHOD(ifdi_detach, em_if_detach), 460 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 461 DEVMETHOD(ifdi_suspend, em_if_suspend), 462 DEVMETHOD(ifdi_resume, em_if_resume), 463 DEVMETHOD(ifdi_init, em_if_init), 464 DEVMETHOD(ifdi_stop, em_if_stop), 465 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 466 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 467 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 468 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 469 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 470 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 471 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 472 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 473 DEVMETHOD(ifdi_media_status, em_if_media_status), 474 DEVMETHOD(ifdi_media_change, em_if_media_change), 475 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 476 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 477 DEVMETHOD(ifdi_timer, em_if_timer), 478 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 479 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 480 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 481 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 482 DEVMETHOD(ifdi_led_func, em_if_led_func), 483 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 484 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 485 DEVMETHOD(ifdi_debug, em_if_debug), 486 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 487 DEVMETHOD_END 488 }; 489 490 static driver_t igb_if_driver = { 491 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 492 }; 493 494 /********************************************************************* 495 * Tunable default values. 496 *********************************************************************/ 497 498 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 499 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 500 501 #define MAX_INTS_PER_SEC 8000 502 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 503 504 /* Allow common code without TSO */ 505 #ifndef CSUM_TSO 506 #define CSUM_TSO 0 507 #endif 508 509 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 510 "EM driver parameters"); 511 512 static int em_disable_crc_stripping = 0; 513 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 514 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 515 516 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 517 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 518 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 519 0, "Default transmit interrupt delay in usecs"); 520 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 521 0, "Default receive interrupt delay in usecs"); 522 523 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 524 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 525 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 526 &em_tx_abs_int_delay_dflt, 0, 527 "Default transmit interrupt delay limit in usecs"); 528 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 529 &em_rx_abs_int_delay_dflt, 0, 530 "Default receive interrupt delay limit in usecs"); 531 532 static int em_smart_pwr_down = false; 533 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 534 0, "Set to true to leave smart power down enabled on newer adapters"); 535 536 /* Controls whether promiscuous also shows bad packets */ 537 static int em_debug_sbp = false; 538 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 539 "Show bad packets in promiscuous mode"); 540 541 /* How many packets rxeof tries to clean at a time */ 542 static int em_rx_process_limit = 100; 543 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 544 &em_rx_process_limit, 0, 545 "Maximum number of received packets to process " 546 "at a time, -1 means unlimited"); 547 548 /* Energy efficient ethernet - default to OFF */ 549 static int eee_setting = 1; 550 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 551 "Enable Energy Efficient Ethernet"); 552 553 /* 554 ** Tuneable Interrupt rate 555 */ 556 static int em_max_interrupt_rate = 8000; 557 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 558 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 559 560 561 562 /* Global used in WOL setup with multiport cards */ 563 static int global_quad_port_a = 0; 564 565 extern struct if_txrx igb_txrx; 566 extern struct if_txrx em_txrx; 567 extern struct if_txrx lem_txrx; 568 569 static struct if_shared_ctx em_sctx_init = { 570 .isc_magic = IFLIB_MAGIC, 571 .isc_q_align = PAGE_SIZE, 572 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 573 .isc_tx_maxsegsize = PAGE_SIZE, 574 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 575 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 576 .isc_rx_maxsize = MJUM9BYTES, 577 .isc_rx_nsegments = 1, 578 .isc_rx_maxsegsize = MJUM9BYTES, 579 .isc_nfl = 1, 580 .isc_nrxqs = 1, 581 .isc_ntxqs = 1, 582 .isc_admin_intrcnt = 1, 583 .isc_vendor_info = em_vendor_info_array, 584 .isc_driver_version = em_driver_version, 585 .isc_driver = &em_if_driver, 586 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 587 588 .isc_nrxd_min = {EM_MIN_RXD}, 589 .isc_ntxd_min = {EM_MIN_TXD}, 590 .isc_nrxd_max = {EM_MAX_RXD}, 591 .isc_ntxd_max = {EM_MAX_TXD}, 592 .isc_nrxd_default = {EM_DEFAULT_RXD}, 593 .isc_ntxd_default = {EM_DEFAULT_TXD}, 594 }; 595 596 static struct if_shared_ctx igb_sctx_init = { 597 .isc_magic = IFLIB_MAGIC, 598 .isc_q_align = PAGE_SIZE, 599 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 600 .isc_tx_maxsegsize = PAGE_SIZE, 601 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 602 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 603 .isc_rx_maxsize = MJUM9BYTES, 604 .isc_rx_nsegments = 1, 605 .isc_rx_maxsegsize = MJUM9BYTES, 606 .isc_nfl = 1, 607 .isc_nrxqs = 1, 608 .isc_ntxqs = 1, 609 .isc_admin_intrcnt = 1, 610 .isc_vendor_info = igb_vendor_info_array, 611 .isc_driver_version = igb_driver_version, 612 .isc_driver = &igb_if_driver, 613 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 614 615 .isc_nrxd_min = {EM_MIN_RXD}, 616 .isc_ntxd_min = {EM_MIN_TXD}, 617 .isc_nrxd_max = {IGB_MAX_RXD}, 618 .isc_ntxd_max = {IGB_MAX_TXD}, 619 .isc_nrxd_default = {EM_DEFAULT_RXD}, 620 .isc_ntxd_default = {EM_DEFAULT_TXD}, 621 }; 622 623 /***************************************************************** 624 * 625 * Dump Registers 626 * 627 ****************************************************************/ 628 #define IGB_REGS_LEN 739 629 630 static int em_get_regs(SYSCTL_HANDLER_ARGS) 631 { 632 struct e1000_softc *sc = (struct e1000_softc *)arg1; 633 struct e1000_hw *hw = &sc->hw; 634 struct sbuf *sb; 635 u32 *regs_buff; 636 int rc; 637 638 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 639 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 640 641 rc = sysctl_wire_old_buffer(req, 0); 642 MPASS(rc == 0); 643 if (rc != 0) { 644 free(regs_buff, M_DEVBUF); 645 return (rc); 646 } 647 648 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 649 MPASS(sb != NULL); 650 if (sb == NULL) { 651 free(regs_buff, M_DEVBUF); 652 return (ENOMEM); 653 } 654 655 /* General Registers */ 656 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 657 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 658 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 659 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 660 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 661 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 662 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 663 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 664 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 665 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 666 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 667 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 668 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 669 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 670 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 671 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 672 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 673 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 674 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 675 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 676 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 677 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 678 679 sbuf_printf(sb, "General Registers\n"); 680 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 681 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 682 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 683 684 sbuf_printf(sb, "Interrupt Registers\n"); 685 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 686 687 sbuf_printf(sb, "RX Registers\n"); 688 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 689 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 690 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 691 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 692 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 693 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 694 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 695 696 sbuf_printf(sb, "TX Registers\n"); 697 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 698 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 699 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 700 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 701 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 702 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 703 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 704 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 705 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 706 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 707 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 708 709 free(regs_buff, M_DEVBUF); 710 711 #ifdef DUMP_DESCS 712 { 713 if_softc_ctx_t scctx = sc->shared; 714 struct rx_ring *rxr = &rx_que->rxr; 715 struct tx_ring *txr = &tx_que->txr; 716 int ntxd = scctx->isc_ntxd[0]; 717 int nrxd = scctx->isc_nrxd[0]; 718 int j; 719 720 for (j = 0; j < nrxd; j++) { 721 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 722 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 723 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 724 } 725 726 for (j = 0; j < min(ntxd, 256); j++) { 727 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 728 729 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 730 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 731 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 732 733 } 734 } 735 #endif 736 737 rc = sbuf_finish(sb); 738 sbuf_delete(sb); 739 return(rc); 740 } 741 742 static void * 743 em_register(device_t dev) 744 { 745 return (&em_sctx_init); 746 } 747 748 static void * 749 igb_register(device_t dev) 750 { 751 return (&igb_sctx_init); 752 } 753 754 static int 755 em_set_num_queues(if_ctx_t ctx) 756 { 757 struct e1000_softc *sc = iflib_get_softc(ctx); 758 int maxqueues; 759 760 /* Sanity check based on HW */ 761 switch (sc->hw.mac.type) { 762 case e1000_82576: 763 case e1000_82580: 764 case e1000_i350: 765 case e1000_i354: 766 maxqueues = 8; 767 break; 768 case e1000_i210: 769 case e1000_82575: 770 maxqueues = 4; 771 break; 772 case e1000_i211: 773 case e1000_82574: 774 maxqueues = 2; 775 break; 776 default: 777 maxqueues = 1; 778 break; 779 } 780 781 return (maxqueues); 782 } 783 784 #define LEM_CAPS \ 785 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 786 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 787 IFCAP_LRO | IFCAP_VLAN_HWTSO| IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 788 IFCAP_TSO6 789 790 #define EM_CAPS \ 791 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 792 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 793 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 794 IFCAP_TSO6 795 796 #define IGB_CAPS \ 797 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 798 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 799 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 800 IFCAP_TSO6 801 802 /********************************************************************* 803 * Device initialization routine 804 * 805 * The attach entry point is called when the driver is being loaded. 806 * This routine identifies the type of hardware, allocates all resources 807 * and initializes the hardware. 808 * 809 * return 0 on success, positive on failure 810 *********************************************************************/ 811 static int 812 em_if_attach_pre(if_ctx_t ctx) 813 { 814 struct e1000_softc *sc; 815 if_softc_ctx_t scctx; 816 device_t dev; 817 struct e1000_hw *hw; 818 struct sysctl_oid_list *child; 819 struct sysctl_ctx_list *ctx_list; 820 int error = 0; 821 822 INIT_DEBUGOUT("em_if_attach_pre: begin"); 823 dev = iflib_get_dev(ctx); 824 sc = iflib_get_softc(ctx); 825 826 sc->ctx = sc->osdep.ctx = ctx; 827 sc->dev = sc->osdep.dev = dev; 828 scctx = sc->shared = iflib_get_softc_ctx(ctx); 829 sc->media = iflib_get_media(ctx); 830 hw = &sc->hw; 831 832 sc->tx_process_limit = scctx->isc_ntxd[0]; 833 834 /* Determine hardware and mac info */ 835 em_identify_hardware(ctx); 836 837 /* SYSCTL stuff */ 838 ctx_list = device_get_sysctl_ctx(dev); 839 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 840 841 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 842 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 843 em_sysctl_nvm_info, "I", "NVM Information"); 844 845 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 846 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 847 em_sysctl_print_fw_version, "A", 848 "Prints FW/NVM Versions"); 849 850 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 851 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 852 em_sysctl_debug_info, "I", "Debug Information"); 853 854 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 855 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 856 em_set_flowcntl, "I", "Flow Control"); 857 858 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 859 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 860 em_get_regs, "A", "Dump Registers"); 861 862 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 863 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 864 em_get_rs, "I", "Dump RS indexes"); 865 866 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 867 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 868 if (bootverbose) 869 device_printf(dev, "attach_pre capping queues at %d\n", 870 scctx->isc_ntxqsets_max); 871 872 if (hw->mac.type >= igb_mac_min) { 873 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 874 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 875 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 876 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 877 scctx->isc_txrx = &igb_txrx; 878 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 879 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 880 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 881 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 882 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 883 CSUM_IP6_TCP | CSUM_IP6_UDP; 884 if (hw->mac.type != e1000_82575) 885 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 886 /* 887 ** Some new devices, as with ixgbe, now may 888 ** use a different BAR, so we need to keep 889 ** track of which is used. 890 */ 891 scctx->isc_msix_bar = pci_msix_table_bar(dev); 892 } else if (hw->mac.type >= em_mac_min) { 893 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 894 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 895 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 896 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 897 scctx->isc_txrx = &em_txrx; 898 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 899 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 900 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 901 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 902 /* 903 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO,TSO6} 904 * by default as we don't have workarounds for all associated 905 * silicon errata. E. g., with several MACs such as 82573E, 906 * TSO only works at Gigabit speed and otherwise can cause the 907 * hardware to hang (which also would be next to impossible to 908 * work around given that already queued TSO-using descriptors 909 * would need to be flushed and vlan(4) reconfigured at runtime 910 * in case of a link speed change). Moreover, MACs like 82579 911 * still can hang at Gigabit even with all publicly documented 912 * TSO workarounds implemented. Generally, the penality of 913 * these workarounds is rather high and may involve copying 914 * mbuf data around so advantages of TSO lapse. Still, TSO may 915 * work for a few MACs of this class - at least when sticking 916 * with Gigabit - in which case users may enable TSO manually. 917 */ 918 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO | IFCAP_TSO6); 919 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 920 CSUM_IP6_TCP | CSUM_IP6_UDP; 921 /* 922 * We support MSI-X with 82574 only, but indicate to iflib(4) 923 * that it shall give MSI at least a try with other devices. 924 */ 925 if (hw->mac.type == e1000_82574) { 926 scctx->isc_msix_bar = pci_msix_table_bar(dev); 927 } else { 928 scctx->isc_msix_bar = -1; 929 scctx->isc_disable_msix = 1; 930 } 931 } else { 932 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 933 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 934 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 935 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 936 scctx->isc_txrx = &lem_txrx; 937 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 938 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 939 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 940 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 941 /* 942 * For LEM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO,TSO6} 943 * by default as we don't have workarounds for all associated 944 * silicon errata. TSO4 may work on > 82544 but its status 945 * is unknown by the authors. Please report any success or failures. 946 */ 947 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO | IFCAP_TSO6); 948 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 949 CSUM_IP6_TCP | CSUM_IP6_UDP; 950 951 /* 8254x SDM4.0 page 33 - FDX requirement on these chips */ 952 if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) 953 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 954 955 if (hw->mac.type < e1000_82543) 956 scctx->isc_capabilities &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 957 /* 82541ER doesn't do HW tagging */ 958 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 959 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 960 /* INTx only */ 961 scctx->isc_msix_bar = 0; 962 } 963 964 /* Setup PCI resources */ 965 if (em_allocate_pci_resources(ctx)) { 966 device_printf(dev, "Allocation of PCI resources failed\n"); 967 error = ENXIO; 968 goto err_pci; 969 } 970 971 /* 972 ** For ICH8 and family we need to 973 ** map the flash memory, and this 974 ** must happen after the MAC is 975 ** identified 976 */ 977 if ((hw->mac.type == e1000_ich8lan) || 978 (hw->mac.type == e1000_ich9lan) || 979 (hw->mac.type == e1000_ich10lan) || 980 (hw->mac.type == e1000_pchlan) || 981 (hw->mac.type == e1000_pch2lan) || 982 (hw->mac.type == e1000_pch_lpt)) { 983 int rid = EM_BAR_TYPE_FLASH; 984 sc->flash = bus_alloc_resource_any(dev, 985 SYS_RES_MEMORY, &rid, RF_ACTIVE); 986 if (sc->flash == NULL) { 987 device_printf(dev, "Mapping of Flash failed\n"); 988 error = ENXIO; 989 goto err_pci; 990 } 991 /* This is used in the shared code */ 992 hw->flash_address = (u8 *)sc->flash; 993 sc->osdep.flash_bus_space_tag = 994 rman_get_bustag(sc->flash); 995 sc->osdep.flash_bus_space_handle = 996 rman_get_bushandle(sc->flash); 997 } 998 /* 999 ** In the new SPT device flash is not a 1000 ** separate BAR, rather it is also in BAR0, 1001 ** so use the same tag and an offset handle for the 1002 ** FLASH read/write macros in the shared code. 1003 */ 1004 else if (hw->mac.type >= e1000_pch_spt) { 1005 sc->osdep.flash_bus_space_tag = 1006 sc->osdep.mem_bus_space_tag; 1007 sc->osdep.flash_bus_space_handle = 1008 sc->osdep.mem_bus_space_handle 1009 + E1000_FLASH_BASE_ADDR; 1010 } 1011 1012 /* Do Shared Code initialization */ 1013 error = e1000_setup_init_funcs(hw, true); 1014 if (error) { 1015 device_printf(dev, "Setup of Shared code failed, error %d\n", 1016 error); 1017 error = ENXIO; 1018 goto err_pci; 1019 } 1020 1021 em_setup_msix(ctx); 1022 e1000_get_bus_info(hw); 1023 1024 /* Set up some sysctls for the tunable interrupt delays */ 1025 em_add_int_delay_sysctl(sc, "rx_int_delay", 1026 "receive interrupt delay in usecs", &sc->rx_int_delay, 1027 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1028 em_add_int_delay_sysctl(sc, "tx_int_delay", 1029 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1030 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1031 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1032 "receive interrupt delay limit in usecs", 1033 &sc->rx_abs_int_delay, 1034 E1000_REGISTER(hw, E1000_RADV), 1035 em_rx_abs_int_delay_dflt); 1036 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1037 "transmit interrupt delay limit in usecs", 1038 &sc->tx_abs_int_delay, 1039 E1000_REGISTER(hw, E1000_TADV), 1040 em_tx_abs_int_delay_dflt); 1041 em_add_int_delay_sysctl(sc, "itr", 1042 "interrupt delay limit in usecs/4", 1043 &sc->tx_itr, 1044 E1000_REGISTER(hw, E1000_ITR), 1045 DEFAULT_ITR); 1046 1047 hw->mac.autoneg = DO_AUTO_NEG; 1048 hw->phy.autoneg_wait_to_complete = false; 1049 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1050 1051 if (hw->mac.type < em_mac_min) { 1052 e1000_init_script_state_82541(hw, true); 1053 e1000_set_tbi_compatibility_82543(hw, true); 1054 } 1055 /* Copper options */ 1056 if (hw->phy.media_type == e1000_media_type_copper) { 1057 hw->phy.mdix = AUTO_ALL_MODES; 1058 hw->phy.disable_polarity_correction = false; 1059 hw->phy.ms_type = EM_MASTER_SLAVE; 1060 } 1061 1062 /* 1063 * Set the frame limits assuming 1064 * standard ethernet sized frames. 1065 */ 1066 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1067 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1068 1069 /* 1070 * This controls when hardware reports transmit completion 1071 * status. 1072 */ 1073 hw->mac.report_tx_early = 1; 1074 1075 /* Allocate multicast array memory. */ 1076 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1077 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1078 if (sc->mta == NULL) { 1079 device_printf(dev, "Can not allocate multicast setup array\n"); 1080 error = ENOMEM; 1081 goto err_late; 1082 } 1083 1084 /* Check SOL/IDER usage */ 1085 if (e1000_check_reset_block(hw)) 1086 device_printf(dev, "PHY reset is blocked" 1087 " due to SOL/IDER session.\n"); 1088 1089 /* Sysctl for setting Energy Efficient Ethernet */ 1090 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1091 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1092 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1093 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1094 1095 /* 1096 ** Start from a known state, this is 1097 ** important in reading the nvm and 1098 ** mac from that. 1099 */ 1100 e1000_reset_hw(hw); 1101 1102 /* Make sure we have a good EEPROM before we read from it */ 1103 if (e1000_validate_nvm_checksum(hw) < 0) { 1104 /* 1105 ** Some PCI-E parts fail the first check due to 1106 ** the link being in sleep state, call it again, 1107 ** if it fails a second time its a real issue. 1108 */ 1109 if (e1000_validate_nvm_checksum(hw) < 0) { 1110 device_printf(dev, 1111 "The EEPROM Checksum Is Not Valid\n"); 1112 error = EIO; 1113 goto err_late; 1114 } 1115 } 1116 1117 /* Copy the permanent MAC address out of the EEPROM */ 1118 if (e1000_read_mac_addr(hw) < 0) { 1119 device_printf(dev, "EEPROM read error while reading MAC" 1120 " address\n"); 1121 error = EIO; 1122 goto err_late; 1123 } 1124 1125 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1126 if (sc->vf_ifp) { 1127 ether_gen_addr(iflib_get_ifp(ctx), 1128 (struct ether_addr *)hw->mac.addr); 1129 } else { 1130 device_printf(dev, "Invalid MAC address\n"); 1131 error = EIO; 1132 goto err_late; 1133 } 1134 } 1135 1136 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1137 em_fw_version_locked(ctx); 1138 1139 em_print_fw_version(sc); 1140 1141 /* 1142 * Get Wake-on-Lan and Management info for later use 1143 */ 1144 em_get_wakeup(ctx); 1145 1146 /* Enable only WOL MAGIC by default */ 1147 scctx->isc_capenable &= ~IFCAP_WOL; 1148 if (sc->wol != 0) 1149 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1150 1151 iflib_set_mac(ctx, hw->mac.addr); 1152 1153 return (0); 1154 1155 err_late: 1156 em_release_hw_control(sc); 1157 err_pci: 1158 em_free_pci_resources(ctx); 1159 free(sc->mta, M_DEVBUF); 1160 1161 return (error); 1162 } 1163 1164 static int 1165 em_if_attach_post(if_ctx_t ctx) 1166 { 1167 struct e1000_softc *sc = iflib_get_softc(ctx); 1168 struct e1000_hw *hw = &sc->hw; 1169 int error = 0; 1170 1171 /* Setup OS specific network interface */ 1172 error = em_setup_interface(ctx); 1173 if (error != 0) { 1174 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1175 goto err_late; 1176 } 1177 1178 em_reset(ctx); 1179 1180 /* Initialize statistics */ 1181 em_update_stats_counters(sc); 1182 hw->mac.get_link_status = 1; 1183 em_if_update_admin_status(ctx); 1184 em_add_hw_stats(sc); 1185 1186 /* Non-AMT based hardware can now take control from firmware */ 1187 if (sc->has_manage && !sc->has_amt) 1188 em_get_hw_control(sc); 1189 1190 INIT_DEBUGOUT("em_if_attach_post: end"); 1191 1192 return (0); 1193 1194 err_late: 1195 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1196 return (error); 1197 } 1198 1199 /********************************************************************* 1200 * Device removal routine 1201 * 1202 * The detach entry point is called when the driver is being removed. 1203 * This routine stops the adapter and deallocates all the resources 1204 * that were allocated for driver operation. 1205 * 1206 * return 0 on success, positive on failure 1207 *********************************************************************/ 1208 static int 1209 em_if_detach(if_ctx_t ctx) 1210 { 1211 struct e1000_softc *sc = iflib_get_softc(ctx); 1212 1213 INIT_DEBUGOUT("em_if_detach: begin"); 1214 1215 e1000_phy_hw_reset(&sc->hw); 1216 1217 em_release_manageability(sc); 1218 em_release_hw_control(sc); 1219 em_free_pci_resources(ctx); 1220 free(sc->mta, M_DEVBUF); 1221 sc->mta = NULL; 1222 1223 return (0); 1224 } 1225 1226 /********************************************************************* 1227 * 1228 * Shutdown entry point 1229 * 1230 **********************************************************************/ 1231 1232 static int 1233 em_if_shutdown(if_ctx_t ctx) 1234 { 1235 return em_if_suspend(ctx); 1236 } 1237 1238 /* 1239 * Suspend/resume device methods. 1240 */ 1241 static int 1242 em_if_suspend(if_ctx_t ctx) 1243 { 1244 struct e1000_softc *sc = iflib_get_softc(ctx); 1245 1246 em_release_manageability(sc); 1247 em_release_hw_control(sc); 1248 em_enable_wakeup(ctx); 1249 return (0); 1250 } 1251 1252 static int 1253 em_if_resume(if_ctx_t ctx) 1254 { 1255 struct e1000_softc *sc = iflib_get_softc(ctx); 1256 1257 if (sc->hw.mac.type == e1000_pch2lan) 1258 e1000_resume_workarounds_pchlan(&sc->hw); 1259 em_if_init(ctx); 1260 em_init_manageability(sc); 1261 1262 return(0); 1263 } 1264 1265 static int 1266 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1267 { 1268 int max_frame_size; 1269 struct e1000_softc *sc = iflib_get_softc(ctx); 1270 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1271 1272 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1273 1274 switch (sc->hw.mac.type) { 1275 case e1000_82571: 1276 case e1000_82572: 1277 case e1000_ich9lan: 1278 case e1000_ich10lan: 1279 case e1000_pch2lan: 1280 case e1000_pch_lpt: 1281 case e1000_pch_spt: 1282 case e1000_pch_cnp: 1283 case e1000_pch_tgp: 1284 case e1000_pch_adp: 1285 case e1000_pch_mtp: 1286 case e1000_pch_ptp: 1287 case e1000_82574: 1288 case e1000_82583: 1289 case e1000_80003es2lan: 1290 /* 9K Jumbo Frame size */ 1291 max_frame_size = 9234; 1292 break; 1293 case e1000_pchlan: 1294 max_frame_size = 4096; 1295 break; 1296 case e1000_82542: 1297 case e1000_ich8lan: 1298 /* Adapters that do not support jumbo frames */ 1299 max_frame_size = ETHER_MAX_LEN; 1300 break; 1301 default: 1302 if (sc->hw.mac.type >= igb_mac_min) 1303 max_frame_size = 9234; 1304 else /* lem */ 1305 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1306 } 1307 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1308 return (EINVAL); 1309 } 1310 1311 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1312 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1313 return (0); 1314 } 1315 1316 /********************************************************************* 1317 * Init entry point 1318 * 1319 * This routine is used in two ways. It is used by the stack as 1320 * init entry point in network interface structure. It is also used 1321 * by the driver as a hw/sw initialization routine to get to a 1322 * consistent state. 1323 * 1324 **********************************************************************/ 1325 static void 1326 em_if_init(if_ctx_t ctx) 1327 { 1328 struct e1000_softc *sc = iflib_get_softc(ctx); 1329 if_softc_ctx_t scctx = sc->shared; 1330 if_t ifp = iflib_get_ifp(ctx); 1331 struct em_tx_queue *tx_que; 1332 int i; 1333 1334 INIT_DEBUGOUT("em_if_init: begin"); 1335 1336 /* Get the latest mac address, User can use a LAA */ 1337 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1338 ETHER_ADDR_LEN); 1339 1340 /* Put the address into the Receive Address Array */ 1341 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1342 1343 /* 1344 * With the 82571 adapter, RAR[0] may be overwritten 1345 * when the other port is reset, we make a duplicate 1346 * in RAR[14] for that eventuality, this assures 1347 * the interface continues to function. 1348 */ 1349 if (sc->hw.mac.type == e1000_82571) { 1350 e1000_set_laa_state_82571(&sc->hw, true); 1351 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1352 E1000_RAR_ENTRIES - 1); 1353 } 1354 1355 1356 /* Initialize the hardware */ 1357 em_reset(ctx); 1358 em_if_update_admin_status(ctx); 1359 1360 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1361 struct tx_ring *txr = &tx_que->txr; 1362 1363 txr->tx_rs_cidx = txr->tx_rs_pidx; 1364 1365 /* Initialize the last processed descriptor to be the end of 1366 * the ring, rather than the start, so that we avoid an 1367 * off-by-one error when calculating how many descriptors are 1368 * done in the credits_update function. 1369 */ 1370 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1371 } 1372 1373 /* Setup VLAN support, basic and offload if available */ 1374 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1375 1376 /* Clear bad data from Rx FIFOs */ 1377 if (sc->hw.mac.type >= igb_mac_min) 1378 e1000_rx_fifo_flush_base(&sc->hw); 1379 1380 /* Configure for OS presence */ 1381 em_init_manageability(sc); 1382 1383 /* Prepare transmit descriptors and buffers */ 1384 em_initialize_transmit_unit(ctx); 1385 1386 /* Setup Multicast table */ 1387 em_if_multi_set(ctx); 1388 1389 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1390 em_initialize_receive_unit(ctx); 1391 1392 /* Set up VLAN support and filter */ 1393 em_setup_vlan_hw_support(ctx); 1394 1395 /* Don't lose promiscuous settings */ 1396 em_if_set_promisc(ctx, if_getflags(ifp)); 1397 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1398 1399 /* MSI-X configuration for 82574 */ 1400 if (sc->hw.mac.type == e1000_82574) { 1401 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1402 1403 tmp |= E1000_CTRL_EXT_PBA_CLR; 1404 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1405 /* Set the IVAR - interrupt vector routing. */ 1406 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1407 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1408 igb_configure_queues(sc); 1409 1410 /* this clears any pending interrupts */ 1411 E1000_READ_REG(&sc->hw, E1000_ICR); 1412 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1413 1414 /* AMT based hardware can now take control from firmware */ 1415 if (sc->has_manage && sc->has_amt) 1416 em_get_hw_control(sc); 1417 1418 /* Set Energy Efficient Ethernet */ 1419 if (sc->hw.mac.type >= igb_mac_min && 1420 sc->hw.phy.media_type == e1000_media_type_copper) { 1421 if (sc->hw.mac.type == e1000_i354) 1422 e1000_set_eee_i354(&sc->hw, true, true); 1423 else 1424 e1000_set_eee_i350(&sc->hw, true, true); 1425 } 1426 } 1427 1428 /********************************************************************* 1429 * 1430 * Fast Legacy/MSI Combined Interrupt Service routine 1431 * 1432 *********************************************************************/ 1433 int 1434 em_intr(void *arg) 1435 { 1436 struct e1000_softc *sc = arg; 1437 if_ctx_t ctx = sc->ctx; 1438 u32 reg_icr; 1439 1440 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1441 1442 /* Hot eject? */ 1443 if (reg_icr == 0xffffffff) 1444 return FILTER_STRAY; 1445 1446 /* Definitely not our interrupt. */ 1447 if (reg_icr == 0x0) 1448 return FILTER_STRAY; 1449 1450 /* 1451 * Starting with the 82571 chip, bit 31 should be used to 1452 * determine whether the interrupt belongs to us. 1453 */ 1454 if (sc->hw.mac.type >= e1000_82571 && 1455 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1456 return FILTER_STRAY; 1457 1458 /* 1459 * Only MSI-X interrupts have one-shot behavior by taking advantage 1460 * of the EIAC register. Thus, explicitly disable interrupts. This 1461 * also works around the MSI message reordering errata on certain 1462 * systems. 1463 */ 1464 IFDI_INTR_DISABLE(ctx); 1465 1466 /* Link status change */ 1467 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1468 em_handle_link(ctx); 1469 1470 if (reg_icr & E1000_ICR_RXO) 1471 sc->rx_overruns++; 1472 1473 return (FILTER_SCHEDULE_THREAD); 1474 } 1475 1476 static int 1477 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1478 { 1479 struct e1000_softc *sc = iflib_get_softc(ctx); 1480 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1481 1482 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1483 return (0); 1484 } 1485 1486 static int 1487 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1488 { 1489 struct e1000_softc *sc = iflib_get_softc(ctx); 1490 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1491 1492 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1493 return (0); 1494 } 1495 1496 static int 1497 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1498 { 1499 struct e1000_softc *sc = iflib_get_softc(ctx); 1500 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1501 1502 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1503 return (0); 1504 } 1505 1506 static int 1507 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1508 { 1509 struct e1000_softc *sc = iflib_get_softc(ctx); 1510 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1511 1512 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1513 return (0); 1514 } 1515 1516 /********************************************************************* 1517 * 1518 * MSI-X RX Interrupt Service routine 1519 * 1520 **********************************************************************/ 1521 static int 1522 em_msix_que(void *arg) 1523 { 1524 struct em_rx_queue *que = arg; 1525 1526 ++que->irqs; 1527 1528 return (FILTER_SCHEDULE_THREAD); 1529 } 1530 1531 /********************************************************************* 1532 * 1533 * MSI-X Link Fast Interrupt Service routine 1534 * 1535 **********************************************************************/ 1536 static int 1537 em_msix_link(void *arg) 1538 { 1539 struct e1000_softc *sc = arg; 1540 u32 reg_icr; 1541 1542 ++sc->link_irq; 1543 MPASS(sc->hw.back != NULL); 1544 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1545 1546 if (reg_icr & E1000_ICR_RXO) 1547 sc->rx_overruns++; 1548 1549 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1550 em_handle_link(sc->ctx); 1551 1552 /* Re-arm unconditionally */ 1553 if (sc->hw.mac.type >= igb_mac_min) { 1554 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1555 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1556 } else if (sc->hw.mac.type == e1000_82574) { 1557 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1558 E1000_IMS_OTHER); 1559 /* 1560 * Because we must read the ICR for this interrupt it may 1561 * clear other causes using autoclear, for this reason we 1562 * simply create a soft interrupt for all these vectors. 1563 */ 1564 if (reg_icr) 1565 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1566 } else 1567 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1568 1569 return (FILTER_HANDLED); 1570 } 1571 1572 static void 1573 em_handle_link(void *context) 1574 { 1575 if_ctx_t ctx = context; 1576 struct e1000_softc *sc = iflib_get_softc(ctx); 1577 1578 sc->hw.mac.get_link_status = 1; 1579 iflib_admin_intr_deferred(ctx); 1580 } 1581 1582 /********************************************************************* 1583 * 1584 * Media Ioctl callback 1585 * 1586 * This routine is called whenever the user queries the status of 1587 * the interface using ifconfig. 1588 * 1589 **********************************************************************/ 1590 static void 1591 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1592 { 1593 struct e1000_softc *sc = iflib_get_softc(ctx); 1594 u_char fiber_type = IFM_1000_SX; 1595 1596 INIT_DEBUGOUT("em_if_media_status: begin"); 1597 1598 iflib_admin_intr_deferred(ctx); 1599 1600 ifmr->ifm_status = IFM_AVALID; 1601 ifmr->ifm_active = IFM_ETHER; 1602 1603 if (!sc->link_active) { 1604 return; 1605 } 1606 1607 ifmr->ifm_status |= IFM_ACTIVE; 1608 1609 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1610 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1611 if (sc->hw.mac.type == e1000_82545) 1612 fiber_type = IFM_1000_LX; 1613 ifmr->ifm_active |= fiber_type | IFM_FDX; 1614 } else { 1615 switch (sc->link_speed) { 1616 case 10: 1617 ifmr->ifm_active |= IFM_10_T; 1618 break; 1619 case 100: 1620 ifmr->ifm_active |= IFM_100_TX; 1621 break; 1622 case 1000: 1623 ifmr->ifm_active |= IFM_1000_T; 1624 break; 1625 } 1626 if (sc->link_duplex == FULL_DUPLEX) 1627 ifmr->ifm_active |= IFM_FDX; 1628 else 1629 ifmr->ifm_active |= IFM_HDX; 1630 } 1631 } 1632 1633 /********************************************************************* 1634 * 1635 * Media Ioctl callback 1636 * 1637 * This routine is called when the user changes speed/duplex using 1638 * media/mediopt option with ifconfig. 1639 * 1640 **********************************************************************/ 1641 static int 1642 em_if_media_change(if_ctx_t ctx) 1643 { 1644 struct e1000_softc *sc = iflib_get_softc(ctx); 1645 struct ifmedia *ifm = iflib_get_media(ctx); 1646 1647 INIT_DEBUGOUT("em_if_media_change: begin"); 1648 1649 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1650 return (EINVAL); 1651 1652 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1653 case IFM_AUTO: 1654 sc->hw.mac.autoneg = DO_AUTO_NEG; 1655 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1656 break; 1657 case IFM_1000_LX: 1658 case IFM_1000_SX: 1659 case IFM_1000_T: 1660 sc->hw.mac.autoneg = DO_AUTO_NEG; 1661 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1662 break; 1663 case IFM_100_TX: 1664 sc->hw.mac.autoneg = false; 1665 sc->hw.phy.autoneg_advertised = 0; 1666 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1667 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1668 else 1669 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1670 break; 1671 case IFM_10_T: 1672 sc->hw.mac.autoneg = false; 1673 sc->hw.phy.autoneg_advertised = 0; 1674 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1675 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1676 else 1677 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1678 break; 1679 default: 1680 device_printf(sc->dev, "Unsupported media type\n"); 1681 } 1682 1683 em_if_init(ctx); 1684 1685 return (0); 1686 } 1687 1688 static int 1689 em_if_set_promisc(if_ctx_t ctx, int flags) 1690 { 1691 struct e1000_softc *sc = iflib_get_softc(ctx); 1692 if_t ifp = iflib_get_ifp(ctx); 1693 u32 reg_rctl; 1694 int mcnt = 0; 1695 1696 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1697 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1698 if (flags & IFF_ALLMULTI) 1699 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1700 else 1701 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1702 1703 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1704 reg_rctl &= (~E1000_RCTL_MPE); 1705 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1706 1707 if (flags & IFF_PROMISC) { 1708 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1709 em_if_vlan_filter_disable(sc); 1710 /* Turn this on if you want to see bad packets */ 1711 if (em_debug_sbp) 1712 reg_rctl |= E1000_RCTL_SBP; 1713 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1714 } else { 1715 if (flags & IFF_ALLMULTI) { 1716 reg_rctl |= E1000_RCTL_MPE; 1717 reg_rctl &= ~E1000_RCTL_UPE; 1718 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1719 } 1720 if (em_if_vlan_filter_used(ctx)) 1721 em_if_vlan_filter_enable(sc); 1722 } 1723 return (0); 1724 } 1725 1726 static u_int 1727 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1728 { 1729 u8 *mta = arg; 1730 1731 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1732 return (0); 1733 1734 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1735 1736 return (1); 1737 } 1738 1739 /********************************************************************* 1740 * Multicast Update 1741 * 1742 * This routine is called whenever multicast address list is updated. 1743 * 1744 **********************************************************************/ 1745 static void 1746 em_if_multi_set(if_ctx_t ctx) 1747 { 1748 struct e1000_softc *sc = iflib_get_softc(ctx); 1749 if_t ifp = iflib_get_ifp(ctx); 1750 u8 *mta; /* Multicast array memory */ 1751 u32 reg_rctl = 0; 1752 int mcnt = 0; 1753 1754 IOCTL_DEBUGOUT("em_set_multi: begin"); 1755 1756 mta = sc->mta; 1757 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1758 1759 if (sc->hw.mac.type == e1000_82542 && 1760 sc->hw.revision_id == E1000_REVISION_2) { 1761 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1762 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1763 e1000_pci_clear_mwi(&sc->hw); 1764 reg_rctl |= E1000_RCTL_RST; 1765 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1766 msec_delay(5); 1767 } 1768 1769 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1770 1771 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1772 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1773 1774 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1775 1776 if (if_getflags(ifp) & IFF_PROMISC) 1777 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1778 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1779 if_getflags(ifp) & IFF_ALLMULTI) { 1780 reg_rctl |= E1000_RCTL_MPE; 1781 reg_rctl &= ~E1000_RCTL_UPE; 1782 } else 1783 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1784 1785 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1786 1787 if (sc->hw.mac.type == e1000_82542 && 1788 sc->hw.revision_id == E1000_REVISION_2) { 1789 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1790 reg_rctl &= ~E1000_RCTL_RST; 1791 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1792 msec_delay(5); 1793 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1794 e1000_pci_set_mwi(&sc->hw); 1795 } 1796 } 1797 1798 /********************************************************************* 1799 * Timer routine 1800 * 1801 * This routine schedules em_if_update_admin_status() to check for 1802 * link status and to gather statistics as well as to perform some 1803 * controller-specific hardware patting. 1804 * 1805 **********************************************************************/ 1806 static void 1807 em_if_timer(if_ctx_t ctx, uint16_t qid) 1808 { 1809 1810 if (qid != 0) 1811 return; 1812 1813 iflib_admin_intr_deferred(ctx); 1814 } 1815 1816 static void 1817 em_if_update_admin_status(if_ctx_t ctx) 1818 { 1819 struct e1000_softc *sc = iflib_get_softc(ctx); 1820 struct e1000_hw *hw = &sc->hw; 1821 device_t dev = iflib_get_dev(ctx); 1822 u32 link_check, thstat, ctrl; 1823 1824 link_check = thstat = ctrl = 0; 1825 /* Get the cached link value or read phy for real */ 1826 switch (hw->phy.media_type) { 1827 case e1000_media_type_copper: 1828 if (hw->mac.get_link_status) { 1829 if (hw->mac.type == e1000_pch_spt) 1830 msec_delay(50); 1831 /* Do the work to read phy */ 1832 e1000_check_for_link(hw); 1833 link_check = !hw->mac.get_link_status; 1834 if (link_check) /* ESB2 fix */ 1835 e1000_cfg_on_link_up(hw); 1836 } else { 1837 link_check = true; 1838 } 1839 break; 1840 case e1000_media_type_fiber: 1841 e1000_check_for_link(hw); 1842 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1843 E1000_STATUS_LU); 1844 break; 1845 case e1000_media_type_internal_serdes: 1846 e1000_check_for_link(hw); 1847 link_check = hw->mac.serdes_has_link; 1848 break; 1849 /* VF device is type_unknown */ 1850 case e1000_media_type_unknown: 1851 e1000_check_for_link(hw); 1852 link_check = !hw->mac.get_link_status; 1853 /* FALLTHROUGH */ 1854 default: 1855 break; 1856 } 1857 1858 /* Check for thermal downshift or shutdown */ 1859 if (hw->mac.type == e1000_i350) { 1860 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1861 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1862 } 1863 1864 /* Now check for a transition */ 1865 if (link_check && (sc->link_active == 0)) { 1866 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1867 &sc->link_duplex); 1868 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1869 if ((sc->link_speed != SPEED_1000) && 1870 ((hw->mac.type == e1000_82571) || 1871 (hw->mac.type == e1000_82572))) { 1872 int tarc0; 1873 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1874 tarc0 &= ~TARC_SPEED_MODE_BIT; 1875 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1876 } 1877 if (bootverbose) 1878 device_printf(dev, "Link is up %d Mbps %s\n", 1879 sc->link_speed, 1880 ((sc->link_duplex == FULL_DUPLEX) ? 1881 "Full Duplex" : "Half Duplex")); 1882 sc->link_active = 1; 1883 sc->smartspeed = 0; 1884 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1885 E1000_CTRL_EXT_LINK_MODE_GMII && 1886 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1887 device_printf(dev, "Link: thermal downshift\n"); 1888 /* Delay Link Up for Phy update */ 1889 if (((hw->mac.type == e1000_i210) || 1890 (hw->mac.type == e1000_i211)) && 1891 (hw->phy.id == I210_I_PHY_ID)) 1892 msec_delay(I210_LINK_DELAY); 1893 /* Reset if the media type changed. */ 1894 if (hw->dev_spec._82575.media_changed && 1895 hw->mac.type >= igb_mac_min) { 1896 hw->dev_spec._82575.media_changed = false; 1897 sc->flags |= IGB_MEDIA_RESET; 1898 em_reset(ctx); 1899 } 1900 iflib_link_state_change(ctx, LINK_STATE_UP, 1901 IF_Mbps(sc->link_speed)); 1902 } else if (!link_check && (sc->link_active == 1)) { 1903 sc->link_speed = 0; 1904 sc->link_duplex = 0; 1905 sc->link_active = 0; 1906 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1907 } 1908 em_update_stats_counters(sc); 1909 1910 /* Reset LAA into RAR[0] on 82571 */ 1911 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1912 e1000_rar_set(hw, hw->mac.addr, 0); 1913 1914 if (hw->mac.type < em_mac_min) 1915 lem_smartspeed(sc); 1916 } 1917 1918 static void 1919 em_if_watchdog_reset(if_ctx_t ctx) 1920 { 1921 struct e1000_softc *sc = iflib_get_softc(ctx); 1922 1923 /* 1924 * Just count the event; iflib(4) will already trigger a 1925 * sufficient reset of the controller. 1926 */ 1927 sc->watchdog_events++; 1928 } 1929 1930 /********************************************************************* 1931 * 1932 * This routine disables all traffic on the adapter by issuing a 1933 * global reset on the MAC. 1934 * 1935 **********************************************************************/ 1936 static void 1937 em_if_stop(if_ctx_t ctx) 1938 { 1939 struct e1000_softc *sc = iflib_get_softc(ctx); 1940 1941 INIT_DEBUGOUT("em_if_stop: begin"); 1942 1943 /* I219 needs special flushing to avoid hangs */ 1944 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 1945 em_flush_desc_rings(sc); 1946 1947 e1000_reset_hw(&sc->hw); 1948 if (sc->hw.mac.type >= e1000_82544) 1949 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1950 1951 e1000_led_off(&sc->hw); 1952 e1000_cleanup_led(&sc->hw); 1953 } 1954 1955 /********************************************************************* 1956 * 1957 * Determine hardware revision. 1958 * 1959 **********************************************************************/ 1960 static void 1961 em_identify_hardware(if_ctx_t ctx) 1962 { 1963 device_t dev = iflib_get_dev(ctx); 1964 struct e1000_softc *sc = iflib_get_softc(ctx); 1965 1966 /* Make sure our PCI config space has the necessary stuff set */ 1967 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1968 1969 /* Save off the information about this board */ 1970 sc->hw.vendor_id = pci_get_vendor(dev); 1971 sc->hw.device_id = pci_get_device(dev); 1972 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1973 sc->hw.subsystem_vendor_id = 1974 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1975 sc->hw.subsystem_device_id = 1976 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1977 1978 /* Do Shared Code Init and Setup */ 1979 if (e1000_set_mac_type(&sc->hw)) { 1980 device_printf(dev, "Setup init failure\n"); 1981 return; 1982 } 1983 1984 /* Are we a VF device? */ 1985 if ((sc->hw.mac.type == e1000_vfadapt) || 1986 (sc->hw.mac.type == e1000_vfadapt_i350)) 1987 sc->vf_ifp = 1; 1988 else 1989 sc->vf_ifp = 0; 1990 } 1991 1992 static int 1993 em_allocate_pci_resources(if_ctx_t ctx) 1994 { 1995 struct e1000_softc *sc = iflib_get_softc(ctx); 1996 device_t dev = iflib_get_dev(ctx); 1997 int rid, val; 1998 1999 rid = PCIR_BAR(0); 2000 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2001 &rid, RF_ACTIVE); 2002 if (sc->memory == NULL) { 2003 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2004 return (ENXIO); 2005 } 2006 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2007 sc->osdep.mem_bus_space_handle = 2008 rman_get_bushandle(sc->memory); 2009 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2010 2011 /* Only older adapters use IO mapping */ 2012 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2013 /* Figure our where our IO BAR is ? */ 2014 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2015 val = pci_read_config(dev, rid, 4); 2016 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2017 break; 2018 } 2019 rid += 4; 2020 /* check for 64bit BAR */ 2021 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2022 rid += 4; 2023 } 2024 if (rid >= PCIR_CIS) { 2025 device_printf(dev, "Unable to locate IO BAR\n"); 2026 return (ENXIO); 2027 } 2028 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2029 &rid, RF_ACTIVE); 2030 if (sc->ioport == NULL) { 2031 device_printf(dev, "Unable to allocate bus resource: " 2032 "ioport\n"); 2033 return (ENXIO); 2034 } 2035 sc->hw.io_base = 0; 2036 sc->osdep.io_bus_space_tag = 2037 rman_get_bustag(sc->ioport); 2038 sc->osdep.io_bus_space_handle = 2039 rman_get_bushandle(sc->ioport); 2040 } 2041 2042 sc->hw.back = &sc->osdep; 2043 2044 return (0); 2045 } 2046 2047 /********************************************************************* 2048 * 2049 * Set up the MSI-X Interrupt handlers 2050 * 2051 **********************************************************************/ 2052 static int 2053 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2054 { 2055 struct e1000_softc *sc = iflib_get_softc(ctx); 2056 struct em_rx_queue *rx_que = sc->rx_queues; 2057 struct em_tx_queue *tx_que = sc->tx_queues; 2058 int error, rid, i, vector = 0, rx_vectors; 2059 char buf[16]; 2060 2061 /* First set up ring resources */ 2062 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2063 rid = vector + 1; 2064 snprintf(buf, sizeof(buf), "rxq%d", i); 2065 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2066 if (error) { 2067 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2068 sc->rx_num_queues = i + 1; 2069 goto fail; 2070 } 2071 2072 rx_que->msix = vector; 2073 2074 /* 2075 * Set the bit to enable interrupt 2076 * in E1000_IMS -- bits 20 and 21 2077 * are for RX0 and RX1, note this has 2078 * NOTHING to do with the MSI-X vector 2079 */ 2080 if (sc->hw.mac.type == e1000_82574) { 2081 rx_que->eims = 1 << (20 + i); 2082 sc->ims |= rx_que->eims; 2083 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2084 } else if (sc->hw.mac.type == e1000_82575) 2085 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2086 else 2087 rx_que->eims = 1 << vector; 2088 } 2089 rx_vectors = vector; 2090 2091 vector = 0; 2092 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2093 snprintf(buf, sizeof(buf), "txq%d", i); 2094 tx_que = &sc->tx_queues[i]; 2095 iflib_softirq_alloc_generic(ctx, 2096 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2097 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2098 2099 tx_que->msix = (vector % sc->rx_num_queues); 2100 2101 /* 2102 * Set the bit to enable interrupt 2103 * in E1000_IMS -- bits 22 and 23 2104 * are for TX0 and TX1, note this has 2105 * NOTHING to do with the MSI-X vector 2106 */ 2107 if (sc->hw.mac.type == e1000_82574) { 2108 tx_que->eims = 1 << (22 + i); 2109 sc->ims |= tx_que->eims; 2110 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2111 } else if (sc->hw.mac.type == e1000_82575) { 2112 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2113 } else { 2114 tx_que->eims = 1 << i; 2115 } 2116 } 2117 2118 /* Link interrupt */ 2119 rid = rx_vectors + 1; 2120 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2121 2122 if (error) { 2123 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2124 goto fail; 2125 } 2126 sc->linkvec = rx_vectors; 2127 if (sc->hw.mac.type < igb_mac_min) { 2128 sc->ivars |= (8 | rx_vectors) << 16; 2129 sc->ivars |= 0x80000000; 2130 /* Enable the "Other" interrupt type for link status change */ 2131 sc->ims |= E1000_IMS_OTHER; 2132 } 2133 2134 return (0); 2135 fail: 2136 iflib_irq_free(ctx, &sc->irq); 2137 rx_que = sc->rx_queues; 2138 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2139 iflib_irq_free(ctx, &rx_que->que_irq); 2140 return (error); 2141 } 2142 2143 static void 2144 igb_configure_queues(struct e1000_softc *sc) 2145 { 2146 struct e1000_hw *hw = &sc->hw; 2147 struct em_rx_queue *rx_que; 2148 struct em_tx_queue *tx_que; 2149 u32 tmp, ivar = 0, newitr = 0; 2150 2151 /* First turn on RSS capability */ 2152 if (hw->mac.type != e1000_82575) 2153 E1000_WRITE_REG(hw, E1000_GPIE, 2154 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2155 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2156 2157 /* Turn on MSI-X */ 2158 switch (hw->mac.type) { 2159 case e1000_82580: 2160 case e1000_i350: 2161 case e1000_i354: 2162 case e1000_i210: 2163 case e1000_i211: 2164 case e1000_vfadapt: 2165 case e1000_vfadapt_i350: 2166 /* RX entries */ 2167 for (int i = 0; i < sc->rx_num_queues; i++) { 2168 u32 index = i >> 1; 2169 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2170 rx_que = &sc->rx_queues[i]; 2171 if (i & 1) { 2172 ivar &= 0xFF00FFFF; 2173 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2174 } else { 2175 ivar &= 0xFFFFFF00; 2176 ivar |= rx_que->msix | E1000_IVAR_VALID; 2177 } 2178 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2179 } 2180 /* TX entries */ 2181 for (int i = 0; i < sc->tx_num_queues; i++) { 2182 u32 index = i >> 1; 2183 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2184 tx_que = &sc->tx_queues[i]; 2185 if (i & 1) { 2186 ivar &= 0x00FFFFFF; 2187 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2188 } else { 2189 ivar &= 0xFFFF00FF; 2190 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2191 } 2192 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2193 sc->que_mask |= tx_que->eims; 2194 } 2195 2196 /* And for the link interrupt */ 2197 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2198 sc->link_mask = 1 << sc->linkvec; 2199 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2200 break; 2201 case e1000_82576: 2202 /* RX entries */ 2203 for (int i = 0; i < sc->rx_num_queues; i++) { 2204 u32 index = i & 0x7; /* Each IVAR has two entries */ 2205 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2206 rx_que = &sc->rx_queues[i]; 2207 if (i < 8) { 2208 ivar &= 0xFFFFFF00; 2209 ivar |= rx_que->msix | E1000_IVAR_VALID; 2210 } else { 2211 ivar &= 0xFF00FFFF; 2212 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2213 } 2214 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2215 sc->que_mask |= rx_que->eims; 2216 } 2217 /* TX entries */ 2218 for (int i = 0; i < sc->tx_num_queues; i++) { 2219 u32 index = i & 0x7; /* Each IVAR has two entries */ 2220 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2221 tx_que = &sc->tx_queues[i]; 2222 if (i < 8) { 2223 ivar &= 0xFFFF00FF; 2224 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2225 } else { 2226 ivar &= 0x00FFFFFF; 2227 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2228 } 2229 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2230 sc->que_mask |= tx_que->eims; 2231 } 2232 2233 /* And for the link interrupt */ 2234 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2235 sc->link_mask = 1 << sc->linkvec; 2236 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2237 break; 2238 2239 case e1000_82575: 2240 /* enable MSI-X support*/ 2241 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2242 tmp |= E1000_CTRL_EXT_PBA_CLR; 2243 /* Auto-Mask interrupts upon ICR read. */ 2244 tmp |= E1000_CTRL_EXT_EIAME; 2245 tmp |= E1000_CTRL_EXT_IRCA; 2246 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2247 2248 /* Queues */ 2249 for (int i = 0; i < sc->rx_num_queues; i++) { 2250 rx_que = &sc->rx_queues[i]; 2251 tmp = E1000_EICR_RX_QUEUE0 << i; 2252 tmp |= E1000_EICR_TX_QUEUE0 << i; 2253 rx_que->eims = tmp; 2254 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2255 i, rx_que->eims); 2256 sc->que_mask |= rx_que->eims; 2257 } 2258 2259 /* Link */ 2260 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2261 E1000_EIMS_OTHER); 2262 sc->link_mask |= E1000_EIMS_OTHER; 2263 default: 2264 break; 2265 } 2266 2267 /* Set the starting interrupt rate */ 2268 if (em_max_interrupt_rate > 0) 2269 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2270 2271 if (hw->mac.type == e1000_82575) 2272 newitr |= newitr << 16; 2273 else 2274 newitr |= E1000_EITR_CNT_IGNR; 2275 2276 for (int i = 0; i < sc->rx_num_queues; i++) { 2277 rx_que = &sc->rx_queues[i]; 2278 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2279 } 2280 2281 return; 2282 } 2283 2284 static void 2285 em_free_pci_resources(if_ctx_t ctx) 2286 { 2287 struct e1000_softc *sc = iflib_get_softc(ctx); 2288 struct em_rx_queue *que = sc->rx_queues; 2289 device_t dev = iflib_get_dev(ctx); 2290 2291 /* Release all MSI-X queue resources */ 2292 if (sc->intr_type == IFLIB_INTR_MSIX) 2293 iflib_irq_free(ctx, &sc->irq); 2294 2295 if (que != NULL) { 2296 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2297 iflib_irq_free(ctx, &que->que_irq); 2298 } 2299 } 2300 2301 if (sc->memory != NULL) { 2302 bus_release_resource(dev, SYS_RES_MEMORY, 2303 rman_get_rid(sc->memory), sc->memory); 2304 sc->memory = NULL; 2305 } 2306 2307 if (sc->flash != NULL) { 2308 bus_release_resource(dev, SYS_RES_MEMORY, 2309 rman_get_rid(sc->flash), sc->flash); 2310 sc->flash = NULL; 2311 } 2312 2313 if (sc->ioport != NULL) { 2314 bus_release_resource(dev, SYS_RES_IOPORT, 2315 rman_get_rid(sc->ioport), sc->ioport); 2316 sc->ioport = NULL; 2317 } 2318 } 2319 2320 /* Set up MSI or MSI-X */ 2321 static int 2322 em_setup_msix(if_ctx_t ctx) 2323 { 2324 struct e1000_softc *sc = iflib_get_softc(ctx); 2325 2326 if (sc->hw.mac.type == e1000_82574) { 2327 em_enable_vectors_82574(ctx); 2328 } 2329 return (0); 2330 } 2331 2332 /********************************************************************* 2333 * 2334 * Workaround for SmartSpeed on 82541 and 82547 controllers 2335 * 2336 **********************************************************************/ 2337 static void 2338 lem_smartspeed(struct e1000_softc *sc) 2339 { 2340 u16 phy_tmp; 2341 2342 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2343 sc->hw.mac.autoneg == 0 || 2344 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2345 return; 2346 2347 if (sc->smartspeed == 0) { 2348 /* If Master/Slave config fault is asserted twice, 2349 * we assume back-to-back */ 2350 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2351 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2352 return; 2353 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2354 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2355 e1000_read_phy_reg(&sc->hw, 2356 PHY_1000T_CTRL, &phy_tmp); 2357 if(phy_tmp & CR_1000T_MS_ENABLE) { 2358 phy_tmp &= ~CR_1000T_MS_ENABLE; 2359 e1000_write_phy_reg(&sc->hw, 2360 PHY_1000T_CTRL, phy_tmp); 2361 sc->smartspeed++; 2362 if(sc->hw.mac.autoneg && 2363 !e1000_copper_link_autoneg(&sc->hw) && 2364 !e1000_read_phy_reg(&sc->hw, 2365 PHY_CONTROL, &phy_tmp)) { 2366 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2367 MII_CR_RESTART_AUTO_NEG); 2368 e1000_write_phy_reg(&sc->hw, 2369 PHY_CONTROL, phy_tmp); 2370 } 2371 } 2372 } 2373 return; 2374 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2375 /* If still no link, perhaps using 2/3 pair cable */ 2376 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2377 phy_tmp |= CR_1000T_MS_ENABLE; 2378 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2379 if(sc->hw.mac.autoneg && 2380 !e1000_copper_link_autoneg(&sc->hw) && 2381 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2382 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2383 MII_CR_RESTART_AUTO_NEG); 2384 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2385 } 2386 } 2387 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2388 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2389 sc->smartspeed = 0; 2390 } 2391 2392 /********************************************************************* 2393 * 2394 * Initialize the DMA Coalescing feature 2395 * 2396 **********************************************************************/ 2397 static void 2398 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2399 { 2400 device_t dev = sc->dev; 2401 struct e1000_hw *hw = &sc->hw; 2402 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2403 u16 hwm; 2404 u16 max_frame_size; 2405 2406 if (hw->mac.type == e1000_i211) 2407 return; 2408 2409 max_frame_size = sc->shared->isc_max_frame_size; 2410 if (hw->mac.type > e1000_82580) { 2411 2412 if (sc->dmac == 0) { /* Disabling it */ 2413 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2414 return; 2415 } else 2416 device_printf(dev, "DMA Coalescing enabled\n"); 2417 2418 /* Set starting threshold */ 2419 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2420 2421 hwm = 64 * pba - max_frame_size / 16; 2422 if (hwm < 64 * (pba - 6)) 2423 hwm = 64 * (pba - 6); 2424 reg = E1000_READ_REG(hw, E1000_FCRTC); 2425 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2426 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2427 & E1000_FCRTC_RTH_COAL_MASK); 2428 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2429 2430 2431 dmac = pba - max_frame_size / 512; 2432 if (dmac < pba - 10) 2433 dmac = pba - 10; 2434 reg = E1000_READ_REG(hw, E1000_DMACR); 2435 reg &= ~E1000_DMACR_DMACTHR_MASK; 2436 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2437 & E1000_DMACR_DMACTHR_MASK); 2438 2439 /* transition to L0x or L1 if available..*/ 2440 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2441 2442 /* Check if status is 2.5Gb backplane connection 2443 * before configuration of watchdog timer, which is 2444 * in msec values in 12.8usec intervals 2445 * watchdog timer= msec values in 32usec intervals 2446 * for non 2.5Gb connection 2447 */ 2448 if (hw->mac.type == e1000_i354) { 2449 int status = E1000_READ_REG(hw, E1000_STATUS); 2450 if ((status & E1000_STATUS_2P5_SKU) && 2451 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2452 reg |= ((sc->dmac * 5) >> 6); 2453 else 2454 reg |= (sc->dmac >> 5); 2455 } else { 2456 reg |= (sc->dmac >> 5); 2457 } 2458 2459 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2460 2461 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2462 2463 /* Set the interval before transition */ 2464 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2465 if (hw->mac.type == e1000_i350) 2466 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2467 /* 2468 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2469 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2470 */ 2471 if (hw->mac.type == e1000_i354) { 2472 int status = E1000_READ_REG(hw, E1000_STATUS); 2473 if ((status & E1000_STATUS_2P5_SKU) && 2474 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2475 reg |= 0xA; 2476 else 2477 reg |= 0x4; 2478 } else { 2479 reg |= 0x4; 2480 } 2481 2482 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2483 2484 /* free space in tx packet buffer to wake from DMA coal */ 2485 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2486 (2 * max_frame_size)) >> 6); 2487 2488 /* make low power state decision controlled by DMA coal */ 2489 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2490 reg &= ~E1000_PCIEMISC_LX_DECISION; 2491 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2492 2493 } else if (hw->mac.type == e1000_82580) { 2494 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2495 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2496 reg & ~E1000_PCIEMISC_LX_DECISION); 2497 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2498 } 2499 } 2500 /********************************************************************* 2501 * The 3 following flush routines are used as a workaround in the 2502 * I219 client parts and only for them. 2503 * 2504 * em_flush_tx_ring - remove all descriptors from the tx_ring 2505 * 2506 * We want to clear all pending descriptors from the TX ring. 2507 * zeroing happens when the HW reads the regs. We assign the ring itself as 2508 * the data of the next descriptor. We don't care about the data we are about 2509 * to reset the HW. 2510 **********************************************************************/ 2511 static void 2512 em_flush_tx_ring(struct e1000_softc *sc) 2513 { 2514 struct e1000_hw *hw = &sc->hw; 2515 struct tx_ring *txr = &sc->tx_queues->txr; 2516 struct e1000_tx_desc *txd; 2517 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2518 u16 size = 512; 2519 2520 tctl = E1000_READ_REG(hw, E1000_TCTL); 2521 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2522 2523 txd = &txr->tx_base[txr->tx_cidx_processed]; 2524 2525 /* Just use the ring as a dummy buffer addr */ 2526 txd->buffer_addr = txr->tx_paddr; 2527 txd->lower.data = htole32(txd_lower | size); 2528 txd->upper.data = 0; 2529 2530 /* flush descriptors to memory before notifying the HW */ 2531 wmb(); 2532 2533 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2534 mb(); 2535 usec_delay(250); 2536 } 2537 2538 /********************************************************************* 2539 * em_flush_rx_ring - remove all descriptors from the rx_ring 2540 * 2541 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2542 **********************************************************************/ 2543 static void 2544 em_flush_rx_ring(struct e1000_softc *sc) 2545 { 2546 struct e1000_hw *hw = &sc->hw; 2547 u32 rctl, rxdctl; 2548 2549 rctl = E1000_READ_REG(hw, E1000_RCTL); 2550 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2551 E1000_WRITE_FLUSH(hw); 2552 usec_delay(150); 2553 2554 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2555 /* zero the lower 14 bits (prefetch and host thresholds) */ 2556 rxdctl &= 0xffffc000; 2557 /* 2558 * update thresholds: prefetch threshold to 31, host threshold to 1 2559 * and make sure the granularity is "descriptors" and not "cache lines" 2560 */ 2561 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2562 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2563 2564 /* momentarily enable the RX ring for the changes to take effect */ 2565 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2566 E1000_WRITE_FLUSH(hw); 2567 usec_delay(150); 2568 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2569 } 2570 2571 /********************************************************************* 2572 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2573 * 2574 * In I219, the descriptor rings must be emptied before resetting the HW 2575 * or before changing the device state to D3 during runtime (runtime PM). 2576 * 2577 * Failure to do this will cause the HW to enter a unit hang state which can 2578 * only be released by PCI reset on the device 2579 * 2580 **********************************************************************/ 2581 static void 2582 em_flush_desc_rings(struct e1000_softc *sc) 2583 { 2584 struct e1000_hw *hw = &sc->hw; 2585 device_t dev = sc->dev; 2586 u16 hang_state; 2587 u32 fext_nvm11, tdlen; 2588 2589 /* First, disable MULR fix in FEXTNVM11 */ 2590 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2591 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2592 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2593 2594 /* do nothing if we're not in faulty state, or if the queue is empty */ 2595 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2596 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2597 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2598 return; 2599 em_flush_tx_ring(sc); 2600 2601 /* recheck, maybe the fault is caused by the rx ring */ 2602 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2603 if (hang_state & FLUSH_DESC_REQUIRED) 2604 em_flush_rx_ring(sc); 2605 } 2606 2607 2608 /********************************************************************* 2609 * 2610 * Initialize the hardware to a configuration as specified by the 2611 * sc structure. 2612 * 2613 **********************************************************************/ 2614 static void 2615 em_reset(if_ctx_t ctx) 2616 { 2617 device_t dev = iflib_get_dev(ctx); 2618 struct e1000_softc *sc = iflib_get_softc(ctx); 2619 if_t ifp = iflib_get_ifp(ctx); 2620 struct e1000_hw *hw = &sc->hw; 2621 u32 rx_buffer_size; 2622 u32 pba; 2623 2624 INIT_DEBUGOUT("em_reset: begin"); 2625 /* Let the firmware know the OS is in control */ 2626 em_get_hw_control(sc); 2627 2628 /* Set up smart power down as default off on newer adapters. */ 2629 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2630 hw->mac.type == e1000_82572)) { 2631 u16 phy_tmp = 0; 2632 2633 /* Speed up time to link by disabling smart power down. */ 2634 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2635 phy_tmp &= ~IGP02E1000_PM_SPD; 2636 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2637 } 2638 2639 /* 2640 * Packet Buffer Allocation (PBA) 2641 * Writing PBA sets the receive portion of the buffer 2642 * the remainder is used for the transmit buffer. 2643 */ 2644 switch (hw->mac.type) { 2645 /* 82547: Total Packet Buffer is 40K */ 2646 case e1000_82547: 2647 case e1000_82547_rev_2: 2648 if (hw->mac.max_frame_size > 8192) 2649 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2650 else 2651 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2652 break; 2653 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2654 case e1000_82571: 2655 case e1000_82572: 2656 case e1000_80003es2lan: 2657 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2658 break; 2659 /* 82573: Total Packet Buffer is 32K */ 2660 case e1000_82573: 2661 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2662 break; 2663 case e1000_82574: 2664 case e1000_82583: 2665 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2666 break; 2667 case e1000_ich8lan: 2668 pba = E1000_PBA_8K; 2669 break; 2670 case e1000_ich9lan: 2671 case e1000_ich10lan: 2672 /* Boost Receive side for jumbo frames */ 2673 if (hw->mac.max_frame_size > 4096) 2674 pba = E1000_PBA_14K; 2675 else 2676 pba = E1000_PBA_10K; 2677 break; 2678 case e1000_pchlan: 2679 case e1000_pch2lan: 2680 case e1000_pch_lpt: 2681 case e1000_pch_spt: 2682 case e1000_pch_cnp: 2683 case e1000_pch_tgp: 2684 case e1000_pch_adp: 2685 case e1000_pch_mtp: 2686 case e1000_pch_ptp: 2687 pba = E1000_PBA_26K; 2688 break; 2689 case e1000_82575: 2690 pba = E1000_PBA_32K; 2691 break; 2692 case e1000_82576: 2693 case e1000_vfadapt: 2694 pba = E1000_READ_REG(hw, E1000_RXPBS); 2695 pba &= E1000_RXPBS_SIZE_MASK_82576; 2696 break; 2697 case e1000_82580: 2698 case e1000_i350: 2699 case e1000_i354: 2700 case e1000_vfadapt_i350: 2701 pba = E1000_READ_REG(hw, E1000_RXPBS); 2702 pba = e1000_rxpbs_adjust_82580(pba); 2703 break; 2704 case e1000_i210: 2705 case e1000_i211: 2706 pba = E1000_PBA_34K; 2707 break; 2708 default: 2709 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2710 if (hw->mac.max_frame_size > 8192) 2711 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2712 else 2713 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2714 } 2715 2716 /* Special needs in case of Jumbo frames */ 2717 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2718 u32 tx_space, min_tx, min_rx; 2719 pba = E1000_READ_REG(hw, E1000_PBA); 2720 tx_space = pba >> 16; 2721 pba &= 0xffff; 2722 min_tx = (hw->mac.max_frame_size + 2723 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2724 min_tx = roundup2(min_tx, 1024); 2725 min_tx >>= 10; 2726 min_rx = hw->mac.max_frame_size; 2727 min_rx = roundup2(min_rx, 1024); 2728 min_rx >>= 10; 2729 if (tx_space < min_tx && 2730 ((min_tx - tx_space) < pba)) { 2731 pba = pba - (min_tx - tx_space); 2732 /* 2733 * if short on rx space, rx wins 2734 * and must trump tx adjustment 2735 */ 2736 if (pba < min_rx) 2737 pba = min_rx; 2738 } 2739 E1000_WRITE_REG(hw, E1000_PBA, pba); 2740 } 2741 2742 if (hw->mac.type < igb_mac_min) 2743 E1000_WRITE_REG(hw, E1000_PBA, pba); 2744 2745 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2746 2747 /* 2748 * These parameters control the automatic generation (Tx) and 2749 * response (Rx) to Ethernet PAUSE frames. 2750 * - High water mark should allow for at least two frames to be 2751 * received after sending an XOFF. 2752 * - Low water mark works best when it is very near the high water mark. 2753 * This allows the receiver to restart by sending XON when it has 2754 * drained a bit. Here we use an arbitrary value of 1500 which will 2755 * restart after one full frame is pulled from the buffer. There 2756 * could be several smaller frames in the buffer and if so they will 2757 * not trigger the XON until their total number reduces the buffer 2758 * by 1500. 2759 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2760 */ 2761 rx_buffer_size = (pba & 0xffff) << 10; 2762 hw->fc.high_water = rx_buffer_size - 2763 roundup2(hw->mac.max_frame_size, 1024); 2764 hw->fc.low_water = hw->fc.high_water - 1500; 2765 2766 if (sc->fc) /* locally set flow control value? */ 2767 hw->fc.requested_mode = sc->fc; 2768 else 2769 hw->fc.requested_mode = e1000_fc_full; 2770 2771 if (hw->mac.type == e1000_80003es2lan) 2772 hw->fc.pause_time = 0xFFFF; 2773 else 2774 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2775 2776 hw->fc.send_xon = true; 2777 2778 /* Device specific overrides/settings */ 2779 switch (hw->mac.type) { 2780 case e1000_pchlan: 2781 /* Workaround: no TX flow ctrl for PCH */ 2782 hw->fc.requested_mode = e1000_fc_rx_pause; 2783 hw->fc.pause_time = 0xFFFF; /* override */ 2784 if (if_getmtu(ifp) > ETHERMTU) { 2785 hw->fc.high_water = 0x3500; 2786 hw->fc.low_water = 0x1500; 2787 } else { 2788 hw->fc.high_water = 0x5000; 2789 hw->fc.low_water = 0x3000; 2790 } 2791 hw->fc.refresh_time = 0x1000; 2792 break; 2793 case e1000_pch2lan: 2794 case e1000_pch_lpt: 2795 case e1000_pch_spt: 2796 case e1000_pch_cnp: 2797 case e1000_pch_tgp: 2798 case e1000_pch_adp: 2799 case e1000_pch_mtp: 2800 case e1000_pch_ptp: 2801 hw->fc.high_water = 0x5C20; 2802 hw->fc.low_water = 0x5048; 2803 hw->fc.pause_time = 0x0650; 2804 hw->fc.refresh_time = 0x0400; 2805 /* Jumbos need adjusted PBA */ 2806 if (if_getmtu(ifp) > ETHERMTU) 2807 E1000_WRITE_REG(hw, E1000_PBA, 12); 2808 else 2809 E1000_WRITE_REG(hw, E1000_PBA, 26); 2810 break; 2811 case e1000_82575: 2812 case e1000_82576: 2813 /* 8-byte granularity */ 2814 hw->fc.low_water = hw->fc.high_water - 8; 2815 break; 2816 case e1000_82580: 2817 case e1000_i350: 2818 case e1000_i354: 2819 case e1000_i210: 2820 case e1000_i211: 2821 case e1000_vfadapt: 2822 case e1000_vfadapt_i350: 2823 /* 16-byte granularity */ 2824 hw->fc.low_water = hw->fc.high_water - 16; 2825 break; 2826 case e1000_ich9lan: 2827 case e1000_ich10lan: 2828 if (if_getmtu(ifp) > ETHERMTU) { 2829 hw->fc.high_water = 0x2800; 2830 hw->fc.low_water = hw->fc.high_water - 8; 2831 break; 2832 } 2833 /* FALLTHROUGH */ 2834 default: 2835 if (hw->mac.type == e1000_80003es2lan) 2836 hw->fc.pause_time = 0xFFFF; 2837 break; 2838 } 2839 2840 /* I219 needs some special flushing to avoid hangs */ 2841 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2842 em_flush_desc_rings(sc); 2843 2844 /* Issue a global reset */ 2845 e1000_reset_hw(hw); 2846 if (hw->mac.type >= igb_mac_min) { 2847 E1000_WRITE_REG(hw, E1000_WUC, 0); 2848 } else { 2849 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2850 em_disable_aspm(sc); 2851 } 2852 if (sc->flags & IGB_MEDIA_RESET) { 2853 e1000_setup_init_funcs(hw, true); 2854 e1000_get_bus_info(hw); 2855 sc->flags &= ~IGB_MEDIA_RESET; 2856 } 2857 /* and a re-init */ 2858 if (e1000_init_hw(hw) < 0) { 2859 device_printf(dev, "Hardware Initialization Failed\n"); 2860 return; 2861 } 2862 if (hw->mac.type >= igb_mac_min) 2863 igb_init_dmac(sc, pba); 2864 2865 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2866 e1000_get_phy_info(hw); 2867 e1000_check_for_link(hw); 2868 } 2869 2870 /* 2871 * Initialise the RSS mapping for NICs that support multiple transmit/ 2872 * receive rings. 2873 */ 2874 2875 #define RSSKEYLEN 10 2876 static void 2877 em_initialize_rss_mapping(struct e1000_softc *sc) 2878 { 2879 uint8_t rss_key[4 * RSSKEYLEN]; 2880 uint32_t reta = 0; 2881 struct e1000_hw *hw = &sc->hw; 2882 int i; 2883 2884 /* 2885 * Configure RSS key 2886 */ 2887 arc4rand(rss_key, sizeof(rss_key), 0); 2888 for (i = 0; i < RSSKEYLEN; ++i) { 2889 uint32_t rssrk = 0; 2890 2891 rssrk = EM_RSSRK_VAL(rss_key, i); 2892 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2893 } 2894 2895 /* 2896 * Configure RSS redirect table in following fashion: 2897 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2898 */ 2899 for (i = 0; i < sizeof(reta); ++i) { 2900 uint32_t q; 2901 2902 q = (i % sc->rx_num_queues) << 7; 2903 reta |= q << (8 * i); 2904 } 2905 2906 for (i = 0; i < 32; ++i) 2907 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2908 2909 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2910 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2911 E1000_MRQC_RSS_FIELD_IPV4 | 2912 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2913 E1000_MRQC_RSS_FIELD_IPV6_EX | 2914 E1000_MRQC_RSS_FIELD_IPV6); 2915 } 2916 2917 static void 2918 igb_initialize_rss_mapping(struct e1000_softc *sc) 2919 { 2920 struct e1000_hw *hw = &sc->hw; 2921 int i; 2922 int queue_id; 2923 u32 reta; 2924 u32 rss_key[10], mrqc, shift = 0; 2925 2926 /* XXX? */ 2927 if (hw->mac.type == e1000_82575) 2928 shift = 6; 2929 2930 /* 2931 * The redirection table controls which destination 2932 * queue each bucket redirects traffic to. 2933 * Each DWORD represents four queues, with the LSB 2934 * being the first queue in the DWORD. 2935 * 2936 * This just allocates buckets to queues using round-robin 2937 * allocation. 2938 * 2939 * NOTE: It Just Happens to line up with the default 2940 * RSS allocation method. 2941 */ 2942 2943 /* Warning FM follows */ 2944 reta = 0; 2945 for (i = 0; i < 128; i++) { 2946 #ifdef RSS 2947 queue_id = rss_get_indirection_to_bucket(i); 2948 /* 2949 * If we have more queues than buckets, we'll 2950 * end up mapping buckets to a subset of the 2951 * queues. 2952 * 2953 * If we have more buckets than queues, we'll 2954 * end up instead assigning multiple buckets 2955 * to queues. 2956 * 2957 * Both are suboptimal, but we need to handle 2958 * the case so we don't go out of bounds 2959 * indexing arrays and such. 2960 */ 2961 queue_id = queue_id % sc->rx_num_queues; 2962 #else 2963 queue_id = (i % sc->rx_num_queues); 2964 #endif 2965 /* Adjust if required */ 2966 queue_id = queue_id << shift; 2967 2968 /* 2969 * The low 8 bits are for hash value (n+0); 2970 * The next 8 bits are for hash value (n+1), etc. 2971 */ 2972 reta = reta >> 8; 2973 reta = reta | ( ((uint32_t) queue_id) << 24); 2974 if ((i & 3) == 3) { 2975 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2976 reta = 0; 2977 } 2978 } 2979 2980 /* Now fill in hash table */ 2981 2982 /* 2983 * MRQC: Multiple Receive Queues Command 2984 * Set queuing to RSS control, number depends on the device. 2985 */ 2986 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2987 2988 #ifdef RSS 2989 /* XXX ew typecasting */ 2990 rss_getkey((uint8_t *) &rss_key); 2991 #else 2992 arc4rand(&rss_key, sizeof(rss_key), 0); 2993 #endif 2994 for (i = 0; i < 10; i++) 2995 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2996 2997 /* 2998 * Configure the RSS fields to hash upon. 2999 */ 3000 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3001 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3002 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3003 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3004 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3005 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3006 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3007 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3008 3009 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3010 } 3011 3012 /********************************************************************* 3013 * 3014 * Setup networking device structure and register interface media. 3015 * 3016 **********************************************************************/ 3017 static int 3018 em_setup_interface(if_ctx_t ctx) 3019 { 3020 if_t ifp = iflib_get_ifp(ctx); 3021 struct e1000_softc *sc = iflib_get_softc(ctx); 3022 if_softc_ctx_t scctx = sc->shared; 3023 3024 INIT_DEBUGOUT("em_setup_interface: begin"); 3025 3026 /* Single Queue */ 3027 if (sc->tx_num_queues == 1) { 3028 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3029 if_setsendqready(ifp); 3030 } 3031 3032 /* 3033 * Specify the media types supported by this adapter and register 3034 * callbacks to update media and link information 3035 */ 3036 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3037 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3038 u_char fiber_type = IFM_1000_SX; /* default type */ 3039 3040 if (sc->hw.mac.type == e1000_82545) 3041 fiber_type = IFM_1000_LX; 3042 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3043 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3044 } else { 3045 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3046 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3047 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3048 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3049 if (sc->hw.phy.type != e1000_phy_ife) { 3050 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3051 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3052 } 3053 } 3054 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3055 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3056 return (0); 3057 } 3058 3059 static int 3060 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3061 { 3062 struct e1000_softc *sc = iflib_get_softc(ctx); 3063 if_softc_ctx_t scctx = sc->shared; 3064 int error = E1000_SUCCESS; 3065 struct em_tx_queue *que; 3066 int i, j; 3067 3068 MPASS(sc->tx_num_queues > 0); 3069 MPASS(sc->tx_num_queues == ntxqsets); 3070 3071 /* First allocate the top level queue structs */ 3072 if (!(sc->tx_queues = 3073 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3074 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3075 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3076 return(ENOMEM); 3077 } 3078 3079 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3080 /* Set up some basics */ 3081 3082 struct tx_ring *txr = &que->txr; 3083 txr->sc = que->sc = sc; 3084 que->me = txr->me = i; 3085 3086 /* Allocate report status array */ 3087 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3088 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3089 error = ENOMEM; 3090 goto fail; 3091 } 3092 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3093 txr->tx_rsq[j] = QIDX_INVALID; 3094 /* get the virtual and physical address of the hardware queues */ 3095 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3096 txr->tx_paddr = paddrs[i*ntxqs]; 3097 } 3098 3099 if (bootverbose) 3100 device_printf(iflib_get_dev(ctx), 3101 "allocated for %d tx_queues\n", sc->tx_num_queues); 3102 return (0); 3103 fail: 3104 em_if_queues_free(ctx); 3105 return (error); 3106 } 3107 3108 static int 3109 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3110 { 3111 struct e1000_softc *sc = iflib_get_softc(ctx); 3112 int error = E1000_SUCCESS; 3113 struct em_rx_queue *que; 3114 int i; 3115 3116 MPASS(sc->rx_num_queues > 0); 3117 MPASS(sc->rx_num_queues == nrxqsets); 3118 3119 /* First allocate the top level queue structs */ 3120 if (!(sc->rx_queues = 3121 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3122 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3123 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3124 error = ENOMEM; 3125 goto fail; 3126 } 3127 3128 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3129 /* Set up some basics */ 3130 struct rx_ring *rxr = &que->rxr; 3131 rxr->sc = que->sc = sc; 3132 rxr->que = que; 3133 que->me = rxr->me = i; 3134 3135 /* get the virtual and physical address of the hardware queues */ 3136 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3137 rxr->rx_paddr = paddrs[i*nrxqs]; 3138 } 3139 3140 if (bootverbose) 3141 device_printf(iflib_get_dev(ctx), 3142 "allocated for %d rx_queues\n", sc->rx_num_queues); 3143 3144 return (0); 3145 fail: 3146 em_if_queues_free(ctx); 3147 return (error); 3148 } 3149 3150 static void 3151 em_if_queues_free(if_ctx_t ctx) 3152 { 3153 struct e1000_softc *sc = iflib_get_softc(ctx); 3154 struct em_tx_queue *tx_que = sc->tx_queues; 3155 struct em_rx_queue *rx_que = sc->rx_queues; 3156 3157 if (tx_que != NULL) { 3158 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3159 struct tx_ring *txr = &tx_que->txr; 3160 if (txr->tx_rsq == NULL) 3161 break; 3162 3163 free(txr->tx_rsq, M_DEVBUF); 3164 txr->tx_rsq = NULL; 3165 } 3166 free(sc->tx_queues, M_DEVBUF); 3167 sc->tx_queues = NULL; 3168 } 3169 3170 if (rx_que != NULL) { 3171 free(sc->rx_queues, M_DEVBUF); 3172 sc->rx_queues = NULL; 3173 } 3174 } 3175 3176 /********************************************************************* 3177 * 3178 * Enable transmit unit. 3179 * 3180 **********************************************************************/ 3181 static void 3182 em_initialize_transmit_unit(if_ctx_t ctx) 3183 { 3184 struct e1000_softc *sc = iflib_get_softc(ctx); 3185 if_softc_ctx_t scctx = sc->shared; 3186 struct em_tx_queue *que; 3187 struct tx_ring *txr; 3188 struct e1000_hw *hw = &sc->hw; 3189 u32 tctl, txdctl = 0, tarc, tipg = 0; 3190 3191 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3192 3193 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3194 u64 bus_addr; 3195 caddr_t offp, endp; 3196 3197 que = &sc->tx_queues[i]; 3198 txr = &que->txr; 3199 bus_addr = txr->tx_paddr; 3200 3201 /* Clear checksum offload context. */ 3202 offp = (caddr_t)&txr->csum_flags; 3203 endp = (caddr_t)(txr + 1); 3204 bzero(offp, endp - offp); 3205 3206 /* Base and Len of TX Ring */ 3207 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3208 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3209 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3210 (u32)(bus_addr >> 32)); 3211 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3212 (u32)bus_addr); 3213 /* Init the HEAD/TAIL indices */ 3214 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3215 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3216 3217 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3218 E1000_READ_REG(hw, E1000_TDBAL(i)), 3219 E1000_READ_REG(hw, E1000_TDLEN(i))); 3220 3221 txdctl = 0; /* clear txdctl */ 3222 txdctl |= 0x1f; /* PTHRESH */ 3223 txdctl |= 1 << 8; /* HTHRESH */ 3224 txdctl |= 1 << 16;/* WTHRESH */ 3225 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3226 txdctl |= E1000_TXDCTL_GRAN; 3227 txdctl |= 1 << 25; /* LWTHRESH */ 3228 3229 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3230 } 3231 3232 /* Set the default values for the Tx Inter Packet Gap timer */ 3233 switch (hw->mac.type) { 3234 case e1000_80003es2lan: 3235 tipg = DEFAULT_82543_TIPG_IPGR1; 3236 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3237 E1000_TIPG_IPGR2_SHIFT; 3238 break; 3239 case e1000_82542: 3240 tipg = DEFAULT_82542_TIPG_IPGT; 3241 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3242 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3243 break; 3244 default: 3245 if (hw->phy.media_type == e1000_media_type_fiber || 3246 hw->phy.media_type == e1000_media_type_internal_serdes) 3247 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3248 else 3249 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3250 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3251 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3252 } 3253 3254 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3255 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3256 3257 if(hw->mac.type >= e1000_82540) 3258 E1000_WRITE_REG(hw, E1000_TADV, 3259 sc->tx_abs_int_delay.value); 3260 3261 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3262 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3263 tarc |= TARC_SPEED_MODE_BIT; 3264 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3265 } else if (hw->mac.type == e1000_80003es2lan) { 3266 /* errata: program both queues to unweighted RR */ 3267 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3268 tarc |= 1; 3269 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3270 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3271 tarc |= 1; 3272 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3273 } else if (hw->mac.type == e1000_82574) { 3274 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3275 tarc |= TARC_ERRATA_BIT; 3276 if ( sc->tx_num_queues > 1) { 3277 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3278 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3279 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3280 } else 3281 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3282 } 3283 3284 if (sc->tx_int_delay.value > 0) 3285 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3286 3287 /* Program the Transmit Control Register */ 3288 tctl = E1000_READ_REG(hw, E1000_TCTL); 3289 tctl &= ~E1000_TCTL_CT; 3290 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3291 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3292 3293 if (hw->mac.type >= e1000_82571) 3294 tctl |= E1000_TCTL_MULR; 3295 3296 /* This write will effectively turn on the transmit unit. */ 3297 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3298 3299 /* SPT and KBL errata workarounds */ 3300 if (hw->mac.type == e1000_pch_spt) { 3301 u32 reg; 3302 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3303 reg |= E1000_RCTL_RDMTS_HEX; 3304 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3305 /* i218-i219 Specification Update 1.5.4.5 */ 3306 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3307 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3308 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3309 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3310 } 3311 } 3312 3313 /********************************************************************* 3314 * 3315 * Enable receive unit. 3316 * 3317 **********************************************************************/ 3318 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3319 3320 static void 3321 em_initialize_receive_unit(if_ctx_t ctx) 3322 { 3323 struct e1000_softc *sc = iflib_get_softc(ctx); 3324 if_softc_ctx_t scctx = sc->shared; 3325 if_t ifp = iflib_get_ifp(ctx); 3326 struct e1000_hw *hw = &sc->hw; 3327 struct em_rx_queue *que; 3328 int i; 3329 uint32_t rctl, rxcsum; 3330 3331 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3332 3333 /* 3334 * Make sure receives are disabled while setting 3335 * up the descriptor ring 3336 */ 3337 rctl = E1000_READ_REG(hw, E1000_RCTL); 3338 /* Do not disable if ever enabled on this hardware */ 3339 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3340 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3341 3342 /* Setup the Receive Control Register */ 3343 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3344 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3345 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3346 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3347 3348 /* Do not store bad packets */ 3349 rctl &= ~E1000_RCTL_SBP; 3350 3351 /* Enable Long Packet receive */ 3352 if (if_getmtu(ifp) > ETHERMTU) 3353 rctl |= E1000_RCTL_LPE; 3354 else 3355 rctl &= ~E1000_RCTL_LPE; 3356 3357 /* Strip the CRC */ 3358 if (!em_disable_crc_stripping) 3359 rctl |= E1000_RCTL_SECRC; 3360 3361 if (hw->mac.type >= e1000_82540) { 3362 E1000_WRITE_REG(hw, E1000_RADV, 3363 sc->rx_abs_int_delay.value); 3364 3365 /* 3366 * Set the interrupt throttling rate. Value is calculated 3367 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3368 */ 3369 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3370 } 3371 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3372 3373 if (hw->mac.type >= em_mac_min) { 3374 uint32_t rfctl; 3375 /* Use extended rx descriptor formats */ 3376 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3377 rfctl |= E1000_RFCTL_EXTEN; 3378 3379 /* 3380 * When using MSI-X interrupts we need to throttle 3381 * using the EITR register (82574 only) 3382 */ 3383 if (hw->mac.type == e1000_82574) { 3384 for (int i = 0; i < 4; i++) 3385 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3386 DEFAULT_ITR); 3387 /* Disable accelerated acknowledge */ 3388 rfctl |= E1000_RFCTL_ACK_DIS; 3389 } 3390 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3391 } 3392 3393 /* Set up L3 and L4 csum Rx descriptor offloads */ 3394 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3395 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3396 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3397 if (hw->mac.type > e1000_82575) 3398 rxcsum |= E1000_RXCSUM_CRCOFL; 3399 else if (hw->mac.type < em_mac_min && 3400 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3401 rxcsum |= E1000_RXCSUM_IPV6OFL; 3402 } else { 3403 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3404 if (hw->mac.type > e1000_82575) 3405 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3406 else if (hw->mac.type < em_mac_min) 3407 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3408 } 3409 3410 if (sc->rx_num_queues > 1) { 3411 /* RSS hash needed in the Rx descriptor */ 3412 rxcsum |= E1000_RXCSUM_PCSD; 3413 3414 if (hw->mac.type >= igb_mac_min) 3415 igb_initialize_rss_mapping(sc); 3416 else 3417 em_initialize_rss_mapping(sc); 3418 } 3419 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3420 3421 /* 3422 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3423 * long latencies are observed, like Lenovo X60. This 3424 * change eliminates the problem, but since having positive 3425 * values in RDTR is a known source of problems on other 3426 * platforms another solution is being sought. 3427 */ 3428 if (hw->mac.type == e1000_82573) 3429 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3430 3431 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3432 struct rx_ring *rxr = &que->rxr; 3433 /* Setup the Base and Length of the Rx Descriptor Ring */ 3434 u64 bus_addr = rxr->rx_paddr; 3435 #if 0 3436 u32 rdt = sc->rx_num_queues -1; /* default */ 3437 #endif 3438 3439 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3440 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3441 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3442 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3443 /* Setup the Head and Tail Descriptor Pointers */ 3444 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3445 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3446 } 3447 3448 /* 3449 * Set PTHRESH for improved jumbo performance 3450 * According to 10.2.5.11 of Intel 82574 Datasheet, 3451 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3452 * Only write to RXDCTL(1) if there is a need for different 3453 * settings. 3454 */ 3455 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3456 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3457 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3458 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3459 } else if (hw->mac.type == e1000_82574) { 3460 for (int i = 0; i < sc->rx_num_queues; i++) { 3461 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3462 rxdctl |= 0x20; /* PTHRESH */ 3463 rxdctl |= 4 << 8; /* HTHRESH */ 3464 rxdctl |= 4 << 16;/* WTHRESH */ 3465 rxdctl |= 1 << 24; /* Switch to granularity */ 3466 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3467 } 3468 } else if (hw->mac.type >= igb_mac_min) { 3469 u32 psize, srrctl = 0; 3470 3471 if (if_getmtu(ifp) > ETHERMTU) { 3472 psize = scctx->isc_max_frame_size; 3473 /* are we on a vlan? */ 3474 if (if_vlantrunkinuse(ifp)) 3475 psize += VLAN_TAG_SIZE; 3476 3477 if (sc->vf_ifp) 3478 e1000_rlpml_set_vf(hw, psize); 3479 else 3480 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3481 } 3482 3483 /* Set maximum packet buffer len */ 3484 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3485 E1000_SRRCTL_BSIZEPKT_SHIFT; 3486 3487 /* 3488 * If TX flow control is disabled and there's >1 queue defined, 3489 * enable DROP. 3490 * 3491 * This drops frames rather than hanging the RX MAC for all queues. 3492 */ 3493 if ((sc->rx_num_queues > 1) && 3494 (sc->fc == e1000_fc_none || 3495 sc->fc == e1000_fc_rx_pause)) { 3496 srrctl |= E1000_SRRCTL_DROP_EN; 3497 } 3498 /* Setup the Base and Length of the Rx Descriptor Rings */ 3499 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3500 struct rx_ring *rxr = &que->rxr; 3501 u64 bus_addr = rxr->rx_paddr; 3502 u32 rxdctl; 3503 3504 #ifdef notyet 3505 /* Configure for header split? -- ignore for now */ 3506 rxr->hdr_split = igb_header_split; 3507 #else 3508 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3509 #endif 3510 3511 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3512 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3513 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3514 (uint32_t)(bus_addr >> 32)); 3515 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3516 (uint32_t)bus_addr); 3517 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3518 /* Enable this Queue */ 3519 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3520 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3521 rxdctl &= 0xFFF00000; 3522 rxdctl |= IGB_RX_PTHRESH; 3523 rxdctl |= IGB_RX_HTHRESH << 8; 3524 rxdctl |= IGB_RX_WTHRESH << 16; 3525 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3526 } 3527 } else if (hw->mac.type >= e1000_pch2lan) { 3528 if (if_getmtu(ifp) > ETHERMTU) 3529 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3530 else 3531 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3532 } 3533 3534 /* Make sure VLAN Filters are off */ 3535 rctl &= ~E1000_RCTL_VFE; 3536 3537 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3538 if (hw->mac.type < igb_mac_min) { 3539 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3540 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3541 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3542 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3543 else if (sc->rx_mbuf_sz > 8192) 3544 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3545 else { 3546 rctl |= E1000_RCTL_SZ_2048; 3547 rctl &= ~E1000_RCTL_BSEX; 3548 } 3549 } else 3550 rctl |= E1000_RCTL_SZ_2048; 3551 3552 /* 3553 * rctl bits 11:10 are as follows 3554 * lem: reserved 3555 * em: DTYPE 3556 * igb: reserved 3557 * and should be 00 on all of the above 3558 */ 3559 rctl &= ~0x00000C00; 3560 3561 /* Write out the settings */ 3562 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3563 3564 return; 3565 } 3566 3567 static void 3568 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3569 { 3570 struct e1000_softc *sc = iflib_get_softc(ctx); 3571 u32 index, bit; 3572 3573 index = (vtag >> 5) & 0x7F; 3574 bit = vtag & 0x1F; 3575 sc->shadow_vfta[index] |= (1 << bit); 3576 ++sc->num_vlans; 3577 em_if_vlan_filter_write(sc); 3578 } 3579 3580 static void 3581 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3582 { 3583 struct e1000_softc *sc = iflib_get_softc(ctx); 3584 u32 index, bit; 3585 3586 index = (vtag >> 5) & 0x7F; 3587 bit = vtag & 0x1F; 3588 sc->shadow_vfta[index] &= ~(1 << bit); 3589 --sc->num_vlans; 3590 em_if_vlan_filter_write(sc); 3591 } 3592 3593 static bool 3594 em_if_vlan_filter_capable(if_ctx_t ctx) 3595 { 3596 if_t ifp = iflib_get_ifp(ctx); 3597 3598 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3599 !em_disable_crc_stripping) 3600 return (true); 3601 3602 return (false); 3603 } 3604 3605 static bool 3606 em_if_vlan_filter_used(if_ctx_t ctx) 3607 { 3608 struct e1000_softc *sc = iflib_get_softc(ctx); 3609 3610 if (!em_if_vlan_filter_capable(ctx)) 3611 return (false); 3612 3613 for (int i = 0; i < EM_VFTA_SIZE; i++) 3614 if (sc->shadow_vfta[i] != 0) 3615 return (true); 3616 3617 return (false); 3618 } 3619 3620 static void 3621 em_if_vlan_filter_enable(struct e1000_softc *sc) 3622 { 3623 struct e1000_hw *hw = &sc->hw; 3624 u32 reg; 3625 3626 reg = E1000_READ_REG(hw, E1000_RCTL); 3627 reg &= ~E1000_RCTL_CFIEN; 3628 reg |= E1000_RCTL_VFE; 3629 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3630 } 3631 3632 static void 3633 em_if_vlan_filter_disable(struct e1000_softc *sc) 3634 { 3635 struct e1000_hw *hw = &sc->hw; 3636 u32 reg; 3637 3638 reg = E1000_READ_REG(hw, E1000_RCTL); 3639 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3640 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3641 } 3642 3643 static void 3644 em_if_vlan_filter_write(struct e1000_softc *sc) 3645 { 3646 struct e1000_hw *hw = &sc->hw; 3647 3648 if (sc->vf_ifp) 3649 return; 3650 3651 /* Disable interrupts for lem-class devices during the filter change */ 3652 if (hw->mac.type < em_mac_min) 3653 em_if_intr_disable(sc->ctx); 3654 3655 for (int i = 0; i < EM_VFTA_SIZE; i++) 3656 if (sc->shadow_vfta[i] != 0) { 3657 /* XXXKB: incomplete VF support, we return early above */ 3658 if (sc->vf_ifp) 3659 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3660 else 3661 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3662 } 3663 3664 /* Re-enable interrupts for lem-class devices */ 3665 if (hw->mac.type < em_mac_min) 3666 em_if_intr_enable(sc->ctx); 3667 } 3668 3669 static void 3670 em_setup_vlan_hw_support(if_ctx_t ctx) 3671 { 3672 struct e1000_softc *sc = iflib_get_softc(ctx); 3673 struct e1000_hw *hw = &sc->hw; 3674 if_t ifp = iflib_get_ifp(ctx); 3675 u32 reg; 3676 3677 /* XXXKB: Return early if we are a VF until VF decap and filter management 3678 * is ready and tested. 3679 */ 3680 if (sc->vf_ifp) 3681 return; 3682 3683 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3684 !em_disable_crc_stripping) { 3685 reg = E1000_READ_REG(hw, E1000_CTRL); 3686 reg |= E1000_CTRL_VME; 3687 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3688 } else { 3689 reg = E1000_READ_REG(hw, E1000_CTRL); 3690 reg &= ~E1000_CTRL_VME; 3691 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3692 } 3693 3694 /* If we aren't doing HW filtering, we're done */ 3695 if (!em_if_vlan_filter_capable(ctx)) { 3696 em_if_vlan_filter_disable(sc); 3697 return; 3698 } 3699 3700 /* 3701 * A soft reset zero's out the VFTA, so 3702 * we need to repopulate it now. 3703 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3704 * traffic through. This will write the entire table. 3705 */ 3706 em_if_vlan_register(ctx, 0); 3707 3708 /* Enable the Filter Table */ 3709 em_if_vlan_filter_enable(sc); 3710 } 3711 3712 static void 3713 em_if_intr_enable(if_ctx_t ctx) 3714 { 3715 struct e1000_softc *sc = iflib_get_softc(ctx); 3716 struct e1000_hw *hw = &sc->hw; 3717 u32 ims_mask = IMS_ENABLE_MASK; 3718 3719 if (sc->intr_type == IFLIB_INTR_MSIX) { 3720 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3721 ims_mask |= sc->ims; 3722 } 3723 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3724 E1000_WRITE_FLUSH(hw); 3725 } 3726 3727 static void 3728 em_if_intr_disable(if_ctx_t ctx) 3729 { 3730 struct e1000_softc *sc = iflib_get_softc(ctx); 3731 struct e1000_hw *hw = &sc->hw; 3732 3733 if (sc->intr_type == IFLIB_INTR_MSIX) 3734 E1000_WRITE_REG(hw, EM_EIAC, 0); 3735 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3736 E1000_WRITE_FLUSH(hw); 3737 } 3738 3739 static void 3740 igb_if_intr_enable(if_ctx_t ctx) 3741 { 3742 struct e1000_softc *sc = iflib_get_softc(ctx); 3743 struct e1000_hw *hw = &sc->hw; 3744 u32 mask; 3745 3746 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3747 mask = (sc->que_mask | sc->link_mask); 3748 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3749 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3750 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3751 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3752 } else 3753 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3754 E1000_WRITE_FLUSH(hw); 3755 } 3756 3757 static void 3758 igb_if_intr_disable(if_ctx_t ctx) 3759 { 3760 struct e1000_softc *sc = iflib_get_softc(ctx); 3761 struct e1000_hw *hw = &sc->hw; 3762 3763 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3764 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3765 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3766 } 3767 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3768 E1000_WRITE_FLUSH(hw); 3769 } 3770 3771 /* 3772 * Bit of a misnomer, what this really means is 3773 * to enable OS management of the system... aka 3774 * to disable special hardware management features 3775 */ 3776 static void 3777 em_init_manageability(struct e1000_softc *sc) 3778 { 3779 /* A shared code workaround */ 3780 #define E1000_82542_MANC2H E1000_MANC2H 3781 if (sc->has_manage) { 3782 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3783 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3784 3785 /* disable hardware interception of ARP */ 3786 manc &= ~(E1000_MANC_ARP_EN); 3787 3788 /* enable receiving management packets to the host */ 3789 manc |= E1000_MANC_EN_MNG2HOST; 3790 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3791 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3792 manc2h |= E1000_MNG2HOST_PORT_623; 3793 manc2h |= E1000_MNG2HOST_PORT_664; 3794 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3795 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3796 } 3797 } 3798 3799 /* 3800 * Give control back to hardware management 3801 * controller if there is one. 3802 */ 3803 static void 3804 em_release_manageability(struct e1000_softc *sc) 3805 { 3806 if (sc->has_manage) { 3807 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3808 3809 /* re-enable hardware interception of ARP */ 3810 manc |= E1000_MANC_ARP_EN; 3811 manc &= ~E1000_MANC_EN_MNG2HOST; 3812 3813 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3814 } 3815 } 3816 3817 /* 3818 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3819 * For ASF and Pass Through versions of f/w this means 3820 * that the driver is loaded. For AMT version type f/w 3821 * this means that the network i/f is open. 3822 */ 3823 static void 3824 em_get_hw_control(struct e1000_softc *sc) 3825 { 3826 u32 ctrl_ext, swsm; 3827 3828 if (sc->vf_ifp) 3829 return; 3830 3831 if (sc->hw.mac.type == e1000_82573) { 3832 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3833 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3834 swsm | E1000_SWSM_DRV_LOAD); 3835 return; 3836 } 3837 /* else */ 3838 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3839 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3840 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3841 } 3842 3843 /* 3844 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3845 * For ASF and Pass Through versions of f/w this means that 3846 * the driver is no longer loaded. For AMT versions of the 3847 * f/w this means that the network i/f is closed. 3848 */ 3849 static void 3850 em_release_hw_control(struct e1000_softc *sc) 3851 { 3852 u32 ctrl_ext, swsm; 3853 3854 if (!sc->has_manage) 3855 return; 3856 3857 if (sc->hw.mac.type == e1000_82573) { 3858 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3859 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3860 swsm & ~E1000_SWSM_DRV_LOAD); 3861 return; 3862 } 3863 /* else */ 3864 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3865 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3866 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3867 return; 3868 } 3869 3870 static int 3871 em_is_valid_ether_addr(u8 *addr) 3872 { 3873 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3874 3875 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3876 return (false); 3877 } 3878 3879 return (true); 3880 } 3881 3882 /* 3883 ** Parse the interface capabilities with regard 3884 ** to both system management and wake-on-lan for 3885 ** later use. 3886 */ 3887 static void 3888 em_get_wakeup(if_ctx_t ctx) 3889 { 3890 struct e1000_softc *sc = iflib_get_softc(ctx); 3891 device_t dev = iflib_get_dev(ctx); 3892 u16 eeprom_data = 0, device_id, apme_mask; 3893 3894 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3895 apme_mask = EM_EEPROM_APME; 3896 3897 switch (sc->hw.mac.type) { 3898 case e1000_82542: 3899 case e1000_82543: 3900 break; 3901 case e1000_82544: 3902 e1000_read_nvm(&sc->hw, 3903 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3904 apme_mask = EM_82544_APME; 3905 break; 3906 case e1000_82546: 3907 case e1000_82546_rev_3: 3908 if (sc->hw.bus.func == 1) { 3909 e1000_read_nvm(&sc->hw, 3910 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3911 break; 3912 } else 3913 e1000_read_nvm(&sc->hw, 3914 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3915 break; 3916 case e1000_82573: 3917 case e1000_82583: 3918 sc->has_amt = true; 3919 /* FALLTHROUGH */ 3920 case e1000_82571: 3921 case e1000_82572: 3922 case e1000_80003es2lan: 3923 if (sc->hw.bus.func == 1) { 3924 e1000_read_nvm(&sc->hw, 3925 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3926 break; 3927 } else 3928 e1000_read_nvm(&sc->hw, 3929 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3930 break; 3931 case e1000_ich8lan: 3932 case e1000_ich9lan: 3933 case e1000_ich10lan: 3934 case e1000_pchlan: 3935 case e1000_pch2lan: 3936 case e1000_pch_lpt: 3937 case e1000_pch_spt: 3938 case e1000_82575: /* listing all igb devices */ 3939 case e1000_82576: 3940 case e1000_82580: 3941 case e1000_i350: 3942 case e1000_i354: 3943 case e1000_i210: 3944 case e1000_i211: 3945 case e1000_vfadapt: 3946 case e1000_vfadapt_i350: 3947 apme_mask = E1000_WUC_APME; 3948 sc->has_amt = true; 3949 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 3950 break; 3951 default: 3952 e1000_read_nvm(&sc->hw, 3953 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3954 break; 3955 } 3956 if (eeprom_data & apme_mask) 3957 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3958 /* 3959 * We have the eeprom settings, now apply the special cases 3960 * where the eeprom may be wrong or the board won't support 3961 * wake on lan on a particular port 3962 */ 3963 device_id = pci_get_device(dev); 3964 switch (device_id) { 3965 case E1000_DEV_ID_82546GB_PCIE: 3966 sc->wol = 0; 3967 break; 3968 case E1000_DEV_ID_82546EB_FIBER: 3969 case E1000_DEV_ID_82546GB_FIBER: 3970 /* Wake events only supported on port A for dual fiber 3971 * regardless of eeprom setting */ 3972 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3973 E1000_STATUS_FUNC_1) 3974 sc->wol = 0; 3975 break; 3976 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3977 /* if quad port adapter, disable WoL on all but port A */ 3978 if (global_quad_port_a != 0) 3979 sc->wol = 0; 3980 /* Reset for multiple quad port adapters */ 3981 if (++global_quad_port_a == 4) 3982 global_quad_port_a = 0; 3983 break; 3984 case E1000_DEV_ID_82571EB_FIBER: 3985 /* Wake events only supported on port A for dual fiber 3986 * regardless of eeprom setting */ 3987 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3988 E1000_STATUS_FUNC_1) 3989 sc->wol = 0; 3990 break; 3991 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3992 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3993 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3994 /* if quad port adapter, disable WoL on all but port A */ 3995 if (global_quad_port_a != 0) 3996 sc->wol = 0; 3997 /* Reset for multiple quad port adapters */ 3998 if (++global_quad_port_a == 4) 3999 global_quad_port_a = 0; 4000 break; 4001 } 4002 return; 4003 } 4004 4005 4006 /* 4007 * Enable PCI Wake On Lan capability 4008 */ 4009 static void 4010 em_enable_wakeup(if_ctx_t ctx) 4011 { 4012 struct e1000_softc *sc = iflib_get_softc(ctx); 4013 device_t dev = iflib_get_dev(ctx); 4014 if_t ifp = iflib_get_ifp(ctx); 4015 int error = 0; 4016 u32 pmc, ctrl, ctrl_ext, rctl; 4017 u16 status; 4018 4019 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4020 return; 4021 4022 /* 4023 * Determine type of Wakeup: note that wol 4024 * is set with all bits on by default. 4025 */ 4026 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4027 sc->wol &= ~E1000_WUFC_MAG; 4028 4029 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4030 sc->wol &= ~E1000_WUFC_EX; 4031 4032 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4033 sc->wol &= ~E1000_WUFC_MC; 4034 else { 4035 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4036 rctl |= E1000_RCTL_MPE; 4037 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4038 } 4039 4040 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4041 goto pme; 4042 4043 /* Advertise the wakeup capability */ 4044 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4045 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4046 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4047 4048 /* Keep the laser running on Fiber adapters */ 4049 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4050 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4051 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4052 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4053 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4054 } 4055 4056 if ((sc->hw.mac.type == e1000_ich8lan) || 4057 (sc->hw.mac.type == e1000_pchlan) || 4058 (sc->hw.mac.type == e1000_ich9lan) || 4059 (sc->hw.mac.type == e1000_ich10lan)) 4060 e1000_suspend_workarounds_ich8lan(&sc->hw); 4061 4062 if ( sc->hw.mac.type >= e1000_pchlan) { 4063 error = em_enable_phy_wakeup(sc); 4064 if (error) 4065 goto pme; 4066 } else { 4067 /* Enable wakeup by the MAC */ 4068 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4069 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4070 } 4071 4072 if (sc->hw.phy.type == e1000_phy_igp_3) 4073 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4074 4075 pme: 4076 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4077 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4078 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4079 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4080 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4081 4082 return; 4083 } 4084 4085 /* 4086 * WOL in the newer chipset interfaces (pchlan) 4087 * require thing to be copied into the phy 4088 */ 4089 static int 4090 em_enable_phy_wakeup(struct e1000_softc *sc) 4091 { 4092 struct e1000_hw *hw = &sc->hw; 4093 u32 mreg, ret = 0; 4094 u16 preg; 4095 4096 /* copy MAC RARs to PHY RARs */ 4097 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4098 4099 /* copy MAC MTA to PHY MTA */ 4100 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4101 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4102 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4103 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4104 (u16)((mreg >> 16) & 0xFFFF)); 4105 } 4106 4107 /* configure PHY Rx Control register */ 4108 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4109 mreg = E1000_READ_REG(hw, E1000_RCTL); 4110 if (mreg & E1000_RCTL_UPE) 4111 preg |= BM_RCTL_UPE; 4112 if (mreg & E1000_RCTL_MPE) 4113 preg |= BM_RCTL_MPE; 4114 preg &= ~(BM_RCTL_MO_MASK); 4115 if (mreg & E1000_RCTL_MO_3) 4116 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4117 << BM_RCTL_MO_SHIFT); 4118 if (mreg & E1000_RCTL_BAM) 4119 preg |= BM_RCTL_BAM; 4120 if (mreg & E1000_RCTL_PMCF) 4121 preg |= BM_RCTL_PMCF; 4122 mreg = E1000_READ_REG(hw, E1000_CTRL); 4123 if (mreg & E1000_CTRL_RFCE) 4124 preg |= BM_RCTL_RFCE; 4125 e1000_write_phy_reg(hw, BM_RCTL, preg); 4126 4127 /* enable PHY wakeup in MAC register */ 4128 E1000_WRITE_REG(hw, E1000_WUC, 4129 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4130 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4131 4132 /* configure and enable PHY wakeup in PHY registers */ 4133 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4134 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4135 4136 /* activate PHY wakeup */ 4137 ret = hw->phy.ops.acquire(hw); 4138 if (ret) { 4139 printf("Could not acquire PHY\n"); 4140 return ret; 4141 } 4142 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4143 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4144 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4145 if (ret) { 4146 printf("Could not read PHY page 769\n"); 4147 goto out; 4148 } 4149 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4150 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4151 if (ret) 4152 printf("Could not set PHY Host Wakeup bit\n"); 4153 out: 4154 hw->phy.ops.release(hw); 4155 4156 return ret; 4157 } 4158 4159 static void 4160 em_if_led_func(if_ctx_t ctx, int onoff) 4161 { 4162 struct e1000_softc *sc = iflib_get_softc(ctx); 4163 4164 if (onoff) { 4165 e1000_setup_led(&sc->hw); 4166 e1000_led_on(&sc->hw); 4167 } else { 4168 e1000_led_off(&sc->hw); 4169 e1000_cleanup_led(&sc->hw); 4170 } 4171 } 4172 4173 /* 4174 * Disable the L0S and L1 LINK states 4175 */ 4176 static void 4177 em_disable_aspm(struct e1000_softc *sc) 4178 { 4179 int base, reg; 4180 u16 link_cap,link_ctrl; 4181 device_t dev = sc->dev; 4182 4183 switch (sc->hw.mac.type) { 4184 case e1000_82573: 4185 case e1000_82574: 4186 case e1000_82583: 4187 break; 4188 default: 4189 return; 4190 } 4191 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4192 return; 4193 reg = base + PCIER_LINK_CAP; 4194 link_cap = pci_read_config(dev, reg, 2); 4195 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4196 return; 4197 reg = base + PCIER_LINK_CTL; 4198 link_ctrl = pci_read_config(dev, reg, 2); 4199 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4200 pci_write_config(dev, reg, link_ctrl, 2); 4201 return; 4202 } 4203 4204 /********************************************************************** 4205 * 4206 * Update the board statistics counters. 4207 * 4208 **********************************************************************/ 4209 static void 4210 em_update_stats_counters(struct e1000_softc *sc) 4211 { 4212 u64 prev_xoffrxc = sc->stats.xoffrxc; 4213 4214 if(sc->hw.phy.media_type == e1000_media_type_copper || 4215 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4216 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4217 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4218 } 4219 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4220 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4221 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4222 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4223 4224 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4225 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4226 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4227 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4228 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4229 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4230 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4231 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4232 /* 4233 ** For watchdog management we need to know if we have been 4234 ** paused during the last interval, so capture that here. 4235 */ 4236 if (sc->stats.xoffrxc != prev_xoffrxc) 4237 sc->shared->isc_pause_frames = 1; 4238 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4239 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4240 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4241 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4242 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4243 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4244 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4245 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4246 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4247 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4248 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4249 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4250 4251 /* For the 64-bit byte counters the low dword must be read first. */ 4252 /* Both registers clear on the read of the high dword */ 4253 4254 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4255 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4256 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4257 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4258 4259 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4260 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4261 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4262 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4263 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4264 4265 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4266 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4267 4268 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4269 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4270 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4271 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4272 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4273 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4274 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4275 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4276 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4277 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4278 4279 /* Interrupt Counts */ 4280 4281 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4282 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4283 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4284 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4285 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4286 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4287 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4288 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4289 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4290 4291 if (sc->hw.mac.type >= e1000_82543) { 4292 sc->stats.algnerrc += 4293 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4294 sc->stats.rxerrc += 4295 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4296 sc->stats.tncrs += 4297 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4298 sc->stats.cexterr += 4299 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4300 sc->stats.tsctc += 4301 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4302 sc->stats.tsctfc += 4303 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4304 } 4305 } 4306 4307 static uint64_t 4308 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4309 { 4310 struct e1000_softc *sc = iflib_get_softc(ctx); 4311 if_t ifp = iflib_get_ifp(ctx); 4312 4313 switch (cnt) { 4314 case IFCOUNTER_COLLISIONS: 4315 return (sc->stats.colc); 4316 case IFCOUNTER_IERRORS: 4317 return (sc->dropped_pkts + sc->stats.rxerrc + 4318 sc->stats.crcerrs + sc->stats.algnerrc + 4319 sc->stats.ruc + sc->stats.roc + 4320 sc->stats.mpc + sc->stats.cexterr); 4321 case IFCOUNTER_OERRORS: 4322 return (sc->stats.ecol + sc->stats.latecol + 4323 sc->watchdog_events); 4324 default: 4325 return (if_get_counter_default(ifp, cnt)); 4326 } 4327 } 4328 4329 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4330 * @ctx: iflib context 4331 * @event: event code to check 4332 * 4333 * Defaults to returning true for unknown events. 4334 * 4335 * @returns true if iflib needs to reinit the interface 4336 */ 4337 static bool 4338 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4339 { 4340 switch (event) { 4341 case IFLIB_RESTART_VLAN_CONFIG: 4342 return (false); 4343 default: 4344 return (true); 4345 } 4346 } 4347 4348 /* Export a single 32-bit register via a read-only sysctl. */ 4349 static int 4350 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4351 { 4352 struct e1000_softc *sc; 4353 u_int val; 4354 4355 sc = oidp->oid_arg1; 4356 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4357 return (sysctl_handle_int(oidp, &val, 0, req)); 4358 } 4359 4360 /* 4361 * Add sysctl variables, one per statistic, to the system. 4362 */ 4363 static void 4364 em_add_hw_stats(struct e1000_softc *sc) 4365 { 4366 device_t dev = iflib_get_dev(sc->ctx); 4367 struct em_tx_queue *tx_que = sc->tx_queues; 4368 struct em_rx_queue *rx_que = sc->rx_queues; 4369 4370 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4371 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4372 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4373 struct e1000_hw_stats *stats = &sc->stats; 4374 4375 struct sysctl_oid *stat_node, *queue_node, *int_node; 4376 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4377 4378 #define QUEUE_NAME_LEN 32 4379 char namebuf[QUEUE_NAME_LEN]; 4380 4381 /* Driver Statistics */ 4382 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4383 CTLFLAG_RD, &sc->dropped_pkts, 4384 "Driver dropped packets"); 4385 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4386 CTLFLAG_RD, &sc->link_irq, 4387 "Link MSI-X IRQ Handled"); 4388 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4389 CTLFLAG_RD, &sc->rx_overruns, 4390 "RX overruns"); 4391 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4392 CTLFLAG_RD, &sc->watchdog_events, 4393 "Watchdog timeouts"); 4394 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4395 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4396 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4397 "Device Control Register"); 4398 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4399 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4400 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4401 "Receiver Control Register"); 4402 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4403 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4404 "Flow Control High Watermark"); 4405 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4406 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4407 "Flow Control Low Watermark"); 4408 4409 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4410 struct tx_ring *txr = &tx_que->txr; 4411 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4412 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4413 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4414 queue_list = SYSCTL_CHILDREN(queue_node); 4415 4416 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4417 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4418 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4419 "Transmit Descriptor Head"); 4420 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4421 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4422 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4423 "Transmit Descriptor Tail"); 4424 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4425 CTLFLAG_RD, &txr->tx_irq, 4426 "Queue MSI-X Transmit Interrupts"); 4427 } 4428 4429 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4430 struct rx_ring *rxr = &rx_que->rxr; 4431 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4432 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4433 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4434 queue_list = SYSCTL_CHILDREN(queue_node); 4435 4436 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4437 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4438 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4439 "Receive Descriptor Head"); 4440 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4441 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4442 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4443 "Receive Descriptor Tail"); 4444 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4445 CTLFLAG_RD, &rxr->rx_irq, 4446 "Queue MSI-X Receive Interrupts"); 4447 } 4448 4449 /* MAC stats get their own sub node */ 4450 4451 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4452 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4453 stat_list = SYSCTL_CHILDREN(stat_node); 4454 4455 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4456 CTLFLAG_RD, &stats->ecol, 4457 "Excessive collisions"); 4458 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4459 CTLFLAG_RD, &stats->scc, 4460 "Single collisions"); 4461 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4462 CTLFLAG_RD, &stats->mcc, 4463 "Multiple collisions"); 4464 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4465 CTLFLAG_RD, &stats->latecol, 4466 "Late collisions"); 4467 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4468 CTLFLAG_RD, &stats->colc, 4469 "Collision Count"); 4470 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4471 CTLFLAG_RD, &sc->stats.symerrs, 4472 "Symbol Errors"); 4473 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4474 CTLFLAG_RD, &sc->stats.sec, 4475 "Sequence Errors"); 4476 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4477 CTLFLAG_RD, &sc->stats.dc, 4478 "Defer Count"); 4479 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4480 CTLFLAG_RD, &sc->stats.mpc, 4481 "Missed Packets"); 4482 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4483 CTLFLAG_RD, &sc->stats.rnbc, 4484 "Receive No Buffers"); 4485 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4486 CTLFLAG_RD, &sc->stats.ruc, 4487 "Receive Undersize"); 4488 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4489 CTLFLAG_RD, &sc->stats.rfc, 4490 "Fragmented Packets Received "); 4491 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4492 CTLFLAG_RD, &sc->stats.roc, 4493 "Oversized Packets Received"); 4494 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4495 CTLFLAG_RD, &sc->stats.rjc, 4496 "Recevied Jabber"); 4497 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4498 CTLFLAG_RD, &sc->stats.rxerrc, 4499 "Receive Errors"); 4500 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4501 CTLFLAG_RD, &sc->stats.crcerrs, 4502 "CRC errors"); 4503 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4504 CTLFLAG_RD, &sc->stats.algnerrc, 4505 "Alignment Errors"); 4506 /* On 82575 these are collision counts */ 4507 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4508 CTLFLAG_RD, &sc->stats.cexterr, 4509 "Collision/Carrier extension errors"); 4510 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4511 CTLFLAG_RD, &sc->stats.xonrxc, 4512 "XON Received"); 4513 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4514 CTLFLAG_RD, &sc->stats.xontxc, 4515 "XON Transmitted"); 4516 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4517 CTLFLAG_RD, &sc->stats.xoffrxc, 4518 "XOFF Received"); 4519 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4520 CTLFLAG_RD, &sc->stats.xofftxc, 4521 "XOFF Transmitted"); 4522 4523 /* Packet Reception Stats */ 4524 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4525 CTLFLAG_RD, &sc->stats.tpr, 4526 "Total Packets Received "); 4527 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4528 CTLFLAG_RD, &sc->stats.gprc, 4529 "Good Packets Received"); 4530 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4531 CTLFLAG_RD, &sc->stats.bprc, 4532 "Broadcast Packets Received"); 4533 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4534 CTLFLAG_RD, &sc->stats.mprc, 4535 "Multicast Packets Received"); 4536 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4537 CTLFLAG_RD, &sc->stats.prc64, 4538 "64 byte frames received "); 4539 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4540 CTLFLAG_RD, &sc->stats.prc127, 4541 "65-127 byte frames received"); 4542 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4543 CTLFLAG_RD, &sc->stats.prc255, 4544 "128-255 byte frames received"); 4545 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4546 CTLFLAG_RD, &sc->stats.prc511, 4547 "256-511 byte frames received"); 4548 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4549 CTLFLAG_RD, &sc->stats.prc1023, 4550 "512-1023 byte frames received"); 4551 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4552 CTLFLAG_RD, &sc->stats.prc1522, 4553 "1023-1522 byte frames received"); 4554 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4555 CTLFLAG_RD, &sc->stats.gorc, 4556 "Good Octets Received"); 4557 4558 /* Packet Transmission Stats */ 4559 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4560 CTLFLAG_RD, &sc->stats.gotc, 4561 "Good Octets Transmitted"); 4562 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4563 CTLFLAG_RD, &sc->stats.tpt, 4564 "Total Packets Transmitted"); 4565 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4566 CTLFLAG_RD, &sc->stats.gptc, 4567 "Good Packets Transmitted"); 4568 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4569 CTLFLAG_RD, &sc->stats.bptc, 4570 "Broadcast Packets Transmitted"); 4571 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4572 CTLFLAG_RD, &sc->stats.mptc, 4573 "Multicast Packets Transmitted"); 4574 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4575 CTLFLAG_RD, &sc->stats.ptc64, 4576 "64 byte frames transmitted "); 4577 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4578 CTLFLAG_RD, &sc->stats.ptc127, 4579 "65-127 byte frames transmitted"); 4580 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4581 CTLFLAG_RD, &sc->stats.ptc255, 4582 "128-255 byte frames transmitted"); 4583 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4584 CTLFLAG_RD, &sc->stats.ptc511, 4585 "256-511 byte frames transmitted"); 4586 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4587 CTLFLAG_RD, &sc->stats.ptc1023, 4588 "512-1023 byte frames transmitted"); 4589 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4590 CTLFLAG_RD, &sc->stats.ptc1522, 4591 "1024-1522 byte frames transmitted"); 4592 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4593 CTLFLAG_RD, &sc->stats.tsctc, 4594 "TSO Contexts Transmitted"); 4595 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4596 CTLFLAG_RD, &sc->stats.tsctfc, 4597 "TSO Contexts Failed"); 4598 4599 4600 /* Interrupt Stats */ 4601 4602 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4603 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4604 int_list = SYSCTL_CHILDREN(int_node); 4605 4606 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4607 CTLFLAG_RD, &sc->stats.iac, 4608 "Interrupt Assertion Count"); 4609 4610 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4611 CTLFLAG_RD, &sc->stats.icrxptc, 4612 "Interrupt Cause Rx Pkt Timer Expire Count"); 4613 4614 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4615 CTLFLAG_RD, &sc->stats.icrxatc, 4616 "Interrupt Cause Rx Abs Timer Expire Count"); 4617 4618 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4619 CTLFLAG_RD, &sc->stats.ictxptc, 4620 "Interrupt Cause Tx Pkt Timer Expire Count"); 4621 4622 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4623 CTLFLAG_RD, &sc->stats.ictxatc, 4624 "Interrupt Cause Tx Abs Timer Expire Count"); 4625 4626 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4627 CTLFLAG_RD, &sc->stats.ictxqec, 4628 "Interrupt Cause Tx Queue Empty Count"); 4629 4630 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4631 CTLFLAG_RD, &sc->stats.ictxqmtc, 4632 "Interrupt Cause Tx Queue Min Thresh Count"); 4633 4634 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4635 CTLFLAG_RD, &sc->stats.icrxdmtc, 4636 "Interrupt Cause Rx Desc Min Thresh Count"); 4637 4638 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4639 CTLFLAG_RD, &sc->stats.icrxoc, 4640 "Interrupt Cause Receiver Overrun Count"); 4641 } 4642 4643 static void 4644 em_fw_version_locked(if_ctx_t ctx) 4645 { 4646 struct e1000_softc *sc = iflib_get_softc(ctx); 4647 struct e1000_hw *hw = &sc->hw; 4648 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4649 uint16_t eep = 0; 4650 4651 /* 4652 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4653 * NVM locking model, so we do it in em_if_attach_pre() and store the 4654 * info in the softc 4655 */ 4656 ASSERT_CTX_LOCK_HELD(hw); 4657 4658 *fw_ver = (struct e1000_fw_version){0}; 4659 4660 if (hw->mac.type >= igb_mac_min) { 4661 /* 4662 * Use the Shared Code for igb(4) 4663 */ 4664 e1000_get_fw_version(hw, fw_ver); 4665 } else { 4666 /* 4667 * Otherwise, EEPROM version should be present on (almost?) all 4668 * devices here 4669 */ 4670 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4671 INIT_DEBUGOUT("can't get EEPROM version"); 4672 return; 4673 } 4674 4675 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4676 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4677 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4678 } 4679 } 4680 4681 static void 4682 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4683 { 4684 const char *space = ""; 4685 4686 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4687 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4688 fw_ver->eep_minor, fw_ver->eep_build); 4689 space = " "; 4690 } 4691 4692 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4693 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4694 space, fw_ver->invm_major, fw_ver->invm_minor, 4695 fw_ver->invm_img_type); 4696 space = " "; 4697 } 4698 4699 if (fw_ver->or_valid) { 4700 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4701 space, fw_ver->or_major, fw_ver->or_build, 4702 fw_ver->or_patch); 4703 space = " "; 4704 } 4705 4706 if (fw_ver->etrack_id) 4707 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4708 } 4709 4710 static void 4711 em_print_fw_version(struct e1000_softc *sc ) 4712 { 4713 device_t dev = sc->dev; 4714 struct sbuf *buf; 4715 int error = 0; 4716 4717 buf = sbuf_new_auto(); 4718 if (!buf) { 4719 device_printf(dev, "Could not allocate sbuf for output.\n"); 4720 return; 4721 } 4722 4723 em_sbuf_fw_version(&sc->fw_ver, buf); 4724 4725 error = sbuf_finish(buf); 4726 if (error) 4727 device_printf(dev, "Error finishing sbuf: %d\n", error); 4728 else if (sbuf_len(buf)) 4729 device_printf(dev, "%s\n", sbuf_data(buf)); 4730 4731 sbuf_delete(buf); 4732 } 4733 4734 static int 4735 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4736 { 4737 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4738 device_t dev = sc->dev; 4739 struct sbuf *buf; 4740 int error = 0; 4741 4742 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4743 if (!buf) { 4744 device_printf(dev, "Could not allocate sbuf for output.\n"); 4745 return (ENOMEM); 4746 } 4747 4748 em_sbuf_fw_version(&sc->fw_ver, buf); 4749 4750 error = sbuf_finish(buf); 4751 if (error) 4752 device_printf(dev, "Error finishing sbuf: %d\n", error); 4753 4754 sbuf_delete(buf); 4755 4756 return (0); 4757 } 4758 4759 /********************************************************************** 4760 * 4761 * This routine provides a way to dump out the adapter eeprom, 4762 * often a useful debug/service tool. This only dumps the first 4763 * 32 words, stuff that matters is in that extent. 4764 * 4765 **********************************************************************/ 4766 static int 4767 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4768 { 4769 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4770 int error; 4771 int result; 4772 4773 result = -1; 4774 error = sysctl_handle_int(oidp, &result, 0, req); 4775 4776 if (error || !req->newptr) 4777 return (error); 4778 4779 /* 4780 * This value will cause a hex dump of the 4781 * first 32 16-bit words of the EEPROM to 4782 * the screen. 4783 */ 4784 if (result == 1) 4785 em_print_nvm_info(sc); 4786 4787 return (error); 4788 } 4789 4790 static void 4791 em_print_nvm_info(struct e1000_softc *sc) 4792 { 4793 struct e1000_hw *hw = &sc->hw; 4794 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4795 u16 eeprom_data; 4796 int i, j, row = 0; 4797 4798 /* Its a bit crude, but it gets the job done */ 4799 printf("\nInterface EEPROM Dump:\n"); 4800 printf("Offset\n0x0000 "); 4801 4802 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4803 sx_xlock(iflib_ctx_lock); 4804 ASSERT_CTX_LOCK_HELD(hw); 4805 for (i = 0, j = 0; i < 32; i++, j++) { 4806 if (j == 8) { /* Make the offset block */ 4807 j = 0; ++row; 4808 printf("\n0x00%x0 ",row); 4809 } 4810 e1000_read_nvm(hw, i, 1, &eeprom_data); 4811 printf("%04x ", eeprom_data); 4812 } 4813 sx_xunlock(iflib_ctx_lock); 4814 printf("\n"); 4815 } 4816 4817 static int 4818 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4819 { 4820 struct em_int_delay_info *info; 4821 struct e1000_softc *sc; 4822 u32 regval; 4823 int error, usecs, ticks; 4824 4825 info = (struct em_int_delay_info *) arg1; 4826 usecs = info->value; 4827 error = sysctl_handle_int(oidp, &usecs, 0, req); 4828 if (error != 0 || req->newptr == NULL) 4829 return (error); 4830 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4831 return (EINVAL); 4832 info->value = usecs; 4833 ticks = EM_USECS_TO_TICKS(usecs); 4834 if (info->offset == E1000_ITR) /* units are 256ns here */ 4835 ticks *= 4; 4836 4837 sc = info->sc; 4838 4839 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4840 regval = (regval & ~0xffff) | (ticks & 0xffff); 4841 /* Handle a few special cases. */ 4842 switch (info->offset) { 4843 case E1000_RDTR: 4844 break; 4845 case E1000_TIDV: 4846 if (ticks == 0) { 4847 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4848 /* Don't write 0 into the TIDV register. */ 4849 regval++; 4850 } else 4851 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4852 break; 4853 } 4854 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4855 return (0); 4856 } 4857 4858 static void 4859 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4860 const char *description, struct em_int_delay_info *info, 4861 int offset, int value) 4862 { 4863 info->sc = sc; 4864 info->offset = offset; 4865 info->value = value; 4866 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4867 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4868 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4869 info, 0, em_sysctl_int_delay, "I", description); 4870 } 4871 4872 /* 4873 * Set flow control using sysctl: 4874 * Flow control values: 4875 * 0 - off 4876 * 1 - rx pause 4877 * 2 - tx pause 4878 * 3 - full 4879 */ 4880 static int 4881 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4882 { 4883 int error; 4884 static int input = 3; /* default is full */ 4885 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4886 4887 error = sysctl_handle_int(oidp, &input, 0, req); 4888 4889 if ((error) || (req->newptr == NULL)) 4890 return (error); 4891 4892 if (input == sc->fc) /* no change? */ 4893 return (error); 4894 4895 switch (input) { 4896 case e1000_fc_rx_pause: 4897 case e1000_fc_tx_pause: 4898 case e1000_fc_full: 4899 case e1000_fc_none: 4900 sc->hw.fc.requested_mode = input; 4901 sc->fc = input; 4902 break; 4903 default: 4904 /* Do nothing */ 4905 return (error); 4906 } 4907 4908 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4909 e1000_force_mac_fc(&sc->hw); 4910 return (error); 4911 } 4912 4913 /* 4914 * Manage Energy Efficient Ethernet: 4915 * Control values: 4916 * 0/1 - enabled/disabled 4917 */ 4918 static int 4919 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4920 { 4921 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4922 int error, value; 4923 4924 value = sc->hw.dev_spec.ich8lan.eee_disable; 4925 error = sysctl_handle_int(oidp, &value, 0, req); 4926 if (error || req->newptr == NULL) 4927 return (error); 4928 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4929 em_if_init(sc->ctx); 4930 4931 return (0); 4932 } 4933 4934 static int 4935 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4936 { 4937 struct e1000_softc *sc; 4938 int error; 4939 int result; 4940 4941 result = -1; 4942 error = sysctl_handle_int(oidp, &result, 0, req); 4943 4944 if (error || !req->newptr) 4945 return (error); 4946 4947 if (result == 1) { 4948 sc = (struct e1000_softc *) arg1; 4949 em_print_debug_info(sc); 4950 } 4951 4952 return (error); 4953 } 4954 4955 static int 4956 em_get_rs(SYSCTL_HANDLER_ARGS) 4957 { 4958 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4959 int error; 4960 int result; 4961 4962 result = 0; 4963 error = sysctl_handle_int(oidp, &result, 0, req); 4964 4965 if (error || !req->newptr || result != 1) 4966 return (error); 4967 em_dump_rs(sc); 4968 4969 return (error); 4970 } 4971 4972 static void 4973 em_if_debug(if_ctx_t ctx) 4974 { 4975 em_dump_rs(iflib_get_softc(ctx)); 4976 } 4977 4978 /* 4979 * This routine is meant to be fluid, add whatever is 4980 * needed for debugging a problem. -jfv 4981 */ 4982 static void 4983 em_print_debug_info(struct e1000_softc *sc) 4984 { 4985 device_t dev = iflib_get_dev(sc->ctx); 4986 if_t ifp = iflib_get_ifp(sc->ctx); 4987 struct tx_ring *txr = &sc->tx_queues->txr; 4988 struct rx_ring *rxr = &sc->rx_queues->rxr; 4989 4990 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4991 printf("Interface is RUNNING "); 4992 else 4993 printf("Interface is NOT RUNNING\n"); 4994 4995 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4996 printf("and INACTIVE\n"); 4997 else 4998 printf("and ACTIVE\n"); 4999 5000 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5001 device_printf(dev, "TX Queue %d ------\n", i); 5002 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5003 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5004 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5005 5006 } 5007 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5008 device_printf(dev, "RX Queue %d ------\n", j); 5009 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5010 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5011 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5012 } 5013 } 5014 5015 /* 5016 * 82574 only: 5017 * Write a new value to the EEPROM increasing the number of MSI-X 5018 * vectors from 3 to 5, for proper multiqueue support. 5019 */ 5020 static void 5021 em_enable_vectors_82574(if_ctx_t ctx) 5022 { 5023 struct e1000_softc *sc = iflib_get_softc(ctx); 5024 struct e1000_hw *hw = &sc->hw; 5025 device_t dev = iflib_get_dev(ctx); 5026 u16 edata; 5027 5028 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5029 if (bootverbose) 5030 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5031 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5032 device_printf(dev, "Writing to eeprom: increasing " 5033 "reported MSI-X vectors from 3 to 5...\n"); 5034 edata &= ~(EM_NVM_MSIX_N_MASK); 5035 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5036 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5037 e1000_update_nvm_checksum(hw); 5038 device_printf(dev, "Writing to eeprom: done\n"); 5039 } 5040 } 5041