1 /*- 2 * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 #include "if_em.h" 29 #include <sys/sbuf.h> 30 #include <machine/_inttypes.h> 31 32 #define em_mac_min e1000_82547 33 #define igb_mac_min e1000_82575 34 35 /********************************************************************* 36 * Driver version: 37 *********************************************************************/ 38 char em_driver_version[] = "7.6.1-k"; 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last field stores an index into e1000_strings 45 * Last entry must be all 0s 46 * 47 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 48 *********************************************************************/ 49 50 static pci_vendor_info_t em_vendor_info_array[] = 51 { 52 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 53 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 54 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 55 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 58 59 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 60 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 61 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 66 67 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 70 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 71 72 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 74 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 76 77 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 78 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 79 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 82 83 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 84 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 85 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 92 93 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 94 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 95 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 96 97 /* Intel(R) PRO/1000 Network Connection - em */ 98 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 99 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 100 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 162 /* required last entry */ 163 PVID_END 164 }; 165 166 static pci_vendor_info_t igb_vendor_info_array[] = 167 { 168 /* Intel(R) PRO/1000 Network Connection - em */ 169 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 170 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 171 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 172 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 173 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 174 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 175 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 176 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 177 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 178 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 179 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 180 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 181 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 182 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 183 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 184 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 /* required last entry */ 209 PVID_END 210 }; 211 212 /********************************************************************* 213 * Function prototypes 214 *********************************************************************/ 215 static void *em_register(device_t dev); 216 static void *igb_register(device_t dev); 217 static int em_if_attach_pre(if_ctx_t ctx); 218 static int em_if_attach_post(if_ctx_t ctx); 219 static int em_if_detach(if_ctx_t ctx); 220 static int em_if_shutdown(if_ctx_t ctx); 221 static int em_if_suspend(if_ctx_t ctx); 222 static int em_if_resume(if_ctx_t ctx); 223 224 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 225 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 226 static void em_if_queues_free(if_ctx_t ctx); 227 228 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 229 static void em_if_init(if_ctx_t ctx); 230 static void em_if_stop(if_ctx_t ctx); 231 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 232 static int em_if_media_change(if_ctx_t ctx); 233 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 234 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 235 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 236 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 237 238 static void em_identify_hardware(if_ctx_t ctx); 239 static int em_allocate_pci_resources(if_ctx_t ctx); 240 static void em_free_pci_resources(if_ctx_t ctx); 241 static void em_reset(if_ctx_t ctx); 242 static int em_setup_interface(if_ctx_t ctx); 243 static int em_setup_msix(if_ctx_t ctx); 244 245 static void em_initialize_transmit_unit(if_ctx_t ctx); 246 static void em_initialize_receive_unit(if_ctx_t ctx); 247 248 static void em_if_enable_intr(if_ctx_t ctx); 249 static void em_if_disable_intr(if_ctx_t ctx); 250 static int em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 251 static void em_if_multi_set(if_ctx_t ctx); 252 static void em_if_update_admin_status(if_ctx_t ctx); 253 static void em_update_stats_counters(struct adapter *); 254 static void em_add_hw_stats(struct adapter *adapter); 255 static int em_if_set_promisc(if_ctx_t ctx, int flags); 256 static void em_setup_vlan_hw_support(struct adapter *); 257 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 258 static void em_print_nvm_info(struct adapter *); 259 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 260 static void em_print_debug_info(struct adapter *); 261 static int em_is_valid_ether_addr(u8 *); 262 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 263 static void em_add_int_delay_sysctl(struct adapter *, const char *, 264 const char *, struct em_int_delay_info *, int, int); 265 /* Management and WOL Support */ 266 static void em_init_manageability(struct adapter *); 267 static void em_release_manageability(struct adapter *); 268 static void em_get_hw_control(struct adapter *); 269 static void em_release_hw_control(struct adapter *); 270 static void em_get_wakeup(if_ctx_t ctx); 271 static void em_enable_wakeup(if_ctx_t ctx); 272 static int em_enable_phy_wakeup(struct adapter *); 273 static void em_disable_aspm(struct adapter *); 274 275 int em_intr(void *arg); 276 static void em_disable_promisc(if_ctx_t ctx); 277 278 /* MSIX handlers */ 279 static int em_if_msix_intr_assign(if_ctx_t, int); 280 static int em_msix_link(void *); 281 static void em_handle_link(void *context); 282 283 static void em_enable_vectors_82574(if_ctx_t); 284 285 static void em_set_sysctl_value(struct adapter *, const char *, 286 const char *, int *, int); 287 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 288 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 289 static void em_if_led_func(if_ctx_t ctx, int onoff); 290 291 static void em_init_tx_ring(struct em_tx_queue *que); 292 static int em_get_regs(SYSCTL_HANDLER_ARGS); 293 294 static void lem_smartspeed(struct adapter *adapter); 295 static void igb_configure_queues(struct adapter *adapter); 296 297 298 /********************************************************************* 299 * FreeBSD Device Interface Entry Points 300 *********************************************************************/ 301 static device_method_t em_methods[] = { 302 /* Device interface */ 303 DEVMETHOD(device_register, em_register), 304 DEVMETHOD(device_probe, iflib_device_probe), 305 DEVMETHOD(device_attach, iflib_device_attach), 306 DEVMETHOD(device_detach, iflib_device_detach), 307 DEVMETHOD(device_shutdown, iflib_device_shutdown), 308 DEVMETHOD(device_suspend, iflib_device_suspend), 309 DEVMETHOD(device_resume, iflib_device_resume), 310 DEVMETHOD_END 311 }; 312 313 static device_method_t igb_methods[] = { 314 /* Device interface */ 315 DEVMETHOD(device_register, igb_register), 316 DEVMETHOD(device_probe, iflib_device_probe), 317 DEVMETHOD(device_attach, iflib_device_attach), 318 DEVMETHOD(device_detach, iflib_device_detach), 319 DEVMETHOD(device_shutdown, iflib_device_shutdown), 320 DEVMETHOD(device_suspend, iflib_device_suspend), 321 DEVMETHOD(device_resume, iflib_device_resume), 322 DEVMETHOD_END 323 }; 324 325 326 static driver_t em_driver = { 327 "em", em_methods, sizeof(struct adapter), 328 }; 329 330 static devclass_t em_devclass; 331 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 332 333 MODULE_DEPEND(em, pci, 1, 1, 1); 334 MODULE_DEPEND(em, ether, 1, 1, 1); 335 MODULE_DEPEND(em, iflib, 1, 1, 1); 336 337 static driver_t igb_driver = { 338 "igb", igb_methods, sizeof(struct adapter), 339 }; 340 341 static devclass_t igb_devclass; 342 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 343 344 MODULE_DEPEND(igb, pci, 1, 1, 1); 345 MODULE_DEPEND(igb, ether, 1, 1, 1); 346 MODULE_DEPEND(igb, iflib, 1, 1, 1); 347 348 349 static device_method_t em_if_methods[] = { 350 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 351 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 352 DEVMETHOD(ifdi_detach, em_if_detach), 353 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 354 DEVMETHOD(ifdi_suspend, em_if_suspend), 355 DEVMETHOD(ifdi_resume, em_if_resume), 356 DEVMETHOD(ifdi_init, em_if_init), 357 DEVMETHOD(ifdi_stop, em_if_stop), 358 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 359 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 360 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 361 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 362 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 363 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 364 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 365 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 366 DEVMETHOD(ifdi_media_status, em_if_media_status), 367 DEVMETHOD(ifdi_media_change, em_if_media_change), 368 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 369 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 370 DEVMETHOD(ifdi_timer, em_if_timer), 371 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 372 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 373 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 374 DEVMETHOD(ifdi_led_func, em_if_led_func), 375 DEVMETHOD(ifdi_queue_intr_enable, em_if_queue_intr_enable), 376 DEVMETHOD_END 377 }; 378 379 /* 380 * note that if (adapter->msix_mem) is replaced by: 381 * if (adapter->intr_type == IFLIB_INTR_MSIX) 382 */ 383 static driver_t em_if_driver = { 384 "em_if", em_if_methods, sizeof(struct adapter) 385 }; 386 387 /********************************************************************* 388 * Tunable default values. 389 *********************************************************************/ 390 391 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 392 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 393 #define M_TSO_LEN 66 394 395 #define MAX_INTS_PER_SEC 8000 396 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 397 398 /* Allow common code without TSO */ 399 #ifndef CSUM_TSO 400 #define CSUM_TSO 0 401 #endif 402 403 #define TSO_WORKAROUND 4 404 405 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 406 407 static int em_disable_crc_stripping = 0; 408 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 409 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 410 411 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 412 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 413 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 414 0, "Default transmit interrupt delay in usecs"); 415 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 416 0, "Default receive interrupt delay in usecs"); 417 418 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 419 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 420 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 421 &em_tx_abs_int_delay_dflt, 0, 422 "Default transmit interrupt delay limit in usecs"); 423 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 424 &em_rx_abs_int_delay_dflt, 0, 425 "Default receive interrupt delay limit in usecs"); 426 427 static int em_smart_pwr_down = FALSE; 428 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 429 0, "Set to true to leave smart power down enabled on newer adapters"); 430 431 /* Controls whether promiscuous also shows bad packets */ 432 static int em_debug_sbp = TRUE; 433 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 434 "Show bad packets in promiscuous mode"); 435 436 /* How many packets rxeof tries to clean at a time */ 437 static int em_rx_process_limit = 100; 438 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 439 &em_rx_process_limit, 0, 440 "Maximum number of received packets to process " 441 "at a time, -1 means unlimited"); 442 443 /* Energy efficient ethernet - default to OFF */ 444 static int eee_setting = 1; 445 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 446 "Enable Energy Efficient Ethernet"); 447 448 /* 449 ** Tuneable Interrupt rate 450 */ 451 static int em_max_interrupt_rate = 8000; 452 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 453 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 454 455 456 457 /* Global used in WOL setup with multiport cards */ 458 static int global_quad_port_a = 0; 459 460 extern struct if_txrx igb_txrx; 461 extern struct if_txrx em_txrx; 462 extern struct if_txrx lem_txrx; 463 464 static struct if_shared_ctx em_sctx_init = { 465 .isc_magic = IFLIB_MAGIC, 466 .isc_q_align = PAGE_SIZE, 467 .isc_tx_maxsize = EM_TSO_SIZE, 468 .isc_tx_maxsegsize = PAGE_SIZE, 469 .isc_rx_maxsize = MJUM9BYTES, 470 .isc_rx_nsegments = 1, 471 .isc_rx_maxsegsize = MJUM9BYTES, 472 .isc_nfl = 1, 473 .isc_nrxqs = 1, 474 .isc_ntxqs = 1, 475 .isc_admin_intrcnt = 1, 476 .isc_vendor_info = em_vendor_info_array, 477 .isc_driver_version = em_driver_version, 478 .isc_driver = &em_if_driver, 479 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 480 481 .isc_nrxd_min = {EM_MIN_RXD}, 482 .isc_ntxd_min = {EM_MIN_TXD}, 483 .isc_nrxd_max = {EM_MAX_RXD}, 484 .isc_ntxd_max = {EM_MAX_TXD}, 485 .isc_nrxd_default = {EM_DEFAULT_RXD}, 486 .isc_ntxd_default = {EM_DEFAULT_TXD}, 487 }; 488 489 if_shared_ctx_t em_sctx = &em_sctx_init; 490 491 492 static struct if_shared_ctx igb_sctx_init = { 493 .isc_magic = IFLIB_MAGIC, 494 .isc_q_align = PAGE_SIZE, 495 .isc_tx_maxsize = EM_TSO_SIZE, 496 .isc_tx_maxsegsize = PAGE_SIZE, 497 .isc_rx_maxsize = MJUM9BYTES, 498 .isc_rx_nsegments = 1, 499 .isc_rx_maxsegsize = MJUM9BYTES, 500 .isc_nfl = 1, 501 .isc_nrxqs = 1, 502 .isc_ntxqs = 1, 503 .isc_admin_intrcnt = 1, 504 .isc_vendor_info = igb_vendor_info_array, 505 .isc_driver_version = em_driver_version, 506 .isc_driver = &em_if_driver, 507 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP, 508 509 .isc_nrxd_min = {EM_MIN_RXD}, 510 .isc_ntxd_min = {EM_MIN_TXD}, 511 .isc_nrxd_max = {EM_MAX_RXD}, 512 .isc_ntxd_max = {EM_MAX_TXD}, 513 .isc_nrxd_default = {EM_DEFAULT_RXD}, 514 .isc_ntxd_default = {EM_DEFAULT_TXD}, 515 }; 516 517 if_shared_ctx_t igb_sctx = &igb_sctx_init; 518 519 /***************************************************************** 520 * 521 * Dump Registers 522 * 523 ****************************************************************/ 524 #define IGB_REGS_LEN 739 525 526 static int em_get_regs(SYSCTL_HANDLER_ARGS) 527 { 528 struct adapter *adapter = (struct adapter *)arg1; 529 struct e1000_hw *hw = &adapter->hw; 530 531 struct sbuf *sb; 532 u32 *regs_buff = (u32 *)malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_NOWAIT); 533 int rc; 534 535 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 536 537 rc = sysctl_wire_old_buffer(req, 0); 538 MPASS(rc == 0); 539 if (rc != 0) 540 return (rc); 541 542 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 543 MPASS(sb != NULL); 544 if (sb == NULL) 545 return (ENOMEM); 546 547 /* General Registers */ 548 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 549 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 550 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 551 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 552 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 553 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 554 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 555 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 556 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 557 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 558 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 559 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 560 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 561 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 562 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 563 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 564 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 565 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 566 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 567 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 568 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 569 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 570 571 sbuf_printf(sb, "General Registers\n"); 572 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 573 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 574 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 575 576 sbuf_printf(sb, "Interrupt Registers\n"); 577 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 578 579 sbuf_printf(sb, "RX Registers\n"); 580 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 581 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 582 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 583 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 584 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 585 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 586 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 587 588 sbuf_printf(sb, "TX Registers\n"); 589 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 590 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 591 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 592 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 593 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 594 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 595 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 596 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 597 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 598 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 599 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 600 601 #ifdef DUMP_DESCS 602 { 603 if_softc_ctx_t scctx = adapter->shared; 604 struct rx_ring *rxr = &rx_que->rxr; 605 struct tx_ring *txr = &tx_que->txr; 606 int ntxd = scctx->isc_ntxd[0]; 607 int nrxd = scctx->isc_nrxd[0]; 608 int j; 609 610 for (j = 0; j < nrxd; j++) { 611 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 612 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 613 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 614 } 615 616 for (j = 0; j < min(ntxd, 256); j++) { 617 struct em_txbuffer *buf = &txr->tx_buffers[j]; 618 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 619 620 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 621 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 622 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 623 624 } 625 } 626 #endif 627 628 rc = sbuf_finish(sb); 629 sbuf_delete(sb); 630 return(rc); 631 } 632 633 static void * 634 em_register(device_t dev) 635 { 636 return (em_sctx); 637 } 638 639 static void * 640 igb_register(device_t dev) 641 { 642 return (igb_sctx); 643 } 644 645 static void 646 em_init_tx_ring(struct em_tx_queue *que) 647 { 648 struct adapter *sc = que->adapter; 649 if_softc_ctx_t scctx = sc->shared; 650 struct tx_ring *txr = &que->txr; 651 struct em_txbuffer *tx_buffer; 652 653 tx_buffer = txr->tx_buffers; 654 for (int i = 0; i < scctx->isc_ntxd[0]; i++, tx_buffer++) { 655 tx_buffer->eop = -1; 656 } 657 } 658 659 static int 660 em_set_num_queues(if_ctx_t ctx) 661 { 662 struct adapter *adapter = iflib_get_softc(ctx); 663 int maxqueues; 664 665 /* Sanity check based on HW */ 666 switch (adapter->hw.mac.type) { 667 case e1000_82576: 668 case e1000_82580: 669 case e1000_i350: 670 case e1000_i354: 671 maxqueues = 8; 672 break; 673 case e1000_i210: 674 case e1000_82575: 675 maxqueues = 4; 676 break; 677 case e1000_i211: 678 case e1000_82574: 679 maxqueues = 2; 680 break; 681 default: 682 maxqueues = 1; 683 break; 684 } 685 686 return (maxqueues); 687 } 688 689 690 #define EM_CAPS \ 691 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 692 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \ 693 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 694 695 #define IGB_CAPS \ 696 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 697 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 698 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU; 699 700 /********************************************************************* 701 * Device initialization routine 702 * 703 * The attach entry point is called when the driver is being loaded. 704 * This routine identifies the type of hardware, allocates all resources 705 * and initializes the hardware. 706 * 707 * return 0 on success, positive on failure 708 *********************************************************************/ 709 710 static int 711 em_if_attach_pre(if_ctx_t ctx) 712 { 713 struct adapter *adapter; 714 if_softc_ctx_t scctx; 715 device_t dev; 716 struct e1000_hw *hw; 717 int error = 0; 718 719 INIT_DEBUGOUT("em_if_attach_pre begin"); 720 dev = iflib_get_dev(ctx); 721 adapter = iflib_get_softc(ctx); 722 723 if (resource_disabled("em", device_get_unit(dev))) { 724 device_printf(dev, "Disabled by device hint\n"); 725 return (ENXIO); 726 } 727 728 adapter->ctx = ctx; 729 adapter->dev = adapter->osdep.dev = dev; 730 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 731 adapter->media = iflib_get_media(ctx); 732 hw = &adapter->hw; 733 734 adapter->tx_process_limit = scctx->isc_ntxd[0]; 735 736 /* SYSCTL stuff */ 737 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 738 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 739 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 740 em_sysctl_nvm_info, "I", "NVM Information"); 741 742 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 743 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 744 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 745 em_sysctl_debug_info, "I", "Debug Information"); 746 747 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 748 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 749 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 750 em_set_flowcntl, "I", "Flow Control"); 751 752 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 753 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 754 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 755 em_get_regs, "A", "Dump Registers"); 756 757 /* Determine hardware and mac info */ 758 em_identify_hardware(ctx); 759 760 /* Set isc_msix_bar */ 761 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 762 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 763 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 764 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 765 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 766 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 767 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 768 769 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 770 771 772 if (adapter->hw.mac.type >= igb_mac_min) { 773 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 774 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 775 scctx->isc_txrx = &igb_txrx; 776 scctx->isc_capenable = IGB_CAPS; 777 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \ 778 | CSUM_IP6_UDP | CSUM_IP6_TCP; 779 if (adapter->hw.mac.type != e1000_82575) 780 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 781 782 } else if (adapter->hw.mac.type >= em_mac_min) { 783 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 784 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 785 scctx->isc_txrx = &em_txrx; 786 scctx->isc_capenable = EM_CAPS; 787 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 788 } else { 789 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 790 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 791 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 792 scctx->isc_txrx = &lem_txrx; 793 scctx->isc_capenable = EM_CAPS; 794 if (adapter->hw.mac.type < e1000_82543) 795 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 796 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 797 scctx->isc_msix_bar = 0; 798 } 799 800 /* Setup PCI resources */ 801 if (em_allocate_pci_resources(ctx)) { 802 device_printf(dev, "Allocation of PCI resources failed\n"); 803 error = ENXIO; 804 goto err_pci; 805 } 806 807 /* 808 ** For ICH8 and family we need to 809 ** map the flash memory, and this 810 ** must happen after the MAC is 811 ** identified 812 */ 813 if ((hw->mac.type == e1000_ich8lan) || 814 (hw->mac.type == e1000_ich9lan) || 815 (hw->mac.type == e1000_ich10lan) || 816 (hw->mac.type == e1000_pchlan) || 817 (hw->mac.type == e1000_pch2lan) || 818 (hw->mac.type == e1000_pch_lpt)) { 819 int rid = EM_BAR_TYPE_FLASH; 820 adapter->flash = bus_alloc_resource_any(dev, 821 SYS_RES_MEMORY, &rid, RF_ACTIVE); 822 if (adapter->flash == NULL) { 823 device_printf(dev, "Mapping of Flash failed\n"); 824 error = ENXIO; 825 goto err_pci; 826 } 827 /* This is used in the shared code */ 828 hw->flash_address = (u8 *)adapter->flash; 829 adapter->osdep.flash_bus_space_tag = 830 rman_get_bustag(adapter->flash); 831 adapter->osdep.flash_bus_space_handle = 832 rman_get_bushandle(adapter->flash); 833 } 834 /* 835 ** In the new SPT device flash is not a 836 ** separate BAR, rather it is also in BAR0, 837 ** so use the same tag and an offset handle for the 838 ** FLASH read/write macros in the shared code. 839 */ 840 else if (hw->mac.type == e1000_pch_spt) { 841 adapter->osdep.flash_bus_space_tag = 842 adapter->osdep.mem_bus_space_tag; 843 adapter->osdep.flash_bus_space_handle = 844 adapter->osdep.mem_bus_space_handle 845 + E1000_FLASH_BASE_ADDR; 846 } 847 848 /* Do Shared Code initialization */ 849 error = e1000_setup_init_funcs(hw, TRUE); 850 if (error) { 851 device_printf(dev, "Setup of Shared code failed, error %d\n", 852 error); 853 error = ENXIO; 854 goto err_pci; 855 } 856 857 em_setup_msix(ctx); 858 e1000_get_bus_info(hw); 859 860 /* Set up some sysctls for the tunable interrupt delays */ 861 em_add_int_delay_sysctl(adapter, "rx_int_delay", 862 "receive interrupt delay in usecs", &adapter->rx_int_delay, 863 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 864 em_add_int_delay_sysctl(adapter, "tx_int_delay", 865 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 866 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 867 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 868 "receive interrupt delay limit in usecs", 869 &adapter->rx_abs_int_delay, 870 E1000_REGISTER(hw, E1000_RADV), 871 em_rx_abs_int_delay_dflt); 872 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 873 "transmit interrupt delay limit in usecs", 874 &adapter->tx_abs_int_delay, 875 E1000_REGISTER(hw, E1000_TADV), 876 em_tx_abs_int_delay_dflt); 877 em_add_int_delay_sysctl(adapter, "itr", 878 "interrupt delay limit in usecs/4", 879 &adapter->tx_itr, 880 E1000_REGISTER(hw, E1000_ITR), 881 DEFAULT_ITR); 882 883 /* Sysctl for limiting the amount of work done in the taskqueue */ 884 em_set_sysctl_value(adapter, "rx_processing_limit", 885 "max number of rx packets to process", &adapter->rx_process_limit, 886 em_rx_process_limit); 887 888 hw->mac.autoneg = DO_AUTO_NEG; 889 hw->phy.autoneg_wait_to_complete = FALSE; 890 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 891 892 if (adapter->hw.mac.type < em_mac_min) { 893 e1000_init_script_state_82541(&adapter->hw, TRUE); 894 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 895 } 896 /* Copper options */ 897 if (hw->phy.media_type == e1000_media_type_copper) { 898 hw->phy.mdix = AUTO_ALL_MODES; 899 hw->phy.disable_polarity_correction = FALSE; 900 hw->phy.ms_type = EM_MASTER_SLAVE; 901 } 902 903 /* 904 * Set the frame limits assuming 905 * standard ethernet sized frames. 906 */ 907 adapter->hw.mac.max_frame_size = 908 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 909 910 /* 911 * This controls when hardware reports transmit completion 912 * status. 913 */ 914 hw->mac.report_tx_early = 1; 915 916 /* Allocate multicast array memory. */ 917 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 918 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 919 if (adapter->mta == NULL) { 920 device_printf(dev, "Can not allocate multicast setup array\n"); 921 error = ENOMEM; 922 goto err_late; 923 } 924 925 /* Check SOL/IDER usage */ 926 if (e1000_check_reset_block(hw)) 927 device_printf(dev, "PHY reset is blocked" 928 " due to SOL/IDER session.\n"); 929 930 /* Sysctl for setting Energy Efficient Ethernet */ 931 hw->dev_spec.ich8lan.eee_disable = eee_setting; 932 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 933 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 934 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 935 adapter, 0, em_sysctl_eee, "I", 936 "Disable Energy Efficient Ethernet"); 937 938 /* 939 ** Start from a known state, this is 940 ** important in reading the nvm and 941 ** mac from that. 942 */ 943 e1000_reset_hw(hw); 944 945 /* Make sure we have a good EEPROM before we read from it */ 946 if (e1000_validate_nvm_checksum(hw) < 0) { 947 /* 948 ** Some PCI-E parts fail the first check due to 949 ** the link being in sleep state, call it again, 950 ** if it fails a second time its a real issue. 951 */ 952 if (e1000_validate_nvm_checksum(hw) < 0) { 953 device_printf(dev, 954 "The EEPROM Checksum Is Not Valid\n"); 955 error = EIO; 956 goto err_late; 957 } 958 } 959 960 /* Copy the permanent MAC address out of the EEPROM */ 961 if (e1000_read_mac_addr(hw) < 0) { 962 device_printf(dev, "EEPROM read error while reading MAC" 963 " address\n"); 964 error = EIO; 965 goto err_late; 966 } 967 968 if (!em_is_valid_ether_addr(hw->mac.addr)) { 969 device_printf(dev, "Invalid MAC address\n"); 970 error = EIO; 971 goto err_late; 972 } 973 974 /* Disable ULP support */ 975 e1000_disable_ulp_lpt_lp(hw, TRUE); 976 977 /* 978 * Get Wake-on-Lan and Management info for later use 979 */ 980 em_get_wakeup(ctx); 981 982 iflib_set_mac(ctx, hw->mac.addr); 983 984 return (0); 985 986 err_late: 987 em_release_hw_control(adapter); 988 err_pci: 989 em_free_pci_resources(ctx); 990 free(adapter->mta, M_DEVBUF); 991 992 return (error); 993 } 994 995 static int 996 em_if_attach_post(if_ctx_t ctx) 997 { 998 struct adapter *adapter = iflib_get_softc(ctx); 999 struct e1000_hw *hw = &adapter->hw; 1000 int error = 0; 1001 1002 /* Setup OS specific network interface */ 1003 error = em_setup_interface(ctx); 1004 if (error != 0) { 1005 goto err_late; 1006 } 1007 1008 em_reset(ctx); 1009 1010 /* Initialize statistics */ 1011 em_update_stats_counters(adapter); 1012 hw->mac.get_link_status = 1; 1013 em_if_update_admin_status(ctx); 1014 em_add_hw_stats(adapter); 1015 1016 /* Non-AMT based hardware can now take control from firmware */ 1017 if (adapter->has_manage && !adapter->has_amt) 1018 em_get_hw_control(adapter); 1019 1020 INIT_DEBUGOUT("em_if_attach_post: end"); 1021 1022 return (error); 1023 1024 err_late: 1025 em_release_hw_control(adapter); 1026 em_free_pci_resources(ctx); 1027 em_if_queues_free(ctx); 1028 free(adapter->mta, M_DEVBUF); 1029 1030 return (error); 1031 } 1032 1033 /********************************************************************* 1034 * Device removal routine 1035 * 1036 * The detach entry point is called when the driver is being removed. 1037 * This routine stops the adapter and deallocates all the resources 1038 * that were allocated for driver operation. 1039 * 1040 * return 0 on success, positive on failure 1041 *********************************************************************/ 1042 1043 static int 1044 em_if_detach(if_ctx_t ctx) 1045 { 1046 struct adapter *adapter = iflib_get_softc(ctx); 1047 1048 INIT_DEBUGOUT("em_detach: begin"); 1049 1050 e1000_phy_hw_reset(&adapter->hw); 1051 1052 em_release_manageability(adapter); 1053 em_release_hw_control(adapter); 1054 em_free_pci_resources(ctx); 1055 1056 return (0); 1057 } 1058 1059 /********************************************************************* 1060 * 1061 * Shutdown entry point 1062 * 1063 **********************************************************************/ 1064 1065 static int 1066 em_if_shutdown(if_ctx_t ctx) 1067 { 1068 return em_if_suspend(ctx); 1069 } 1070 1071 /* 1072 * Suspend/resume device methods. 1073 */ 1074 static int 1075 em_if_suspend(if_ctx_t ctx) 1076 { 1077 struct adapter *adapter = iflib_get_softc(ctx); 1078 1079 em_release_manageability(adapter); 1080 em_release_hw_control(adapter); 1081 em_enable_wakeup(ctx); 1082 return (0); 1083 } 1084 1085 static int 1086 em_if_resume(if_ctx_t ctx) 1087 { 1088 struct adapter *adapter = iflib_get_softc(ctx); 1089 1090 if (adapter->hw.mac.type == e1000_pch2lan) 1091 e1000_resume_workarounds_pchlan(&adapter->hw); 1092 em_if_init(ctx); 1093 em_init_manageability(adapter); 1094 1095 return(0); 1096 } 1097 1098 static int 1099 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1100 { 1101 int max_frame_size; 1102 struct adapter *adapter = iflib_get_softc(ctx); 1103 struct ifnet *ifp = iflib_get_ifp(ctx); 1104 1105 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1106 1107 switch (adapter->hw.mac.type) { 1108 case e1000_82571: 1109 case e1000_82572: 1110 case e1000_ich9lan: 1111 case e1000_ich10lan: 1112 case e1000_pch2lan: 1113 case e1000_pch_lpt: 1114 case e1000_pch_spt: 1115 case e1000_82574: 1116 case e1000_82583: 1117 case e1000_80003es2lan: /* 9K Jumbo Frame size */ 1118 max_frame_size = 9234; 1119 break; 1120 case e1000_pchlan: 1121 max_frame_size = 4096; 1122 break; 1123 /* Adapters that do not support jumbo frames */ 1124 case e1000_ich8lan: 1125 max_frame_size = ETHER_MAX_LEN; 1126 break; 1127 default: 1128 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1129 } 1130 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1131 return (EINVAL); 1132 } 1133 1134 adapter->hw.mac.max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN; 1135 return (0); 1136 } 1137 1138 /********************************************************************* 1139 * Init entry point 1140 * 1141 * This routine is used in two ways. It is used by the stack as 1142 * init entry point in network interface structure. It is also used 1143 * by the driver as a hw/sw initialization routine to get to a 1144 * consistent state. 1145 * 1146 * return 0 on success, positive on failure 1147 **********************************************************************/ 1148 1149 static void 1150 em_if_init(if_ctx_t ctx) 1151 { 1152 struct adapter *adapter = iflib_get_softc(ctx); 1153 struct ifnet *ifp = iflib_get_ifp(ctx); 1154 1155 INIT_DEBUGOUT("em_if_init: begin"); 1156 1157 /* Get the latest mac address, User can use a LAA */ 1158 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1159 ETHER_ADDR_LEN); 1160 1161 /* Put the address into the Receive Address Array */ 1162 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1163 1164 /* 1165 * With the 82571 adapter, RAR[0] may be overwritten 1166 * when the other port is reset, we make a duplicate 1167 * in RAR[14] for that eventuality, this assures 1168 * the interface continues to function. 1169 */ 1170 if (adapter->hw.mac.type == e1000_82571) { 1171 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1172 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1173 E1000_RAR_ENTRIES - 1); 1174 } 1175 1176 /* Initialize the hardware */ 1177 em_reset(ctx); 1178 em_if_update_admin_status(ctx); 1179 1180 /* Setup VLAN support, basic and offload if available */ 1181 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1182 1183 /* Clear bad data from Rx FIFOs */ 1184 if (adapter->hw.mac.type >= igb_mac_min) 1185 e1000_rx_fifo_flush_82575(&adapter->hw); 1186 1187 /* Configure for OS presence */ 1188 em_init_manageability(adapter); 1189 1190 /* Prepare transmit descriptors and buffers */ 1191 em_initialize_transmit_unit(ctx); 1192 1193 /* Setup Multicast table */ 1194 em_if_multi_set(ctx); 1195 1196 /* 1197 ** Figure out the desired mbuf 1198 ** pool for doing jumbos 1199 */ 1200 if (adapter->hw.mac.max_frame_size <= 2048) 1201 adapter->rx_mbuf_sz = MCLBYTES; 1202 else if (adapter->hw.mac.max_frame_size <= 4096) 1203 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1204 else 1205 adapter->rx_mbuf_sz = MJUM9BYTES; 1206 1207 em_initialize_receive_unit(ctx); 1208 1209 /* Use real VLAN Filter support? */ 1210 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1211 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1212 /* Use real VLAN Filter support */ 1213 em_setup_vlan_hw_support(adapter); 1214 else { 1215 u32 ctrl; 1216 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1217 ctrl |= E1000_CTRL_VME; 1218 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1219 } 1220 } 1221 1222 /* Don't lose promiscuous settings */ 1223 em_if_set_promisc(ctx, IFF_PROMISC); 1224 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1225 1226 /* MSI/X configuration for 82574 */ 1227 if (adapter->hw.mac.type == e1000_82574) { 1228 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1229 1230 tmp |= E1000_CTRL_EXT_PBA_CLR; 1231 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1232 /* Set the IVAR - interrupt vector routing. */ 1233 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1234 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1235 igb_configure_queues(adapter); 1236 1237 /* this clears any pending interrupts */ 1238 E1000_READ_REG(&adapter->hw, E1000_ICR); 1239 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1240 1241 /* AMT based hardware can now take control from firmware */ 1242 if (adapter->has_manage && adapter->has_amt) 1243 em_get_hw_control(adapter); 1244 1245 /* Set Energy Efficient Ethernet */ 1246 if (adapter->hw.mac.type >= igb_mac_min && 1247 adapter->hw.phy.media_type == e1000_media_type_copper) { 1248 if (adapter->hw.mac.type == e1000_i354) 1249 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1250 else 1251 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1252 } 1253 } 1254 1255 /********************************************************************* 1256 * 1257 * Fast Legacy/MSI Combined Interrupt Service routine 1258 * 1259 *********************************************************************/ 1260 int 1261 em_intr(void *arg) 1262 { 1263 struct adapter *adapter = arg; 1264 if_ctx_t ctx = adapter->ctx; 1265 u32 reg_icr; 1266 1267 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1268 1269 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1270 goto skip_stray; 1271 /* Hot eject? */ 1272 if (reg_icr == 0xffffffff) 1273 return FILTER_STRAY; 1274 1275 /* Definitely not our interrupt. */ 1276 if (reg_icr == 0x0) 1277 return FILTER_STRAY; 1278 1279 /* 1280 * Starting with the 82571 chip, bit 31 should be used to 1281 * determine whether the interrupt belongs to us. 1282 */ 1283 if (adapter->hw.mac.type >= e1000_82571 && 1284 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1285 return FILTER_STRAY; 1286 1287 skip_stray: 1288 /* Link status change */ 1289 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1290 adapter->hw.mac.get_link_status = 1; 1291 iflib_admin_intr_deferred(ctx); 1292 } 1293 1294 if (reg_icr & E1000_ICR_RXO) 1295 adapter->rx_overruns++; 1296 1297 return (FILTER_SCHEDULE_THREAD); 1298 } 1299 1300 static void 1301 igb_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1302 { 1303 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1304 } 1305 1306 static void 1307 em_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1308 { 1309 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1310 } 1311 1312 static int 1313 em_if_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1314 { 1315 struct adapter *adapter = iflib_get_softc(ctx); 1316 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1317 1318 if (adapter->hw.mac.type >= igb_mac_min) 1319 igb_enable_queue(adapter, rxq); 1320 else 1321 em_enable_queue(adapter, rxq); 1322 return (0); 1323 } 1324 1325 /********************************************************************* 1326 * 1327 * MSIX RX Interrupt Service routine 1328 * 1329 **********************************************************************/ 1330 static int 1331 em_msix_que(void *arg) 1332 { 1333 struct em_rx_queue *que = arg; 1334 1335 ++que->irqs; 1336 1337 return (FILTER_SCHEDULE_THREAD); 1338 } 1339 1340 /********************************************************************* 1341 * 1342 * MSIX Link Fast Interrupt Service routine 1343 * 1344 **********************************************************************/ 1345 static int 1346 em_msix_link(void *arg) 1347 { 1348 struct adapter *adapter = arg; 1349 u32 reg_icr; 1350 1351 ++adapter->link_irq; 1352 MPASS(adapter->hw.back != NULL); 1353 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1354 1355 if (reg_icr & E1000_ICR_RXO) 1356 adapter->rx_overruns++; 1357 1358 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1359 em_handle_link(adapter->ctx); 1360 } else { 1361 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1362 EM_MSIX_LINK | E1000_IMS_LSC); 1363 if (adapter->hw.mac.type >= igb_mac_min) 1364 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1365 1366 } 1367 1368 /* 1369 ** Because we must read the ICR for this interrupt 1370 ** it may clear other causes using autoclear, for 1371 ** this reason we simply create a soft interrupt 1372 ** for all these vectors. 1373 */ 1374 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1375 E1000_WRITE_REG(&adapter->hw, 1376 E1000_ICS, adapter->ims); 1377 } 1378 1379 return (FILTER_HANDLED); 1380 } 1381 1382 static void 1383 em_handle_link(void *context) 1384 { 1385 if_ctx_t ctx = context; 1386 struct adapter *adapter = iflib_get_softc(ctx); 1387 1388 adapter->hw.mac.get_link_status = 1; 1389 iflib_admin_intr_deferred(ctx); 1390 } 1391 1392 1393 /********************************************************************* 1394 * 1395 * Media Ioctl callback 1396 * 1397 * This routine is called whenever the user queries the status of 1398 * the interface using ifconfig. 1399 * 1400 **********************************************************************/ 1401 static void 1402 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1403 { 1404 struct adapter *adapter = iflib_get_softc(ctx); 1405 u_char fiber_type = IFM_1000_SX; 1406 1407 INIT_DEBUGOUT("em_if_media_status: begin"); 1408 1409 iflib_admin_intr_deferred(ctx); 1410 1411 ifmr->ifm_status = IFM_AVALID; 1412 ifmr->ifm_active = IFM_ETHER; 1413 1414 if (!adapter->link_active) { 1415 return; 1416 } 1417 1418 ifmr->ifm_status |= IFM_ACTIVE; 1419 1420 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1421 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1422 if (adapter->hw.mac.type == e1000_82545) 1423 fiber_type = IFM_1000_LX; 1424 ifmr->ifm_active |= fiber_type | IFM_FDX; 1425 } else { 1426 switch (adapter->link_speed) { 1427 case 10: 1428 ifmr->ifm_active |= IFM_10_T; 1429 break; 1430 case 100: 1431 ifmr->ifm_active |= IFM_100_TX; 1432 break; 1433 case 1000: 1434 ifmr->ifm_active |= IFM_1000_T; 1435 break; 1436 } 1437 if (adapter->link_duplex == FULL_DUPLEX) 1438 ifmr->ifm_active |= IFM_FDX; 1439 else 1440 ifmr->ifm_active |= IFM_HDX; 1441 } 1442 } 1443 1444 /********************************************************************* 1445 * 1446 * Media Ioctl callback 1447 * 1448 * This routine is called when the user changes speed/duplex using 1449 * media/mediopt option with ifconfig. 1450 * 1451 **********************************************************************/ 1452 static int 1453 em_if_media_change(if_ctx_t ctx) 1454 { 1455 struct adapter *adapter = iflib_get_softc(ctx); 1456 struct ifmedia *ifm = iflib_get_media(ctx); 1457 1458 INIT_DEBUGOUT("em_if_media_change: begin"); 1459 1460 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1461 return (EINVAL); 1462 1463 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1464 case IFM_AUTO: 1465 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1466 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1467 break; 1468 case IFM_1000_LX: 1469 case IFM_1000_SX: 1470 case IFM_1000_T: 1471 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1472 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1473 break; 1474 case IFM_100_TX: 1475 adapter->hw.mac.autoneg = FALSE; 1476 adapter->hw.phy.autoneg_advertised = 0; 1477 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1478 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1479 else 1480 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1481 break; 1482 case IFM_10_T: 1483 adapter->hw.mac.autoneg = FALSE; 1484 adapter->hw.phy.autoneg_advertised = 0; 1485 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1486 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1487 else 1488 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1489 break; 1490 default: 1491 device_printf(adapter->dev, "Unsupported media type\n"); 1492 } 1493 1494 em_if_init(ctx); 1495 1496 return (0); 1497 } 1498 1499 static int 1500 em_if_set_promisc(if_ctx_t ctx, int flags) 1501 { 1502 struct adapter *adapter = iflib_get_softc(ctx); 1503 u32 reg_rctl; 1504 1505 em_disable_promisc(ctx); 1506 1507 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1508 1509 if (flags & IFF_PROMISC) { 1510 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1511 /* Turn this on if you want to see bad packets */ 1512 if (em_debug_sbp) 1513 reg_rctl |= E1000_RCTL_SBP; 1514 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1515 } else if (flags & IFF_ALLMULTI) { 1516 reg_rctl |= E1000_RCTL_MPE; 1517 reg_rctl &= ~E1000_RCTL_UPE; 1518 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1519 } 1520 return (0); 1521 } 1522 1523 static void 1524 em_disable_promisc(if_ctx_t ctx) 1525 { 1526 struct adapter *adapter = iflib_get_softc(ctx); 1527 struct ifnet *ifp = iflib_get_ifp(ctx); 1528 u32 reg_rctl; 1529 int mcnt = 0; 1530 1531 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1532 reg_rctl &= (~E1000_RCTL_UPE); 1533 if (if_getflags(ifp) & IFF_ALLMULTI) 1534 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1535 else 1536 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1537 /* Don't disable if in MAX groups */ 1538 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1539 reg_rctl &= (~E1000_RCTL_MPE); 1540 reg_rctl &= (~E1000_RCTL_SBP); 1541 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1542 } 1543 1544 1545 /********************************************************************* 1546 * Multicast Update 1547 * 1548 * This routine is called whenever multicast address list is updated. 1549 * 1550 **********************************************************************/ 1551 1552 static void 1553 em_if_multi_set(if_ctx_t ctx) 1554 { 1555 struct adapter *adapter = iflib_get_softc(ctx); 1556 struct ifnet *ifp = iflib_get_ifp(ctx); 1557 u32 reg_rctl = 0; 1558 u8 *mta; /* Multicast array memory */ 1559 int mcnt = 0; 1560 1561 IOCTL_DEBUGOUT("em_set_multi: begin"); 1562 1563 mta = adapter->mta; 1564 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1565 1566 if (adapter->hw.mac.type == e1000_82542 && 1567 adapter->hw.revision_id == E1000_REVISION_2) { 1568 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1569 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1570 e1000_pci_clear_mwi(&adapter->hw); 1571 reg_rctl |= E1000_RCTL_RST; 1572 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1573 msec_delay(5); 1574 } 1575 1576 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1577 1578 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1579 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1580 reg_rctl |= E1000_RCTL_MPE; 1581 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1582 } else 1583 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1584 1585 if (adapter->hw.mac.type == e1000_82542 && 1586 adapter->hw.revision_id == E1000_REVISION_2) { 1587 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1588 reg_rctl &= ~E1000_RCTL_RST; 1589 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1590 msec_delay(5); 1591 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1592 e1000_pci_set_mwi(&adapter->hw); 1593 } 1594 } 1595 1596 1597 /********************************************************************* 1598 * Timer routine 1599 * 1600 * This routine checks for link status and updates statistics. 1601 * 1602 **********************************************************************/ 1603 1604 static void 1605 em_if_timer(if_ctx_t ctx, uint16_t qid) 1606 { 1607 struct adapter *adapter = iflib_get_softc(ctx); 1608 struct em_rx_queue *que; 1609 int i; 1610 int trigger = 0; 1611 1612 em_if_update_admin_status(ctx); 1613 em_update_stats_counters(adapter); 1614 1615 /* Reset LAA into RAR[0] on 82571 */ 1616 if ((adapter->hw.mac.type == e1000_82571) && 1617 e1000_get_laa_state_82571(&adapter->hw)) 1618 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1619 1620 if (adapter->hw.mac.type < em_mac_min) 1621 lem_smartspeed(adapter); 1622 1623 /* Mask to use in the irq trigger */ 1624 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1625 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1626 trigger |= que->eims; 1627 } else { 1628 trigger = E1000_ICS_RXDMT0; 1629 } 1630 } 1631 1632 1633 static void 1634 em_if_update_admin_status(if_ctx_t ctx) 1635 { 1636 struct adapter *adapter = iflib_get_softc(ctx); 1637 struct e1000_hw *hw = &adapter->hw; 1638 struct ifnet *ifp = iflib_get_ifp(ctx); 1639 device_t dev = iflib_get_dev(ctx); 1640 u32 link_check = 0; 1641 1642 /* Get the cached link value or read phy for real */ 1643 switch (hw->phy.media_type) { 1644 case e1000_media_type_copper: 1645 if (hw->mac.get_link_status) { 1646 if (hw->mac.type == e1000_pch_spt) 1647 msec_delay(50); 1648 /* Do the work to read phy */ 1649 e1000_check_for_link(hw); 1650 link_check = !hw->mac.get_link_status; 1651 if (link_check) /* ESB2 fix */ 1652 e1000_cfg_on_link_up(hw); 1653 } else { 1654 link_check = TRUE; 1655 } 1656 break; 1657 case e1000_media_type_fiber: 1658 e1000_check_for_link(hw); 1659 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1660 E1000_STATUS_LU); 1661 break; 1662 case e1000_media_type_internal_serdes: 1663 e1000_check_for_link(hw); 1664 link_check = adapter->hw.mac.serdes_has_link; 1665 break; 1666 default: 1667 case e1000_media_type_unknown: 1668 break; 1669 } 1670 1671 /* Now check for a transition */ 1672 if (link_check && (adapter->link_active == 0)) { 1673 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1674 &adapter->link_duplex); 1675 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1676 if ((adapter->link_speed != SPEED_1000) && 1677 ((hw->mac.type == e1000_82571) || 1678 (hw->mac.type == e1000_82572))) { 1679 int tarc0; 1680 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1681 tarc0 &= ~TARC_SPEED_MODE_BIT; 1682 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1683 } 1684 if (bootverbose) 1685 device_printf(dev, "Link is up %d Mbps %s\n", 1686 adapter->link_speed, 1687 ((adapter->link_duplex == FULL_DUPLEX) ? 1688 "Full Duplex" : "Half Duplex")); 1689 adapter->link_active = 1; 1690 adapter->smartspeed = 0; 1691 if_setbaudrate(ifp, adapter->link_speed * 1000000); 1692 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate); 1693 printf("Link state changed to up\n"); 1694 } else if (!link_check && (adapter->link_active == 1)) { 1695 if_setbaudrate(ifp, 0); 1696 adapter->link_speed = 0; 1697 adapter->link_duplex = 0; 1698 if (bootverbose) 1699 device_printf(dev, "Link is Down\n"); 1700 adapter->link_active = 0; 1701 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate); 1702 printf("link state changed to down\n"); 1703 } 1704 1705 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1706 } 1707 1708 /********************************************************************* 1709 * 1710 * This routine disables all traffic on the adapter by issuing a 1711 * global reset on the MAC and deallocates TX/RX buffers. 1712 * 1713 * This routine should always be called with BOTH the CORE 1714 * and TX locks. 1715 **********************************************************************/ 1716 1717 static void 1718 em_if_stop(if_ctx_t ctx) 1719 { 1720 struct adapter *adapter = iflib_get_softc(ctx); 1721 1722 INIT_DEBUGOUT("em_stop: begin"); 1723 1724 e1000_reset_hw(&adapter->hw); 1725 if (adapter->hw.mac.type >= e1000_82544) 1726 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 1727 1728 e1000_led_off(&adapter->hw); 1729 e1000_cleanup_led(&adapter->hw); 1730 } 1731 1732 1733 /********************************************************************* 1734 * 1735 * Determine hardware revision. 1736 * 1737 **********************************************************************/ 1738 static void 1739 em_identify_hardware(if_ctx_t ctx) 1740 { 1741 device_t dev = iflib_get_dev(ctx); 1742 struct adapter *adapter = iflib_get_softc(ctx); 1743 1744 /* Make sure our PCI config space has the necessary stuff set */ 1745 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1746 1747 /* Save off the information about this board */ 1748 adapter->hw.vendor_id = pci_get_vendor(dev); 1749 adapter->hw.device_id = pci_get_device(dev); 1750 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1751 adapter->hw.subsystem_vendor_id = 1752 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1753 adapter->hw.subsystem_device_id = 1754 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1755 1756 /* Do Shared Code Init and Setup */ 1757 if (e1000_set_mac_type(&adapter->hw)) { 1758 device_printf(dev, "Setup init failure\n"); 1759 return; 1760 } 1761 } 1762 1763 static int 1764 em_allocate_pci_resources(if_ctx_t ctx) 1765 { 1766 struct adapter *adapter = iflib_get_softc(ctx); 1767 device_t dev = iflib_get_dev(ctx); 1768 int rid, val; 1769 1770 rid = PCIR_BAR(0); 1771 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1772 &rid, RF_ACTIVE); 1773 if (adapter->memory == NULL) { 1774 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1775 return (ENXIO); 1776 } 1777 adapter->osdep.mem_bus_space_tag = 1778 rman_get_bustag(adapter->memory); 1779 adapter->osdep.mem_bus_space_handle = 1780 rman_get_bushandle(adapter->memory); 1781 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1782 1783 /* Only older adapters use IO mapping */ 1784 if (adapter->hw.mac.type < em_mac_min && 1785 adapter->hw.mac.type > e1000_82543) { 1786 /* Figure our where our IO BAR is ? */ 1787 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1788 val = pci_read_config(dev, rid, 4); 1789 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1790 adapter->io_rid = rid; 1791 break; 1792 } 1793 rid += 4; 1794 /* check for 64bit BAR */ 1795 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1796 rid += 4; 1797 } 1798 if (rid >= PCIR_CIS) { 1799 device_printf(dev, "Unable to locate IO BAR\n"); 1800 return (ENXIO); 1801 } 1802 adapter->ioport = bus_alloc_resource_any(dev, 1803 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1804 if (adapter->ioport == NULL) { 1805 device_printf(dev, "Unable to allocate bus resource: " 1806 "ioport\n"); 1807 return (ENXIO); 1808 } 1809 adapter->hw.io_base = 0; 1810 adapter->osdep.io_bus_space_tag = 1811 rman_get_bustag(adapter->ioport); 1812 adapter->osdep.io_bus_space_handle = 1813 rman_get_bushandle(adapter->ioport); 1814 } 1815 1816 adapter->hw.back = &adapter->osdep; 1817 1818 return (0); 1819 } 1820 1821 /********************************************************************* 1822 * 1823 * Setup the MSIX Interrupt handlers 1824 * 1825 **********************************************************************/ 1826 static int 1827 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1828 { 1829 struct adapter *adapter = iflib_get_softc(ctx); 1830 struct em_rx_queue *rx_que = adapter->rx_queues; 1831 struct em_tx_queue *tx_que = adapter->tx_queues; 1832 int error, rid, i, vector = 0; 1833 char buf[16]; 1834 1835 /* First set up ring resources */ 1836 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1837 rid = vector +1; 1838 snprintf(buf, sizeof(buf), "rxq%d", i); 1839 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RX, em_msix_que, rx_que, rx_que->me, buf); 1840 if (error) { 1841 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1842 adapter->rx_num_queues = i + 1; 1843 goto fail; 1844 } 1845 1846 rx_que->msix = vector; 1847 1848 /* 1849 ** Set the bit to enable interrupt 1850 ** in E1000_IMS -- bits 20 and 21 1851 ** are for RX0 and RX1, note this has 1852 ** NOTHING to do with the MSIX vector 1853 */ 1854 if (adapter->hw.mac.type == e1000_82574) { 1855 rx_que->eims = 1 << (20 + i); 1856 adapter->ims |= rx_que->eims; 1857 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1858 } else if (adapter->hw.mac.type == e1000_82575) 1859 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1860 else 1861 rx_que->eims = 1 << vector; 1862 } 1863 1864 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 1865 rid = vector + 1; 1866 snprintf(buf, sizeof(buf), "txq%d", i); 1867 tx_que = &adapter->tx_queues[i]; 1868 iflib_softirq_alloc_generic(ctx, rid, IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1869 1870 tx_que->msix = vector; 1871 1872 /* 1873 ** Set the bit to enable interrupt 1874 ** in E1000_IMS -- bits 22 and 23 1875 ** are for TX0 and TX1, note this has 1876 ** NOTHING to do with the MSIX vector 1877 */ 1878 if (adapter->hw.mac.type < igb_mac_min) { 1879 tx_que->eims = 1 << (22 + i); 1880 adapter->ims |= tx_que->eims; 1881 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1882 } if (adapter->hw.mac.type == e1000_82575) 1883 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 1884 else 1885 tx_que->eims = 1 << (i % adapter->tx_num_queues); 1886 } 1887 1888 /* Link interrupt */ 1889 rid = vector + 1; 1890 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 1891 1892 if (error) { 1893 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1894 goto fail; 1895 } 1896 adapter->linkvec = vector; 1897 if (adapter->hw.mac.type < igb_mac_min) { 1898 adapter->ivars |= (8 | vector) << 16; 1899 adapter->ivars |= 0x80000000; 1900 } 1901 return (0); 1902 fail: 1903 iflib_irq_free(ctx, &adapter->irq); 1904 rx_que = adapter->rx_queues; 1905 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1906 iflib_irq_free(ctx, &rx_que->que_irq); 1907 return (error); 1908 } 1909 1910 static void 1911 igb_configure_queues(struct adapter *adapter) 1912 { 1913 struct e1000_hw *hw = &adapter->hw; 1914 struct em_rx_queue *rx_que; 1915 struct em_tx_queue *tx_que; 1916 u32 tmp, ivar = 0, newitr = 0; 1917 1918 /* First turn on RSS capability */ 1919 if (adapter->hw.mac.type != e1000_82575) 1920 E1000_WRITE_REG(hw, E1000_GPIE, 1921 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 1922 E1000_GPIE_PBA | E1000_GPIE_NSICR); 1923 1924 /* Turn on MSIX */ 1925 switch (adapter->hw.mac.type) { 1926 case e1000_82580: 1927 case e1000_i350: 1928 case e1000_i354: 1929 case e1000_i210: 1930 case e1000_i211: 1931 case e1000_vfadapt: 1932 case e1000_vfadapt_i350: 1933 /* RX entries */ 1934 for (int i = 0; i < adapter->rx_num_queues; i++) { 1935 u32 index = i >> 1; 1936 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 1937 rx_que = &adapter->rx_queues[i]; 1938 if (i & 1) { 1939 ivar &= 0xFF00FFFF; 1940 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 1941 } else { 1942 ivar &= 0xFFFFFF00; 1943 ivar |= rx_que->msix | E1000_IVAR_VALID; 1944 } 1945 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 1946 } 1947 /* TX entries */ 1948 for (int i = 0; i < adapter->tx_num_queues; i++) { 1949 u32 index = i >> 1; 1950 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 1951 tx_que = &adapter->tx_queues[i]; 1952 if (i & 1) { 1953 ivar &= 0x00FFFFFF; 1954 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 1955 } else { 1956 ivar &= 0xFFFF00FF; 1957 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 1958 } 1959 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 1960 adapter->que_mask |= tx_que->eims; 1961 } 1962 1963 /* And for the link interrupt */ 1964 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 1965 adapter->link_mask = 1 << adapter->linkvec; 1966 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 1967 break; 1968 case e1000_82576: 1969 /* RX entries */ 1970 for (int i = 0; i < adapter->rx_num_queues; i++) { 1971 u32 index = i & 0x7; /* Each IVAR has two entries */ 1972 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 1973 rx_que = &adapter->rx_queues[i]; 1974 if (i < 8) { 1975 ivar &= 0xFFFFFF00; 1976 ivar |= rx_que->msix | E1000_IVAR_VALID; 1977 } else { 1978 ivar &= 0xFF00FFFF; 1979 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 1980 } 1981 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 1982 adapter->que_mask |= rx_que->eims; 1983 } 1984 /* TX entries */ 1985 for (int i = 0; i < adapter->tx_num_queues; i++) { 1986 u32 index = i & 0x7; /* Each IVAR has two entries */ 1987 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 1988 tx_que = &adapter->tx_queues[i]; 1989 if (i < 8) { 1990 ivar &= 0xFFFF00FF; 1991 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 1992 } else { 1993 ivar &= 0x00FFFFFF; 1994 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 1995 } 1996 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 1997 adapter->que_mask |= tx_que->eims; 1998 } 1999 2000 /* And for the link interrupt */ 2001 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2002 adapter->link_mask = 1 << adapter->linkvec; 2003 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2004 break; 2005 2006 case e1000_82575: 2007 /* enable MSI-X support*/ 2008 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2009 tmp |= E1000_CTRL_EXT_PBA_CLR; 2010 /* Auto-Mask interrupts upon ICR read. */ 2011 tmp |= E1000_CTRL_EXT_EIAME; 2012 tmp |= E1000_CTRL_EXT_IRCA; 2013 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2014 2015 /* Queues */ 2016 for (int i = 0; i < adapter->rx_num_queues; i++) { 2017 rx_que = &adapter->rx_queues[i]; 2018 tmp = E1000_EICR_RX_QUEUE0 << i; 2019 tmp |= E1000_EICR_TX_QUEUE0 << i; 2020 rx_que->eims = tmp; 2021 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2022 i, rx_que->eims); 2023 adapter->que_mask |= rx_que->eims; 2024 } 2025 2026 /* Link */ 2027 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2028 E1000_EIMS_OTHER); 2029 adapter->link_mask |= E1000_EIMS_OTHER; 2030 default: 2031 break; 2032 } 2033 2034 /* Set the starting interrupt rate */ 2035 if (em_max_interrupt_rate > 0) 2036 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2037 2038 if (hw->mac.type == e1000_82575) 2039 newitr |= newitr << 16; 2040 else 2041 newitr |= E1000_EITR_CNT_IGNR; 2042 2043 for (int i = 0; i < adapter->rx_num_queues; i++) { 2044 rx_que = &adapter->rx_queues[i]; 2045 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2046 } 2047 2048 return; 2049 } 2050 2051 static void 2052 em_free_pci_resources(if_ctx_t ctx) 2053 { 2054 struct adapter *adapter = iflib_get_softc(ctx); 2055 struct em_rx_queue *que = adapter->rx_queues; 2056 device_t dev = iflib_get_dev(ctx); 2057 2058 /* Release all msix queue resources */ 2059 if (adapter->intr_type == IFLIB_INTR_MSIX) 2060 iflib_irq_free(ctx, &adapter->irq); 2061 2062 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2063 iflib_irq_free(ctx, &que->que_irq); 2064 } 2065 2066 2067 /* First release all the interrupt resources */ 2068 if (adapter->memory != NULL) { 2069 bus_release_resource(dev, SYS_RES_MEMORY, 2070 PCIR_BAR(0), adapter->memory); 2071 adapter->memory = NULL; 2072 } 2073 2074 if (adapter->flash != NULL) { 2075 bus_release_resource(dev, SYS_RES_MEMORY, 2076 EM_FLASH, adapter->flash); 2077 adapter->flash = NULL; 2078 } 2079 if (adapter->ioport != NULL) 2080 bus_release_resource(dev, SYS_RES_IOPORT, 2081 adapter->io_rid, adapter->ioport); 2082 } 2083 2084 /* Setup MSI or MSI/X */ 2085 static int 2086 em_setup_msix(if_ctx_t ctx) 2087 { 2088 struct adapter *adapter = iflib_get_softc(ctx); 2089 2090 if (adapter->hw.mac.type == e1000_82574) { 2091 em_enable_vectors_82574(ctx); 2092 } 2093 return (0); 2094 } 2095 2096 /********************************************************************* 2097 * 2098 * Initialize the hardware to a configuration 2099 * as specified by the adapter structure. 2100 * 2101 **********************************************************************/ 2102 2103 static void 2104 lem_smartspeed(struct adapter *adapter) 2105 { 2106 u16 phy_tmp; 2107 2108 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2109 adapter->hw.mac.autoneg == 0 || 2110 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2111 return; 2112 2113 if (adapter->smartspeed == 0) { 2114 /* If Master/Slave config fault is asserted twice, 2115 * we assume back-to-back */ 2116 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2117 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2118 return; 2119 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2120 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2121 e1000_read_phy_reg(&adapter->hw, 2122 PHY_1000T_CTRL, &phy_tmp); 2123 if(phy_tmp & CR_1000T_MS_ENABLE) { 2124 phy_tmp &= ~CR_1000T_MS_ENABLE; 2125 e1000_write_phy_reg(&adapter->hw, 2126 PHY_1000T_CTRL, phy_tmp); 2127 adapter->smartspeed++; 2128 if(adapter->hw.mac.autoneg && 2129 !e1000_copper_link_autoneg(&adapter->hw) && 2130 !e1000_read_phy_reg(&adapter->hw, 2131 PHY_CONTROL, &phy_tmp)) { 2132 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2133 MII_CR_RESTART_AUTO_NEG); 2134 e1000_write_phy_reg(&adapter->hw, 2135 PHY_CONTROL, phy_tmp); 2136 } 2137 } 2138 } 2139 return; 2140 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2141 /* If still no link, perhaps using 2/3 pair cable */ 2142 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2143 phy_tmp |= CR_1000T_MS_ENABLE; 2144 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2145 if(adapter->hw.mac.autoneg && 2146 !e1000_copper_link_autoneg(&adapter->hw) && 2147 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2148 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2149 MII_CR_RESTART_AUTO_NEG); 2150 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2151 } 2152 } 2153 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2154 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2155 adapter->smartspeed = 0; 2156 } 2157 2158 2159 static void 2160 em_reset(if_ctx_t ctx) 2161 { 2162 device_t dev = iflib_get_dev(ctx); 2163 struct adapter *adapter = iflib_get_softc(ctx); 2164 struct ifnet *ifp = iflib_get_ifp(ctx); 2165 struct e1000_hw *hw = &adapter->hw; 2166 u16 rx_buffer_size; 2167 u32 pba; 2168 2169 INIT_DEBUGOUT("em_reset: begin"); 2170 2171 /* Set up smart power down as default off on newer adapters. */ 2172 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2173 hw->mac.type == e1000_82572)) { 2174 u16 phy_tmp = 0; 2175 2176 /* Speed up time to link by disabling smart power down. */ 2177 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2178 phy_tmp &= ~IGP02E1000_PM_SPD; 2179 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2180 } 2181 2182 /* 2183 * Packet Buffer Allocation (PBA) 2184 * Writing PBA sets the receive portion of the buffer 2185 * the remainder is used for the transmit buffer. 2186 */ 2187 switch (hw->mac.type) { 2188 /* Total Packet Buffer on these is 48K */ 2189 case e1000_82571: 2190 case e1000_82572: 2191 case e1000_80003es2lan: 2192 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2193 break; 2194 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2195 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2196 break; 2197 case e1000_82574: 2198 case e1000_82583: 2199 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2200 break; 2201 case e1000_ich8lan: 2202 pba = E1000_PBA_8K; 2203 break; 2204 case e1000_ich9lan: 2205 case e1000_ich10lan: 2206 /* Boost Receive side for jumbo frames */ 2207 if (adapter->hw.mac.max_frame_size > 4096) 2208 pba = E1000_PBA_14K; 2209 else 2210 pba = E1000_PBA_10K; 2211 break; 2212 case e1000_pchlan: 2213 case e1000_pch2lan: 2214 case e1000_pch_lpt: 2215 case e1000_pch_spt: 2216 pba = E1000_PBA_26K; 2217 break; 2218 default: 2219 if (adapter->hw.mac.max_frame_size > 8192) 2220 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2221 else 2222 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2223 } 2224 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2225 2226 /* 2227 * These parameters control the automatic generation (Tx) and 2228 * response (Rx) to Ethernet PAUSE frames. 2229 * - High water mark should allow for at least two frames to be 2230 * received after sending an XOFF. 2231 * - Low water mark works best when it is very near the high water mark. 2232 * This allows the receiver to restart by sending XON when it has 2233 * drained a bit. Here we use an arbitrary value of 1500 which will 2234 * restart after one full frame is pulled from the buffer. There 2235 * could be several smaller frames in the buffer and if so they will 2236 * not trigger the XON until their total number reduces the buffer 2237 * by 1500. 2238 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2239 */ 2240 rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 ); 2241 hw->fc.high_water = rx_buffer_size - 2242 roundup2(adapter->hw.mac.max_frame_size, 1024); 2243 hw->fc.low_water = hw->fc.high_water - 1500; 2244 2245 if (adapter->fc) /* locally set flow control value? */ 2246 hw->fc.requested_mode = adapter->fc; 2247 else 2248 hw->fc.requested_mode = e1000_fc_full; 2249 2250 if (hw->mac.type == e1000_80003es2lan) 2251 hw->fc.pause_time = 0xFFFF; 2252 else 2253 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2254 2255 hw->fc.send_xon = TRUE; 2256 2257 /* Device specific overrides/settings */ 2258 switch (hw->mac.type) { 2259 case e1000_pchlan: 2260 /* Workaround: no TX flow ctrl for PCH */ 2261 hw->fc.requested_mode = e1000_fc_rx_pause; 2262 hw->fc.pause_time = 0xFFFF; /* override */ 2263 if (if_getmtu(ifp) > ETHERMTU) { 2264 hw->fc.high_water = 0x3500; 2265 hw->fc.low_water = 0x1500; 2266 } else { 2267 hw->fc.high_water = 0x5000; 2268 hw->fc.low_water = 0x3000; 2269 } 2270 hw->fc.refresh_time = 0x1000; 2271 break; 2272 case e1000_pch2lan: 2273 case e1000_pch_lpt: 2274 case e1000_pch_spt: 2275 hw->fc.high_water = 0x5C20; 2276 hw->fc.low_water = 0x5048; 2277 hw->fc.pause_time = 0x0650; 2278 hw->fc.refresh_time = 0x0400; 2279 /* Jumbos need adjusted PBA */ 2280 if (if_getmtu(ifp) > ETHERMTU) 2281 E1000_WRITE_REG(hw, E1000_PBA, 12); 2282 else 2283 E1000_WRITE_REG(hw, E1000_PBA, 26); 2284 break; 2285 case e1000_ich9lan: 2286 case e1000_ich10lan: 2287 if (if_getmtu(ifp) > ETHERMTU) { 2288 hw->fc.high_water = 0x2800; 2289 hw->fc.low_water = hw->fc.high_water - 8; 2290 break; 2291 } 2292 /* else fall thru */ 2293 default: 2294 if (hw->mac.type == e1000_80003es2lan) 2295 hw->fc.pause_time = 0xFFFF; 2296 break; 2297 } 2298 2299 /* Issue a global reset */ 2300 e1000_reset_hw(hw); 2301 E1000_WRITE_REG(hw, E1000_WUC, 0); 2302 em_disable_aspm(adapter); 2303 /* and a re-init */ 2304 if (e1000_init_hw(hw) < 0) { 2305 device_printf(dev, "Hardware Initialization Failed\n"); 2306 return; 2307 } 2308 2309 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2310 e1000_get_phy_info(hw); 2311 e1000_check_for_link(hw); 2312 } 2313 2314 #define RSSKEYLEN 10 2315 static void 2316 em_initialize_rss_mapping(struct adapter *adapter) 2317 { 2318 uint8_t rss_key[4 * RSSKEYLEN]; 2319 uint32_t reta = 0; 2320 struct e1000_hw *hw = &adapter->hw; 2321 int i; 2322 2323 /* 2324 * Configure RSS key 2325 */ 2326 arc4rand(rss_key, sizeof(rss_key), 0); 2327 for (i = 0; i < RSSKEYLEN; ++i) { 2328 uint32_t rssrk = 0; 2329 2330 rssrk = EM_RSSRK_VAL(rss_key, i); 2331 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2332 } 2333 2334 /* 2335 * Configure RSS redirect table in following fashion: 2336 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2337 */ 2338 for (i = 0; i < sizeof(reta); ++i) { 2339 uint32_t q; 2340 2341 q = (i % adapter->rx_num_queues) << 7; 2342 reta |= q << (8 * i); 2343 } 2344 2345 for (i = 0; i < 32; ++i) 2346 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2347 2348 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2349 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2350 E1000_MRQC_RSS_FIELD_IPV4 | 2351 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2352 E1000_MRQC_RSS_FIELD_IPV6_EX | 2353 E1000_MRQC_RSS_FIELD_IPV6); 2354 2355 } 2356 2357 static void 2358 igb_initialize_rss_mapping(struct adapter *adapter) 2359 { 2360 struct e1000_hw *hw = &adapter->hw; 2361 int i; 2362 int queue_id; 2363 u32 reta; 2364 u32 rss_key[10], mrqc, shift = 0; 2365 2366 /* XXX? */ 2367 if (adapter->hw.mac.type == e1000_82575) 2368 shift = 6; 2369 2370 /* 2371 * The redirection table controls which destination 2372 * queue each bucket redirects traffic to. 2373 * Each DWORD represents four queues, with the LSB 2374 * being the first queue in the DWORD. 2375 * 2376 * This just allocates buckets to queues using round-robin 2377 * allocation. 2378 * 2379 * NOTE: It Just Happens to line up with the default 2380 * RSS allocation method. 2381 */ 2382 2383 /* Warning FM follows */ 2384 reta = 0; 2385 for (i = 0; i < 128; i++) { 2386 #ifdef RSS 2387 queue_id = rss_get_indirection_to_bucket(i); 2388 /* 2389 * If we have more queues than buckets, we'll 2390 * end up mapping buckets to a subset of the 2391 * queues. 2392 * 2393 * If we have more buckets than queues, we'll 2394 * end up instead assigning multiple buckets 2395 * to queues. 2396 * 2397 * Both are suboptimal, but we need to handle 2398 * the case so we don't go out of bounds 2399 * indexing arrays and such. 2400 */ 2401 queue_id = queue_id % adapter->rx_num_queues; 2402 #else 2403 queue_id = (i % adapter->rx_num_queues); 2404 #endif 2405 /* Adjust if required */ 2406 queue_id = queue_id << shift; 2407 2408 /* 2409 * The low 8 bits are for hash value (n+0); 2410 * The next 8 bits are for hash value (n+1), etc. 2411 */ 2412 reta = reta >> 8; 2413 reta = reta | ( ((uint32_t) queue_id) << 24); 2414 if ((i & 3) == 3) { 2415 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2416 reta = 0; 2417 } 2418 } 2419 2420 /* Now fill in hash table */ 2421 2422 /* 2423 * MRQC: Multiple Receive Queues Command 2424 * Set queuing to RSS control, number depends on the device. 2425 */ 2426 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2427 2428 #ifdef RSS 2429 /* XXX ew typecasting */ 2430 rss_getkey((uint8_t *) &rss_key); 2431 #else 2432 arc4rand(&rss_key, sizeof(rss_key), 0); 2433 #endif 2434 for (i = 0; i < 10; i++) 2435 E1000_WRITE_REG_ARRAY(hw, 2436 E1000_RSSRK(0), i, rss_key[i]); 2437 2438 /* 2439 * Configure the RSS fields to hash upon. 2440 */ 2441 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2442 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2443 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2444 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2445 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2446 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2447 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2448 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2449 2450 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2451 } 2452 2453 /********************************************************************* 2454 * 2455 * Setup networking device structure and register an interface. 2456 * 2457 **********************************************************************/ 2458 static int 2459 em_setup_interface(if_ctx_t ctx) 2460 { 2461 struct ifnet *ifp = iflib_get_ifp(ctx); 2462 struct adapter *adapter = iflib_get_softc(ctx); 2463 if_softc_ctx_t scctx = adapter->shared; 2464 uint64_t cap = 0; 2465 2466 INIT_DEBUGOUT("em_setup_interface: begin"); 2467 2468 /* TSO parameters */ 2469 ifp->if_hw_tsomax = IP_MAXPACKET; 2470 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */ 2471 ifp->if_hw_tsomaxsegcount = EM_MAX_SCATTER - 5; 2472 ifp->if_hw_tsomaxsegsize = EM_TSO_SEG_SIZE; 2473 2474 /* Single Queue */ 2475 if (adapter->tx_num_queues == 1) { 2476 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2477 if_setsendqready(ifp); 2478 } 2479 2480 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4; 2481 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 2482 2483 /* 2484 * Tell the upper layer(s) we 2485 * support full VLAN capability 2486 */ 2487 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2488 if_setcapabilitiesbit(ifp, cap, 0); 2489 2490 /* 2491 ** Don't turn this on by default, if vlans are 2492 ** created on another pseudo device (eg. lagg) 2493 ** then vlan events are not passed thru, breaking 2494 ** operation, but with HW FILTER off it works. If 2495 ** using vlans directly on the em driver you can 2496 ** enable this and get full hardware tag filtering. 2497 */ 2498 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0); 2499 2500 /* Enable only WOL MAGIC by default */ 2501 if (adapter->wol) { 2502 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 2503 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0); 2504 } 2505 2506 /* 2507 * Specify the media types supported by this adapter and register 2508 * callbacks to update media and link information 2509 */ 2510 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2511 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2512 u_char fiber_type = IFM_1000_SX; /* default type */ 2513 2514 if (adapter->hw.mac.type == e1000_82545) 2515 fiber_type = IFM_1000_LX; 2516 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2517 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2518 } else { 2519 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2520 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2521 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2522 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2523 if (adapter->hw.phy.type != e1000_phy_ife) { 2524 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2525 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2526 } 2527 } 2528 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2529 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2530 return (0); 2531 } 2532 2533 static int 2534 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2535 { 2536 struct adapter *adapter = iflib_get_softc(ctx); 2537 if_softc_ctx_t scctx = adapter->shared; 2538 int error = E1000_SUCCESS; 2539 struct em_tx_queue *que; 2540 int i; 2541 2542 MPASS(adapter->tx_num_queues > 0); 2543 MPASS(adapter->tx_num_queues == ntxqsets); 2544 2545 /* First allocate the top level queue structs */ 2546 if (!(adapter->tx_queues = 2547 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2548 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2549 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2550 return(ENOMEM); 2551 } 2552 2553 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2554 /* Set up some basics */ 2555 struct tx_ring *txr = &que->txr; 2556 txr->adapter = que->adapter = adapter; 2557 txr->que = que; 2558 que->me = txr->me = i; 2559 2560 /* Allocate transmit buffer memory */ 2561 if (!(txr->tx_buffers = (struct em_txbuffer *) malloc(sizeof(struct em_txbuffer) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2562 device_printf(iflib_get_dev(ctx), "failed to allocate tx_buffer memory\n"); 2563 error = ENOMEM; 2564 goto fail; 2565 } 2566 2567 /* get the virtual and physical address of the hardware queues */ 2568 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2569 txr->tx_paddr = paddrs[i*ntxqs]; 2570 2571 } 2572 2573 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2574 return (0); 2575 fail: 2576 em_if_queues_free(ctx); 2577 return (error); 2578 } 2579 2580 static int 2581 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2582 { 2583 struct adapter *adapter = iflib_get_softc(ctx); 2584 int error = E1000_SUCCESS; 2585 struct em_rx_queue *que; 2586 int i; 2587 2588 MPASS(adapter->rx_num_queues > 0); 2589 MPASS(adapter->rx_num_queues == nrxqsets); 2590 2591 /* First allocate the top level queue structs */ 2592 if (!(adapter->rx_queues = 2593 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2594 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2595 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2596 error = ENOMEM; 2597 goto fail; 2598 } 2599 2600 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2601 /* Set up some basics */ 2602 struct rx_ring *rxr = &que->rxr; 2603 rxr->adapter = que->adapter = adapter; 2604 rxr->que = que; 2605 que->me = rxr->me = i; 2606 2607 /* get the virtual and physical address of the hardware queues */ 2608 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2609 rxr->rx_paddr = paddrs[i*nrxqs]; 2610 } 2611 2612 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2613 2614 return (0); 2615 fail: 2616 em_if_queues_free(ctx); 2617 return (error); 2618 } 2619 2620 static void 2621 em_if_queues_free(if_ctx_t ctx) 2622 { 2623 struct adapter *adapter = iflib_get_softc(ctx); 2624 struct em_tx_queue *tx_que = adapter->tx_queues; 2625 struct em_rx_queue *rx_que = adapter->rx_queues; 2626 2627 if (tx_que != NULL) { 2628 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2629 struct tx_ring *txr = &tx_que->txr; 2630 if (txr->tx_buffers == NULL) 2631 break; 2632 2633 free(txr->tx_buffers, M_DEVBUF); 2634 txr->tx_buffers = NULL; 2635 } 2636 free(adapter->tx_queues, M_DEVBUF); 2637 adapter->tx_queues = NULL; 2638 } 2639 2640 if (rx_que != NULL) { 2641 free(adapter->rx_queues, M_DEVBUF); 2642 adapter->rx_queues = NULL; 2643 } 2644 2645 em_release_hw_control(adapter); 2646 2647 if (adapter->mta != NULL) { 2648 free(adapter->mta, M_DEVBUF); 2649 } 2650 } 2651 2652 /********************************************************************* 2653 * 2654 * Enable transmit unit. 2655 * 2656 **********************************************************************/ 2657 static void 2658 em_initialize_transmit_unit(if_ctx_t ctx) 2659 { 2660 struct adapter *adapter = iflib_get_softc(ctx); 2661 if_softc_ctx_t scctx = adapter->shared; 2662 struct em_tx_queue *que; 2663 struct tx_ring *txr; 2664 struct e1000_hw *hw = &adapter->hw; 2665 u32 tctl, txdctl = 0, tarc, tipg = 0; 2666 2667 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2668 2669 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2670 u64 bus_addr; 2671 caddr_t offp, endp; 2672 2673 que = &adapter->tx_queues[i]; 2674 txr = &que->txr; 2675 bus_addr = txr->tx_paddr; 2676 2677 /*Enable all queues */ 2678 em_init_tx_ring(que); 2679 2680 /* Clear checksum offload context. */ 2681 offp = (caddr_t)&txr->csum_flags; 2682 endp = (caddr_t)(txr + 1); 2683 bzero(offp, endp - offp); 2684 2685 /* Base and Len of TX Ring */ 2686 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2687 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2688 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2689 (u32)(bus_addr >> 32)); 2690 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2691 (u32)bus_addr); 2692 /* Init the HEAD/TAIL indices */ 2693 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2694 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2695 2696 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2697 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2698 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2699 2700 txdctl = 0; /* clear txdctl */ 2701 txdctl |= 0x1f; /* PTHRESH */ 2702 txdctl |= 1 << 8; /* HTHRESH */ 2703 txdctl |= 1 << 16;/* WTHRESH */ 2704 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2705 txdctl |= E1000_TXDCTL_GRAN; 2706 txdctl |= 1 << 25; /* LWTHRESH */ 2707 2708 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2709 } 2710 2711 /* Set the default values for the Tx Inter Packet Gap timer */ 2712 switch (adapter->hw.mac.type) { 2713 case e1000_80003es2lan: 2714 tipg = DEFAULT_82543_TIPG_IPGR1; 2715 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2716 E1000_TIPG_IPGR2_SHIFT; 2717 break; 2718 case e1000_82542: 2719 tipg = DEFAULT_82542_TIPG_IPGT; 2720 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2721 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2722 break; 2723 default: 2724 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2725 (adapter->hw.phy.media_type == 2726 e1000_media_type_internal_serdes)) 2727 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2728 else 2729 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2730 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2731 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2732 } 2733 2734 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 2735 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 2736 2737 if(adapter->hw.mac.type >= e1000_82540) 2738 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 2739 adapter->tx_abs_int_delay.value); 2740 2741 if ((adapter->hw.mac.type == e1000_82571) || 2742 (adapter->hw.mac.type == e1000_82572)) { 2743 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2744 tarc |= TARC_SPEED_MODE_BIT; 2745 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2746 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 2747 /* errata: program both queues to unweighted RR */ 2748 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2749 tarc |= 1; 2750 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2751 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 2752 tarc |= 1; 2753 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2754 } else if (adapter->hw.mac.type == e1000_82574) { 2755 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 2756 tarc |= TARC_ERRATA_BIT; 2757 if ( adapter->tx_num_queues > 1) { 2758 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 2759 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2760 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 2761 } else 2762 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 2763 } 2764 2765 if (adapter->tx_int_delay.value > 0) 2766 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2767 2768 /* Program the Transmit Control Register */ 2769 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2770 tctl &= ~E1000_TCTL_CT; 2771 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 2772 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 2773 2774 if (adapter->hw.mac.type >= e1000_82571) 2775 tctl |= E1000_TCTL_MULR; 2776 2777 /* This write will effectively turn on the transmit unit. */ 2778 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2779 2780 if (hw->mac.type == e1000_pch_spt) { 2781 u32 reg; 2782 reg = E1000_READ_REG(hw, E1000_IOSFPC); 2783 reg |= E1000_RCTL_RDMTS_HEX; 2784 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 2785 reg = E1000_READ_REG(hw, E1000_TARC(0)); 2786 reg |= E1000_TARC0_CB_MULTIQ_3_REQ; 2787 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 2788 } 2789 } 2790 2791 /********************************************************************* 2792 * 2793 * Enable receive unit. 2794 * 2795 **********************************************************************/ 2796 2797 static void 2798 em_initialize_receive_unit(if_ctx_t ctx) 2799 { 2800 struct adapter *adapter = iflib_get_softc(ctx); 2801 if_softc_ctx_t scctx = adapter->shared; 2802 struct ifnet *ifp = iflib_get_ifp(ctx); 2803 struct e1000_hw *hw = &adapter->hw; 2804 struct em_rx_queue *que; 2805 int i; 2806 u32 rctl, rxcsum, rfctl; 2807 2808 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 2809 2810 /* 2811 * Make sure receives are disabled while setting 2812 * up the descriptor ring 2813 */ 2814 rctl = E1000_READ_REG(hw, E1000_RCTL); 2815 /* Do not disable if ever enabled on this hardware */ 2816 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 2817 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2818 2819 /* Setup the Receive Control Register */ 2820 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2821 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 2822 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 2823 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2824 2825 /* Do not store bad packets */ 2826 rctl &= ~E1000_RCTL_SBP; 2827 2828 /* Enable Long Packet receive */ 2829 if (if_getmtu(ifp) > ETHERMTU) 2830 rctl |= E1000_RCTL_LPE; 2831 else 2832 rctl &= ~E1000_RCTL_LPE; 2833 2834 /* Strip the CRC */ 2835 if (!em_disable_crc_stripping) 2836 rctl |= E1000_RCTL_SECRC; 2837 2838 if (adapter->hw.mac.type >= e1000_82540) { 2839 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 2840 adapter->rx_abs_int_delay.value); 2841 2842 /* 2843 * Set the interrupt throttling rate. Value is calculated 2844 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2845 */ 2846 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 2847 } 2848 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 2849 adapter->rx_int_delay.value); 2850 2851 /* Use extended rx descriptor formats */ 2852 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2853 rfctl |= E1000_RFCTL_EXTEN; 2854 /* 2855 ** When using MSIX interrupts we need to throttle 2856 ** using the EITR register (82574 only) 2857 */ 2858 if (hw->mac.type == e1000_82574) { 2859 for (int i = 0; i < 4; i++) 2860 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 2861 DEFAULT_ITR); 2862 /* Disable accelerated acknowledge */ 2863 rfctl |= E1000_RFCTL_ACK_DIS; 2864 } 2865 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2866 2867 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2868 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 2869 adapter->hw.mac.type >= e1000_82543) { 2870 if (adapter->tx_num_queues > 1) { 2871 if (adapter->hw.mac.type >= igb_mac_min) { 2872 rxcsum |= E1000_RXCSUM_PCSD; 2873 if (hw->mac.type != e1000_82575) 2874 rxcsum |= E1000_RXCSUM_CRCOFL; 2875 } else 2876 rxcsum |= E1000_RXCSUM_TUOFL | 2877 E1000_RXCSUM_IPOFL | 2878 E1000_RXCSUM_PCSD; 2879 } else { 2880 if (adapter->hw.mac.type >= igb_mac_min) 2881 rxcsum |= E1000_RXCSUM_IPPCSE; 2882 else 2883 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 2884 if (adapter->hw.mac.type > e1000_82575) 2885 rxcsum |= E1000_RXCSUM_CRCOFL; 2886 } 2887 } else 2888 rxcsum &= ~E1000_RXCSUM_TUOFL; 2889 2890 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2891 2892 if (adapter->rx_num_queues > 1) { 2893 if (adapter->hw.mac.type >= igb_mac_min) 2894 igb_initialize_rss_mapping(adapter); 2895 else 2896 em_initialize_rss_mapping(adapter); 2897 } 2898 2899 /* 2900 ** XXX TEMPORARY WORKAROUND: on some systems with 82573 2901 ** long latencies are observed, like Lenovo X60. This 2902 ** change eliminates the problem, but since having positive 2903 ** values in RDTR is a known source of problems on other 2904 ** platforms another solution is being sought. 2905 */ 2906 if (hw->mac.type == e1000_82573) 2907 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 2908 2909 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 2910 struct rx_ring *rxr = &que->rxr; 2911 /* Setup the Base and Length of the Rx Descriptor Ring */ 2912 u64 bus_addr = rxr->rx_paddr; 2913 #if 0 2914 u32 rdt = adapter->rx_num_queues -1; /* default */ 2915 #endif 2916 2917 E1000_WRITE_REG(hw, E1000_RDLEN(i), 2918 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 2919 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 2920 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 2921 /* Setup the Head and Tail Descriptor Pointers */ 2922 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 2923 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 2924 } 2925 2926 /* 2927 * Set PTHRESH for improved jumbo performance 2928 * According to 10.2.5.11 of Intel 82574 Datasheet, 2929 * RXDCTL(1) is written whenever RXDCTL(0) is written. 2930 * Only write to RXDCTL(1) if there is a need for different 2931 * settings. 2932 */ 2933 2934 if (((adapter->hw.mac.type == e1000_ich9lan) || 2935 (adapter->hw.mac.type == e1000_pch2lan) || 2936 (adapter->hw.mac.type == e1000_ich10lan)) && 2937 (if_getmtu(ifp) > ETHERMTU)) { 2938 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2939 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 2940 } else if (adapter->hw.mac.type == e1000_82574) { 2941 for (int i = 0; i < adapter->rx_num_queues; i++) { 2942 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 2943 rxdctl |= 0x20; /* PTHRESH */ 2944 rxdctl |= 4 << 8; /* HTHRESH */ 2945 rxdctl |= 4 << 16;/* WTHRESH */ 2946 rxdctl |= 1 << 24; /* Switch to granularity */ 2947 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 2948 } 2949 } else if (adapter->hw.mac.type >= igb_mac_min) { 2950 u32 psize, srrctl = 0; 2951 2952 if (ifp->if_mtu > ETHERMTU) { 2953 rctl |= E1000_RCTL_LPE; 2954 2955 /* Set maximum packet len */ 2956 psize = scctx->isc_max_frame_size; 2957 if (psize <= 4096) { 2958 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 2959 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 2960 } else if (psize > 4096) { 2961 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 2962 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 2963 } 2964 2965 /* are we on a vlan? */ 2966 if (ifp->if_vlantrunk != NULL) 2967 psize += VLAN_TAG_SIZE; 2968 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 2969 } else { 2970 rctl &= ~E1000_RCTL_LPE; 2971 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 2972 rctl |= E1000_RCTL_SZ_2048; 2973 } 2974 2975 /* 2976 * If TX flow control is disabled and there's >1 queue defined, 2977 * enable DROP. 2978 * 2979 * This drops frames rather than hanging the RX MAC for all queues. 2980 */ 2981 if ((adapter->rx_num_queues > 1) && 2982 (adapter->fc == e1000_fc_none || 2983 adapter->fc == e1000_fc_rx_pause)) { 2984 srrctl |= E1000_SRRCTL_DROP_EN; 2985 } 2986 /* Setup the Base and Length of the Rx Descriptor Rings */ 2987 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 2988 struct rx_ring *rxr = &que->rxr; 2989 u64 bus_addr = rxr->rx_paddr; 2990 u32 rxdctl; 2991 2992 #ifdef notyet 2993 /* Configure for header split? -- ignore for now */ 2994 rxr->hdr_split = igb_header_split; 2995 #else 2996 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 2997 #endif 2998 2999 3000 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3001 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3002 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3003 (uint32_t)(bus_addr >> 32)); 3004 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3005 (uint32_t)bus_addr); 3006 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3007 /* Enable this Queue */ 3008 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3009 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3010 rxdctl &= 0xFFF00000; 3011 rxdctl |= IGB_RX_PTHRESH; 3012 rxdctl |= IGB_RX_HTHRESH << 8; 3013 rxdctl |= IGB_RX_WTHRESH << 16; 3014 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3015 } 3016 } 3017 if (adapter->hw.mac.type >= e1000_pch2lan) { 3018 if (if_getmtu(ifp) > ETHERMTU) 3019 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3020 else 3021 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3022 } 3023 3024 /* Make sure VLAN Filters are off */ 3025 rctl &= ~E1000_RCTL_VFE; 3026 3027 if (adapter->rx_mbuf_sz == MCLBYTES) 3028 rctl |= E1000_RCTL_SZ_2048; 3029 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3030 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3031 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3032 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3033 3034 /* ensure we clear use DTYPE of 00 here */ 3035 rctl &= ~0x00000C00; 3036 /* Write out the settings */ 3037 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3038 3039 return; 3040 } 3041 3042 static void 3043 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3044 { 3045 struct adapter *adapter = iflib_get_softc(ctx); 3046 u32 index, bit; 3047 3048 index = (vtag >> 5) & 0x7F; 3049 bit = vtag & 0x1F; 3050 adapter->shadow_vfta[index] |= (1 << bit); 3051 ++adapter->num_vlans; 3052 } 3053 3054 static void 3055 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3056 { 3057 struct adapter *adapter = iflib_get_softc(ctx); 3058 u32 index, bit; 3059 3060 index = (vtag >> 5) & 0x7F; 3061 bit = vtag & 0x1F; 3062 adapter->shadow_vfta[index] &= ~(1 << bit); 3063 --adapter->num_vlans; 3064 } 3065 3066 static void 3067 em_setup_vlan_hw_support(struct adapter *adapter) 3068 { 3069 struct e1000_hw *hw = &adapter->hw; 3070 u32 reg; 3071 3072 /* 3073 ** We get here thru init_locked, meaning 3074 ** a soft reset, this has already cleared 3075 ** the VFTA and other state, so if there 3076 ** have been no vlan's registered do nothing. 3077 */ 3078 if (adapter->num_vlans == 0) 3079 return; 3080 3081 /* 3082 ** A soft reset zero's out the VFTA, so 3083 ** we need to repopulate it now. 3084 */ 3085 for (int i = 0; i < EM_VFTA_SIZE; i++) 3086 if (adapter->shadow_vfta[i] != 0) 3087 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3088 i, adapter->shadow_vfta[i]); 3089 3090 reg = E1000_READ_REG(hw, E1000_CTRL); 3091 reg |= E1000_CTRL_VME; 3092 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3093 3094 /* Enable the Filter Table */ 3095 reg = E1000_READ_REG(hw, E1000_RCTL); 3096 reg &= ~E1000_RCTL_CFIEN; 3097 reg |= E1000_RCTL_VFE; 3098 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3099 } 3100 3101 static void 3102 em_if_enable_intr(if_ctx_t ctx) 3103 { 3104 struct adapter *adapter = iflib_get_softc(ctx); 3105 struct e1000_hw *hw = &adapter->hw; 3106 u32 ims_mask = IMS_ENABLE_MASK; 3107 3108 if (hw->mac.type == e1000_82574) { 3109 E1000_WRITE_REG(hw, EM_EIAC, adapter->ims); 3110 ims_mask |= adapter->ims; 3111 } if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3112 u32 mask = (adapter->que_mask | adapter->link_mask); 3113 3114 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3115 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3116 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3117 ims_mask = E1000_IMS_LSC; 3118 } 3119 3120 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3121 } 3122 3123 static void 3124 em_if_disable_intr(if_ctx_t ctx) 3125 { 3126 struct adapter *adapter = iflib_get_softc(ctx); 3127 struct e1000_hw *hw = &adapter->hw; 3128 3129 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3130 if (hw->mac.type >= igb_mac_min) 3131 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3132 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3133 } 3134 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3135 } 3136 3137 /* 3138 * Bit of a misnomer, what this really means is 3139 * to enable OS management of the system... aka 3140 * to disable special hardware management features 3141 */ 3142 static void 3143 em_init_manageability(struct adapter *adapter) 3144 { 3145 /* A shared code workaround */ 3146 #define E1000_82542_MANC2H E1000_MANC2H 3147 if (adapter->has_manage) { 3148 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3149 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3150 3151 /* disable hardware interception of ARP */ 3152 manc &= ~(E1000_MANC_ARP_EN); 3153 3154 /* enable receiving management packets to the host */ 3155 manc |= E1000_MANC_EN_MNG2HOST; 3156 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3157 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3158 manc2h |= E1000_MNG2HOST_PORT_623; 3159 manc2h |= E1000_MNG2HOST_PORT_664; 3160 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3161 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3162 } 3163 } 3164 3165 /* 3166 * Give control back to hardware management 3167 * controller if there is one. 3168 */ 3169 static void 3170 em_release_manageability(struct adapter *adapter) 3171 { 3172 if (adapter->has_manage) { 3173 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3174 3175 /* re-enable hardware interception of ARP */ 3176 manc |= E1000_MANC_ARP_EN; 3177 manc &= ~E1000_MANC_EN_MNG2HOST; 3178 3179 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3180 } 3181 } 3182 3183 /* 3184 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3185 * For ASF and Pass Through versions of f/w this means 3186 * that the driver is loaded. For AMT version type f/w 3187 * this means that the network i/f is open. 3188 */ 3189 static void 3190 em_get_hw_control(struct adapter *adapter) 3191 { 3192 u32 ctrl_ext, swsm; 3193 3194 if (adapter->hw.mac.type == e1000_82573) { 3195 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3196 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3197 swsm | E1000_SWSM_DRV_LOAD); 3198 return; 3199 } 3200 /* else */ 3201 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3202 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3203 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3204 return; 3205 } 3206 3207 /* 3208 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3209 * For ASF and Pass Through versions of f/w this means that 3210 * the driver is no longer loaded. For AMT versions of the 3211 * f/w this means that the network i/f is closed. 3212 */ 3213 static void 3214 em_release_hw_control(struct adapter *adapter) 3215 { 3216 u32 ctrl_ext, swsm; 3217 3218 if (!adapter->has_manage) 3219 return; 3220 3221 if (adapter->hw.mac.type == e1000_82573) { 3222 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3223 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3224 swsm & ~E1000_SWSM_DRV_LOAD); 3225 return; 3226 } 3227 /* else */ 3228 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3229 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3230 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3231 return; 3232 } 3233 3234 static int 3235 em_is_valid_ether_addr(u8 *addr) 3236 { 3237 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3238 3239 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3240 return (FALSE); 3241 } 3242 3243 return (TRUE); 3244 } 3245 3246 /* 3247 ** Parse the interface capabilities with regard 3248 ** to both system management and wake-on-lan for 3249 ** later use. 3250 */ 3251 static void 3252 em_get_wakeup(if_ctx_t ctx) 3253 { 3254 struct adapter *adapter = iflib_get_softc(ctx); 3255 device_t dev = iflib_get_dev(ctx); 3256 u16 eeprom_data = 0, device_id, apme_mask; 3257 3258 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3259 apme_mask = EM_EEPROM_APME; 3260 3261 switch (adapter->hw.mac.type) { 3262 case e1000_82542: 3263 case e1000_82543: 3264 break; 3265 case e1000_82544: 3266 e1000_read_nvm(&adapter->hw, 3267 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3268 apme_mask = EM_82544_APME; 3269 break; 3270 case e1000_82546: 3271 case e1000_82546_rev_3: 3272 if (adapter->hw.bus.func == 1) { 3273 e1000_read_nvm(&adapter->hw, 3274 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3275 break; 3276 } else 3277 e1000_read_nvm(&adapter->hw, 3278 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3279 break; 3280 case e1000_82573: 3281 case e1000_82583: 3282 adapter->has_amt = TRUE; 3283 /* Falls thru */ 3284 case e1000_82571: 3285 case e1000_82572: 3286 case e1000_80003es2lan: 3287 if (adapter->hw.bus.func == 1) { 3288 e1000_read_nvm(&adapter->hw, 3289 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3290 break; 3291 } else 3292 e1000_read_nvm(&adapter->hw, 3293 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3294 break; 3295 case e1000_ich8lan: 3296 case e1000_ich9lan: 3297 case e1000_ich10lan: 3298 case e1000_pchlan: 3299 case e1000_pch2lan: 3300 apme_mask = E1000_WUC_APME; 3301 adapter->has_amt = TRUE; 3302 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3303 break; 3304 default: 3305 e1000_read_nvm(&adapter->hw, 3306 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3307 break; 3308 } 3309 if (eeprom_data & apme_mask) 3310 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3311 /* 3312 * We have the eeprom settings, now apply the special cases 3313 * where the eeprom may be wrong or the board won't support 3314 * wake on lan on a particular port 3315 */ 3316 device_id = pci_get_device(dev); 3317 switch (device_id) { 3318 case E1000_DEV_ID_82546GB_PCIE: 3319 adapter->wol = 0; 3320 break; 3321 case E1000_DEV_ID_82546EB_FIBER: 3322 case E1000_DEV_ID_82546GB_FIBER: 3323 /* Wake events only supported on port A for dual fiber 3324 * regardless of eeprom setting */ 3325 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3326 E1000_STATUS_FUNC_1) 3327 adapter->wol = 0; 3328 break; 3329 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3330 /* if quad port adapter, disable WoL on all but port A */ 3331 if (global_quad_port_a != 0) 3332 adapter->wol = 0; 3333 /* Reset for multiple quad port adapters */ 3334 if (++global_quad_port_a == 4) 3335 global_quad_port_a = 0; 3336 break; 3337 case E1000_DEV_ID_82571EB_FIBER: 3338 /* Wake events only supported on port A for dual fiber 3339 * regardless of eeprom setting */ 3340 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3341 E1000_STATUS_FUNC_1) 3342 adapter->wol = 0; 3343 break; 3344 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3345 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3346 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3347 /* if quad port adapter, disable WoL on all but port A */ 3348 if (global_quad_port_a != 0) 3349 adapter->wol = 0; 3350 /* Reset for multiple quad port adapters */ 3351 if (++global_quad_port_a == 4) 3352 global_quad_port_a = 0; 3353 break; 3354 } 3355 return; 3356 } 3357 3358 3359 /* 3360 * Enable PCI Wake On Lan capability 3361 */ 3362 static void 3363 em_enable_wakeup(if_ctx_t ctx) 3364 { 3365 struct adapter *adapter = iflib_get_softc(ctx); 3366 device_t dev = iflib_get_dev(ctx); 3367 if_t ifp = iflib_get_ifp(ctx); 3368 u32 pmc, ctrl, ctrl_ext, rctl; 3369 u16 status; 3370 3371 if ((pci_find_cap(dev, PCIY_PMG, &pmc) != 0)) 3372 return; 3373 3374 /* Advertise the wakeup capability */ 3375 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3376 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3377 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3378 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3379 3380 if ((adapter->hw.mac.type == e1000_ich8lan) || 3381 (adapter->hw.mac.type == e1000_pchlan) || 3382 (adapter->hw.mac.type == e1000_ich9lan) || 3383 (adapter->hw.mac.type == e1000_ich10lan)) 3384 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3385 3386 /* Keep the laser running on Fiber adapters */ 3387 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3388 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3389 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3390 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3391 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3392 } 3393 3394 /* 3395 ** Determine type of Wakeup: note that wol 3396 ** is set with all bits on by default. 3397 */ 3398 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3399 adapter->wol &= ~E1000_WUFC_MAG; 3400 3401 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3402 adapter->wol &= ~E1000_WUFC_MC; 3403 else { 3404 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3405 rctl |= E1000_RCTL_MPE; 3406 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3407 } 3408 3409 if ((adapter->hw.mac.type == e1000_pchlan) || 3410 (adapter->hw.mac.type == e1000_pch2lan)) { 3411 if (em_enable_phy_wakeup(adapter)) 3412 return; 3413 } else { 3414 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3415 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3416 } 3417 3418 if (adapter->hw.phy.type == e1000_phy_igp_3) 3419 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3420 3421 /* Request PME */ 3422 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3423 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3424 if (if_getcapenable(ifp) & IFCAP_WOL) 3425 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3426 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3427 3428 return; 3429 } 3430 3431 /* 3432 ** WOL in the newer chipset interfaces (pchlan) 3433 ** require thing to be copied into the phy 3434 */ 3435 static int 3436 em_enable_phy_wakeup(struct adapter *adapter) 3437 { 3438 struct e1000_hw *hw = &adapter->hw; 3439 u32 mreg, ret = 0; 3440 u16 preg; 3441 3442 /* copy MAC RARs to PHY RARs */ 3443 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3444 3445 /* copy MAC MTA to PHY MTA */ 3446 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3447 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3448 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3449 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3450 (u16)((mreg >> 16) & 0xFFFF)); 3451 } 3452 3453 /* configure PHY Rx Control register */ 3454 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3455 mreg = E1000_READ_REG(hw, E1000_RCTL); 3456 if (mreg & E1000_RCTL_UPE) 3457 preg |= BM_RCTL_UPE; 3458 if (mreg & E1000_RCTL_MPE) 3459 preg |= BM_RCTL_MPE; 3460 preg &= ~(BM_RCTL_MO_MASK); 3461 if (mreg & E1000_RCTL_MO_3) 3462 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3463 << BM_RCTL_MO_SHIFT); 3464 if (mreg & E1000_RCTL_BAM) 3465 preg |= BM_RCTL_BAM; 3466 if (mreg & E1000_RCTL_PMCF) 3467 preg |= BM_RCTL_PMCF; 3468 mreg = E1000_READ_REG(hw, E1000_CTRL); 3469 if (mreg & E1000_CTRL_RFCE) 3470 preg |= BM_RCTL_RFCE; 3471 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3472 3473 /* enable PHY wakeup in MAC register */ 3474 E1000_WRITE_REG(hw, E1000_WUC, 3475 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN); 3476 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3477 3478 /* configure and enable PHY wakeup in PHY registers */ 3479 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3480 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3481 3482 /* activate PHY wakeup */ 3483 ret = hw->phy.ops.acquire(hw); 3484 if (ret) { 3485 printf("Could not acquire PHY\n"); 3486 return ret; 3487 } 3488 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3489 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3490 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3491 if (ret) { 3492 printf("Could not read PHY page 769\n"); 3493 goto out; 3494 } 3495 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3496 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3497 if (ret) 3498 printf("Could not set PHY Host Wakeup bit\n"); 3499 out: 3500 hw->phy.ops.release(hw); 3501 3502 return ret; 3503 } 3504 3505 static void 3506 em_if_led_func(if_ctx_t ctx, int onoff) 3507 { 3508 struct adapter *adapter = iflib_get_softc(ctx); 3509 3510 if (onoff) { 3511 e1000_setup_led(&adapter->hw); 3512 e1000_led_on(&adapter->hw); 3513 } else { 3514 e1000_led_off(&adapter->hw); 3515 e1000_cleanup_led(&adapter->hw); 3516 } 3517 } 3518 3519 /* 3520 ** Disable the L0S and L1 LINK states 3521 */ 3522 static void 3523 em_disable_aspm(struct adapter *adapter) 3524 { 3525 int base, reg; 3526 u16 link_cap,link_ctrl; 3527 device_t dev = adapter->dev; 3528 3529 switch (adapter->hw.mac.type) { 3530 case e1000_82573: 3531 case e1000_82574: 3532 case e1000_82583: 3533 break; 3534 default: 3535 return; 3536 } 3537 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3538 return; 3539 reg = base + PCIER_LINK_CAP; 3540 link_cap = pci_read_config(dev, reg, 2); 3541 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3542 return; 3543 reg = base + PCIER_LINK_CTL; 3544 link_ctrl = pci_read_config(dev, reg, 2); 3545 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3546 pci_write_config(dev, reg, link_ctrl, 2); 3547 return; 3548 } 3549 3550 /********************************************************************** 3551 * 3552 * Update the board statistics counters. 3553 * 3554 **********************************************************************/ 3555 static void 3556 em_update_stats_counters(struct adapter *adapter) 3557 { 3558 3559 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3560 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3561 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3562 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3563 } 3564 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3565 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3566 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3567 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3568 3569 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3570 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3571 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3572 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3573 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3574 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3575 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3576 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3577 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3578 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3579 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3580 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3581 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3582 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3583 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3584 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3585 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3586 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3587 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3588 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3589 3590 /* For the 64-bit byte counters the low dword must be read first. */ 3591 /* Both registers clear on the read of the high dword */ 3592 3593 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3594 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3595 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3596 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3597 3598 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3599 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3600 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3601 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3602 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3603 3604 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3605 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3606 3607 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3608 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3609 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3610 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3611 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3612 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3613 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3614 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3615 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3616 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3617 3618 /* Interrupt Counts */ 3619 3620 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3621 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3622 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3623 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3624 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3625 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3626 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3627 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3628 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3629 3630 if (adapter->hw.mac.type >= e1000_82543) { 3631 adapter->stats.algnerrc += 3632 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3633 adapter->stats.rxerrc += 3634 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3635 adapter->stats.tncrs += 3636 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3637 adapter->stats.cexterr += 3638 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3639 adapter->stats.tsctc += 3640 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3641 adapter->stats.tsctfc += 3642 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3643 } 3644 } 3645 3646 static uint64_t 3647 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3648 { 3649 struct adapter *adapter = iflib_get_softc(ctx); 3650 struct ifnet *ifp = iflib_get_ifp(ctx); 3651 3652 switch (cnt) { 3653 case IFCOUNTER_COLLISIONS: 3654 return (adapter->stats.colc); 3655 case IFCOUNTER_IERRORS: 3656 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3657 adapter->stats.crcerrs + adapter->stats.algnerrc + 3658 adapter->stats.ruc + adapter->stats.roc + 3659 adapter->stats.mpc + adapter->stats.cexterr); 3660 case IFCOUNTER_OERRORS: 3661 return (adapter->stats.ecol + adapter->stats.latecol + 3662 adapter->watchdog_events); 3663 default: 3664 return (if_get_counter_default(ifp, cnt)); 3665 } 3666 } 3667 3668 /* Export a single 32-bit register via a read-only sysctl. */ 3669 static int 3670 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3671 { 3672 struct adapter *adapter; 3673 u_int val; 3674 3675 adapter = oidp->oid_arg1; 3676 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3677 return (sysctl_handle_int(oidp, &val, 0, req)); 3678 } 3679 3680 /* 3681 * Add sysctl variables, one per statistic, to the system. 3682 */ 3683 static void 3684 em_add_hw_stats(struct adapter *adapter) 3685 { 3686 device_t dev = iflib_get_dev(adapter->ctx); 3687 struct em_tx_queue *tx_que = adapter->tx_queues; 3688 struct em_rx_queue *rx_que = adapter->rx_queues; 3689 3690 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3691 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3692 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3693 struct e1000_hw_stats *stats = &adapter->stats; 3694 3695 struct sysctl_oid *stat_node, *queue_node, *int_node; 3696 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3697 3698 #define QUEUE_NAME_LEN 32 3699 char namebuf[QUEUE_NAME_LEN]; 3700 3701 /* Driver Statistics */ 3702 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 3703 CTLFLAG_RD, &adapter->dropped_pkts, 3704 "Driver dropped packets"); 3705 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 3706 CTLFLAG_RD, &adapter->link_irq, 3707 "Link MSIX IRQ Handled"); 3708 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 3709 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 3710 "Defragmenting mbuf chain failed"); 3711 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 3712 CTLFLAG_RD, &adapter->no_tx_dma_setup, 3713 "Driver tx dma failure in xmit"); 3714 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 3715 CTLFLAG_RD, &adapter->rx_overruns, 3716 "RX overruns"); 3717 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 3718 CTLFLAG_RD, &adapter->watchdog_events, 3719 "Watchdog timeouts"); 3720 3721 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 3722 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 3723 em_sysctl_reg_handler, "IU", 3724 "Device Control Register"); 3725 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 3726 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 3727 em_sysctl_reg_handler, "IU", 3728 "Receiver Control Register"); 3729 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 3730 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 3731 "Flow Control High Watermark"); 3732 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 3733 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 3734 "Flow Control Low Watermark"); 3735 3736 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 3737 struct tx_ring *txr = &tx_que->txr; 3738 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 3739 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3740 CTLFLAG_RD, NULL, "TX Queue Name"); 3741 queue_list = SYSCTL_CHILDREN(queue_node); 3742 3743 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 3744 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3745 E1000_TDH(txr->me), 3746 em_sysctl_reg_handler, "IU", 3747 "Transmit Descriptor Head"); 3748 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 3749 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3750 E1000_TDT(txr->me), 3751 em_sysctl_reg_handler, "IU", 3752 "Transmit Descriptor Tail"); 3753 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 3754 CTLFLAG_RD, &txr->tx_irq, 3755 "Queue MSI-X Transmit Interrupts"); 3756 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "no_desc_avail", 3757 CTLFLAG_RD, &txr->no_desc_avail, 3758 "Queue No Descriptor Available"); 3759 } 3760 3761 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 3762 struct rx_ring *rxr = &rx_que->rxr; 3763 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 3764 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3765 CTLFLAG_RD, NULL, "RX Queue Name"); 3766 queue_list = SYSCTL_CHILDREN(queue_node); 3767 3768 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 3769 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3770 E1000_RDH(rxr->me), 3771 em_sysctl_reg_handler, "IU", 3772 "Receive Descriptor Head"); 3773 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 3774 CTLTYPE_UINT | CTLFLAG_RD, adapter, 3775 E1000_RDT(rxr->me), 3776 em_sysctl_reg_handler, "IU", 3777 "Receive Descriptor Tail"); 3778 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 3779 CTLFLAG_RD, &rxr->rx_irq, 3780 "Queue MSI-X Receive Interrupts"); 3781 } 3782 3783 /* MAC stats get their own sub node */ 3784 3785 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 3786 CTLFLAG_RD, NULL, "Statistics"); 3787 stat_list = SYSCTL_CHILDREN(stat_node); 3788 3789 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 3790 CTLFLAG_RD, &stats->ecol, 3791 "Excessive collisions"); 3792 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 3793 CTLFLAG_RD, &stats->scc, 3794 "Single collisions"); 3795 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 3796 CTLFLAG_RD, &stats->mcc, 3797 "Multiple collisions"); 3798 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 3799 CTLFLAG_RD, &stats->latecol, 3800 "Late collisions"); 3801 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 3802 CTLFLAG_RD, &stats->colc, 3803 "Collision Count"); 3804 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 3805 CTLFLAG_RD, &adapter->stats.symerrs, 3806 "Symbol Errors"); 3807 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 3808 CTLFLAG_RD, &adapter->stats.sec, 3809 "Sequence Errors"); 3810 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 3811 CTLFLAG_RD, &adapter->stats.dc, 3812 "Defer Count"); 3813 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 3814 CTLFLAG_RD, &adapter->stats.mpc, 3815 "Missed Packets"); 3816 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 3817 CTLFLAG_RD, &adapter->stats.rnbc, 3818 "Receive No Buffers"); 3819 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 3820 CTLFLAG_RD, &adapter->stats.ruc, 3821 "Receive Undersize"); 3822 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 3823 CTLFLAG_RD, &adapter->stats.rfc, 3824 "Fragmented Packets Received "); 3825 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 3826 CTLFLAG_RD, &adapter->stats.roc, 3827 "Oversized Packets Received"); 3828 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 3829 CTLFLAG_RD, &adapter->stats.rjc, 3830 "Recevied Jabber"); 3831 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 3832 CTLFLAG_RD, &adapter->stats.rxerrc, 3833 "Receive Errors"); 3834 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 3835 CTLFLAG_RD, &adapter->stats.crcerrs, 3836 "CRC errors"); 3837 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 3838 CTLFLAG_RD, &adapter->stats.algnerrc, 3839 "Alignment Errors"); 3840 /* On 82575 these are collision counts */ 3841 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 3842 CTLFLAG_RD, &adapter->stats.cexterr, 3843 "Collision/Carrier extension errors"); 3844 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 3845 CTLFLAG_RD, &adapter->stats.xonrxc, 3846 "XON Received"); 3847 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 3848 CTLFLAG_RD, &adapter->stats.xontxc, 3849 "XON Transmitted"); 3850 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 3851 CTLFLAG_RD, &adapter->stats.xoffrxc, 3852 "XOFF Received"); 3853 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 3854 CTLFLAG_RD, &adapter->stats.xofftxc, 3855 "XOFF Transmitted"); 3856 3857 /* Packet Reception Stats */ 3858 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 3859 CTLFLAG_RD, &adapter->stats.tpr, 3860 "Total Packets Received "); 3861 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 3862 CTLFLAG_RD, &adapter->stats.gprc, 3863 "Good Packets Received"); 3864 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 3865 CTLFLAG_RD, &adapter->stats.bprc, 3866 "Broadcast Packets Received"); 3867 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 3868 CTLFLAG_RD, &adapter->stats.mprc, 3869 "Multicast Packets Received"); 3870 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 3871 CTLFLAG_RD, &adapter->stats.prc64, 3872 "64 byte frames received "); 3873 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 3874 CTLFLAG_RD, &adapter->stats.prc127, 3875 "65-127 byte frames received"); 3876 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 3877 CTLFLAG_RD, &adapter->stats.prc255, 3878 "128-255 byte frames received"); 3879 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 3880 CTLFLAG_RD, &adapter->stats.prc511, 3881 "256-511 byte frames received"); 3882 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 3883 CTLFLAG_RD, &adapter->stats.prc1023, 3884 "512-1023 byte frames received"); 3885 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 3886 CTLFLAG_RD, &adapter->stats.prc1522, 3887 "1023-1522 byte frames received"); 3888 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 3889 CTLFLAG_RD, &adapter->stats.gorc, 3890 "Good Octets Received"); 3891 3892 /* Packet Transmission Stats */ 3893 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 3894 CTLFLAG_RD, &adapter->stats.gotc, 3895 "Good Octets Transmitted"); 3896 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 3897 CTLFLAG_RD, &adapter->stats.tpt, 3898 "Total Packets Transmitted"); 3899 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 3900 CTLFLAG_RD, &adapter->stats.gptc, 3901 "Good Packets Transmitted"); 3902 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 3903 CTLFLAG_RD, &adapter->stats.bptc, 3904 "Broadcast Packets Transmitted"); 3905 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 3906 CTLFLAG_RD, &adapter->stats.mptc, 3907 "Multicast Packets Transmitted"); 3908 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 3909 CTLFLAG_RD, &adapter->stats.ptc64, 3910 "64 byte frames transmitted "); 3911 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 3912 CTLFLAG_RD, &adapter->stats.ptc127, 3913 "65-127 byte frames transmitted"); 3914 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 3915 CTLFLAG_RD, &adapter->stats.ptc255, 3916 "128-255 byte frames transmitted"); 3917 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 3918 CTLFLAG_RD, &adapter->stats.ptc511, 3919 "256-511 byte frames transmitted"); 3920 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 3921 CTLFLAG_RD, &adapter->stats.ptc1023, 3922 "512-1023 byte frames transmitted"); 3923 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 3924 CTLFLAG_RD, &adapter->stats.ptc1522, 3925 "1024-1522 byte frames transmitted"); 3926 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 3927 CTLFLAG_RD, &adapter->stats.tsctc, 3928 "TSO Contexts Transmitted"); 3929 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 3930 CTLFLAG_RD, &adapter->stats.tsctfc, 3931 "TSO Contexts Failed"); 3932 3933 3934 /* Interrupt Stats */ 3935 3936 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 3937 CTLFLAG_RD, NULL, "Interrupt Statistics"); 3938 int_list = SYSCTL_CHILDREN(int_node); 3939 3940 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 3941 CTLFLAG_RD, &adapter->stats.iac, 3942 "Interrupt Assertion Count"); 3943 3944 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 3945 CTLFLAG_RD, &adapter->stats.icrxptc, 3946 "Interrupt Cause Rx Pkt Timer Expire Count"); 3947 3948 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 3949 CTLFLAG_RD, &adapter->stats.icrxatc, 3950 "Interrupt Cause Rx Abs Timer Expire Count"); 3951 3952 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 3953 CTLFLAG_RD, &adapter->stats.ictxptc, 3954 "Interrupt Cause Tx Pkt Timer Expire Count"); 3955 3956 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 3957 CTLFLAG_RD, &adapter->stats.ictxatc, 3958 "Interrupt Cause Tx Abs Timer Expire Count"); 3959 3960 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 3961 CTLFLAG_RD, &adapter->stats.ictxqec, 3962 "Interrupt Cause Tx Queue Empty Count"); 3963 3964 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 3965 CTLFLAG_RD, &adapter->stats.ictxqmtc, 3966 "Interrupt Cause Tx Queue Min Thresh Count"); 3967 3968 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 3969 CTLFLAG_RD, &adapter->stats.icrxdmtc, 3970 "Interrupt Cause Rx Desc Min Thresh Count"); 3971 3972 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 3973 CTLFLAG_RD, &adapter->stats.icrxoc, 3974 "Interrupt Cause Receiver Overrun Count"); 3975 } 3976 3977 /********************************************************************** 3978 * 3979 * This routine provides a way to dump out the adapter eeprom, 3980 * often a useful debug/service tool. This only dumps the first 3981 * 32 words, stuff that matters is in that extent. 3982 * 3983 **********************************************************************/ 3984 static int 3985 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 3986 { 3987 struct adapter *adapter = (struct adapter *)arg1; 3988 int error; 3989 int result; 3990 3991 result = -1; 3992 error = sysctl_handle_int(oidp, &result, 0, req); 3993 3994 if (error || !req->newptr) 3995 return (error); 3996 3997 /* 3998 * This value will cause a hex dump of the 3999 * first 32 16-bit words of the EEPROM to 4000 * the screen. 4001 */ 4002 if (result == 1) 4003 em_print_nvm_info(adapter); 4004 4005 return (error); 4006 } 4007 4008 static void 4009 em_print_nvm_info(struct adapter *adapter) 4010 { 4011 u16 eeprom_data; 4012 int i, j, row = 0; 4013 4014 /* Its a bit crude, but it gets the job done */ 4015 printf("\nInterface EEPROM Dump:\n"); 4016 printf("Offset\n0x0000 "); 4017 for (i = 0, j = 0; i < 32; i++, j++) { 4018 if (j == 8) { /* Make the offset block */ 4019 j = 0; ++row; 4020 printf("\n0x00%x0 ",row); 4021 } 4022 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4023 printf("%04x ", eeprom_data); 4024 } 4025 printf("\n"); 4026 } 4027 4028 static int 4029 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4030 { 4031 struct em_int_delay_info *info; 4032 struct adapter *adapter; 4033 u32 regval; 4034 int error, usecs, ticks; 4035 4036 info = (struct em_int_delay_info *)arg1; 4037 usecs = info->value; 4038 error = sysctl_handle_int(oidp, &usecs, 0, req); 4039 if (error != 0 || req->newptr == NULL) 4040 return (error); 4041 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4042 return (EINVAL); 4043 info->value = usecs; 4044 ticks = EM_USECS_TO_TICKS(usecs); 4045 if (info->offset == E1000_ITR) /* units are 256ns here */ 4046 ticks *= 4; 4047 4048 adapter = info->adapter; 4049 4050 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4051 regval = (regval & ~0xffff) | (ticks & 0xffff); 4052 /* Handle a few special cases. */ 4053 switch (info->offset) { 4054 case E1000_RDTR: 4055 break; 4056 case E1000_TIDV: 4057 if (ticks == 0) { 4058 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4059 /* Don't write 0 into the TIDV register. */ 4060 regval++; 4061 } else 4062 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4063 break; 4064 } 4065 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4066 return (0); 4067 } 4068 4069 static void 4070 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4071 const char *description, struct em_int_delay_info *info, 4072 int offset, int value) 4073 { 4074 info->adapter = adapter; 4075 info->offset = offset; 4076 info->value = value; 4077 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4078 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4079 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4080 info, 0, em_sysctl_int_delay, "I", description); 4081 } 4082 4083 static void 4084 em_set_sysctl_value(struct adapter *adapter, const char *name, 4085 const char *description, int *limit, int value) 4086 { 4087 *limit = value; 4088 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), 4089 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4090 OID_AUTO, name, CTLFLAG_RW, limit, value, description); 4091 } 4092 4093 4094 /* 4095 ** Set flow control using sysctl: 4096 ** Flow control values: 4097 ** 0 - off 4098 ** 1 - rx pause 4099 ** 2 - tx pause 4100 ** 3 - full 4101 */ 4102 static int 4103 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4104 { 4105 int error; 4106 static int input = 3; /* default is full */ 4107 struct adapter *adapter = (struct adapter *) arg1; 4108 4109 error = sysctl_handle_int(oidp, &input, 0, req); 4110 4111 if ((error) || (req->newptr == NULL)) 4112 return (error); 4113 4114 if (input == adapter->fc) /* no change? */ 4115 return (error); 4116 4117 switch (input) { 4118 case e1000_fc_rx_pause: 4119 case e1000_fc_tx_pause: 4120 case e1000_fc_full: 4121 case e1000_fc_none: 4122 adapter->hw.fc.requested_mode = input; 4123 adapter->fc = input; 4124 break; 4125 default: 4126 /* Do nothing */ 4127 return (error); 4128 } 4129 4130 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4131 e1000_force_mac_fc(&adapter->hw); 4132 return (error); 4133 } 4134 4135 /* 4136 ** Manage Energy Efficient Ethernet: 4137 ** Control values: 4138 ** 0/1 - enabled/disabled 4139 */ 4140 static int 4141 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4142 { 4143 struct adapter *adapter = (struct adapter *) arg1; 4144 int error, value; 4145 4146 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4147 error = sysctl_handle_int(oidp, &value, 0, req); 4148 if (error || req->newptr == NULL) 4149 return (error); 4150 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4151 em_if_init(adapter->ctx); 4152 4153 return (0); 4154 } 4155 4156 static int 4157 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4158 { 4159 struct adapter *adapter; 4160 int error; 4161 int result; 4162 4163 result = -1; 4164 error = sysctl_handle_int(oidp, &result, 0, req); 4165 4166 if (error || !req->newptr) 4167 return (error); 4168 4169 if (result == 1) { 4170 adapter = (struct adapter *)arg1; 4171 em_print_debug_info(adapter); 4172 } 4173 4174 return (error); 4175 } 4176 4177 /* 4178 ** This routine is meant to be fluid, add whatever is 4179 ** needed for debugging a problem. -jfv 4180 */ 4181 static void 4182 em_print_debug_info(struct adapter *adapter) 4183 { 4184 device_t dev = adapter->dev; 4185 struct tx_ring *txr = &adapter->tx_queues->txr; 4186 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4187 4188 if (if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) 4189 printf("Interface is RUNNING "); 4190 else 4191 printf("Interface is NOT RUNNING\n"); 4192 4193 if (if_getdrvflags(adapter->ifp) & IFF_DRV_OACTIVE) 4194 printf("and INACTIVE\n"); 4195 else 4196 printf("and ACTIVE\n"); 4197 4198 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4199 device_printf(dev, "TX Queue %d ------\n", i); 4200 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4201 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4202 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4203 4204 } 4205 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4206 device_printf(dev, "RX Queue %d ------\n", j); 4207 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4208 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4209 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4210 } 4211 } 4212 4213 4214 /* 4215 * 82574 only: 4216 * Write a new value to the EEPROM increasing the number of MSIX 4217 * vectors from 3 to 5, for proper multiqueue support. 4218 */ 4219 static void 4220 em_enable_vectors_82574(if_ctx_t ctx) 4221 { 4222 struct adapter *adapter = iflib_get_softc(ctx); 4223 struct e1000_hw *hw = &adapter->hw; 4224 device_t dev = iflib_get_dev(ctx); 4225 u16 edata; 4226 4227 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4228 printf("Current cap: %#06x\n", edata); 4229 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4230 device_printf(dev, "Writing to eeprom: increasing " 4231 "reported MSIX vectors from 3 to 5...\n"); 4232 edata &= ~(EM_NVM_MSIX_N_MASK); 4233 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4234 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4235 e1000_update_nvm_checksum(hw); 4236 device_printf(dev, "Writing to eeprom: done\n"); 4237 } 4238 } 4239 4240 4241 #ifdef DDB 4242 DB_COMMAND(em_reset_dev, em_ddb_reset_dev) 4243 { 4244 devclass_t dc; 4245 int max_em; 4246 4247 dc = devclass_find("em"); 4248 max_em = devclass_get_maxunit(dc); 4249 4250 for (int index = 0; index < (max_em - 1); index++) { 4251 device_t dev; 4252 dev = devclass_get_device(dc, index); 4253 if (device_get_driver(dev) == &em_driver) { 4254 struct adapter *adapter = device_get_softc(dev); 4255 em_if_init(adapter->ctx); 4256 } 4257 } 4258 } 4259 DB_COMMAND(em_dump_queue, em_ddb_dump_queue) 4260 { 4261 devclass_t dc; 4262 int max_em; 4263 4264 dc = devclass_find("em"); 4265 max_em = devclass_get_maxunit(dc); 4266 4267 for (int index = 0; index < (max_em - 1); index++) { 4268 device_t dev; 4269 dev = devclass_get_device(dc, index); 4270 if (device_get_driver(dev) == &em_driver) 4271 em_print_debug_info(device_get_softc(dev)); 4272 } 4273 4274 } 4275 #endif 4276