1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82547 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 98 99 /* Intel(R) PRO/1000 Network Connection - em */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) PRO/1000 Network Connection"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) PRO/1000 Network Connection"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) PRO/1000 Network Connection"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) PRO/1000 Network Connection"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) PRO/1000 Network Connection"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) PRO/1000 Network Connection"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) PRO/1000 Network Connection"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) PRO/1000 Network Connection"), 177 /* required last entry */ 178 PVID_END 179 }; 180 181 static pci_vendor_info_t igb_vendor_info_array[] = 182 { 183 /* Intel(R) PRO/1000 Network Connection - igb */ 184 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 214 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 215 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 216 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 217 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 218 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 219 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 220 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 221 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 222 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 223 /* required last entry */ 224 PVID_END 225 }; 226 227 /********************************************************************* 228 * Function prototypes 229 *********************************************************************/ 230 static void *em_register(device_t dev); 231 static void *igb_register(device_t dev); 232 static int em_if_attach_pre(if_ctx_t ctx); 233 static int em_if_attach_post(if_ctx_t ctx); 234 static int em_if_detach(if_ctx_t ctx); 235 static int em_if_shutdown(if_ctx_t ctx); 236 static int em_if_suspend(if_ctx_t ctx); 237 static int em_if_resume(if_ctx_t ctx); 238 239 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 240 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 241 static void em_if_queues_free(if_ctx_t ctx); 242 243 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 244 static void em_if_init(if_ctx_t ctx); 245 static void em_if_stop(if_ctx_t ctx); 246 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 247 static int em_if_media_change(if_ctx_t ctx); 248 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 249 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 250 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 251 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 252 static void em_if_watchdog_reset(if_ctx_t ctx); 253 254 static void em_identify_hardware(if_ctx_t ctx); 255 static int em_allocate_pci_resources(if_ctx_t ctx); 256 static void em_free_pci_resources(if_ctx_t ctx); 257 static void em_reset(if_ctx_t ctx); 258 static int em_setup_interface(if_ctx_t ctx); 259 static int em_setup_msix(if_ctx_t ctx); 260 261 static void em_initialize_transmit_unit(if_ctx_t ctx); 262 static void em_initialize_receive_unit(if_ctx_t ctx); 263 264 static void em_if_enable_intr(if_ctx_t ctx); 265 static void em_if_disable_intr(if_ctx_t ctx); 266 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 267 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 268 static void em_if_multi_set(if_ctx_t ctx); 269 static void em_if_update_admin_status(if_ctx_t ctx); 270 static void em_if_debug(if_ctx_t ctx); 271 static void em_update_stats_counters(struct adapter *); 272 static void em_add_hw_stats(struct adapter *adapter); 273 static int em_if_set_promisc(if_ctx_t ctx, int flags); 274 static void em_setup_vlan_hw_support(struct adapter *); 275 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 276 static void em_print_nvm_info(struct adapter *); 277 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 278 static int em_get_rs(SYSCTL_HANDLER_ARGS); 279 static void em_print_debug_info(struct adapter *); 280 static int em_is_valid_ether_addr(u8 *); 281 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 282 static void em_add_int_delay_sysctl(struct adapter *, const char *, 283 const char *, struct em_int_delay_info *, int, int); 284 /* Management and WOL Support */ 285 static void em_init_manageability(struct adapter *); 286 static void em_release_manageability(struct adapter *); 287 static void em_get_hw_control(struct adapter *); 288 static void em_release_hw_control(struct adapter *); 289 static void em_get_wakeup(if_ctx_t ctx); 290 static void em_enable_wakeup(if_ctx_t ctx); 291 static int em_enable_phy_wakeup(struct adapter *); 292 static void em_disable_aspm(struct adapter *); 293 294 int em_intr(void *arg); 295 static void em_disable_promisc(if_ctx_t ctx); 296 297 /* MSI-X handlers */ 298 static int em_if_msix_intr_assign(if_ctx_t, int); 299 static int em_msix_link(void *); 300 static void em_handle_link(void *context); 301 302 static void em_enable_vectors_82574(if_ctx_t); 303 304 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 305 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 306 static void em_if_led_func(if_ctx_t ctx, int onoff); 307 308 static int em_get_regs(SYSCTL_HANDLER_ARGS); 309 310 static void lem_smartspeed(struct adapter *adapter); 311 static void igb_configure_queues(struct adapter *adapter); 312 313 314 /********************************************************************* 315 * FreeBSD Device Interface Entry Points 316 *********************************************************************/ 317 static device_method_t em_methods[] = { 318 /* Device interface */ 319 DEVMETHOD(device_register, em_register), 320 DEVMETHOD(device_probe, iflib_device_probe), 321 DEVMETHOD(device_attach, iflib_device_attach), 322 DEVMETHOD(device_detach, iflib_device_detach), 323 DEVMETHOD(device_shutdown, iflib_device_shutdown), 324 DEVMETHOD(device_suspend, iflib_device_suspend), 325 DEVMETHOD(device_resume, iflib_device_resume), 326 DEVMETHOD_END 327 }; 328 329 static device_method_t igb_methods[] = { 330 /* Device interface */ 331 DEVMETHOD(device_register, igb_register), 332 DEVMETHOD(device_probe, iflib_device_probe), 333 DEVMETHOD(device_attach, iflib_device_attach), 334 DEVMETHOD(device_detach, iflib_device_detach), 335 DEVMETHOD(device_shutdown, iflib_device_shutdown), 336 DEVMETHOD(device_suspend, iflib_device_suspend), 337 DEVMETHOD(device_resume, iflib_device_resume), 338 DEVMETHOD_END 339 }; 340 341 342 static driver_t em_driver = { 343 "em", em_methods, sizeof(struct adapter), 344 }; 345 346 static devclass_t em_devclass; 347 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 348 349 MODULE_DEPEND(em, pci, 1, 1, 1); 350 MODULE_DEPEND(em, ether, 1, 1, 1); 351 MODULE_DEPEND(em, iflib, 1, 1, 1); 352 353 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 354 355 static driver_t igb_driver = { 356 "igb", igb_methods, sizeof(struct adapter), 357 }; 358 359 static devclass_t igb_devclass; 360 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 361 362 MODULE_DEPEND(igb, pci, 1, 1, 1); 363 MODULE_DEPEND(igb, ether, 1, 1, 1); 364 MODULE_DEPEND(igb, iflib, 1, 1, 1); 365 366 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 367 368 static device_method_t em_if_methods[] = { 369 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 370 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 371 DEVMETHOD(ifdi_detach, em_if_detach), 372 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 373 DEVMETHOD(ifdi_suspend, em_if_suspend), 374 DEVMETHOD(ifdi_resume, em_if_resume), 375 DEVMETHOD(ifdi_init, em_if_init), 376 DEVMETHOD(ifdi_stop, em_if_stop), 377 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 378 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 379 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 380 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 381 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 382 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 383 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 384 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 385 DEVMETHOD(ifdi_media_status, em_if_media_status), 386 DEVMETHOD(ifdi_media_change, em_if_media_change), 387 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 388 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 389 DEVMETHOD(ifdi_timer, em_if_timer), 390 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 391 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 392 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 393 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 394 DEVMETHOD(ifdi_led_func, em_if_led_func), 395 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 396 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 397 DEVMETHOD(ifdi_debug, em_if_debug), 398 DEVMETHOD_END 399 }; 400 401 /* 402 * note that if (adapter->msix_mem) is replaced by: 403 * if (adapter->intr_type == IFLIB_INTR_MSIX) 404 */ 405 static driver_t em_if_driver = { 406 "em_if", em_if_methods, sizeof(struct adapter) 407 }; 408 409 /********************************************************************* 410 * Tunable default values. 411 *********************************************************************/ 412 413 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 414 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 415 416 #define MAX_INTS_PER_SEC 8000 417 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 418 419 /* Allow common code without TSO */ 420 #ifndef CSUM_TSO 421 #define CSUM_TSO 0 422 #endif 423 424 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 425 426 static int em_disable_crc_stripping = 0; 427 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 428 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 429 430 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 431 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 432 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 433 0, "Default transmit interrupt delay in usecs"); 434 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 435 0, "Default receive interrupt delay in usecs"); 436 437 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 438 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 439 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 440 &em_tx_abs_int_delay_dflt, 0, 441 "Default transmit interrupt delay limit in usecs"); 442 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 443 &em_rx_abs_int_delay_dflt, 0, 444 "Default receive interrupt delay limit in usecs"); 445 446 static int em_smart_pwr_down = FALSE; 447 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 448 0, "Set to true to leave smart power down enabled on newer adapters"); 449 450 /* Controls whether promiscuous also shows bad packets */ 451 static int em_debug_sbp = TRUE; 452 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 453 "Show bad packets in promiscuous mode"); 454 455 /* How many packets rxeof tries to clean at a time */ 456 static int em_rx_process_limit = 100; 457 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 458 &em_rx_process_limit, 0, 459 "Maximum number of received packets to process " 460 "at a time, -1 means unlimited"); 461 462 /* Energy efficient ethernet - default to OFF */ 463 static int eee_setting = 1; 464 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 465 "Enable Energy Efficient Ethernet"); 466 467 /* 468 ** Tuneable Interrupt rate 469 */ 470 static int em_max_interrupt_rate = 8000; 471 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 472 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 473 474 475 476 /* Global used in WOL setup with multiport cards */ 477 static int global_quad_port_a = 0; 478 479 extern struct if_txrx igb_txrx; 480 extern struct if_txrx em_txrx; 481 extern struct if_txrx lem_txrx; 482 483 static struct if_shared_ctx em_sctx_init = { 484 .isc_magic = IFLIB_MAGIC, 485 .isc_q_align = PAGE_SIZE, 486 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 487 .isc_tx_maxsegsize = PAGE_SIZE, 488 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 489 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 490 .isc_rx_maxsize = MJUM9BYTES, 491 .isc_rx_nsegments = 1, 492 .isc_rx_maxsegsize = MJUM9BYTES, 493 .isc_nfl = 1, 494 .isc_nrxqs = 1, 495 .isc_ntxqs = 1, 496 .isc_admin_intrcnt = 1, 497 .isc_vendor_info = em_vendor_info_array, 498 .isc_driver_version = em_driver_version, 499 .isc_driver = &em_if_driver, 500 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 501 502 .isc_nrxd_min = {EM_MIN_RXD}, 503 .isc_ntxd_min = {EM_MIN_TXD}, 504 .isc_nrxd_max = {EM_MAX_RXD}, 505 .isc_ntxd_max = {EM_MAX_TXD}, 506 .isc_nrxd_default = {EM_DEFAULT_RXD}, 507 .isc_ntxd_default = {EM_DEFAULT_TXD}, 508 }; 509 510 if_shared_ctx_t em_sctx = &em_sctx_init; 511 512 static struct if_shared_ctx igb_sctx_init = { 513 .isc_magic = IFLIB_MAGIC, 514 .isc_q_align = PAGE_SIZE, 515 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 516 .isc_tx_maxsegsize = PAGE_SIZE, 517 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 518 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 519 .isc_rx_maxsize = MJUM9BYTES, 520 .isc_rx_nsegments = 1, 521 .isc_rx_maxsegsize = MJUM9BYTES, 522 .isc_nfl = 1, 523 .isc_nrxqs = 1, 524 .isc_ntxqs = 1, 525 .isc_admin_intrcnt = 1, 526 .isc_vendor_info = igb_vendor_info_array, 527 .isc_driver_version = em_driver_version, 528 .isc_driver = &em_if_driver, 529 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 530 531 .isc_nrxd_min = {EM_MIN_RXD}, 532 .isc_ntxd_min = {EM_MIN_TXD}, 533 .isc_nrxd_max = {IGB_MAX_RXD}, 534 .isc_ntxd_max = {IGB_MAX_TXD}, 535 .isc_nrxd_default = {EM_DEFAULT_RXD}, 536 .isc_ntxd_default = {EM_DEFAULT_TXD}, 537 }; 538 539 if_shared_ctx_t igb_sctx = &igb_sctx_init; 540 541 /***************************************************************** 542 * 543 * Dump Registers 544 * 545 ****************************************************************/ 546 #define IGB_REGS_LEN 739 547 548 static int em_get_regs(SYSCTL_HANDLER_ARGS) 549 { 550 struct adapter *adapter = (struct adapter *)arg1; 551 struct e1000_hw *hw = &adapter->hw; 552 struct sbuf *sb; 553 u32 *regs_buff; 554 int rc; 555 556 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 557 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 558 559 rc = sysctl_wire_old_buffer(req, 0); 560 MPASS(rc == 0); 561 if (rc != 0) { 562 free(regs_buff, M_DEVBUF); 563 return (rc); 564 } 565 566 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 567 MPASS(sb != NULL); 568 if (sb == NULL) { 569 free(regs_buff, M_DEVBUF); 570 return (ENOMEM); 571 } 572 573 /* General Registers */ 574 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 575 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 576 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 577 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 578 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 579 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 580 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 581 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 582 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 583 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 584 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 585 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 586 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 587 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 588 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 589 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 590 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 591 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 592 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 593 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 594 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 595 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 596 597 sbuf_printf(sb, "General Registers\n"); 598 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 599 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 600 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 601 602 sbuf_printf(sb, "Interrupt Registers\n"); 603 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 604 605 sbuf_printf(sb, "RX Registers\n"); 606 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 607 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 608 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 609 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 610 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 611 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 612 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 613 614 sbuf_printf(sb, "TX Registers\n"); 615 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 616 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 617 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 618 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 619 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 620 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 621 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 622 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 623 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 624 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 625 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 626 627 free(regs_buff, M_DEVBUF); 628 629 #ifdef DUMP_DESCS 630 { 631 if_softc_ctx_t scctx = adapter->shared; 632 struct rx_ring *rxr = &rx_que->rxr; 633 struct tx_ring *txr = &tx_que->txr; 634 int ntxd = scctx->isc_ntxd[0]; 635 int nrxd = scctx->isc_nrxd[0]; 636 int j; 637 638 for (j = 0; j < nrxd; j++) { 639 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 640 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 641 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 642 } 643 644 for (j = 0; j < min(ntxd, 256); j++) { 645 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 646 647 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 648 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 649 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 650 651 } 652 } 653 #endif 654 655 rc = sbuf_finish(sb); 656 sbuf_delete(sb); 657 return(rc); 658 } 659 660 static void * 661 em_register(device_t dev) 662 { 663 return (em_sctx); 664 } 665 666 static void * 667 igb_register(device_t dev) 668 { 669 return (igb_sctx); 670 } 671 672 static int 673 em_set_num_queues(if_ctx_t ctx) 674 { 675 struct adapter *adapter = iflib_get_softc(ctx); 676 int maxqueues; 677 678 /* Sanity check based on HW */ 679 switch (adapter->hw.mac.type) { 680 case e1000_82576: 681 case e1000_82580: 682 case e1000_i350: 683 case e1000_i354: 684 maxqueues = 8; 685 break; 686 case e1000_i210: 687 case e1000_82575: 688 maxqueues = 4; 689 break; 690 case e1000_i211: 691 case e1000_82574: 692 maxqueues = 2; 693 break; 694 default: 695 maxqueues = 1; 696 break; 697 } 698 699 return (maxqueues); 700 } 701 702 #define LEM_CAPS \ 703 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 704 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 705 706 #define EM_CAPS \ 707 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 708 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 709 IFCAP_LRO | IFCAP_VLAN_HWTSO 710 711 #define IGB_CAPS \ 712 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 713 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 714 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 715 IFCAP_TSO6 716 717 /********************************************************************* 718 * Device initialization routine 719 * 720 * The attach entry point is called when the driver is being loaded. 721 * This routine identifies the type of hardware, allocates all resources 722 * and initializes the hardware. 723 * 724 * return 0 on success, positive on failure 725 *********************************************************************/ 726 static int 727 em_if_attach_pre(if_ctx_t ctx) 728 { 729 struct adapter *adapter; 730 if_softc_ctx_t scctx; 731 device_t dev; 732 struct e1000_hw *hw; 733 int error = 0; 734 735 INIT_DEBUGOUT("em_if_attach_pre: begin"); 736 dev = iflib_get_dev(ctx); 737 adapter = iflib_get_softc(ctx); 738 739 adapter->ctx = adapter->osdep.ctx = ctx; 740 adapter->dev = adapter->osdep.dev = dev; 741 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 742 adapter->media = iflib_get_media(ctx); 743 hw = &adapter->hw; 744 745 adapter->tx_process_limit = scctx->isc_ntxd[0]; 746 747 /* SYSCTL stuff */ 748 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 749 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 750 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 751 em_sysctl_nvm_info, "I", "NVM Information"); 752 753 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 754 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 755 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 756 em_sysctl_debug_info, "I", "Debug Information"); 757 758 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 759 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 760 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 761 em_set_flowcntl, "I", "Flow Control"); 762 763 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 764 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 765 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 766 em_get_regs, "A", "Dump Registers"); 767 768 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 769 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 770 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 771 em_get_rs, "I", "Dump RS indexes"); 772 773 /* Determine hardware and mac info */ 774 em_identify_hardware(ctx); 775 776 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 777 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 778 if (bootverbose) 779 device_printf(dev, "attach_pre capping queues at %d\n", 780 scctx->isc_ntxqsets_max); 781 782 if (adapter->hw.mac.type >= igb_mac_min) { 783 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 784 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 785 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 786 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 787 scctx->isc_txrx = &igb_txrx; 788 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 789 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 790 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 791 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 792 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 793 CSUM_IP6_TCP | CSUM_IP6_UDP; 794 if (adapter->hw.mac.type != e1000_82575) 795 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 796 /* 797 ** Some new devices, as with ixgbe, now may 798 ** use a different BAR, so we need to keep 799 ** track of which is used. 800 */ 801 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 802 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 803 scctx->isc_msix_bar += 4; 804 } else if (adapter->hw.mac.type >= em_mac_min) { 805 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 806 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 807 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 808 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 809 scctx->isc_txrx = &em_txrx; 810 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 811 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 812 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 813 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 814 /* 815 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 816 * by default as we don't have workarounds for all associated 817 * silicon errata. E. g., with several MACs such as 82573E, 818 * TSO only works at Gigabit speed and otherwise can cause the 819 * hardware to hang (which also would be next to impossible to 820 * work around given that already queued TSO-using descriptors 821 * would need to be flushed and vlan(4) reconfigured at runtime 822 * in case of a link speed change). Moreover, MACs like 82579 823 * still can hang at Gigabit even with all publicly documented 824 * TSO workarounds implemented. Generally, the penality of 825 * these workarounds is rather high and may involve copying 826 * mbuf data around so advantages of TSO lapse. Still, TSO may 827 * work for a few MACs of this class - at least when sticking 828 * with Gigabit - in which case users may enable TSO manually. 829 */ 830 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 831 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 832 /* 833 * We support MSI-X with 82574 only, but indicate to iflib(4) 834 * that it shall give MSI at least a try with other devices. 835 */ 836 if (adapter->hw.mac.type == e1000_82574) { 837 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 838 } else { 839 scctx->isc_msix_bar = -1; 840 scctx->isc_disable_msix = 1; 841 } 842 } else { 843 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 844 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 845 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 846 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 847 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 848 scctx->isc_txrx = &lem_txrx; 849 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 850 if (adapter->hw.mac.type < e1000_82543) 851 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 852 /* INTx only */ 853 scctx->isc_msix_bar = 0; 854 } 855 856 /* Setup PCI resources */ 857 if (em_allocate_pci_resources(ctx)) { 858 device_printf(dev, "Allocation of PCI resources failed\n"); 859 error = ENXIO; 860 goto err_pci; 861 } 862 863 /* 864 ** For ICH8 and family we need to 865 ** map the flash memory, and this 866 ** must happen after the MAC is 867 ** identified 868 */ 869 if ((hw->mac.type == e1000_ich8lan) || 870 (hw->mac.type == e1000_ich9lan) || 871 (hw->mac.type == e1000_ich10lan) || 872 (hw->mac.type == e1000_pchlan) || 873 (hw->mac.type == e1000_pch2lan) || 874 (hw->mac.type == e1000_pch_lpt)) { 875 int rid = EM_BAR_TYPE_FLASH; 876 adapter->flash = bus_alloc_resource_any(dev, 877 SYS_RES_MEMORY, &rid, RF_ACTIVE); 878 if (adapter->flash == NULL) { 879 device_printf(dev, "Mapping of Flash failed\n"); 880 error = ENXIO; 881 goto err_pci; 882 } 883 /* This is used in the shared code */ 884 hw->flash_address = (u8 *)adapter->flash; 885 adapter->osdep.flash_bus_space_tag = 886 rman_get_bustag(adapter->flash); 887 adapter->osdep.flash_bus_space_handle = 888 rman_get_bushandle(adapter->flash); 889 } 890 /* 891 ** In the new SPT device flash is not a 892 ** separate BAR, rather it is also in BAR0, 893 ** so use the same tag and an offset handle for the 894 ** FLASH read/write macros in the shared code. 895 */ 896 else if (hw->mac.type >= e1000_pch_spt) { 897 adapter->osdep.flash_bus_space_tag = 898 adapter->osdep.mem_bus_space_tag; 899 adapter->osdep.flash_bus_space_handle = 900 adapter->osdep.mem_bus_space_handle 901 + E1000_FLASH_BASE_ADDR; 902 } 903 904 /* Do Shared Code initialization */ 905 error = e1000_setup_init_funcs(hw, TRUE); 906 if (error) { 907 device_printf(dev, "Setup of Shared code failed, error %d\n", 908 error); 909 error = ENXIO; 910 goto err_pci; 911 } 912 913 em_setup_msix(ctx); 914 e1000_get_bus_info(hw); 915 916 /* Set up some sysctls for the tunable interrupt delays */ 917 em_add_int_delay_sysctl(adapter, "rx_int_delay", 918 "receive interrupt delay in usecs", &adapter->rx_int_delay, 919 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 920 em_add_int_delay_sysctl(adapter, "tx_int_delay", 921 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 922 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 923 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 924 "receive interrupt delay limit in usecs", 925 &adapter->rx_abs_int_delay, 926 E1000_REGISTER(hw, E1000_RADV), 927 em_rx_abs_int_delay_dflt); 928 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 929 "transmit interrupt delay limit in usecs", 930 &adapter->tx_abs_int_delay, 931 E1000_REGISTER(hw, E1000_TADV), 932 em_tx_abs_int_delay_dflt); 933 em_add_int_delay_sysctl(adapter, "itr", 934 "interrupt delay limit in usecs/4", 935 &adapter->tx_itr, 936 E1000_REGISTER(hw, E1000_ITR), 937 DEFAULT_ITR); 938 939 hw->mac.autoneg = DO_AUTO_NEG; 940 hw->phy.autoneg_wait_to_complete = FALSE; 941 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 942 943 if (adapter->hw.mac.type < em_mac_min) { 944 e1000_init_script_state_82541(&adapter->hw, TRUE); 945 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 946 } 947 /* Copper options */ 948 if (hw->phy.media_type == e1000_media_type_copper) { 949 hw->phy.mdix = AUTO_ALL_MODES; 950 hw->phy.disable_polarity_correction = FALSE; 951 hw->phy.ms_type = EM_MASTER_SLAVE; 952 } 953 954 /* 955 * Set the frame limits assuming 956 * standard ethernet sized frames. 957 */ 958 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 959 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 960 961 /* 962 * This controls when hardware reports transmit completion 963 * status. 964 */ 965 hw->mac.report_tx_early = 1; 966 967 /* Allocate multicast array memory. */ 968 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 969 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 970 if (adapter->mta == NULL) { 971 device_printf(dev, "Can not allocate multicast setup array\n"); 972 error = ENOMEM; 973 goto err_late; 974 } 975 976 /* Check SOL/IDER usage */ 977 if (e1000_check_reset_block(hw)) 978 device_printf(dev, "PHY reset is blocked" 979 " due to SOL/IDER session.\n"); 980 981 /* Sysctl for setting Energy Efficient Ethernet */ 982 hw->dev_spec.ich8lan.eee_disable = eee_setting; 983 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 984 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 985 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 986 adapter, 0, em_sysctl_eee, "I", 987 "Disable Energy Efficient Ethernet"); 988 989 /* 990 ** Start from a known state, this is 991 ** important in reading the nvm and 992 ** mac from that. 993 */ 994 e1000_reset_hw(hw); 995 996 /* Make sure we have a good EEPROM before we read from it */ 997 if (e1000_validate_nvm_checksum(hw) < 0) { 998 /* 999 ** Some PCI-E parts fail the first check due to 1000 ** the link being in sleep state, call it again, 1001 ** if it fails a second time its a real issue. 1002 */ 1003 if (e1000_validate_nvm_checksum(hw) < 0) { 1004 device_printf(dev, 1005 "The EEPROM Checksum Is Not Valid\n"); 1006 error = EIO; 1007 goto err_late; 1008 } 1009 } 1010 1011 /* Copy the permanent MAC address out of the EEPROM */ 1012 if (e1000_read_mac_addr(hw) < 0) { 1013 device_printf(dev, "EEPROM read error while reading MAC" 1014 " address\n"); 1015 error = EIO; 1016 goto err_late; 1017 } 1018 1019 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1020 device_printf(dev, "Invalid MAC address\n"); 1021 error = EIO; 1022 goto err_late; 1023 } 1024 1025 /* Disable ULP support */ 1026 e1000_disable_ulp_lpt_lp(hw, TRUE); 1027 1028 /* 1029 * Get Wake-on-Lan and Management info for later use 1030 */ 1031 em_get_wakeup(ctx); 1032 1033 /* Enable only WOL MAGIC by default */ 1034 scctx->isc_capenable &= ~IFCAP_WOL; 1035 if (adapter->wol != 0) 1036 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1037 1038 iflib_set_mac(ctx, hw->mac.addr); 1039 1040 return (0); 1041 1042 err_late: 1043 em_release_hw_control(adapter); 1044 err_pci: 1045 em_free_pci_resources(ctx); 1046 free(adapter->mta, M_DEVBUF); 1047 1048 return (error); 1049 } 1050 1051 static int 1052 em_if_attach_post(if_ctx_t ctx) 1053 { 1054 struct adapter *adapter = iflib_get_softc(ctx); 1055 struct e1000_hw *hw = &adapter->hw; 1056 int error = 0; 1057 1058 /* Setup OS specific network interface */ 1059 error = em_setup_interface(ctx); 1060 if (error != 0) { 1061 goto err_late; 1062 } 1063 1064 em_reset(ctx); 1065 1066 /* Initialize statistics */ 1067 em_update_stats_counters(adapter); 1068 hw->mac.get_link_status = 1; 1069 em_if_update_admin_status(ctx); 1070 em_add_hw_stats(adapter); 1071 1072 /* Non-AMT based hardware can now take control from firmware */ 1073 if (adapter->has_manage && !adapter->has_amt) 1074 em_get_hw_control(adapter); 1075 1076 INIT_DEBUGOUT("em_if_attach_post: end"); 1077 1078 return (error); 1079 1080 err_late: 1081 em_release_hw_control(adapter); 1082 em_free_pci_resources(ctx); 1083 em_if_queues_free(ctx); 1084 free(adapter->mta, M_DEVBUF); 1085 1086 return (error); 1087 } 1088 1089 /********************************************************************* 1090 * Device removal routine 1091 * 1092 * The detach entry point is called when the driver is being removed. 1093 * This routine stops the adapter and deallocates all the resources 1094 * that were allocated for driver operation. 1095 * 1096 * return 0 on success, positive on failure 1097 *********************************************************************/ 1098 static int 1099 em_if_detach(if_ctx_t ctx) 1100 { 1101 struct adapter *adapter = iflib_get_softc(ctx); 1102 1103 INIT_DEBUGOUT("em_if_detach: begin"); 1104 1105 e1000_phy_hw_reset(&adapter->hw); 1106 1107 em_release_manageability(adapter); 1108 em_release_hw_control(adapter); 1109 em_free_pci_resources(ctx); 1110 1111 return (0); 1112 } 1113 1114 /********************************************************************* 1115 * 1116 * Shutdown entry point 1117 * 1118 **********************************************************************/ 1119 1120 static int 1121 em_if_shutdown(if_ctx_t ctx) 1122 { 1123 return em_if_suspend(ctx); 1124 } 1125 1126 /* 1127 * Suspend/resume device methods. 1128 */ 1129 static int 1130 em_if_suspend(if_ctx_t ctx) 1131 { 1132 struct adapter *adapter = iflib_get_softc(ctx); 1133 1134 em_release_manageability(adapter); 1135 em_release_hw_control(adapter); 1136 em_enable_wakeup(ctx); 1137 return (0); 1138 } 1139 1140 static int 1141 em_if_resume(if_ctx_t ctx) 1142 { 1143 struct adapter *adapter = iflib_get_softc(ctx); 1144 1145 if (adapter->hw.mac.type == e1000_pch2lan) 1146 e1000_resume_workarounds_pchlan(&adapter->hw); 1147 em_if_init(ctx); 1148 em_init_manageability(adapter); 1149 1150 return(0); 1151 } 1152 1153 static int 1154 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1155 { 1156 int max_frame_size; 1157 struct adapter *adapter = iflib_get_softc(ctx); 1158 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1159 1160 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1161 1162 switch (adapter->hw.mac.type) { 1163 case e1000_82571: 1164 case e1000_82572: 1165 case e1000_ich9lan: 1166 case e1000_ich10lan: 1167 case e1000_pch2lan: 1168 case e1000_pch_lpt: 1169 case e1000_pch_spt: 1170 case e1000_pch_cnp: 1171 case e1000_82574: 1172 case e1000_82583: 1173 case e1000_80003es2lan: 1174 /* 9K Jumbo Frame size */ 1175 max_frame_size = 9234; 1176 break; 1177 case e1000_pchlan: 1178 max_frame_size = 4096; 1179 break; 1180 case e1000_82542: 1181 case e1000_ich8lan: 1182 /* Adapters that do not support jumbo frames */ 1183 max_frame_size = ETHER_MAX_LEN; 1184 break; 1185 default: 1186 if (adapter->hw.mac.type >= igb_mac_min) 1187 max_frame_size = 9234; 1188 else /* lem */ 1189 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1190 } 1191 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1192 return (EINVAL); 1193 } 1194 1195 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1196 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1197 return (0); 1198 } 1199 1200 /********************************************************************* 1201 * Init entry point 1202 * 1203 * This routine is used in two ways. It is used by the stack as 1204 * init entry point in network interface structure. It is also used 1205 * by the driver as a hw/sw initialization routine to get to a 1206 * consistent state. 1207 * 1208 **********************************************************************/ 1209 static void 1210 em_if_init(if_ctx_t ctx) 1211 { 1212 struct adapter *adapter = iflib_get_softc(ctx); 1213 if_softc_ctx_t scctx = adapter->shared; 1214 struct ifnet *ifp = iflib_get_ifp(ctx); 1215 struct em_tx_queue *tx_que; 1216 int i; 1217 1218 INIT_DEBUGOUT("em_if_init: begin"); 1219 1220 /* Get the latest mac address, User can use a LAA */ 1221 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1222 ETHER_ADDR_LEN); 1223 1224 /* Put the address into the Receive Address Array */ 1225 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1226 1227 /* 1228 * With the 82571 adapter, RAR[0] may be overwritten 1229 * when the other port is reset, we make a duplicate 1230 * in RAR[14] for that eventuality, this assures 1231 * the interface continues to function. 1232 */ 1233 if (adapter->hw.mac.type == e1000_82571) { 1234 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1235 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1236 E1000_RAR_ENTRIES - 1); 1237 } 1238 1239 1240 /* Initialize the hardware */ 1241 em_reset(ctx); 1242 em_if_update_admin_status(ctx); 1243 1244 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1245 struct tx_ring *txr = &tx_que->txr; 1246 1247 txr->tx_rs_cidx = txr->tx_rs_pidx; 1248 1249 /* Initialize the last processed descriptor to be the end of 1250 * the ring, rather than the start, so that we avoid an 1251 * off-by-one error when calculating how many descriptors are 1252 * done in the credits_update function. 1253 */ 1254 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1255 } 1256 1257 /* Setup VLAN support, basic and offload if available */ 1258 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1259 1260 /* Clear bad data from Rx FIFOs */ 1261 if (adapter->hw.mac.type >= igb_mac_min) 1262 e1000_rx_fifo_flush_82575(&adapter->hw); 1263 1264 /* Configure for OS presence */ 1265 em_init_manageability(adapter); 1266 1267 /* Prepare transmit descriptors and buffers */ 1268 em_initialize_transmit_unit(ctx); 1269 1270 /* Setup Multicast table */ 1271 em_if_multi_set(ctx); 1272 1273 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1274 em_initialize_receive_unit(ctx); 1275 1276 /* Use real VLAN Filter support? */ 1277 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1278 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1279 /* Use real VLAN Filter support */ 1280 em_setup_vlan_hw_support(adapter); 1281 else { 1282 u32 ctrl; 1283 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1284 ctrl |= E1000_CTRL_VME; 1285 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1286 } 1287 } 1288 1289 /* Don't lose promiscuous settings */ 1290 em_if_set_promisc(ctx, IFF_PROMISC); 1291 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1292 1293 /* MSI-X configuration for 82574 */ 1294 if (adapter->hw.mac.type == e1000_82574) { 1295 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1296 1297 tmp |= E1000_CTRL_EXT_PBA_CLR; 1298 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1299 /* Set the IVAR - interrupt vector routing. */ 1300 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1301 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1302 igb_configure_queues(adapter); 1303 1304 /* this clears any pending interrupts */ 1305 E1000_READ_REG(&adapter->hw, E1000_ICR); 1306 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1307 1308 /* AMT based hardware can now take control from firmware */ 1309 if (adapter->has_manage && adapter->has_amt) 1310 em_get_hw_control(adapter); 1311 1312 /* Set Energy Efficient Ethernet */ 1313 if (adapter->hw.mac.type >= igb_mac_min && 1314 adapter->hw.phy.media_type == e1000_media_type_copper) { 1315 if (adapter->hw.mac.type == e1000_i354) 1316 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1317 else 1318 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1319 } 1320 } 1321 1322 /********************************************************************* 1323 * 1324 * Fast Legacy/MSI Combined Interrupt Service routine 1325 * 1326 *********************************************************************/ 1327 int 1328 em_intr(void *arg) 1329 { 1330 struct adapter *adapter = arg; 1331 if_ctx_t ctx = adapter->ctx; 1332 u32 reg_icr; 1333 1334 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1335 1336 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1337 goto skip_stray; 1338 /* Hot eject? */ 1339 if (reg_icr == 0xffffffff) 1340 return FILTER_STRAY; 1341 1342 /* Definitely not our interrupt. */ 1343 if (reg_icr == 0x0) 1344 return FILTER_STRAY; 1345 1346 /* 1347 * Starting with the 82571 chip, bit 31 should be used to 1348 * determine whether the interrupt belongs to us. 1349 */ 1350 if (adapter->hw.mac.type >= e1000_82571 && 1351 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1352 return FILTER_STRAY; 1353 1354 skip_stray: 1355 /* Link status change */ 1356 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1357 adapter->hw.mac.get_link_status = 1; 1358 iflib_admin_intr_deferred(ctx); 1359 } 1360 1361 if (reg_icr & E1000_ICR_RXO) 1362 adapter->rx_overruns++; 1363 1364 return (FILTER_SCHEDULE_THREAD); 1365 } 1366 1367 static void 1368 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1369 { 1370 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1371 } 1372 1373 static void 1374 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1375 { 1376 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1377 } 1378 1379 static void 1380 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1381 { 1382 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1383 } 1384 1385 static void 1386 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1387 { 1388 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1389 } 1390 1391 static int 1392 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1393 { 1394 struct adapter *adapter = iflib_get_softc(ctx); 1395 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1396 1397 if (adapter->hw.mac.type >= igb_mac_min) 1398 igb_rx_enable_queue(adapter, rxq); 1399 else 1400 em_rx_enable_queue(adapter, rxq); 1401 return (0); 1402 } 1403 1404 static int 1405 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1406 { 1407 struct adapter *adapter = iflib_get_softc(ctx); 1408 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1409 1410 if (adapter->hw.mac.type >= igb_mac_min) 1411 igb_tx_enable_queue(adapter, txq); 1412 else 1413 em_tx_enable_queue(adapter, txq); 1414 return (0); 1415 } 1416 1417 /********************************************************************* 1418 * 1419 * MSI-X RX Interrupt Service routine 1420 * 1421 **********************************************************************/ 1422 static int 1423 em_msix_que(void *arg) 1424 { 1425 struct em_rx_queue *que = arg; 1426 1427 ++que->irqs; 1428 1429 return (FILTER_SCHEDULE_THREAD); 1430 } 1431 1432 /********************************************************************* 1433 * 1434 * MSI-X Link Fast Interrupt Service routine 1435 * 1436 **********************************************************************/ 1437 static int 1438 em_msix_link(void *arg) 1439 { 1440 struct adapter *adapter = arg; 1441 u32 reg_icr; 1442 1443 ++adapter->link_irq; 1444 MPASS(adapter->hw.back != NULL); 1445 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1446 1447 if (reg_icr & E1000_ICR_RXO) 1448 adapter->rx_overruns++; 1449 1450 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1451 em_handle_link(adapter->ctx); 1452 } else { 1453 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1454 EM_MSIX_LINK | E1000_IMS_LSC); 1455 if (adapter->hw.mac.type >= igb_mac_min) 1456 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1457 } 1458 1459 /* 1460 * Because we must read the ICR for this interrupt 1461 * it may clear other causes using autoclear, for 1462 * this reason we simply create a soft interrupt 1463 * for all these vectors. 1464 */ 1465 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1466 E1000_WRITE_REG(&adapter->hw, 1467 E1000_ICS, adapter->ims); 1468 } 1469 1470 return (FILTER_HANDLED); 1471 } 1472 1473 static void 1474 em_handle_link(void *context) 1475 { 1476 if_ctx_t ctx = context; 1477 struct adapter *adapter = iflib_get_softc(ctx); 1478 1479 adapter->hw.mac.get_link_status = 1; 1480 iflib_admin_intr_deferred(ctx); 1481 } 1482 1483 1484 /********************************************************************* 1485 * 1486 * Media Ioctl callback 1487 * 1488 * This routine is called whenever the user queries the status of 1489 * the interface using ifconfig. 1490 * 1491 **********************************************************************/ 1492 static void 1493 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1494 { 1495 struct adapter *adapter = iflib_get_softc(ctx); 1496 u_char fiber_type = IFM_1000_SX; 1497 1498 INIT_DEBUGOUT("em_if_media_status: begin"); 1499 1500 iflib_admin_intr_deferred(ctx); 1501 1502 ifmr->ifm_status = IFM_AVALID; 1503 ifmr->ifm_active = IFM_ETHER; 1504 1505 if (!adapter->link_active) { 1506 return; 1507 } 1508 1509 ifmr->ifm_status |= IFM_ACTIVE; 1510 1511 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1512 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1513 if (adapter->hw.mac.type == e1000_82545) 1514 fiber_type = IFM_1000_LX; 1515 ifmr->ifm_active |= fiber_type | IFM_FDX; 1516 } else { 1517 switch (adapter->link_speed) { 1518 case 10: 1519 ifmr->ifm_active |= IFM_10_T; 1520 break; 1521 case 100: 1522 ifmr->ifm_active |= IFM_100_TX; 1523 break; 1524 case 1000: 1525 ifmr->ifm_active |= IFM_1000_T; 1526 break; 1527 } 1528 if (adapter->link_duplex == FULL_DUPLEX) 1529 ifmr->ifm_active |= IFM_FDX; 1530 else 1531 ifmr->ifm_active |= IFM_HDX; 1532 } 1533 } 1534 1535 /********************************************************************* 1536 * 1537 * Media Ioctl callback 1538 * 1539 * This routine is called when the user changes speed/duplex using 1540 * media/mediopt option with ifconfig. 1541 * 1542 **********************************************************************/ 1543 static int 1544 em_if_media_change(if_ctx_t ctx) 1545 { 1546 struct adapter *adapter = iflib_get_softc(ctx); 1547 struct ifmedia *ifm = iflib_get_media(ctx); 1548 1549 INIT_DEBUGOUT("em_if_media_change: begin"); 1550 1551 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1552 return (EINVAL); 1553 1554 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1555 case IFM_AUTO: 1556 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1557 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1558 break; 1559 case IFM_1000_LX: 1560 case IFM_1000_SX: 1561 case IFM_1000_T: 1562 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1563 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1564 break; 1565 case IFM_100_TX: 1566 adapter->hw.mac.autoneg = FALSE; 1567 adapter->hw.phy.autoneg_advertised = 0; 1568 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1569 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1570 else 1571 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1572 break; 1573 case IFM_10_T: 1574 adapter->hw.mac.autoneg = FALSE; 1575 adapter->hw.phy.autoneg_advertised = 0; 1576 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1577 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1578 else 1579 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1580 break; 1581 default: 1582 device_printf(adapter->dev, "Unsupported media type\n"); 1583 } 1584 1585 em_if_init(ctx); 1586 1587 return (0); 1588 } 1589 1590 static int 1591 em_if_set_promisc(if_ctx_t ctx, int flags) 1592 { 1593 struct adapter *adapter = iflib_get_softc(ctx); 1594 u32 reg_rctl; 1595 1596 em_disable_promisc(ctx); 1597 1598 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1599 1600 if (flags & IFF_PROMISC) { 1601 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1602 /* Turn this on if you want to see bad packets */ 1603 if (em_debug_sbp) 1604 reg_rctl |= E1000_RCTL_SBP; 1605 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1606 } else if (flags & IFF_ALLMULTI) { 1607 reg_rctl |= E1000_RCTL_MPE; 1608 reg_rctl &= ~E1000_RCTL_UPE; 1609 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1610 } 1611 return (0); 1612 } 1613 1614 static void 1615 em_disable_promisc(if_ctx_t ctx) 1616 { 1617 struct adapter *adapter = iflib_get_softc(ctx); 1618 struct ifnet *ifp = iflib_get_ifp(ctx); 1619 u32 reg_rctl; 1620 int mcnt = 0; 1621 1622 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1623 reg_rctl &= (~E1000_RCTL_UPE); 1624 if (if_getflags(ifp) & IFF_ALLMULTI) 1625 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1626 else 1627 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1628 /* Don't disable if in MAX groups */ 1629 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1630 reg_rctl &= (~E1000_RCTL_MPE); 1631 reg_rctl &= (~E1000_RCTL_SBP); 1632 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1633 } 1634 1635 1636 /********************************************************************* 1637 * Multicast Update 1638 * 1639 * This routine is called whenever multicast address list is updated. 1640 * 1641 **********************************************************************/ 1642 1643 static void 1644 em_if_multi_set(if_ctx_t ctx) 1645 { 1646 struct adapter *adapter = iflib_get_softc(ctx); 1647 struct ifnet *ifp = iflib_get_ifp(ctx); 1648 u32 reg_rctl = 0; 1649 u8 *mta; /* Multicast array memory */ 1650 int mcnt = 0; 1651 1652 IOCTL_DEBUGOUT("em_set_multi: begin"); 1653 1654 mta = adapter->mta; 1655 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1656 1657 if (adapter->hw.mac.type == e1000_82542 && 1658 adapter->hw.revision_id == E1000_REVISION_2) { 1659 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1660 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1661 e1000_pci_clear_mwi(&adapter->hw); 1662 reg_rctl |= E1000_RCTL_RST; 1663 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1664 msec_delay(5); 1665 } 1666 1667 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1668 1669 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1670 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1671 reg_rctl |= E1000_RCTL_MPE; 1672 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1673 } else 1674 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1675 1676 if (adapter->hw.mac.type == e1000_82542 && 1677 adapter->hw.revision_id == E1000_REVISION_2) { 1678 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1679 reg_rctl &= ~E1000_RCTL_RST; 1680 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1681 msec_delay(5); 1682 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1683 e1000_pci_set_mwi(&adapter->hw); 1684 } 1685 } 1686 1687 /********************************************************************* 1688 * Timer routine 1689 * 1690 * This routine schedules em_if_update_admin_status() to check for 1691 * link status and to gather statistics as well as to perform some 1692 * controller-specific hardware patting. 1693 * 1694 **********************************************************************/ 1695 static void 1696 em_if_timer(if_ctx_t ctx, uint16_t qid) 1697 { 1698 1699 if (qid != 0) 1700 return; 1701 1702 iflib_admin_intr_deferred(ctx); 1703 } 1704 1705 static void 1706 em_if_update_admin_status(if_ctx_t ctx) 1707 { 1708 struct adapter *adapter = iflib_get_softc(ctx); 1709 struct e1000_hw *hw = &adapter->hw; 1710 device_t dev = iflib_get_dev(ctx); 1711 u32 link_check, thstat, ctrl; 1712 1713 link_check = thstat = ctrl = 0; 1714 /* Get the cached link value or read phy for real */ 1715 switch (hw->phy.media_type) { 1716 case e1000_media_type_copper: 1717 if (hw->mac.get_link_status) { 1718 if (hw->mac.type == e1000_pch_spt) 1719 msec_delay(50); 1720 /* Do the work to read phy */ 1721 e1000_check_for_link(hw); 1722 link_check = !hw->mac.get_link_status; 1723 if (link_check) /* ESB2 fix */ 1724 e1000_cfg_on_link_up(hw); 1725 } else { 1726 link_check = TRUE; 1727 } 1728 break; 1729 case e1000_media_type_fiber: 1730 e1000_check_for_link(hw); 1731 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1732 E1000_STATUS_LU); 1733 break; 1734 case e1000_media_type_internal_serdes: 1735 e1000_check_for_link(hw); 1736 link_check = adapter->hw.mac.serdes_has_link; 1737 break; 1738 /* VF device is type_unknown */ 1739 case e1000_media_type_unknown: 1740 e1000_check_for_link(hw); 1741 link_check = !hw->mac.get_link_status; 1742 /* FALLTHROUGH */ 1743 default: 1744 break; 1745 } 1746 1747 /* Check for thermal downshift or shutdown */ 1748 if (hw->mac.type == e1000_i350) { 1749 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1750 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1751 } 1752 1753 /* Now check for a transition */ 1754 if (link_check && (adapter->link_active == 0)) { 1755 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1756 &adapter->link_duplex); 1757 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1758 if ((adapter->link_speed != SPEED_1000) && 1759 ((hw->mac.type == e1000_82571) || 1760 (hw->mac.type == e1000_82572))) { 1761 int tarc0; 1762 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1763 tarc0 &= ~TARC_SPEED_MODE_BIT; 1764 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1765 } 1766 if (bootverbose) 1767 device_printf(dev, "Link is up %d Mbps %s\n", 1768 adapter->link_speed, 1769 ((adapter->link_duplex == FULL_DUPLEX) ? 1770 "Full Duplex" : "Half Duplex")); 1771 adapter->link_active = 1; 1772 adapter->smartspeed = 0; 1773 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1774 E1000_CTRL_EXT_LINK_MODE_GMII && 1775 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1776 device_printf(dev, "Link: thermal downshift\n"); 1777 /* Delay Link Up for Phy update */ 1778 if (((hw->mac.type == e1000_i210) || 1779 (hw->mac.type == e1000_i211)) && 1780 (hw->phy.id == I210_I_PHY_ID)) 1781 msec_delay(I210_LINK_DELAY); 1782 /* Reset if the media type changed. */ 1783 if ((hw->dev_spec._82575.media_changed) && 1784 (adapter->hw.mac.type >= igb_mac_min)) { 1785 hw->dev_spec._82575.media_changed = false; 1786 adapter->flags |= IGB_MEDIA_RESET; 1787 em_reset(ctx); 1788 } 1789 iflib_link_state_change(ctx, LINK_STATE_UP, 1790 IF_Mbps(adapter->link_speed)); 1791 } else if (!link_check && (adapter->link_active == 1)) { 1792 adapter->link_speed = 0; 1793 adapter->link_duplex = 0; 1794 adapter->link_active = 0; 1795 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1796 } 1797 em_update_stats_counters(adapter); 1798 1799 /* Reset LAA into RAR[0] on 82571 */ 1800 if ((adapter->hw.mac.type == e1000_82571) && 1801 e1000_get_laa_state_82571(&adapter->hw)) 1802 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1803 1804 if (adapter->hw.mac.type < em_mac_min) 1805 lem_smartspeed(adapter); 1806 1807 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1808 } 1809 1810 static void 1811 em_if_watchdog_reset(if_ctx_t ctx) 1812 { 1813 struct adapter *adapter = iflib_get_softc(ctx); 1814 1815 /* 1816 * Just count the event; iflib(4) will already trigger a 1817 * sufficient reset of the controller. 1818 */ 1819 adapter->watchdog_events++; 1820 } 1821 1822 /********************************************************************* 1823 * 1824 * This routine disables all traffic on the adapter by issuing a 1825 * global reset on the MAC. 1826 * 1827 **********************************************************************/ 1828 static void 1829 em_if_stop(if_ctx_t ctx) 1830 { 1831 struct adapter *adapter = iflib_get_softc(ctx); 1832 1833 INIT_DEBUGOUT("em_if_stop: begin"); 1834 1835 e1000_reset_hw(&adapter->hw); 1836 if (adapter->hw.mac.type >= e1000_82544) 1837 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1838 1839 e1000_led_off(&adapter->hw); 1840 e1000_cleanup_led(&adapter->hw); 1841 } 1842 1843 /********************************************************************* 1844 * 1845 * Determine hardware revision. 1846 * 1847 **********************************************************************/ 1848 static void 1849 em_identify_hardware(if_ctx_t ctx) 1850 { 1851 device_t dev = iflib_get_dev(ctx); 1852 struct adapter *adapter = iflib_get_softc(ctx); 1853 1854 /* Make sure our PCI config space has the necessary stuff set */ 1855 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1856 1857 /* Save off the information about this board */ 1858 adapter->hw.vendor_id = pci_get_vendor(dev); 1859 adapter->hw.device_id = pci_get_device(dev); 1860 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1861 adapter->hw.subsystem_vendor_id = 1862 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1863 adapter->hw.subsystem_device_id = 1864 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1865 1866 /* Do Shared Code Init and Setup */ 1867 if (e1000_set_mac_type(&adapter->hw)) { 1868 device_printf(dev, "Setup init failure\n"); 1869 return; 1870 } 1871 } 1872 1873 static int 1874 em_allocate_pci_resources(if_ctx_t ctx) 1875 { 1876 struct adapter *adapter = iflib_get_softc(ctx); 1877 device_t dev = iflib_get_dev(ctx); 1878 int rid, val; 1879 1880 rid = PCIR_BAR(0); 1881 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1882 &rid, RF_ACTIVE); 1883 if (adapter->memory == NULL) { 1884 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1885 return (ENXIO); 1886 } 1887 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1888 adapter->osdep.mem_bus_space_handle = 1889 rman_get_bushandle(adapter->memory); 1890 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1891 1892 /* Only older adapters use IO mapping */ 1893 if (adapter->hw.mac.type < em_mac_min && 1894 adapter->hw.mac.type > e1000_82543) { 1895 /* Figure our where our IO BAR is ? */ 1896 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1897 val = pci_read_config(dev, rid, 4); 1898 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1899 break; 1900 } 1901 rid += 4; 1902 /* check for 64bit BAR */ 1903 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1904 rid += 4; 1905 } 1906 if (rid >= PCIR_CIS) { 1907 device_printf(dev, "Unable to locate IO BAR\n"); 1908 return (ENXIO); 1909 } 1910 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1911 &rid, RF_ACTIVE); 1912 if (adapter->ioport == NULL) { 1913 device_printf(dev, "Unable to allocate bus resource: " 1914 "ioport\n"); 1915 return (ENXIO); 1916 } 1917 adapter->hw.io_base = 0; 1918 adapter->osdep.io_bus_space_tag = 1919 rman_get_bustag(adapter->ioport); 1920 adapter->osdep.io_bus_space_handle = 1921 rman_get_bushandle(adapter->ioport); 1922 } 1923 1924 adapter->hw.back = &adapter->osdep; 1925 1926 return (0); 1927 } 1928 1929 /********************************************************************* 1930 * 1931 * Set up the MSI-X Interrupt handlers 1932 * 1933 **********************************************************************/ 1934 static int 1935 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1936 { 1937 struct adapter *adapter = iflib_get_softc(ctx); 1938 struct em_rx_queue *rx_que = adapter->rx_queues; 1939 struct em_tx_queue *tx_que = adapter->tx_queues; 1940 int error, rid, i, vector = 0, rx_vectors; 1941 char buf[16]; 1942 1943 /* First set up ring resources */ 1944 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1945 rid = vector + 1; 1946 snprintf(buf, sizeof(buf), "rxq%d", i); 1947 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1948 if (error) { 1949 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1950 adapter->rx_num_queues = i + 1; 1951 goto fail; 1952 } 1953 1954 rx_que->msix = vector; 1955 1956 /* 1957 * Set the bit to enable interrupt 1958 * in E1000_IMS -- bits 20 and 21 1959 * are for RX0 and RX1, note this has 1960 * NOTHING to do with the MSI-X vector 1961 */ 1962 if (adapter->hw.mac.type == e1000_82574) { 1963 rx_que->eims = 1 << (20 + i); 1964 adapter->ims |= rx_que->eims; 1965 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1966 } else if (adapter->hw.mac.type == e1000_82575) 1967 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1968 else 1969 rx_que->eims = 1 << vector; 1970 } 1971 rx_vectors = vector; 1972 1973 vector = 0; 1974 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1975 snprintf(buf, sizeof(buf), "txq%d", i); 1976 tx_que = &adapter->tx_queues[i]; 1977 iflib_softirq_alloc_generic(ctx, 1978 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1979 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1980 1981 tx_que->msix = (vector % adapter->rx_num_queues); 1982 1983 /* 1984 * Set the bit to enable interrupt 1985 * in E1000_IMS -- bits 22 and 23 1986 * are for TX0 and TX1, note this has 1987 * NOTHING to do with the MSI-X vector 1988 */ 1989 if (adapter->hw.mac.type == e1000_82574) { 1990 tx_que->eims = 1 << (22 + i); 1991 adapter->ims |= tx_que->eims; 1992 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1993 } else if (adapter->hw.mac.type == e1000_82575) { 1994 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 1995 } else { 1996 tx_que->eims = 1 << i; 1997 } 1998 } 1999 2000 /* Link interrupt */ 2001 rid = rx_vectors + 1; 2002 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2003 2004 if (error) { 2005 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2006 goto fail; 2007 } 2008 adapter->linkvec = rx_vectors; 2009 if (adapter->hw.mac.type < igb_mac_min) { 2010 adapter->ivars |= (8 | rx_vectors) << 16; 2011 adapter->ivars |= 0x80000000; 2012 } 2013 return (0); 2014 fail: 2015 iflib_irq_free(ctx, &adapter->irq); 2016 rx_que = adapter->rx_queues; 2017 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2018 iflib_irq_free(ctx, &rx_que->que_irq); 2019 return (error); 2020 } 2021 2022 static void 2023 igb_configure_queues(struct adapter *adapter) 2024 { 2025 struct e1000_hw *hw = &adapter->hw; 2026 struct em_rx_queue *rx_que; 2027 struct em_tx_queue *tx_que; 2028 u32 tmp, ivar = 0, newitr = 0; 2029 2030 /* First turn on RSS capability */ 2031 if (adapter->hw.mac.type != e1000_82575) 2032 E1000_WRITE_REG(hw, E1000_GPIE, 2033 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2034 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2035 2036 /* Turn on MSI-X */ 2037 switch (adapter->hw.mac.type) { 2038 case e1000_82580: 2039 case e1000_i350: 2040 case e1000_i354: 2041 case e1000_i210: 2042 case e1000_i211: 2043 case e1000_vfadapt: 2044 case e1000_vfadapt_i350: 2045 /* RX entries */ 2046 for (int i = 0; i < adapter->rx_num_queues; i++) { 2047 u32 index = i >> 1; 2048 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2049 rx_que = &adapter->rx_queues[i]; 2050 if (i & 1) { 2051 ivar &= 0xFF00FFFF; 2052 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2053 } else { 2054 ivar &= 0xFFFFFF00; 2055 ivar |= rx_que->msix | E1000_IVAR_VALID; 2056 } 2057 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2058 } 2059 /* TX entries */ 2060 for (int i = 0; i < adapter->tx_num_queues; i++) { 2061 u32 index = i >> 1; 2062 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2063 tx_que = &adapter->tx_queues[i]; 2064 if (i & 1) { 2065 ivar &= 0x00FFFFFF; 2066 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2067 } else { 2068 ivar &= 0xFFFF00FF; 2069 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2070 } 2071 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2072 adapter->que_mask |= tx_que->eims; 2073 } 2074 2075 /* And for the link interrupt */ 2076 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2077 adapter->link_mask = 1 << adapter->linkvec; 2078 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2079 break; 2080 case e1000_82576: 2081 /* RX entries */ 2082 for (int i = 0; i < adapter->rx_num_queues; i++) { 2083 u32 index = i & 0x7; /* Each IVAR has two entries */ 2084 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2085 rx_que = &adapter->rx_queues[i]; 2086 if (i < 8) { 2087 ivar &= 0xFFFFFF00; 2088 ivar |= rx_que->msix | E1000_IVAR_VALID; 2089 } else { 2090 ivar &= 0xFF00FFFF; 2091 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2092 } 2093 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2094 adapter->que_mask |= rx_que->eims; 2095 } 2096 /* TX entries */ 2097 for (int i = 0; i < adapter->tx_num_queues; i++) { 2098 u32 index = i & 0x7; /* Each IVAR has two entries */ 2099 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2100 tx_que = &adapter->tx_queues[i]; 2101 if (i < 8) { 2102 ivar &= 0xFFFF00FF; 2103 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2104 } else { 2105 ivar &= 0x00FFFFFF; 2106 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2107 } 2108 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2109 adapter->que_mask |= tx_que->eims; 2110 } 2111 2112 /* And for the link interrupt */ 2113 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2114 adapter->link_mask = 1 << adapter->linkvec; 2115 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2116 break; 2117 2118 case e1000_82575: 2119 /* enable MSI-X support*/ 2120 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2121 tmp |= E1000_CTRL_EXT_PBA_CLR; 2122 /* Auto-Mask interrupts upon ICR read. */ 2123 tmp |= E1000_CTRL_EXT_EIAME; 2124 tmp |= E1000_CTRL_EXT_IRCA; 2125 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2126 2127 /* Queues */ 2128 for (int i = 0; i < adapter->rx_num_queues; i++) { 2129 rx_que = &adapter->rx_queues[i]; 2130 tmp = E1000_EICR_RX_QUEUE0 << i; 2131 tmp |= E1000_EICR_TX_QUEUE0 << i; 2132 rx_que->eims = tmp; 2133 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2134 i, rx_que->eims); 2135 adapter->que_mask |= rx_que->eims; 2136 } 2137 2138 /* Link */ 2139 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2140 E1000_EIMS_OTHER); 2141 adapter->link_mask |= E1000_EIMS_OTHER; 2142 default: 2143 break; 2144 } 2145 2146 /* Set the starting interrupt rate */ 2147 if (em_max_interrupt_rate > 0) 2148 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2149 2150 if (hw->mac.type == e1000_82575) 2151 newitr |= newitr << 16; 2152 else 2153 newitr |= E1000_EITR_CNT_IGNR; 2154 2155 for (int i = 0; i < adapter->rx_num_queues; i++) { 2156 rx_que = &adapter->rx_queues[i]; 2157 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2158 } 2159 2160 return; 2161 } 2162 2163 static void 2164 em_free_pci_resources(if_ctx_t ctx) 2165 { 2166 struct adapter *adapter = iflib_get_softc(ctx); 2167 struct em_rx_queue *que = adapter->rx_queues; 2168 device_t dev = iflib_get_dev(ctx); 2169 2170 /* Release all MSI-X queue resources */ 2171 if (adapter->intr_type == IFLIB_INTR_MSIX) 2172 iflib_irq_free(ctx, &adapter->irq); 2173 2174 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2175 iflib_irq_free(ctx, &que->que_irq); 2176 } 2177 2178 if (adapter->memory != NULL) { 2179 bus_release_resource(dev, SYS_RES_MEMORY, 2180 rman_get_rid(adapter->memory), adapter->memory); 2181 adapter->memory = NULL; 2182 } 2183 2184 if (adapter->flash != NULL) { 2185 bus_release_resource(dev, SYS_RES_MEMORY, 2186 rman_get_rid(adapter->flash), adapter->flash); 2187 adapter->flash = NULL; 2188 } 2189 2190 if (adapter->ioport != NULL) { 2191 bus_release_resource(dev, SYS_RES_IOPORT, 2192 rman_get_rid(adapter->ioport), adapter->ioport); 2193 adapter->ioport = NULL; 2194 } 2195 } 2196 2197 /* Set up MSI or MSI-X */ 2198 static int 2199 em_setup_msix(if_ctx_t ctx) 2200 { 2201 struct adapter *adapter = iflib_get_softc(ctx); 2202 2203 if (adapter->hw.mac.type == e1000_82574) { 2204 em_enable_vectors_82574(ctx); 2205 } 2206 return (0); 2207 } 2208 2209 /********************************************************************* 2210 * 2211 * Workaround for SmartSpeed on 82541 and 82547 controllers 2212 * 2213 **********************************************************************/ 2214 static void 2215 lem_smartspeed(struct adapter *adapter) 2216 { 2217 u16 phy_tmp; 2218 2219 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2220 adapter->hw.mac.autoneg == 0 || 2221 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2222 return; 2223 2224 if (adapter->smartspeed == 0) { 2225 /* If Master/Slave config fault is asserted twice, 2226 * we assume back-to-back */ 2227 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2228 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2229 return; 2230 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2231 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2232 e1000_read_phy_reg(&adapter->hw, 2233 PHY_1000T_CTRL, &phy_tmp); 2234 if(phy_tmp & CR_1000T_MS_ENABLE) { 2235 phy_tmp &= ~CR_1000T_MS_ENABLE; 2236 e1000_write_phy_reg(&adapter->hw, 2237 PHY_1000T_CTRL, phy_tmp); 2238 adapter->smartspeed++; 2239 if(adapter->hw.mac.autoneg && 2240 !e1000_copper_link_autoneg(&adapter->hw) && 2241 !e1000_read_phy_reg(&adapter->hw, 2242 PHY_CONTROL, &phy_tmp)) { 2243 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2244 MII_CR_RESTART_AUTO_NEG); 2245 e1000_write_phy_reg(&adapter->hw, 2246 PHY_CONTROL, phy_tmp); 2247 } 2248 } 2249 } 2250 return; 2251 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2252 /* If still no link, perhaps using 2/3 pair cable */ 2253 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2254 phy_tmp |= CR_1000T_MS_ENABLE; 2255 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2256 if(adapter->hw.mac.autoneg && 2257 !e1000_copper_link_autoneg(&adapter->hw) && 2258 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2259 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2260 MII_CR_RESTART_AUTO_NEG); 2261 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2262 } 2263 } 2264 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2265 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2266 adapter->smartspeed = 0; 2267 } 2268 2269 /********************************************************************* 2270 * 2271 * Initialize the DMA Coalescing feature 2272 * 2273 **********************************************************************/ 2274 static void 2275 igb_init_dmac(struct adapter *adapter, u32 pba) 2276 { 2277 device_t dev = adapter->dev; 2278 struct e1000_hw *hw = &adapter->hw; 2279 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2280 u16 hwm; 2281 u16 max_frame_size; 2282 2283 if (hw->mac.type == e1000_i211) 2284 return; 2285 2286 max_frame_size = adapter->shared->isc_max_frame_size; 2287 if (hw->mac.type > e1000_82580) { 2288 2289 if (adapter->dmac == 0) { /* Disabling it */ 2290 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2291 return; 2292 } else 2293 device_printf(dev, "DMA Coalescing enabled\n"); 2294 2295 /* Set starting threshold */ 2296 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2297 2298 hwm = 64 * pba - max_frame_size / 16; 2299 if (hwm < 64 * (pba - 6)) 2300 hwm = 64 * (pba - 6); 2301 reg = E1000_READ_REG(hw, E1000_FCRTC); 2302 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2303 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2304 & E1000_FCRTC_RTH_COAL_MASK); 2305 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2306 2307 2308 dmac = pba - max_frame_size / 512; 2309 if (dmac < pba - 10) 2310 dmac = pba - 10; 2311 reg = E1000_READ_REG(hw, E1000_DMACR); 2312 reg &= ~E1000_DMACR_DMACTHR_MASK; 2313 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2314 & E1000_DMACR_DMACTHR_MASK); 2315 2316 /* transition to L0x or L1 if available..*/ 2317 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2318 2319 /* Check if status is 2.5Gb backplane connection 2320 * before configuration of watchdog timer, which is 2321 * in msec values in 12.8usec intervals 2322 * watchdog timer= msec values in 32usec intervals 2323 * for non 2.5Gb connection 2324 */ 2325 if (hw->mac.type == e1000_i354) { 2326 int status = E1000_READ_REG(hw, E1000_STATUS); 2327 if ((status & E1000_STATUS_2P5_SKU) && 2328 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2329 reg |= ((adapter->dmac * 5) >> 6); 2330 else 2331 reg |= (adapter->dmac >> 5); 2332 } else { 2333 reg |= (adapter->dmac >> 5); 2334 } 2335 2336 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2337 2338 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2339 2340 /* Set the interval before transition */ 2341 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2342 if (hw->mac.type == e1000_i350) 2343 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2344 /* 2345 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2346 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2347 */ 2348 if (hw->mac.type == e1000_i354) { 2349 int status = E1000_READ_REG(hw, E1000_STATUS); 2350 if ((status & E1000_STATUS_2P5_SKU) && 2351 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2352 reg |= 0xA; 2353 else 2354 reg |= 0x4; 2355 } else { 2356 reg |= 0x4; 2357 } 2358 2359 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2360 2361 /* free space in tx packet buffer to wake from DMA coal */ 2362 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2363 (2 * max_frame_size)) >> 6); 2364 2365 /* make low power state decision controlled by DMA coal */ 2366 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2367 reg &= ~E1000_PCIEMISC_LX_DECISION; 2368 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2369 2370 } else if (hw->mac.type == e1000_82580) { 2371 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2372 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2373 reg & ~E1000_PCIEMISC_LX_DECISION); 2374 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2375 } 2376 } 2377 2378 /********************************************************************* 2379 * 2380 * Initialize the hardware to a configuration as specified by the 2381 * adapter structure. 2382 * 2383 **********************************************************************/ 2384 static void 2385 em_reset(if_ctx_t ctx) 2386 { 2387 device_t dev = iflib_get_dev(ctx); 2388 struct adapter *adapter = iflib_get_softc(ctx); 2389 struct ifnet *ifp = iflib_get_ifp(ctx); 2390 struct e1000_hw *hw = &adapter->hw; 2391 u16 rx_buffer_size; 2392 u32 pba; 2393 2394 INIT_DEBUGOUT("em_reset: begin"); 2395 /* Let the firmware know the OS is in control */ 2396 em_get_hw_control(adapter); 2397 2398 /* Set up smart power down as default off on newer adapters. */ 2399 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2400 hw->mac.type == e1000_82572)) { 2401 u16 phy_tmp = 0; 2402 2403 /* Speed up time to link by disabling smart power down. */ 2404 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2405 phy_tmp &= ~IGP02E1000_PM_SPD; 2406 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2407 } 2408 2409 /* 2410 * Packet Buffer Allocation (PBA) 2411 * Writing PBA sets the receive portion of the buffer 2412 * the remainder is used for the transmit buffer. 2413 */ 2414 switch (hw->mac.type) { 2415 /* Total Packet Buffer on these is 48K */ 2416 case e1000_82571: 2417 case e1000_82572: 2418 case e1000_80003es2lan: 2419 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2420 break; 2421 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2422 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2423 break; 2424 case e1000_82574: 2425 case e1000_82583: 2426 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2427 break; 2428 case e1000_ich8lan: 2429 pba = E1000_PBA_8K; 2430 break; 2431 case e1000_ich9lan: 2432 case e1000_ich10lan: 2433 /* Boost Receive side for jumbo frames */ 2434 if (adapter->hw.mac.max_frame_size > 4096) 2435 pba = E1000_PBA_14K; 2436 else 2437 pba = E1000_PBA_10K; 2438 break; 2439 case e1000_pchlan: 2440 case e1000_pch2lan: 2441 case e1000_pch_lpt: 2442 case e1000_pch_spt: 2443 case e1000_pch_cnp: 2444 pba = E1000_PBA_26K; 2445 break; 2446 case e1000_82575: 2447 pba = E1000_PBA_32K; 2448 break; 2449 case e1000_82576: 2450 case e1000_vfadapt: 2451 pba = E1000_READ_REG(hw, E1000_RXPBS); 2452 pba &= E1000_RXPBS_SIZE_MASK_82576; 2453 break; 2454 case e1000_82580: 2455 case e1000_i350: 2456 case e1000_i354: 2457 case e1000_vfadapt_i350: 2458 pba = E1000_READ_REG(hw, E1000_RXPBS); 2459 pba = e1000_rxpbs_adjust_82580(pba); 2460 break; 2461 case e1000_i210: 2462 case e1000_i211: 2463 pba = E1000_PBA_34K; 2464 break; 2465 default: 2466 if (adapter->hw.mac.max_frame_size > 8192) 2467 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2468 else 2469 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2470 } 2471 2472 /* Special needs in case of Jumbo frames */ 2473 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2474 u32 tx_space, min_tx, min_rx; 2475 pba = E1000_READ_REG(hw, E1000_PBA); 2476 tx_space = pba >> 16; 2477 pba &= 0xffff; 2478 min_tx = (adapter->hw.mac.max_frame_size + 2479 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2480 min_tx = roundup2(min_tx, 1024); 2481 min_tx >>= 10; 2482 min_rx = adapter->hw.mac.max_frame_size; 2483 min_rx = roundup2(min_rx, 1024); 2484 min_rx >>= 10; 2485 if (tx_space < min_tx && 2486 ((min_tx - tx_space) < pba)) { 2487 pba = pba - (min_tx - tx_space); 2488 /* 2489 * if short on rx space, rx wins 2490 * and must trump tx adjustment 2491 */ 2492 if (pba < min_rx) 2493 pba = min_rx; 2494 } 2495 E1000_WRITE_REG(hw, E1000_PBA, pba); 2496 } 2497 2498 if (hw->mac.type < igb_mac_min) 2499 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2500 2501 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2502 2503 /* 2504 * These parameters control the automatic generation (Tx) and 2505 * response (Rx) to Ethernet PAUSE frames. 2506 * - High water mark should allow for at least two frames to be 2507 * received after sending an XOFF. 2508 * - Low water mark works best when it is very near the high water mark. 2509 * This allows the receiver to restart by sending XON when it has 2510 * drained a bit. Here we use an arbitrary value of 1500 which will 2511 * restart after one full frame is pulled from the buffer. There 2512 * could be several smaller frames in the buffer and if so they will 2513 * not trigger the XON until their total number reduces the buffer 2514 * by 1500. 2515 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2516 */ 2517 rx_buffer_size = (pba & 0xffff) << 10; 2518 hw->fc.high_water = rx_buffer_size - 2519 roundup2(adapter->hw.mac.max_frame_size, 1024); 2520 hw->fc.low_water = hw->fc.high_water - 1500; 2521 2522 if (adapter->fc) /* locally set flow control value? */ 2523 hw->fc.requested_mode = adapter->fc; 2524 else 2525 hw->fc.requested_mode = e1000_fc_full; 2526 2527 if (hw->mac.type == e1000_80003es2lan) 2528 hw->fc.pause_time = 0xFFFF; 2529 else 2530 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2531 2532 hw->fc.send_xon = TRUE; 2533 2534 /* Device specific overrides/settings */ 2535 switch (hw->mac.type) { 2536 case e1000_pchlan: 2537 /* Workaround: no TX flow ctrl for PCH */ 2538 hw->fc.requested_mode = e1000_fc_rx_pause; 2539 hw->fc.pause_time = 0xFFFF; /* override */ 2540 if (if_getmtu(ifp) > ETHERMTU) { 2541 hw->fc.high_water = 0x3500; 2542 hw->fc.low_water = 0x1500; 2543 } else { 2544 hw->fc.high_water = 0x5000; 2545 hw->fc.low_water = 0x3000; 2546 } 2547 hw->fc.refresh_time = 0x1000; 2548 break; 2549 case e1000_pch2lan: 2550 case e1000_pch_lpt: 2551 case e1000_pch_spt: 2552 case e1000_pch_cnp: 2553 hw->fc.high_water = 0x5C20; 2554 hw->fc.low_water = 0x5048; 2555 hw->fc.pause_time = 0x0650; 2556 hw->fc.refresh_time = 0x0400; 2557 /* Jumbos need adjusted PBA */ 2558 if (if_getmtu(ifp) > ETHERMTU) 2559 E1000_WRITE_REG(hw, E1000_PBA, 12); 2560 else 2561 E1000_WRITE_REG(hw, E1000_PBA, 26); 2562 break; 2563 case e1000_82575: 2564 case e1000_82576: 2565 /* 8-byte granularity */ 2566 hw->fc.low_water = hw->fc.high_water - 8; 2567 break; 2568 case e1000_82580: 2569 case e1000_i350: 2570 case e1000_i354: 2571 case e1000_i210: 2572 case e1000_i211: 2573 case e1000_vfadapt: 2574 case e1000_vfadapt_i350: 2575 /* 16-byte granularity */ 2576 hw->fc.low_water = hw->fc.high_water - 16; 2577 break; 2578 case e1000_ich9lan: 2579 case e1000_ich10lan: 2580 if (if_getmtu(ifp) > ETHERMTU) { 2581 hw->fc.high_water = 0x2800; 2582 hw->fc.low_water = hw->fc.high_water - 8; 2583 break; 2584 } 2585 /* FALLTHROUGH */ 2586 default: 2587 if (hw->mac.type == e1000_80003es2lan) 2588 hw->fc.pause_time = 0xFFFF; 2589 break; 2590 } 2591 2592 /* Issue a global reset */ 2593 e1000_reset_hw(hw); 2594 if (adapter->hw.mac.type >= igb_mac_min) { 2595 E1000_WRITE_REG(hw, E1000_WUC, 0); 2596 } else { 2597 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2598 em_disable_aspm(adapter); 2599 } 2600 if (adapter->flags & IGB_MEDIA_RESET) { 2601 e1000_setup_init_funcs(hw, TRUE); 2602 e1000_get_bus_info(hw); 2603 adapter->flags &= ~IGB_MEDIA_RESET; 2604 } 2605 /* and a re-init */ 2606 if (e1000_init_hw(hw) < 0) { 2607 device_printf(dev, "Hardware Initialization Failed\n"); 2608 return; 2609 } 2610 if (adapter->hw.mac.type >= igb_mac_min) 2611 igb_init_dmac(adapter, pba); 2612 2613 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2614 e1000_get_phy_info(hw); 2615 e1000_check_for_link(hw); 2616 } 2617 2618 /* 2619 * Initialise the RSS mapping for NICs that support multiple transmit/ 2620 * receive rings. 2621 */ 2622 2623 #define RSSKEYLEN 10 2624 static void 2625 em_initialize_rss_mapping(struct adapter *adapter) 2626 { 2627 uint8_t rss_key[4 * RSSKEYLEN]; 2628 uint32_t reta = 0; 2629 struct e1000_hw *hw = &adapter->hw; 2630 int i; 2631 2632 /* 2633 * Configure RSS key 2634 */ 2635 arc4rand(rss_key, sizeof(rss_key), 0); 2636 for (i = 0; i < RSSKEYLEN; ++i) { 2637 uint32_t rssrk = 0; 2638 2639 rssrk = EM_RSSRK_VAL(rss_key, i); 2640 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2641 } 2642 2643 /* 2644 * Configure RSS redirect table in following fashion: 2645 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2646 */ 2647 for (i = 0; i < sizeof(reta); ++i) { 2648 uint32_t q; 2649 2650 q = (i % adapter->rx_num_queues) << 7; 2651 reta |= q << (8 * i); 2652 } 2653 2654 for (i = 0; i < 32; ++i) 2655 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2656 2657 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2658 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2659 E1000_MRQC_RSS_FIELD_IPV4 | 2660 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2661 E1000_MRQC_RSS_FIELD_IPV6_EX | 2662 E1000_MRQC_RSS_FIELD_IPV6); 2663 } 2664 2665 static void 2666 igb_initialize_rss_mapping(struct adapter *adapter) 2667 { 2668 struct e1000_hw *hw = &adapter->hw; 2669 int i; 2670 int queue_id; 2671 u32 reta; 2672 u32 rss_key[10], mrqc, shift = 0; 2673 2674 /* XXX? */ 2675 if (adapter->hw.mac.type == e1000_82575) 2676 shift = 6; 2677 2678 /* 2679 * The redirection table controls which destination 2680 * queue each bucket redirects traffic to. 2681 * Each DWORD represents four queues, with the LSB 2682 * being the first queue in the DWORD. 2683 * 2684 * This just allocates buckets to queues using round-robin 2685 * allocation. 2686 * 2687 * NOTE: It Just Happens to line up with the default 2688 * RSS allocation method. 2689 */ 2690 2691 /* Warning FM follows */ 2692 reta = 0; 2693 for (i = 0; i < 128; i++) { 2694 #ifdef RSS 2695 queue_id = rss_get_indirection_to_bucket(i); 2696 /* 2697 * If we have more queues than buckets, we'll 2698 * end up mapping buckets to a subset of the 2699 * queues. 2700 * 2701 * If we have more buckets than queues, we'll 2702 * end up instead assigning multiple buckets 2703 * to queues. 2704 * 2705 * Both are suboptimal, but we need to handle 2706 * the case so we don't go out of bounds 2707 * indexing arrays and such. 2708 */ 2709 queue_id = queue_id % adapter->rx_num_queues; 2710 #else 2711 queue_id = (i % adapter->rx_num_queues); 2712 #endif 2713 /* Adjust if required */ 2714 queue_id = queue_id << shift; 2715 2716 /* 2717 * The low 8 bits are for hash value (n+0); 2718 * The next 8 bits are for hash value (n+1), etc. 2719 */ 2720 reta = reta >> 8; 2721 reta = reta | ( ((uint32_t) queue_id) << 24); 2722 if ((i & 3) == 3) { 2723 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2724 reta = 0; 2725 } 2726 } 2727 2728 /* Now fill in hash table */ 2729 2730 /* 2731 * MRQC: Multiple Receive Queues Command 2732 * Set queuing to RSS control, number depends on the device. 2733 */ 2734 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2735 2736 #ifdef RSS 2737 /* XXX ew typecasting */ 2738 rss_getkey((uint8_t *) &rss_key); 2739 #else 2740 arc4rand(&rss_key, sizeof(rss_key), 0); 2741 #endif 2742 for (i = 0; i < 10; i++) 2743 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2744 2745 /* 2746 * Configure the RSS fields to hash upon. 2747 */ 2748 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2749 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2750 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2751 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2752 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2753 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2754 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2755 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2756 2757 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2758 } 2759 2760 /********************************************************************* 2761 * 2762 * Setup networking device structure and register interface media. 2763 * 2764 **********************************************************************/ 2765 static int 2766 em_setup_interface(if_ctx_t ctx) 2767 { 2768 struct ifnet *ifp = iflib_get_ifp(ctx); 2769 struct adapter *adapter = iflib_get_softc(ctx); 2770 if_softc_ctx_t scctx = adapter->shared; 2771 2772 INIT_DEBUGOUT("em_setup_interface: begin"); 2773 2774 /* Single Queue */ 2775 if (adapter->tx_num_queues == 1) { 2776 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2777 if_setsendqready(ifp); 2778 } 2779 2780 /* 2781 * Specify the media types supported by this adapter and register 2782 * callbacks to update media and link information 2783 */ 2784 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2785 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2786 u_char fiber_type = IFM_1000_SX; /* default type */ 2787 2788 if (adapter->hw.mac.type == e1000_82545) 2789 fiber_type = IFM_1000_LX; 2790 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2791 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2792 } else { 2793 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2794 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2795 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2796 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2797 if (adapter->hw.phy.type != e1000_phy_ife) { 2798 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2799 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2800 } 2801 } 2802 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2803 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2804 return (0); 2805 } 2806 2807 static int 2808 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2809 { 2810 struct adapter *adapter = iflib_get_softc(ctx); 2811 if_softc_ctx_t scctx = adapter->shared; 2812 int error = E1000_SUCCESS; 2813 struct em_tx_queue *que; 2814 int i, j; 2815 2816 MPASS(adapter->tx_num_queues > 0); 2817 MPASS(adapter->tx_num_queues == ntxqsets); 2818 2819 /* First allocate the top level queue structs */ 2820 if (!(adapter->tx_queues = 2821 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2822 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2823 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2824 return(ENOMEM); 2825 } 2826 2827 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2828 /* Set up some basics */ 2829 2830 struct tx_ring *txr = &que->txr; 2831 txr->adapter = que->adapter = adapter; 2832 que->me = txr->me = i; 2833 2834 /* Allocate report status array */ 2835 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2836 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2837 error = ENOMEM; 2838 goto fail; 2839 } 2840 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2841 txr->tx_rsq[j] = QIDX_INVALID; 2842 /* get the virtual and physical address of the hardware queues */ 2843 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2844 txr->tx_paddr = paddrs[i*ntxqs]; 2845 } 2846 2847 if (bootverbose) 2848 device_printf(iflib_get_dev(ctx), 2849 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2850 return (0); 2851 fail: 2852 em_if_queues_free(ctx); 2853 return (error); 2854 } 2855 2856 static int 2857 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2858 { 2859 struct adapter *adapter = iflib_get_softc(ctx); 2860 int error = E1000_SUCCESS; 2861 struct em_rx_queue *que; 2862 int i; 2863 2864 MPASS(adapter->rx_num_queues > 0); 2865 MPASS(adapter->rx_num_queues == nrxqsets); 2866 2867 /* First allocate the top level queue structs */ 2868 if (!(adapter->rx_queues = 2869 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2870 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2871 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2872 error = ENOMEM; 2873 goto fail; 2874 } 2875 2876 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2877 /* Set up some basics */ 2878 struct rx_ring *rxr = &que->rxr; 2879 rxr->adapter = que->adapter = adapter; 2880 rxr->que = que; 2881 que->me = rxr->me = i; 2882 2883 /* get the virtual and physical address of the hardware queues */ 2884 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2885 rxr->rx_paddr = paddrs[i*nrxqs]; 2886 } 2887 2888 if (bootverbose) 2889 device_printf(iflib_get_dev(ctx), 2890 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2891 2892 return (0); 2893 fail: 2894 em_if_queues_free(ctx); 2895 return (error); 2896 } 2897 2898 static void 2899 em_if_queues_free(if_ctx_t ctx) 2900 { 2901 struct adapter *adapter = iflib_get_softc(ctx); 2902 struct em_tx_queue *tx_que = adapter->tx_queues; 2903 struct em_rx_queue *rx_que = adapter->rx_queues; 2904 2905 if (tx_que != NULL) { 2906 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2907 struct tx_ring *txr = &tx_que->txr; 2908 if (txr->tx_rsq == NULL) 2909 break; 2910 2911 free(txr->tx_rsq, M_DEVBUF); 2912 txr->tx_rsq = NULL; 2913 } 2914 free(adapter->tx_queues, M_DEVBUF); 2915 adapter->tx_queues = NULL; 2916 } 2917 2918 if (rx_que != NULL) { 2919 free(adapter->rx_queues, M_DEVBUF); 2920 adapter->rx_queues = NULL; 2921 } 2922 2923 em_release_hw_control(adapter); 2924 2925 if (adapter->mta != NULL) { 2926 free(adapter->mta, M_DEVBUF); 2927 } 2928 } 2929 2930 /********************************************************************* 2931 * 2932 * Enable transmit unit. 2933 * 2934 **********************************************************************/ 2935 static void 2936 em_initialize_transmit_unit(if_ctx_t ctx) 2937 { 2938 struct adapter *adapter = iflib_get_softc(ctx); 2939 if_softc_ctx_t scctx = adapter->shared; 2940 struct em_tx_queue *que; 2941 struct tx_ring *txr; 2942 struct e1000_hw *hw = &adapter->hw; 2943 u32 tctl, txdctl = 0, tarc, tipg = 0; 2944 2945 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2946 2947 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2948 u64 bus_addr; 2949 caddr_t offp, endp; 2950 2951 que = &adapter->tx_queues[i]; 2952 txr = &que->txr; 2953 bus_addr = txr->tx_paddr; 2954 2955 /* Clear checksum offload context. */ 2956 offp = (caddr_t)&txr->csum_flags; 2957 endp = (caddr_t)(txr + 1); 2958 bzero(offp, endp - offp); 2959 2960 /* Base and Len of TX Ring */ 2961 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2962 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2963 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2964 (u32)(bus_addr >> 32)); 2965 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2966 (u32)bus_addr); 2967 /* Init the HEAD/TAIL indices */ 2968 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2969 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2970 2971 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2972 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2973 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2974 2975 txdctl = 0; /* clear txdctl */ 2976 txdctl |= 0x1f; /* PTHRESH */ 2977 txdctl |= 1 << 8; /* HTHRESH */ 2978 txdctl |= 1 << 16;/* WTHRESH */ 2979 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2980 txdctl |= E1000_TXDCTL_GRAN; 2981 txdctl |= 1 << 25; /* LWTHRESH */ 2982 2983 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2984 } 2985 2986 /* Set the default values for the Tx Inter Packet Gap timer */ 2987 switch (adapter->hw.mac.type) { 2988 case e1000_80003es2lan: 2989 tipg = DEFAULT_82543_TIPG_IPGR1; 2990 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2991 E1000_TIPG_IPGR2_SHIFT; 2992 break; 2993 case e1000_82542: 2994 tipg = DEFAULT_82542_TIPG_IPGT; 2995 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2996 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2997 break; 2998 default: 2999 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3000 (adapter->hw.phy.media_type == 3001 e1000_media_type_internal_serdes)) 3002 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3003 else 3004 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3005 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3006 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3007 } 3008 3009 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3010 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3011 3012 if(adapter->hw.mac.type >= e1000_82540) 3013 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3014 adapter->tx_abs_int_delay.value); 3015 3016 if ((adapter->hw.mac.type == e1000_82571) || 3017 (adapter->hw.mac.type == e1000_82572)) { 3018 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3019 tarc |= TARC_SPEED_MODE_BIT; 3020 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3021 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3022 /* errata: program both queues to unweighted RR */ 3023 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3024 tarc |= 1; 3025 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3026 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3027 tarc |= 1; 3028 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3029 } else if (adapter->hw.mac.type == e1000_82574) { 3030 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3031 tarc |= TARC_ERRATA_BIT; 3032 if ( adapter->tx_num_queues > 1) { 3033 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3034 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3035 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3036 } else 3037 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3038 } 3039 3040 if (adapter->tx_int_delay.value > 0) 3041 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3042 3043 /* Program the Transmit Control Register */ 3044 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3045 tctl &= ~E1000_TCTL_CT; 3046 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3047 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3048 3049 if (adapter->hw.mac.type >= e1000_82571) 3050 tctl |= E1000_TCTL_MULR; 3051 3052 /* This write will effectively turn on the transmit unit. */ 3053 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3054 3055 /* SPT and KBL errata workarounds */ 3056 if (hw->mac.type == e1000_pch_spt) { 3057 u32 reg; 3058 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3059 reg |= E1000_RCTL_RDMTS_HEX; 3060 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3061 /* i218-i219 Specification Update 1.5.4.5 */ 3062 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3063 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3064 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3065 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3066 } 3067 } 3068 3069 /********************************************************************* 3070 * 3071 * Enable receive unit. 3072 * 3073 **********************************************************************/ 3074 3075 static void 3076 em_initialize_receive_unit(if_ctx_t ctx) 3077 { 3078 struct adapter *adapter = iflib_get_softc(ctx); 3079 if_softc_ctx_t scctx = adapter->shared; 3080 struct ifnet *ifp = iflib_get_ifp(ctx); 3081 struct e1000_hw *hw = &adapter->hw; 3082 struct em_rx_queue *que; 3083 int i; 3084 u32 rctl, rxcsum, rfctl; 3085 3086 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3087 3088 /* 3089 * Make sure receives are disabled while setting 3090 * up the descriptor ring 3091 */ 3092 rctl = E1000_READ_REG(hw, E1000_RCTL); 3093 /* Do not disable if ever enabled on this hardware */ 3094 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3095 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3096 3097 /* Setup the Receive Control Register */ 3098 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3099 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3100 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3101 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3102 3103 /* Do not store bad packets */ 3104 rctl &= ~E1000_RCTL_SBP; 3105 3106 /* Enable Long Packet receive */ 3107 if (if_getmtu(ifp) > ETHERMTU) 3108 rctl |= E1000_RCTL_LPE; 3109 else 3110 rctl &= ~E1000_RCTL_LPE; 3111 3112 /* Strip the CRC */ 3113 if (!em_disable_crc_stripping) 3114 rctl |= E1000_RCTL_SECRC; 3115 3116 if (adapter->hw.mac.type >= e1000_82540) { 3117 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3118 adapter->rx_abs_int_delay.value); 3119 3120 /* 3121 * Set the interrupt throttling rate. Value is calculated 3122 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3123 */ 3124 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3125 } 3126 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3127 adapter->rx_int_delay.value); 3128 3129 /* Use extended rx descriptor formats */ 3130 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3131 rfctl |= E1000_RFCTL_EXTEN; 3132 /* 3133 * When using MSI-X interrupts we need to throttle 3134 * using the EITR register (82574 only) 3135 */ 3136 if (hw->mac.type == e1000_82574) { 3137 for (int i = 0; i < 4; i++) 3138 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3139 DEFAULT_ITR); 3140 /* Disable accelerated acknowledge */ 3141 rfctl |= E1000_RFCTL_ACK_DIS; 3142 } 3143 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3144 3145 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3146 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3147 adapter->hw.mac.type >= e1000_82543) { 3148 if (adapter->tx_num_queues > 1) { 3149 if (adapter->hw.mac.type >= igb_mac_min) { 3150 rxcsum |= E1000_RXCSUM_PCSD; 3151 if (hw->mac.type != e1000_82575) 3152 rxcsum |= E1000_RXCSUM_CRCOFL; 3153 } else 3154 rxcsum |= E1000_RXCSUM_TUOFL | 3155 E1000_RXCSUM_IPOFL | 3156 E1000_RXCSUM_PCSD; 3157 } else { 3158 if (adapter->hw.mac.type >= igb_mac_min) 3159 rxcsum |= E1000_RXCSUM_IPPCSE; 3160 else 3161 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3162 if (adapter->hw.mac.type > e1000_82575) 3163 rxcsum |= E1000_RXCSUM_CRCOFL; 3164 } 3165 } else 3166 rxcsum &= ~E1000_RXCSUM_TUOFL; 3167 3168 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3169 3170 if (adapter->rx_num_queues > 1) { 3171 if (adapter->hw.mac.type >= igb_mac_min) 3172 igb_initialize_rss_mapping(adapter); 3173 else 3174 em_initialize_rss_mapping(adapter); 3175 } 3176 3177 /* 3178 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3179 * long latencies are observed, like Lenovo X60. This 3180 * change eliminates the problem, but since having positive 3181 * values in RDTR is a known source of problems on other 3182 * platforms another solution is being sought. 3183 */ 3184 if (hw->mac.type == e1000_82573) 3185 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3186 3187 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3188 struct rx_ring *rxr = &que->rxr; 3189 /* Setup the Base and Length of the Rx Descriptor Ring */ 3190 u64 bus_addr = rxr->rx_paddr; 3191 #if 0 3192 u32 rdt = adapter->rx_num_queues -1; /* default */ 3193 #endif 3194 3195 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3196 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3197 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3198 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3199 /* Setup the Head and Tail Descriptor Pointers */ 3200 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3201 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3202 } 3203 3204 /* 3205 * Set PTHRESH for improved jumbo performance 3206 * According to 10.2.5.11 of Intel 82574 Datasheet, 3207 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3208 * Only write to RXDCTL(1) if there is a need for different 3209 * settings. 3210 */ 3211 3212 if (((adapter->hw.mac.type == e1000_ich9lan) || 3213 (adapter->hw.mac.type == e1000_pch2lan) || 3214 (adapter->hw.mac.type == e1000_ich10lan)) && 3215 (if_getmtu(ifp) > ETHERMTU)) { 3216 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3217 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3218 } else if (adapter->hw.mac.type == e1000_82574) { 3219 for (int i = 0; i < adapter->rx_num_queues; i++) { 3220 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3221 rxdctl |= 0x20; /* PTHRESH */ 3222 rxdctl |= 4 << 8; /* HTHRESH */ 3223 rxdctl |= 4 << 16;/* WTHRESH */ 3224 rxdctl |= 1 << 24; /* Switch to granularity */ 3225 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3226 } 3227 } else if (adapter->hw.mac.type >= igb_mac_min) { 3228 u32 psize, srrctl = 0; 3229 3230 if (if_getmtu(ifp) > ETHERMTU) { 3231 /* Set maximum packet len */ 3232 if (adapter->rx_mbuf_sz <= 4096) { 3233 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3234 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3235 } else if (adapter->rx_mbuf_sz > 4096) { 3236 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3237 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3238 } 3239 psize = scctx->isc_max_frame_size; 3240 /* are we on a vlan? */ 3241 if (ifp->if_vlantrunk != NULL) 3242 psize += VLAN_TAG_SIZE; 3243 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3244 } else { 3245 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3246 rctl |= E1000_RCTL_SZ_2048; 3247 } 3248 3249 /* 3250 * If TX flow control is disabled and there's >1 queue defined, 3251 * enable DROP. 3252 * 3253 * This drops frames rather than hanging the RX MAC for all queues. 3254 */ 3255 if ((adapter->rx_num_queues > 1) && 3256 (adapter->fc == e1000_fc_none || 3257 adapter->fc == e1000_fc_rx_pause)) { 3258 srrctl |= E1000_SRRCTL_DROP_EN; 3259 } 3260 /* Setup the Base and Length of the Rx Descriptor Rings */ 3261 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3262 struct rx_ring *rxr = &que->rxr; 3263 u64 bus_addr = rxr->rx_paddr; 3264 u32 rxdctl; 3265 3266 #ifdef notyet 3267 /* Configure for header split? -- ignore for now */ 3268 rxr->hdr_split = igb_header_split; 3269 #else 3270 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3271 #endif 3272 3273 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3274 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3275 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3276 (uint32_t)(bus_addr >> 32)); 3277 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3278 (uint32_t)bus_addr); 3279 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3280 /* Enable this Queue */ 3281 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3282 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3283 rxdctl &= 0xFFF00000; 3284 rxdctl |= IGB_RX_PTHRESH; 3285 rxdctl |= IGB_RX_HTHRESH << 8; 3286 rxdctl |= IGB_RX_WTHRESH << 16; 3287 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3288 } 3289 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3290 if (if_getmtu(ifp) > ETHERMTU) 3291 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3292 else 3293 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3294 } 3295 3296 /* Make sure VLAN Filters are off */ 3297 rctl &= ~E1000_RCTL_VFE; 3298 3299 if (adapter->hw.mac.type < igb_mac_min) { 3300 if (adapter->rx_mbuf_sz == MCLBYTES) 3301 rctl |= E1000_RCTL_SZ_2048; 3302 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3303 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3304 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3305 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3306 3307 /* ensure we clear use DTYPE of 00 here */ 3308 rctl &= ~0x00000C00; 3309 } 3310 3311 /* Write out the settings */ 3312 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3313 3314 return; 3315 } 3316 3317 static void 3318 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3319 { 3320 struct adapter *adapter = iflib_get_softc(ctx); 3321 u32 index, bit; 3322 3323 index = (vtag >> 5) & 0x7F; 3324 bit = vtag & 0x1F; 3325 adapter->shadow_vfta[index] |= (1 << bit); 3326 ++adapter->num_vlans; 3327 } 3328 3329 static void 3330 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3331 { 3332 struct adapter *adapter = iflib_get_softc(ctx); 3333 u32 index, bit; 3334 3335 index = (vtag >> 5) & 0x7F; 3336 bit = vtag & 0x1F; 3337 adapter->shadow_vfta[index] &= ~(1 << bit); 3338 --adapter->num_vlans; 3339 } 3340 3341 static void 3342 em_setup_vlan_hw_support(struct adapter *adapter) 3343 { 3344 struct e1000_hw *hw = &adapter->hw; 3345 u32 reg; 3346 3347 /* 3348 * We get here thru init_locked, meaning 3349 * a soft reset, this has already cleared 3350 * the VFTA and other state, so if there 3351 * have been no vlan's registered do nothing. 3352 */ 3353 if (adapter->num_vlans == 0) 3354 return; 3355 3356 /* 3357 * A soft reset zero's out the VFTA, so 3358 * we need to repopulate it now. 3359 */ 3360 for (int i = 0; i < EM_VFTA_SIZE; i++) 3361 if (adapter->shadow_vfta[i] != 0) 3362 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3363 i, adapter->shadow_vfta[i]); 3364 3365 reg = E1000_READ_REG(hw, E1000_CTRL); 3366 reg |= E1000_CTRL_VME; 3367 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3368 3369 /* Enable the Filter Table */ 3370 reg = E1000_READ_REG(hw, E1000_RCTL); 3371 reg &= ~E1000_RCTL_CFIEN; 3372 reg |= E1000_RCTL_VFE; 3373 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3374 } 3375 3376 static void 3377 em_if_enable_intr(if_ctx_t ctx) 3378 { 3379 struct adapter *adapter = iflib_get_softc(ctx); 3380 struct e1000_hw *hw = &adapter->hw; 3381 u32 ims_mask = IMS_ENABLE_MASK; 3382 3383 if (hw->mac.type == e1000_82574) { 3384 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3385 ims_mask |= adapter->ims; 3386 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3387 u32 mask = (adapter->que_mask | adapter->link_mask); 3388 3389 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3390 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3391 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3392 ims_mask = E1000_IMS_LSC; 3393 } 3394 3395 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3396 } 3397 3398 static void 3399 em_if_disable_intr(if_ctx_t ctx) 3400 { 3401 struct adapter *adapter = iflib_get_softc(ctx); 3402 struct e1000_hw *hw = &adapter->hw; 3403 3404 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3405 if (hw->mac.type >= igb_mac_min) 3406 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3407 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3408 } 3409 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3410 } 3411 3412 /* 3413 * Bit of a misnomer, what this really means is 3414 * to enable OS management of the system... aka 3415 * to disable special hardware management features 3416 */ 3417 static void 3418 em_init_manageability(struct adapter *adapter) 3419 { 3420 /* A shared code workaround */ 3421 #define E1000_82542_MANC2H E1000_MANC2H 3422 if (adapter->has_manage) { 3423 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3424 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3425 3426 /* disable hardware interception of ARP */ 3427 manc &= ~(E1000_MANC_ARP_EN); 3428 3429 /* enable receiving management packets to the host */ 3430 manc |= E1000_MANC_EN_MNG2HOST; 3431 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3432 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3433 manc2h |= E1000_MNG2HOST_PORT_623; 3434 manc2h |= E1000_MNG2HOST_PORT_664; 3435 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3436 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3437 } 3438 } 3439 3440 /* 3441 * Give control back to hardware management 3442 * controller if there is one. 3443 */ 3444 static void 3445 em_release_manageability(struct adapter *adapter) 3446 { 3447 if (adapter->has_manage) { 3448 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3449 3450 /* re-enable hardware interception of ARP */ 3451 manc |= E1000_MANC_ARP_EN; 3452 manc &= ~E1000_MANC_EN_MNG2HOST; 3453 3454 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3455 } 3456 } 3457 3458 /* 3459 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3460 * For ASF and Pass Through versions of f/w this means 3461 * that the driver is loaded. For AMT version type f/w 3462 * this means that the network i/f is open. 3463 */ 3464 static void 3465 em_get_hw_control(struct adapter *adapter) 3466 { 3467 u32 ctrl_ext, swsm; 3468 3469 if (adapter->vf_ifp) 3470 return; 3471 3472 if (adapter->hw.mac.type == e1000_82573) { 3473 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3474 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3475 swsm | E1000_SWSM_DRV_LOAD); 3476 return; 3477 } 3478 /* else */ 3479 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3480 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3481 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3482 } 3483 3484 /* 3485 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3486 * For ASF and Pass Through versions of f/w this means that 3487 * the driver is no longer loaded. For AMT versions of the 3488 * f/w this means that the network i/f is closed. 3489 */ 3490 static void 3491 em_release_hw_control(struct adapter *adapter) 3492 { 3493 u32 ctrl_ext, swsm; 3494 3495 if (!adapter->has_manage) 3496 return; 3497 3498 if (adapter->hw.mac.type == e1000_82573) { 3499 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3500 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3501 swsm & ~E1000_SWSM_DRV_LOAD); 3502 return; 3503 } 3504 /* else */ 3505 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3506 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3507 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3508 return; 3509 } 3510 3511 static int 3512 em_is_valid_ether_addr(u8 *addr) 3513 { 3514 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3515 3516 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3517 return (FALSE); 3518 } 3519 3520 return (TRUE); 3521 } 3522 3523 /* 3524 ** Parse the interface capabilities with regard 3525 ** to both system management and wake-on-lan for 3526 ** later use. 3527 */ 3528 static void 3529 em_get_wakeup(if_ctx_t ctx) 3530 { 3531 struct adapter *adapter = iflib_get_softc(ctx); 3532 device_t dev = iflib_get_dev(ctx); 3533 u16 eeprom_data = 0, device_id, apme_mask; 3534 3535 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3536 apme_mask = EM_EEPROM_APME; 3537 3538 switch (adapter->hw.mac.type) { 3539 case e1000_82542: 3540 case e1000_82543: 3541 break; 3542 case e1000_82544: 3543 e1000_read_nvm(&adapter->hw, 3544 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3545 apme_mask = EM_82544_APME; 3546 break; 3547 case e1000_82546: 3548 case e1000_82546_rev_3: 3549 if (adapter->hw.bus.func == 1) { 3550 e1000_read_nvm(&adapter->hw, 3551 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3552 break; 3553 } else 3554 e1000_read_nvm(&adapter->hw, 3555 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3556 break; 3557 case e1000_82573: 3558 case e1000_82583: 3559 adapter->has_amt = TRUE; 3560 /* FALLTHROUGH */ 3561 case e1000_82571: 3562 case e1000_82572: 3563 case e1000_80003es2lan: 3564 if (adapter->hw.bus.func == 1) { 3565 e1000_read_nvm(&adapter->hw, 3566 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3567 break; 3568 } else 3569 e1000_read_nvm(&adapter->hw, 3570 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3571 break; 3572 case e1000_ich8lan: 3573 case e1000_ich9lan: 3574 case e1000_ich10lan: 3575 case e1000_pchlan: 3576 case e1000_pch2lan: 3577 case e1000_pch_lpt: 3578 case e1000_pch_spt: 3579 case e1000_82575: /* listing all igb devices */ 3580 case e1000_82576: 3581 case e1000_82580: 3582 case e1000_i350: 3583 case e1000_i354: 3584 case e1000_i210: 3585 case e1000_i211: 3586 case e1000_vfadapt: 3587 case e1000_vfadapt_i350: 3588 apme_mask = E1000_WUC_APME; 3589 adapter->has_amt = TRUE; 3590 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3591 break; 3592 default: 3593 e1000_read_nvm(&adapter->hw, 3594 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3595 break; 3596 } 3597 if (eeprom_data & apme_mask) 3598 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3599 /* 3600 * We have the eeprom settings, now apply the special cases 3601 * where the eeprom may be wrong or the board won't support 3602 * wake on lan on a particular port 3603 */ 3604 device_id = pci_get_device(dev); 3605 switch (device_id) { 3606 case E1000_DEV_ID_82546GB_PCIE: 3607 adapter->wol = 0; 3608 break; 3609 case E1000_DEV_ID_82546EB_FIBER: 3610 case E1000_DEV_ID_82546GB_FIBER: 3611 /* Wake events only supported on port A for dual fiber 3612 * regardless of eeprom setting */ 3613 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3614 E1000_STATUS_FUNC_1) 3615 adapter->wol = 0; 3616 break; 3617 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3618 /* if quad port adapter, disable WoL on all but port A */ 3619 if (global_quad_port_a != 0) 3620 adapter->wol = 0; 3621 /* Reset for multiple quad port adapters */ 3622 if (++global_quad_port_a == 4) 3623 global_quad_port_a = 0; 3624 break; 3625 case E1000_DEV_ID_82571EB_FIBER: 3626 /* Wake events only supported on port A for dual fiber 3627 * regardless of eeprom setting */ 3628 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3629 E1000_STATUS_FUNC_1) 3630 adapter->wol = 0; 3631 break; 3632 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3633 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3634 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3635 /* if quad port adapter, disable WoL on all but port A */ 3636 if (global_quad_port_a != 0) 3637 adapter->wol = 0; 3638 /* Reset for multiple quad port adapters */ 3639 if (++global_quad_port_a == 4) 3640 global_quad_port_a = 0; 3641 break; 3642 } 3643 return; 3644 } 3645 3646 3647 /* 3648 * Enable PCI Wake On Lan capability 3649 */ 3650 static void 3651 em_enable_wakeup(if_ctx_t ctx) 3652 { 3653 struct adapter *adapter = iflib_get_softc(ctx); 3654 device_t dev = iflib_get_dev(ctx); 3655 if_t ifp = iflib_get_ifp(ctx); 3656 int error = 0; 3657 u32 pmc, ctrl, ctrl_ext, rctl; 3658 u16 status; 3659 3660 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3661 return; 3662 3663 /* 3664 * Determine type of Wakeup: note that wol 3665 * is set with all bits on by default. 3666 */ 3667 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3668 adapter->wol &= ~E1000_WUFC_MAG; 3669 3670 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3671 adapter->wol &= ~E1000_WUFC_EX; 3672 3673 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3674 adapter->wol &= ~E1000_WUFC_MC; 3675 else { 3676 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3677 rctl |= E1000_RCTL_MPE; 3678 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3679 } 3680 3681 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3682 goto pme; 3683 3684 /* Advertise the wakeup capability */ 3685 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3686 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3687 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3688 3689 /* Keep the laser running on Fiber adapters */ 3690 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3691 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3692 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3693 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3694 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3695 } 3696 3697 if ((adapter->hw.mac.type == e1000_ich8lan) || 3698 (adapter->hw.mac.type == e1000_pchlan) || 3699 (adapter->hw.mac.type == e1000_ich9lan) || 3700 (adapter->hw.mac.type == e1000_ich10lan)) 3701 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3702 3703 if ( adapter->hw.mac.type >= e1000_pchlan) { 3704 error = em_enable_phy_wakeup(adapter); 3705 if (error) 3706 goto pme; 3707 } else { 3708 /* Enable wakeup by the MAC */ 3709 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3710 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3711 } 3712 3713 if (adapter->hw.phy.type == e1000_phy_igp_3) 3714 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3715 3716 pme: 3717 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3718 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3719 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3720 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3721 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3722 3723 return; 3724 } 3725 3726 /* 3727 * WOL in the newer chipset interfaces (pchlan) 3728 * require thing to be copied into the phy 3729 */ 3730 static int 3731 em_enable_phy_wakeup(struct adapter *adapter) 3732 { 3733 struct e1000_hw *hw = &adapter->hw; 3734 u32 mreg, ret = 0; 3735 u16 preg; 3736 3737 /* copy MAC RARs to PHY RARs */ 3738 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3739 3740 /* copy MAC MTA to PHY MTA */ 3741 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3742 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3743 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3744 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3745 (u16)((mreg >> 16) & 0xFFFF)); 3746 } 3747 3748 /* configure PHY Rx Control register */ 3749 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3750 mreg = E1000_READ_REG(hw, E1000_RCTL); 3751 if (mreg & E1000_RCTL_UPE) 3752 preg |= BM_RCTL_UPE; 3753 if (mreg & E1000_RCTL_MPE) 3754 preg |= BM_RCTL_MPE; 3755 preg &= ~(BM_RCTL_MO_MASK); 3756 if (mreg & E1000_RCTL_MO_3) 3757 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3758 << BM_RCTL_MO_SHIFT); 3759 if (mreg & E1000_RCTL_BAM) 3760 preg |= BM_RCTL_BAM; 3761 if (mreg & E1000_RCTL_PMCF) 3762 preg |= BM_RCTL_PMCF; 3763 mreg = E1000_READ_REG(hw, E1000_CTRL); 3764 if (mreg & E1000_CTRL_RFCE) 3765 preg |= BM_RCTL_RFCE; 3766 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3767 3768 /* enable PHY wakeup in MAC register */ 3769 E1000_WRITE_REG(hw, E1000_WUC, 3770 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3771 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3772 3773 /* configure and enable PHY wakeup in PHY registers */ 3774 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3775 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3776 3777 /* activate PHY wakeup */ 3778 ret = hw->phy.ops.acquire(hw); 3779 if (ret) { 3780 printf("Could not acquire PHY\n"); 3781 return ret; 3782 } 3783 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3784 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3785 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3786 if (ret) { 3787 printf("Could not read PHY page 769\n"); 3788 goto out; 3789 } 3790 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3791 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3792 if (ret) 3793 printf("Could not set PHY Host Wakeup bit\n"); 3794 out: 3795 hw->phy.ops.release(hw); 3796 3797 return ret; 3798 } 3799 3800 static void 3801 em_if_led_func(if_ctx_t ctx, int onoff) 3802 { 3803 struct adapter *adapter = iflib_get_softc(ctx); 3804 3805 if (onoff) { 3806 e1000_setup_led(&adapter->hw); 3807 e1000_led_on(&adapter->hw); 3808 } else { 3809 e1000_led_off(&adapter->hw); 3810 e1000_cleanup_led(&adapter->hw); 3811 } 3812 } 3813 3814 /* 3815 * Disable the L0S and L1 LINK states 3816 */ 3817 static void 3818 em_disable_aspm(struct adapter *adapter) 3819 { 3820 int base, reg; 3821 u16 link_cap,link_ctrl; 3822 device_t dev = adapter->dev; 3823 3824 switch (adapter->hw.mac.type) { 3825 case e1000_82573: 3826 case e1000_82574: 3827 case e1000_82583: 3828 break; 3829 default: 3830 return; 3831 } 3832 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3833 return; 3834 reg = base + PCIER_LINK_CAP; 3835 link_cap = pci_read_config(dev, reg, 2); 3836 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3837 return; 3838 reg = base + PCIER_LINK_CTL; 3839 link_ctrl = pci_read_config(dev, reg, 2); 3840 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3841 pci_write_config(dev, reg, link_ctrl, 2); 3842 return; 3843 } 3844 3845 /********************************************************************** 3846 * 3847 * Update the board statistics counters. 3848 * 3849 **********************************************************************/ 3850 static void 3851 em_update_stats_counters(struct adapter *adapter) 3852 { 3853 3854 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3855 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3856 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3857 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3858 } 3859 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3860 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3861 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3862 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3863 3864 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3865 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3866 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3867 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3868 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3869 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3870 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3871 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3872 /* 3873 ** For watchdog management we need to know if we have been 3874 ** paused during the last interval, so capture that here. 3875 */ 3876 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3877 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3878 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3879 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3880 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3881 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3882 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3883 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3884 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3885 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3886 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3887 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3888 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3889 3890 /* For the 64-bit byte counters the low dword must be read first. */ 3891 /* Both registers clear on the read of the high dword */ 3892 3893 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3894 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3895 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3896 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3897 3898 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3899 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3900 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3901 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3902 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3903 3904 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3905 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3906 3907 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3908 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3909 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3910 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3911 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3912 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3913 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3914 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3915 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3916 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3917 3918 /* Interrupt Counts */ 3919 3920 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3921 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3922 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3923 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3924 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3925 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3926 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3927 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3928 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3929 3930 if (adapter->hw.mac.type >= e1000_82543) { 3931 adapter->stats.algnerrc += 3932 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3933 adapter->stats.rxerrc += 3934 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3935 adapter->stats.tncrs += 3936 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3937 adapter->stats.cexterr += 3938 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3939 adapter->stats.tsctc += 3940 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3941 adapter->stats.tsctfc += 3942 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3943 } 3944 } 3945 3946 static uint64_t 3947 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3948 { 3949 struct adapter *adapter = iflib_get_softc(ctx); 3950 struct ifnet *ifp = iflib_get_ifp(ctx); 3951 3952 switch (cnt) { 3953 case IFCOUNTER_COLLISIONS: 3954 return (adapter->stats.colc); 3955 case IFCOUNTER_IERRORS: 3956 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3957 adapter->stats.crcerrs + adapter->stats.algnerrc + 3958 adapter->stats.ruc + adapter->stats.roc + 3959 adapter->stats.mpc + adapter->stats.cexterr); 3960 case IFCOUNTER_OERRORS: 3961 return (adapter->stats.ecol + adapter->stats.latecol + 3962 adapter->watchdog_events); 3963 default: 3964 return (if_get_counter_default(ifp, cnt)); 3965 } 3966 } 3967 3968 /* Export a single 32-bit register via a read-only sysctl. */ 3969 static int 3970 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3971 { 3972 struct adapter *adapter; 3973 u_int val; 3974 3975 adapter = oidp->oid_arg1; 3976 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3977 return (sysctl_handle_int(oidp, &val, 0, req)); 3978 } 3979 3980 /* 3981 * Add sysctl variables, one per statistic, to the system. 3982 */ 3983 static void 3984 em_add_hw_stats(struct adapter *adapter) 3985 { 3986 device_t dev = iflib_get_dev(adapter->ctx); 3987 struct em_tx_queue *tx_que = adapter->tx_queues; 3988 struct em_rx_queue *rx_que = adapter->rx_queues; 3989 3990 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3991 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3992 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3993 struct e1000_hw_stats *stats = &adapter->stats; 3994 3995 struct sysctl_oid *stat_node, *queue_node, *int_node; 3996 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3997 3998 #define QUEUE_NAME_LEN 32 3999 char namebuf[QUEUE_NAME_LEN]; 4000 4001 /* Driver Statistics */ 4002 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4003 CTLFLAG_RD, &adapter->dropped_pkts, 4004 "Driver dropped packets"); 4005 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4006 CTLFLAG_RD, &adapter->link_irq, 4007 "Link MSI-X IRQ Handled"); 4008 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4009 CTLFLAG_RD, &adapter->rx_overruns, 4010 "RX overruns"); 4011 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4012 CTLFLAG_RD, &adapter->watchdog_events, 4013 "Watchdog timeouts"); 4014 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4015 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4016 em_sysctl_reg_handler, "IU", 4017 "Device Control Register"); 4018 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4019 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4020 em_sysctl_reg_handler, "IU", 4021 "Receiver Control Register"); 4022 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4023 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4024 "Flow Control High Watermark"); 4025 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4026 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4027 "Flow Control Low Watermark"); 4028 4029 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4030 struct tx_ring *txr = &tx_que->txr; 4031 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4032 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4033 CTLFLAG_RD, NULL, "TX Queue Name"); 4034 queue_list = SYSCTL_CHILDREN(queue_node); 4035 4036 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4037 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4038 E1000_TDH(txr->me), 4039 em_sysctl_reg_handler, "IU", 4040 "Transmit Descriptor Head"); 4041 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4042 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4043 E1000_TDT(txr->me), 4044 em_sysctl_reg_handler, "IU", 4045 "Transmit Descriptor Tail"); 4046 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4047 CTLFLAG_RD, &txr->tx_irq, 4048 "Queue MSI-X Transmit Interrupts"); 4049 } 4050 4051 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4052 struct rx_ring *rxr = &rx_que->rxr; 4053 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4054 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4055 CTLFLAG_RD, NULL, "RX Queue Name"); 4056 queue_list = SYSCTL_CHILDREN(queue_node); 4057 4058 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4059 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4060 E1000_RDH(rxr->me), 4061 em_sysctl_reg_handler, "IU", 4062 "Receive Descriptor Head"); 4063 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4064 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4065 E1000_RDT(rxr->me), 4066 em_sysctl_reg_handler, "IU", 4067 "Receive Descriptor Tail"); 4068 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4069 CTLFLAG_RD, &rxr->rx_irq, 4070 "Queue MSI-X Receive Interrupts"); 4071 } 4072 4073 /* MAC stats get their own sub node */ 4074 4075 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4076 CTLFLAG_RD, NULL, "Statistics"); 4077 stat_list = SYSCTL_CHILDREN(stat_node); 4078 4079 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4080 CTLFLAG_RD, &stats->ecol, 4081 "Excessive collisions"); 4082 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4083 CTLFLAG_RD, &stats->scc, 4084 "Single collisions"); 4085 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4086 CTLFLAG_RD, &stats->mcc, 4087 "Multiple collisions"); 4088 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4089 CTLFLAG_RD, &stats->latecol, 4090 "Late collisions"); 4091 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4092 CTLFLAG_RD, &stats->colc, 4093 "Collision Count"); 4094 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4095 CTLFLAG_RD, &adapter->stats.symerrs, 4096 "Symbol Errors"); 4097 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4098 CTLFLAG_RD, &adapter->stats.sec, 4099 "Sequence Errors"); 4100 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4101 CTLFLAG_RD, &adapter->stats.dc, 4102 "Defer Count"); 4103 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4104 CTLFLAG_RD, &adapter->stats.mpc, 4105 "Missed Packets"); 4106 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4107 CTLFLAG_RD, &adapter->stats.rnbc, 4108 "Receive No Buffers"); 4109 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4110 CTLFLAG_RD, &adapter->stats.ruc, 4111 "Receive Undersize"); 4112 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4113 CTLFLAG_RD, &adapter->stats.rfc, 4114 "Fragmented Packets Received "); 4115 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4116 CTLFLAG_RD, &adapter->stats.roc, 4117 "Oversized Packets Received"); 4118 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4119 CTLFLAG_RD, &adapter->stats.rjc, 4120 "Recevied Jabber"); 4121 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4122 CTLFLAG_RD, &adapter->stats.rxerrc, 4123 "Receive Errors"); 4124 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4125 CTLFLAG_RD, &adapter->stats.crcerrs, 4126 "CRC errors"); 4127 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4128 CTLFLAG_RD, &adapter->stats.algnerrc, 4129 "Alignment Errors"); 4130 /* On 82575 these are collision counts */ 4131 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4132 CTLFLAG_RD, &adapter->stats.cexterr, 4133 "Collision/Carrier extension errors"); 4134 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4135 CTLFLAG_RD, &adapter->stats.xonrxc, 4136 "XON Received"); 4137 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4138 CTLFLAG_RD, &adapter->stats.xontxc, 4139 "XON Transmitted"); 4140 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4141 CTLFLAG_RD, &adapter->stats.xoffrxc, 4142 "XOFF Received"); 4143 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4144 CTLFLAG_RD, &adapter->stats.xofftxc, 4145 "XOFF Transmitted"); 4146 4147 /* Packet Reception Stats */ 4148 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4149 CTLFLAG_RD, &adapter->stats.tpr, 4150 "Total Packets Received "); 4151 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4152 CTLFLAG_RD, &adapter->stats.gprc, 4153 "Good Packets Received"); 4154 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4155 CTLFLAG_RD, &adapter->stats.bprc, 4156 "Broadcast Packets Received"); 4157 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4158 CTLFLAG_RD, &adapter->stats.mprc, 4159 "Multicast Packets Received"); 4160 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4161 CTLFLAG_RD, &adapter->stats.prc64, 4162 "64 byte frames received "); 4163 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4164 CTLFLAG_RD, &adapter->stats.prc127, 4165 "65-127 byte frames received"); 4166 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4167 CTLFLAG_RD, &adapter->stats.prc255, 4168 "128-255 byte frames received"); 4169 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4170 CTLFLAG_RD, &adapter->stats.prc511, 4171 "256-511 byte frames received"); 4172 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4173 CTLFLAG_RD, &adapter->stats.prc1023, 4174 "512-1023 byte frames received"); 4175 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4176 CTLFLAG_RD, &adapter->stats.prc1522, 4177 "1023-1522 byte frames received"); 4178 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4179 CTLFLAG_RD, &adapter->stats.gorc, 4180 "Good Octets Received"); 4181 4182 /* Packet Transmission Stats */ 4183 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4184 CTLFLAG_RD, &adapter->stats.gotc, 4185 "Good Octets Transmitted"); 4186 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4187 CTLFLAG_RD, &adapter->stats.tpt, 4188 "Total Packets Transmitted"); 4189 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4190 CTLFLAG_RD, &adapter->stats.gptc, 4191 "Good Packets Transmitted"); 4192 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4193 CTLFLAG_RD, &adapter->stats.bptc, 4194 "Broadcast Packets Transmitted"); 4195 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4196 CTLFLAG_RD, &adapter->stats.mptc, 4197 "Multicast Packets Transmitted"); 4198 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4199 CTLFLAG_RD, &adapter->stats.ptc64, 4200 "64 byte frames transmitted "); 4201 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4202 CTLFLAG_RD, &adapter->stats.ptc127, 4203 "65-127 byte frames transmitted"); 4204 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4205 CTLFLAG_RD, &adapter->stats.ptc255, 4206 "128-255 byte frames transmitted"); 4207 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4208 CTLFLAG_RD, &adapter->stats.ptc511, 4209 "256-511 byte frames transmitted"); 4210 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4211 CTLFLAG_RD, &adapter->stats.ptc1023, 4212 "512-1023 byte frames transmitted"); 4213 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4214 CTLFLAG_RD, &adapter->stats.ptc1522, 4215 "1024-1522 byte frames transmitted"); 4216 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4217 CTLFLAG_RD, &adapter->stats.tsctc, 4218 "TSO Contexts Transmitted"); 4219 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4220 CTLFLAG_RD, &adapter->stats.tsctfc, 4221 "TSO Contexts Failed"); 4222 4223 4224 /* Interrupt Stats */ 4225 4226 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4227 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4228 int_list = SYSCTL_CHILDREN(int_node); 4229 4230 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4231 CTLFLAG_RD, &adapter->stats.iac, 4232 "Interrupt Assertion Count"); 4233 4234 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4235 CTLFLAG_RD, &adapter->stats.icrxptc, 4236 "Interrupt Cause Rx Pkt Timer Expire Count"); 4237 4238 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4239 CTLFLAG_RD, &adapter->stats.icrxatc, 4240 "Interrupt Cause Rx Abs Timer Expire Count"); 4241 4242 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4243 CTLFLAG_RD, &adapter->stats.ictxptc, 4244 "Interrupt Cause Tx Pkt Timer Expire Count"); 4245 4246 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4247 CTLFLAG_RD, &adapter->stats.ictxatc, 4248 "Interrupt Cause Tx Abs Timer Expire Count"); 4249 4250 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4251 CTLFLAG_RD, &adapter->stats.ictxqec, 4252 "Interrupt Cause Tx Queue Empty Count"); 4253 4254 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4255 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4256 "Interrupt Cause Tx Queue Min Thresh Count"); 4257 4258 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4259 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4260 "Interrupt Cause Rx Desc Min Thresh Count"); 4261 4262 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4263 CTLFLAG_RD, &adapter->stats.icrxoc, 4264 "Interrupt Cause Receiver Overrun Count"); 4265 } 4266 4267 /********************************************************************** 4268 * 4269 * This routine provides a way to dump out the adapter eeprom, 4270 * often a useful debug/service tool. This only dumps the first 4271 * 32 words, stuff that matters is in that extent. 4272 * 4273 **********************************************************************/ 4274 static int 4275 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4276 { 4277 struct adapter *adapter = (struct adapter *)arg1; 4278 int error; 4279 int result; 4280 4281 result = -1; 4282 error = sysctl_handle_int(oidp, &result, 0, req); 4283 4284 if (error || !req->newptr) 4285 return (error); 4286 4287 /* 4288 * This value will cause a hex dump of the 4289 * first 32 16-bit words of the EEPROM to 4290 * the screen. 4291 */ 4292 if (result == 1) 4293 em_print_nvm_info(adapter); 4294 4295 return (error); 4296 } 4297 4298 static void 4299 em_print_nvm_info(struct adapter *adapter) 4300 { 4301 u16 eeprom_data; 4302 int i, j, row = 0; 4303 4304 /* Its a bit crude, but it gets the job done */ 4305 printf("\nInterface EEPROM Dump:\n"); 4306 printf("Offset\n0x0000 "); 4307 for (i = 0, j = 0; i < 32; i++, j++) { 4308 if (j == 8) { /* Make the offset block */ 4309 j = 0; ++row; 4310 printf("\n0x00%x0 ",row); 4311 } 4312 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4313 printf("%04x ", eeprom_data); 4314 } 4315 printf("\n"); 4316 } 4317 4318 static int 4319 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4320 { 4321 struct em_int_delay_info *info; 4322 struct adapter *adapter; 4323 u32 regval; 4324 int error, usecs, ticks; 4325 4326 info = (struct em_int_delay_info *) arg1; 4327 usecs = info->value; 4328 error = sysctl_handle_int(oidp, &usecs, 0, req); 4329 if (error != 0 || req->newptr == NULL) 4330 return (error); 4331 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4332 return (EINVAL); 4333 info->value = usecs; 4334 ticks = EM_USECS_TO_TICKS(usecs); 4335 if (info->offset == E1000_ITR) /* units are 256ns here */ 4336 ticks *= 4; 4337 4338 adapter = info->adapter; 4339 4340 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4341 regval = (regval & ~0xffff) | (ticks & 0xffff); 4342 /* Handle a few special cases. */ 4343 switch (info->offset) { 4344 case E1000_RDTR: 4345 break; 4346 case E1000_TIDV: 4347 if (ticks == 0) { 4348 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4349 /* Don't write 0 into the TIDV register. */ 4350 regval++; 4351 } else 4352 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4353 break; 4354 } 4355 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4356 return (0); 4357 } 4358 4359 static void 4360 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4361 const char *description, struct em_int_delay_info *info, 4362 int offset, int value) 4363 { 4364 info->adapter = adapter; 4365 info->offset = offset; 4366 info->value = value; 4367 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4368 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4369 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4370 info, 0, em_sysctl_int_delay, "I", description); 4371 } 4372 4373 /* 4374 * Set flow control using sysctl: 4375 * Flow control values: 4376 * 0 - off 4377 * 1 - rx pause 4378 * 2 - tx pause 4379 * 3 - full 4380 */ 4381 static int 4382 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4383 { 4384 int error; 4385 static int input = 3; /* default is full */ 4386 struct adapter *adapter = (struct adapter *) arg1; 4387 4388 error = sysctl_handle_int(oidp, &input, 0, req); 4389 4390 if ((error) || (req->newptr == NULL)) 4391 return (error); 4392 4393 if (input == adapter->fc) /* no change? */ 4394 return (error); 4395 4396 switch (input) { 4397 case e1000_fc_rx_pause: 4398 case e1000_fc_tx_pause: 4399 case e1000_fc_full: 4400 case e1000_fc_none: 4401 adapter->hw.fc.requested_mode = input; 4402 adapter->fc = input; 4403 break; 4404 default: 4405 /* Do nothing */ 4406 return (error); 4407 } 4408 4409 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4410 e1000_force_mac_fc(&adapter->hw); 4411 return (error); 4412 } 4413 4414 /* 4415 * Manage Energy Efficient Ethernet: 4416 * Control values: 4417 * 0/1 - enabled/disabled 4418 */ 4419 static int 4420 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4421 { 4422 struct adapter *adapter = (struct adapter *) arg1; 4423 int error, value; 4424 4425 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4426 error = sysctl_handle_int(oidp, &value, 0, req); 4427 if (error || req->newptr == NULL) 4428 return (error); 4429 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4430 em_if_init(adapter->ctx); 4431 4432 return (0); 4433 } 4434 4435 static int 4436 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4437 { 4438 struct adapter *adapter; 4439 int error; 4440 int result; 4441 4442 result = -1; 4443 error = sysctl_handle_int(oidp, &result, 0, req); 4444 4445 if (error || !req->newptr) 4446 return (error); 4447 4448 if (result == 1) { 4449 adapter = (struct adapter *) arg1; 4450 em_print_debug_info(adapter); 4451 } 4452 4453 return (error); 4454 } 4455 4456 static int 4457 em_get_rs(SYSCTL_HANDLER_ARGS) 4458 { 4459 struct adapter *adapter = (struct adapter *) arg1; 4460 int error; 4461 int result; 4462 4463 result = 0; 4464 error = sysctl_handle_int(oidp, &result, 0, req); 4465 4466 if (error || !req->newptr || result != 1) 4467 return (error); 4468 em_dump_rs(adapter); 4469 4470 return (error); 4471 } 4472 4473 static void 4474 em_if_debug(if_ctx_t ctx) 4475 { 4476 em_dump_rs(iflib_get_softc(ctx)); 4477 } 4478 4479 /* 4480 * This routine is meant to be fluid, add whatever is 4481 * needed for debugging a problem. -jfv 4482 */ 4483 static void 4484 em_print_debug_info(struct adapter *adapter) 4485 { 4486 device_t dev = iflib_get_dev(adapter->ctx); 4487 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4488 struct tx_ring *txr = &adapter->tx_queues->txr; 4489 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4490 4491 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4492 printf("Interface is RUNNING "); 4493 else 4494 printf("Interface is NOT RUNNING\n"); 4495 4496 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4497 printf("and INACTIVE\n"); 4498 else 4499 printf("and ACTIVE\n"); 4500 4501 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4502 device_printf(dev, "TX Queue %d ------\n", i); 4503 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4504 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4505 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4506 4507 } 4508 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4509 device_printf(dev, "RX Queue %d ------\n", j); 4510 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4511 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4512 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4513 } 4514 } 4515 4516 /* 4517 * 82574 only: 4518 * Write a new value to the EEPROM increasing the number of MSI-X 4519 * vectors from 3 to 5, for proper multiqueue support. 4520 */ 4521 static void 4522 em_enable_vectors_82574(if_ctx_t ctx) 4523 { 4524 struct adapter *adapter = iflib_get_softc(ctx); 4525 struct e1000_hw *hw = &adapter->hw; 4526 device_t dev = iflib_get_dev(ctx); 4527 u16 edata; 4528 4529 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4530 if (bootverbose) 4531 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4532 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4533 device_printf(dev, "Writing to eeprom: increasing " 4534 "reported MSI-X vectors from 3 to 5...\n"); 4535 edata &= ~(EM_NVM_MSIX_N_MASK); 4536 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4537 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4538 e1000_update_nvm_checksum(hw); 4539 device_printf(dev, "Writing to eeprom: done\n"); 4540 } 4541 } 4542