1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) - lem-class legacy devices */ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 98 99 /* Intel(R) - em-class devices */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 197 /* required last entry */ 198 PVID_END 199 }; 200 201 static pci_vendor_info_t igb_vendor_info_array[] = 202 { 203 /* Intel(R) - igb-class devices */ 204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 238 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 239 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 240 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 242 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 244 /* required last entry */ 245 PVID_END 246 }; 247 248 /********************************************************************* 249 * Function prototypes 250 *********************************************************************/ 251 static void *em_register(device_t dev); 252 static void *igb_register(device_t dev); 253 static int em_if_attach_pre(if_ctx_t ctx); 254 static int em_if_attach_post(if_ctx_t ctx); 255 static int em_if_detach(if_ctx_t ctx); 256 static int em_if_shutdown(if_ctx_t ctx); 257 static int em_if_suspend(if_ctx_t ctx); 258 static int em_if_resume(if_ctx_t ctx); 259 260 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 261 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 262 static void em_if_queues_free(if_ctx_t ctx); 263 264 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 265 static void em_if_init(if_ctx_t ctx); 266 static void em_if_stop(if_ctx_t ctx); 267 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 268 static int em_if_media_change(if_ctx_t ctx); 269 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 270 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 271 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 272 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 273 static void em_if_watchdog_reset(if_ctx_t ctx); 274 static bool em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 275 276 static void em_identify_hardware(if_ctx_t ctx); 277 static int em_allocate_pci_resources(if_ctx_t ctx); 278 static void em_free_pci_resources(if_ctx_t ctx); 279 static void em_reset(if_ctx_t ctx); 280 static int em_setup_interface(if_ctx_t ctx); 281 static int em_setup_msix(if_ctx_t ctx); 282 283 static void em_initialize_transmit_unit(if_ctx_t ctx); 284 static void em_initialize_receive_unit(if_ctx_t ctx); 285 286 static void em_if_intr_enable(if_ctx_t ctx); 287 static void em_if_intr_disable(if_ctx_t ctx); 288 static void igb_if_intr_enable(if_ctx_t ctx); 289 static void igb_if_intr_disable(if_ctx_t ctx); 290 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 291 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 292 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 293 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 294 static void em_if_multi_set(if_ctx_t ctx); 295 static void em_if_update_admin_status(if_ctx_t ctx); 296 static void em_if_debug(if_ctx_t ctx); 297 static void em_update_stats_counters(struct adapter *); 298 static void em_add_hw_stats(struct adapter *adapter); 299 static int em_if_set_promisc(if_ctx_t ctx, int flags); 300 static void em_setup_vlan_hw_support(struct adapter *); 301 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 302 static void em_print_nvm_info(struct adapter *); 303 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 304 static int em_get_rs(SYSCTL_HANDLER_ARGS); 305 static void em_print_debug_info(struct adapter *); 306 static int em_is_valid_ether_addr(u8 *); 307 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 308 static void em_add_int_delay_sysctl(struct adapter *, const char *, 309 const char *, struct em_int_delay_info *, int, int); 310 /* Management and WOL Support */ 311 static void em_init_manageability(struct adapter *); 312 static void em_release_manageability(struct adapter *); 313 static void em_get_hw_control(struct adapter *); 314 static void em_release_hw_control(struct adapter *); 315 static void em_get_wakeup(if_ctx_t ctx); 316 static void em_enable_wakeup(if_ctx_t ctx); 317 static int em_enable_phy_wakeup(struct adapter *); 318 static void em_disable_aspm(struct adapter *); 319 320 int em_intr(void *arg); 321 322 /* MSI-X handlers */ 323 static int em_if_msix_intr_assign(if_ctx_t, int); 324 static int em_msix_link(void *); 325 static void em_handle_link(void *context); 326 327 static void em_enable_vectors_82574(if_ctx_t); 328 329 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 330 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 331 static void em_if_led_func(if_ctx_t ctx, int onoff); 332 333 static int em_get_regs(SYSCTL_HANDLER_ARGS); 334 335 static void lem_smartspeed(struct adapter *adapter); 336 static void igb_configure_queues(struct adapter *adapter); 337 338 339 /********************************************************************* 340 * FreeBSD Device Interface Entry Points 341 *********************************************************************/ 342 static device_method_t em_methods[] = { 343 /* Device interface */ 344 DEVMETHOD(device_register, em_register), 345 DEVMETHOD(device_probe, iflib_device_probe), 346 DEVMETHOD(device_attach, iflib_device_attach), 347 DEVMETHOD(device_detach, iflib_device_detach), 348 DEVMETHOD(device_shutdown, iflib_device_shutdown), 349 DEVMETHOD(device_suspend, iflib_device_suspend), 350 DEVMETHOD(device_resume, iflib_device_resume), 351 DEVMETHOD_END 352 }; 353 354 static device_method_t igb_methods[] = { 355 /* Device interface */ 356 DEVMETHOD(device_register, igb_register), 357 DEVMETHOD(device_probe, iflib_device_probe), 358 DEVMETHOD(device_attach, iflib_device_attach), 359 DEVMETHOD(device_detach, iflib_device_detach), 360 DEVMETHOD(device_shutdown, iflib_device_shutdown), 361 DEVMETHOD(device_suspend, iflib_device_suspend), 362 DEVMETHOD(device_resume, iflib_device_resume), 363 DEVMETHOD_END 364 }; 365 366 367 static driver_t em_driver = { 368 "em", em_methods, sizeof(struct adapter), 369 }; 370 371 static devclass_t em_devclass; 372 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 373 374 MODULE_DEPEND(em, pci, 1, 1, 1); 375 MODULE_DEPEND(em, ether, 1, 1, 1); 376 MODULE_DEPEND(em, iflib, 1, 1, 1); 377 378 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 379 380 static driver_t igb_driver = { 381 "igb", igb_methods, sizeof(struct adapter), 382 }; 383 384 static devclass_t igb_devclass; 385 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 386 387 MODULE_DEPEND(igb, pci, 1, 1, 1); 388 MODULE_DEPEND(igb, ether, 1, 1, 1); 389 MODULE_DEPEND(igb, iflib, 1, 1, 1); 390 391 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 392 393 static device_method_t em_if_methods[] = { 394 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 395 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 396 DEVMETHOD(ifdi_detach, em_if_detach), 397 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 398 DEVMETHOD(ifdi_suspend, em_if_suspend), 399 DEVMETHOD(ifdi_resume, em_if_resume), 400 DEVMETHOD(ifdi_init, em_if_init), 401 DEVMETHOD(ifdi_stop, em_if_stop), 402 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 403 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 404 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 405 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 406 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 407 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 408 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 409 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 410 DEVMETHOD(ifdi_media_status, em_if_media_status), 411 DEVMETHOD(ifdi_media_change, em_if_media_change), 412 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 413 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 414 DEVMETHOD(ifdi_timer, em_if_timer), 415 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 416 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 417 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 418 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 419 DEVMETHOD(ifdi_led_func, em_if_led_func), 420 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 421 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 422 DEVMETHOD(ifdi_debug, em_if_debug), 423 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 424 DEVMETHOD_END 425 }; 426 427 static driver_t em_if_driver = { 428 "em_if", em_if_methods, sizeof(struct adapter) 429 }; 430 431 static device_method_t igb_if_methods[] = { 432 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 433 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 434 DEVMETHOD(ifdi_detach, em_if_detach), 435 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 436 DEVMETHOD(ifdi_suspend, em_if_suspend), 437 DEVMETHOD(ifdi_resume, em_if_resume), 438 DEVMETHOD(ifdi_init, em_if_init), 439 DEVMETHOD(ifdi_stop, em_if_stop), 440 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 441 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 442 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 443 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 444 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 445 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 446 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 447 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 448 DEVMETHOD(ifdi_media_status, em_if_media_status), 449 DEVMETHOD(ifdi_media_change, em_if_media_change), 450 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 451 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 452 DEVMETHOD(ifdi_timer, em_if_timer), 453 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 454 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 455 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 456 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 457 DEVMETHOD(ifdi_led_func, em_if_led_func), 458 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 459 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 460 DEVMETHOD(ifdi_debug, em_if_debug), 461 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 462 DEVMETHOD_END 463 }; 464 465 static driver_t igb_if_driver = { 466 "igb_if", igb_if_methods, sizeof(struct adapter) 467 }; 468 469 /********************************************************************* 470 * Tunable default values. 471 *********************************************************************/ 472 473 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 474 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 475 476 #define MAX_INTS_PER_SEC 8000 477 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 478 479 /* Allow common code without TSO */ 480 #ifndef CSUM_TSO 481 #define CSUM_TSO 0 482 #endif 483 484 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 485 "EM driver parameters"); 486 487 static int em_disable_crc_stripping = 0; 488 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 489 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 490 491 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 492 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 493 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 494 0, "Default transmit interrupt delay in usecs"); 495 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 496 0, "Default receive interrupt delay in usecs"); 497 498 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 499 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 500 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 501 &em_tx_abs_int_delay_dflt, 0, 502 "Default transmit interrupt delay limit in usecs"); 503 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 504 &em_rx_abs_int_delay_dflt, 0, 505 "Default receive interrupt delay limit in usecs"); 506 507 static int em_smart_pwr_down = FALSE; 508 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 509 0, "Set to true to leave smart power down enabled on newer adapters"); 510 511 /* Controls whether promiscuous also shows bad packets */ 512 static int em_debug_sbp = FALSE; 513 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 514 "Show bad packets in promiscuous mode"); 515 516 /* How many packets rxeof tries to clean at a time */ 517 static int em_rx_process_limit = 100; 518 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 519 &em_rx_process_limit, 0, 520 "Maximum number of received packets to process " 521 "at a time, -1 means unlimited"); 522 523 /* Energy efficient ethernet - default to OFF */ 524 static int eee_setting = 1; 525 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 526 "Enable Energy Efficient Ethernet"); 527 528 /* 529 ** Tuneable Interrupt rate 530 */ 531 static int em_max_interrupt_rate = 8000; 532 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 533 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 534 535 536 537 /* Global used in WOL setup with multiport cards */ 538 static int global_quad_port_a = 0; 539 540 extern struct if_txrx igb_txrx; 541 extern struct if_txrx em_txrx; 542 extern struct if_txrx lem_txrx; 543 544 static struct if_shared_ctx em_sctx_init = { 545 .isc_magic = IFLIB_MAGIC, 546 .isc_q_align = PAGE_SIZE, 547 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 548 .isc_tx_maxsegsize = PAGE_SIZE, 549 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 550 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 551 .isc_rx_maxsize = MJUM9BYTES, 552 .isc_rx_nsegments = 1, 553 .isc_rx_maxsegsize = MJUM9BYTES, 554 .isc_nfl = 1, 555 .isc_nrxqs = 1, 556 .isc_ntxqs = 1, 557 .isc_admin_intrcnt = 1, 558 .isc_vendor_info = em_vendor_info_array, 559 .isc_driver_version = em_driver_version, 560 .isc_driver = &em_if_driver, 561 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 562 563 .isc_nrxd_min = {EM_MIN_RXD}, 564 .isc_ntxd_min = {EM_MIN_TXD}, 565 .isc_nrxd_max = {EM_MAX_RXD}, 566 .isc_ntxd_max = {EM_MAX_TXD}, 567 .isc_nrxd_default = {EM_DEFAULT_RXD}, 568 .isc_ntxd_default = {EM_DEFAULT_TXD}, 569 }; 570 571 static struct if_shared_ctx igb_sctx_init = { 572 .isc_magic = IFLIB_MAGIC, 573 .isc_q_align = PAGE_SIZE, 574 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 575 .isc_tx_maxsegsize = PAGE_SIZE, 576 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 577 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 578 .isc_rx_maxsize = MJUM9BYTES, 579 .isc_rx_nsegments = 1, 580 .isc_rx_maxsegsize = MJUM9BYTES, 581 .isc_nfl = 1, 582 .isc_nrxqs = 1, 583 .isc_ntxqs = 1, 584 .isc_admin_intrcnt = 1, 585 .isc_vendor_info = igb_vendor_info_array, 586 .isc_driver_version = em_driver_version, 587 .isc_driver = &igb_if_driver, 588 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 589 590 .isc_nrxd_min = {EM_MIN_RXD}, 591 .isc_ntxd_min = {EM_MIN_TXD}, 592 .isc_nrxd_max = {IGB_MAX_RXD}, 593 .isc_ntxd_max = {IGB_MAX_TXD}, 594 .isc_nrxd_default = {EM_DEFAULT_RXD}, 595 .isc_ntxd_default = {EM_DEFAULT_TXD}, 596 }; 597 598 /***************************************************************** 599 * 600 * Dump Registers 601 * 602 ****************************************************************/ 603 #define IGB_REGS_LEN 739 604 605 static int em_get_regs(SYSCTL_HANDLER_ARGS) 606 { 607 struct adapter *adapter = (struct adapter *)arg1; 608 struct e1000_hw *hw = &adapter->hw; 609 struct sbuf *sb; 610 u32 *regs_buff; 611 int rc; 612 613 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 614 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 615 616 rc = sysctl_wire_old_buffer(req, 0); 617 MPASS(rc == 0); 618 if (rc != 0) { 619 free(regs_buff, M_DEVBUF); 620 return (rc); 621 } 622 623 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 624 MPASS(sb != NULL); 625 if (sb == NULL) { 626 free(regs_buff, M_DEVBUF); 627 return (ENOMEM); 628 } 629 630 /* General Registers */ 631 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 632 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 633 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 634 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 635 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 636 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 637 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 638 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 639 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 640 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 641 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 642 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 643 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 644 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 645 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 646 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 647 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 648 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 649 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 650 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 651 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 652 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 653 654 sbuf_printf(sb, "General Registers\n"); 655 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 656 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 657 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 658 659 sbuf_printf(sb, "Interrupt Registers\n"); 660 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 661 662 sbuf_printf(sb, "RX Registers\n"); 663 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 664 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 665 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 666 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 667 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 668 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 669 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 670 671 sbuf_printf(sb, "TX Registers\n"); 672 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 673 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 674 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 675 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 676 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 677 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 678 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 679 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 680 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 681 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 682 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 683 684 free(regs_buff, M_DEVBUF); 685 686 #ifdef DUMP_DESCS 687 { 688 if_softc_ctx_t scctx = adapter->shared; 689 struct rx_ring *rxr = &rx_que->rxr; 690 struct tx_ring *txr = &tx_que->txr; 691 int ntxd = scctx->isc_ntxd[0]; 692 int nrxd = scctx->isc_nrxd[0]; 693 int j; 694 695 for (j = 0; j < nrxd; j++) { 696 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 697 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 698 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 699 } 700 701 for (j = 0; j < min(ntxd, 256); j++) { 702 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 703 704 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 705 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 706 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 707 708 } 709 } 710 #endif 711 712 rc = sbuf_finish(sb); 713 sbuf_delete(sb); 714 return(rc); 715 } 716 717 static void * 718 em_register(device_t dev) 719 { 720 return (&em_sctx_init); 721 } 722 723 static void * 724 igb_register(device_t dev) 725 { 726 return (&igb_sctx_init); 727 } 728 729 static int 730 em_set_num_queues(if_ctx_t ctx) 731 { 732 struct adapter *adapter = iflib_get_softc(ctx); 733 int maxqueues; 734 735 /* Sanity check based on HW */ 736 switch (adapter->hw.mac.type) { 737 case e1000_82576: 738 case e1000_82580: 739 case e1000_i350: 740 case e1000_i354: 741 maxqueues = 8; 742 break; 743 case e1000_i210: 744 case e1000_82575: 745 maxqueues = 4; 746 break; 747 case e1000_i211: 748 case e1000_82574: 749 maxqueues = 2; 750 break; 751 default: 752 maxqueues = 1; 753 break; 754 } 755 756 return (maxqueues); 757 } 758 759 #define LEM_CAPS \ 760 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 761 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 762 763 #define EM_CAPS \ 764 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 765 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 766 IFCAP_LRO | IFCAP_VLAN_HWTSO 767 768 #define IGB_CAPS \ 769 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 770 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 771 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 772 IFCAP_TSO6 773 774 /********************************************************************* 775 * Device initialization routine 776 * 777 * The attach entry point is called when the driver is being loaded. 778 * This routine identifies the type of hardware, allocates all resources 779 * and initializes the hardware. 780 * 781 * return 0 on success, positive on failure 782 *********************************************************************/ 783 static int 784 em_if_attach_pre(if_ctx_t ctx) 785 { 786 struct adapter *adapter; 787 if_softc_ctx_t scctx; 788 device_t dev; 789 struct e1000_hw *hw; 790 int error = 0; 791 792 INIT_DEBUGOUT("em_if_attach_pre: begin"); 793 dev = iflib_get_dev(ctx); 794 adapter = iflib_get_softc(ctx); 795 796 adapter->ctx = adapter->osdep.ctx = ctx; 797 adapter->dev = adapter->osdep.dev = dev; 798 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 799 adapter->media = iflib_get_media(ctx); 800 hw = &adapter->hw; 801 802 adapter->tx_process_limit = scctx->isc_ntxd[0]; 803 804 /* SYSCTL stuff */ 805 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 806 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 807 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 808 adapter, 0, em_sysctl_nvm_info, "I", "NVM Information"); 809 810 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 811 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 812 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 813 adapter, 0, em_sysctl_debug_info, "I", "Debug Information"); 814 815 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 817 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 818 adapter, 0, em_set_flowcntl, "I", "Flow Control"); 819 820 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 821 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 822 OID_AUTO, "reg_dump", 823 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 824 em_get_regs, "A", "Dump Registers"); 825 826 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 827 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 828 OID_AUTO, "rs_dump", 829 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 830 em_get_rs, "I", "Dump RS indexes"); 831 832 /* Determine hardware and mac info */ 833 em_identify_hardware(ctx); 834 835 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 836 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 837 if (bootverbose) 838 device_printf(dev, "attach_pre capping queues at %d\n", 839 scctx->isc_ntxqsets_max); 840 841 if (hw->mac.type >= igb_mac_min) { 842 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 843 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 844 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 845 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 846 scctx->isc_txrx = &igb_txrx; 847 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 848 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 849 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 850 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 851 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 852 CSUM_IP6_TCP | CSUM_IP6_UDP; 853 if (hw->mac.type != e1000_82575) 854 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 855 /* 856 ** Some new devices, as with ixgbe, now may 857 ** use a different BAR, so we need to keep 858 ** track of which is used. 859 */ 860 scctx->isc_msix_bar = pci_msix_table_bar(dev); 861 } else if (hw->mac.type >= em_mac_min) { 862 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 863 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 864 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 865 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 866 scctx->isc_txrx = &em_txrx; 867 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 868 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 869 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 870 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 871 /* 872 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 873 * by default as we don't have workarounds for all associated 874 * silicon errata. E. g., with several MACs such as 82573E, 875 * TSO only works at Gigabit speed and otherwise can cause the 876 * hardware to hang (which also would be next to impossible to 877 * work around given that already queued TSO-using descriptors 878 * would need to be flushed and vlan(4) reconfigured at runtime 879 * in case of a link speed change). Moreover, MACs like 82579 880 * still can hang at Gigabit even with all publicly documented 881 * TSO workarounds implemented. Generally, the penality of 882 * these workarounds is rather high and may involve copying 883 * mbuf data around so advantages of TSO lapse. Still, TSO may 884 * work for a few MACs of this class - at least when sticking 885 * with Gigabit - in which case users may enable TSO manually. 886 */ 887 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 888 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 889 /* 890 * We support MSI-X with 82574 only, but indicate to iflib(4) 891 * that it shall give MSI at least a try with other devices. 892 */ 893 if (hw->mac.type == e1000_82574) { 894 scctx->isc_msix_bar = pci_msix_table_bar(dev);; 895 } else { 896 scctx->isc_msix_bar = -1; 897 scctx->isc_disable_msix = 1; 898 } 899 } else { 900 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 901 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 902 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 903 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 904 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 905 scctx->isc_txrx = &lem_txrx; 906 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 907 if (hw->mac.type < e1000_82543) 908 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 909 /* INTx only */ 910 scctx->isc_msix_bar = 0; 911 } 912 913 /* Setup PCI resources */ 914 if (em_allocate_pci_resources(ctx)) { 915 device_printf(dev, "Allocation of PCI resources failed\n"); 916 error = ENXIO; 917 goto err_pci; 918 } 919 920 /* 921 ** For ICH8 and family we need to 922 ** map the flash memory, and this 923 ** must happen after the MAC is 924 ** identified 925 */ 926 if ((hw->mac.type == e1000_ich8lan) || 927 (hw->mac.type == e1000_ich9lan) || 928 (hw->mac.type == e1000_ich10lan) || 929 (hw->mac.type == e1000_pchlan) || 930 (hw->mac.type == e1000_pch2lan) || 931 (hw->mac.type == e1000_pch_lpt)) { 932 int rid = EM_BAR_TYPE_FLASH; 933 adapter->flash = bus_alloc_resource_any(dev, 934 SYS_RES_MEMORY, &rid, RF_ACTIVE); 935 if (adapter->flash == NULL) { 936 device_printf(dev, "Mapping of Flash failed\n"); 937 error = ENXIO; 938 goto err_pci; 939 } 940 /* This is used in the shared code */ 941 hw->flash_address = (u8 *)adapter->flash; 942 adapter->osdep.flash_bus_space_tag = 943 rman_get_bustag(adapter->flash); 944 adapter->osdep.flash_bus_space_handle = 945 rman_get_bushandle(adapter->flash); 946 } 947 /* 948 ** In the new SPT device flash is not a 949 ** separate BAR, rather it is also in BAR0, 950 ** so use the same tag and an offset handle for the 951 ** FLASH read/write macros in the shared code. 952 */ 953 else if (hw->mac.type >= e1000_pch_spt) { 954 adapter->osdep.flash_bus_space_tag = 955 adapter->osdep.mem_bus_space_tag; 956 adapter->osdep.flash_bus_space_handle = 957 adapter->osdep.mem_bus_space_handle 958 + E1000_FLASH_BASE_ADDR; 959 } 960 961 /* Do Shared Code initialization */ 962 error = e1000_setup_init_funcs(hw, TRUE); 963 if (error) { 964 device_printf(dev, "Setup of Shared code failed, error %d\n", 965 error); 966 error = ENXIO; 967 goto err_pci; 968 } 969 970 em_setup_msix(ctx); 971 e1000_get_bus_info(hw); 972 973 /* Set up some sysctls for the tunable interrupt delays */ 974 em_add_int_delay_sysctl(adapter, "rx_int_delay", 975 "receive interrupt delay in usecs", &adapter->rx_int_delay, 976 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 977 em_add_int_delay_sysctl(adapter, "tx_int_delay", 978 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 979 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 980 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 981 "receive interrupt delay limit in usecs", 982 &adapter->rx_abs_int_delay, 983 E1000_REGISTER(hw, E1000_RADV), 984 em_rx_abs_int_delay_dflt); 985 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 986 "transmit interrupt delay limit in usecs", 987 &adapter->tx_abs_int_delay, 988 E1000_REGISTER(hw, E1000_TADV), 989 em_tx_abs_int_delay_dflt); 990 em_add_int_delay_sysctl(adapter, "itr", 991 "interrupt delay limit in usecs/4", 992 &adapter->tx_itr, 993 E1000_REGISTER(hw, E1000_ITR), 994 DEFAULT_ITR); 995 996 hw->mac.autoneg = DO_AUTO_NEG; 997 hw->phy.autoneg_wait_to_complete = FALSE; 998 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 999 1000 if (hw->mac.type < em_mac_min) { 1001 e1000_init_script_state_82541(hw, TRUE); 1002 e1000_set_tbi_compatibility_82543(hw, TRUE); 1003 } 1004 /* Copper options */ 1005 if (hw->phy.media_type == e1000_media_type_copper) { 1006 hw->phy.mdix = AUTO_ALL_MODES; 1007 hw->phy.disable_polarity_correction = FALSE; 1008 hw->phy.ms_type = EM_MASTER_SLAVE; 1009 } 1010 1011 /* 1012 * Set the frame limits assuming 1013 * standard ethernet sized frames. 1014 */ 1015 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1016 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1017 1018 /* 1019 * This controls when hardware reports transmit completion 1020 * status. 1021 */ 1022 hw->mac.report_tx_early = 1; 1023 1024 /* Allocate multicast array memory. */ 1025 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1026 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1027 if (adapter->mta == NULL) { 1028 device_printf(dev, "Can not allocate multicast setup array\n"); 1029 error = ENOMEM; 1030 goto err_late; 1031 } 1032 1033 /* Check SOL/IDER usage */ 1034 if (e1000_check_reset_block(hw)) 1035 device_printf(dev, "PHY reset is blocked" 1036 " due to SOL/IDER session.\n"); 1037 1038 /* Sysctl for setting Energy Efficient Ethernet */ 1039 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1040 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1041 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1042 OID_AUTO, "eee_control", 1043 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1044 adapter, 0, em_sysctl_eee, "I", 1045 "Disable Energy Efficient Ethernet"); 1046 1047 /* 1048 ** Start from a known state, this is 1049 ** important in reading the nvm and 1050 ** mac from that. 1051 */ 1052 e1000_reset_hw(hw); 1053 1054 /* Make sure we have a good EEPROM before we read from it */ 1055 if (e1000_validate_nvm_checksum(hw) < 0) { 1056 /* 1057 ** Some PCI-E parts fail the first check due to 1058 ** the link being in sleep state, call it again, 1059 ** if it fails a second time its a real issue. 1060 */ 1061 if (e1000_validate_nvm_checksum(hw) < 0) { 1062 device_printf(dev, 1063 "The EEPROM Checksum Is Not Valid\n"); 1064 error = EIO; 1065 goto err_late; 1066 } 1067 } 1068 1069 /* Copy the permanent MAC address out of the EEPROM */ 1070 if (e1000_read_mac_addr(hw) < 0) { 1071 device_printf(dev, "EEPROM read error while reading MAC" 1072 " address\n"); 1073 error = EIO; 1074 goto err_late; 1075 } 1076 1077 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1078 if (adapter->vf_ifp) { 1079 u8 addr[ETHER_ADDR_LEN]; 1080 arc4rand(&addr, sizeof(addr), 0); 1081 addr[0] &= 0xFE; 1082 addr[0] |= 0x02; 1083 bcopy(addr, hw->mac.addr, sizeof(addr)); 1084 } else { 1085 device_printf(dev, "Invalid MAC address\n"); 1086 error = EIO; 1087 goto err_late; 1088 } 1089 } 1090 1091 /* 1092 * Get Wake-on-Lan and Management info for later use 1093 */ 1094 em_get_wakeup(ctx); 1095 1096 /* Enable only WOL MAGIC by default */ 1097 scctx->isc_capenable &= ~IFCAP_WOL; 1098 if (adapter->wol != 0) 1099 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1100 1101 iflib_set_mac(ctx, hw->mac.addr); 1102 1103 return (0); 1104 1105 err_late: 1106 em_release_hw_control(adapter); 1107 err_pci: 1108 em_free_pci_resources(ctx); 1109 free(adapter->mta, M_DEVBUF); 1110 1111 return (error); 1112 } 1113 1114 static int 1115 em_if_attach_post(if_ctx_t ctx) 1116 { 1117 struct adapter *adapter = iflib_get_softc(ctx); 1118 struct e1000_hw *hw = &adapter->hw; 1119 int error = 0; 1120 1121 /* Setup OS specific network interface */ 1122 error = em_setup_interface(ctx); 1123 if (error != 0) { 1124 device_printf(adapter->dev, "Interface setup failed: %d\n", error); 1125 goto err_late; 1126 } 1127 1128 em_reset(ctx); 1129 1130 /* Initialize statistics */ 1131 em_update_stats_counters(adapter); 1132 hw->mac.get_link_status = 1; 1133 em_if_update_admin_status(ctx); 1134 em_add_hw_stats(adapter); 1135 1136 /* Non-AMT based hardware can now take control from firmware */ 1137 if (adapter->has_manage && !adapter->has_amt) 1138 em_get_hw_control(adapter); 1139 1140 INIT_DEBUGOUT("em_if_attach_post: end"); 1141 1142 return (0); 1143 1144 err_late: 1145 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1146 return (error); 1147 } 1148 1149 /********************************************************************* 1150 * Device removal routine 1151 * 1152 * The detach entry point is called when the driver is being removed. 1153 * This routine stops the adapter and deallocates all the resources 1154 * that were allocated for driver operation. 1155 * 1156 * return 0 on success, positive on failure 1157 *********************************************************************/ 1158 static int 1159 em_if_detach(if_ctx_t ctx) 1160 { 1161 struct adapter *adapter = iflib_get_softc(ctx); 1162 1163 INIT_DEBUGOUT("em_if_detach: begin"); 1164 1165 e1000_phy_hw_reset(&adapter->hw); 1166 1167 em_release_manageability(adapter); 1168 em_release_hw_control(adapter); 1169 em_free_pci_resources(ctx); 1170 free(adapter->mta, M_DEVBUF); 1171 adapter->mta = NULL; 1172 1173 return (0); 1174 } 1175 1176 /********************************************************************* 1177 * 1178 * Shutdown entry point 1179 * 1180 **********************************************************************/ 1181 1182 static int 1183 em_if_shutdown(if_ctx_t ctx) 1184 { 1185 return em_if_suspend(ctx); 1186 } 1187 1188 /* 1189 * Suspend/resume device methods. 1190 */ 1191 static int 1192 em_if_suspend(if_ctx_t ctx) 1193 { 1194 struct adapter *adapter = iflib_get_softc(ctx); 1195 1196 em_release_manageability(adapter); 1197 em_release_hw_control(adapter); 1198 em_enable_wakeup(ctx); 1199 return (0); 1200 } 1201 1202 static int 1203 em_if_resume(if_ctx_t ctx) 1204 { 1205 struct adapter *adapter = iflib_get_softc(ctx); 1206 1207 if (adapter->hw.mac.type == e1000_pch2lan) 1208 e1000_resume_workarounds_pchlan(&adapter->hw); 1209 em_if_init(ctx); 1210 em_init_manageability(adapter); 1211 1212 return(0); 1213 } 1214 1215 static int 1216 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1217 { 1218 int max_frame_size; 1219 struct adapter *adapter = iflib_get_softc(ctx); 1220 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1221 1222 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1223 1224 switch (adapter->hw.mac.type) { 1225 case e1000_82571: 1226 case e1000_82572: 1227 case e1000_ich9lan: 1228 case e1000_ich10lan: 1229 case e1000_pch2lan: 1230 case e1000_pch_lpt: 1231 case e1000_pch_spt: 1232 case e1000_pch_cnp: 1233 case e1000_pch_tgp: 1234 case e1000_pch_adp: 1235 case e1000_pch_mtp: 1236 case e1000_82574: 1237 case e1000_82583: 1238 case e1000_80003es2lan: 1239 /* 9K Jumbo Frame size */ 1240 max_frame_size = 9234; 1241 break; 1242 case e1000_pchlan: 1243 max_frame_size = 4096; 1244 break; 1245 case e1000_82542: 1246 case e1000_ich8lan: 1247 /* Adapters that do not support jumbo frames */ 1248 max_frame_size = ETHER_MAX_LEN; 1249 break; 1250 default: 1251 if (adapter->hw.mac.type >= igb_mac_min) 1252 max_frame_size = 9234; 1253 else /* lem */ 1254 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1255 } 1256 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1257 return (EINVAL); 1258 } 1259 1260 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1261 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1262 return (0); 1263 } 1264 1265 /********************************************************************* 1266 * Init entry point 1267 * 1268 * This routine is used in two ways. It is used by the stack as 1269 * init entry point in network interface structure. It is also used 1270 * by the driver as a hw/sw initialization routine to get to a 1271 * consistent state. 1272 * 1273 **********************************************************************/ 1274 static void 1275 em_if_init(if_ctx_t ctx) 1276 { 1277 struct adapter *adapter = iflib_get_softc(ctx); 1278 if_softc_ctx_t scctx = adapter->shared; 1279 struct ifnet *ifp = iflib_get_ifp(ctx); 1280 struct em_tx_queue *tx_que; 1281 int i; 1282 1283 INIT_DEBUGOUT("em_if_init: begin"); 1284 1285 /* Get the latest mac address, User can use a LAA */ 1286 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1287 ETHER_ADDR_LEN); 1288 1289 /* Put the address into the Receive Address Array */ 1290 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1291 1292 /* 1293 * With the 82571 adapter, RAR[0] may be overwritten 1294 * when the other port is reset, we make a duplicate 1295 * in RAR[14] for that eventuality, this assures 1296 * the interface continues to function. 1297 */ 1298 if (adapter->hw.mac.type == e1000_82571) { 1299 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1300 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1301 E1000_RAR_ENTRIES - 1); 1302 } 1303 1304 1305 /* Initialize the hardware */ 1306 em_reset(ctx); 1307 em_if_update_admin_status(ctx); 1308 1309 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1310 struct tx_ring *txr = &tx_que->txr; 1311 1312 txr->tx_rs_cidx = txr->tx_rs_pidx; 1313 1314 /* Initialize the last processed descriptor to be the end of 1315 * the ring, rather than the start, so that we avoid an 1316 * off-by-one error when calculating how many descriptors are 1317 * done in the credits_update function. 1318 */ 1319 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1320 } 1321 1322 /* Setup VLAN support, basic and offload if available */ 1323 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1324 1325 /* Clear bad data from Rx FIFOs */ 1326 if (adapter->hw.mac.type >= igb_mac_min) 1327 e1000_rx_fifo_flush_82575(&adapter->hw); 1328 1329 /* Configure for OS presence */ 1330 em_init_manageability(adapter); 1331 1332 /* Prepare transmit descriptors and buffers */ 1333 em_initialize_transmit_unit(ctx); 1334 1335 /* Setup Multicast table */ 1336 em_if_multi_set(ctx); 1337 1338 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1339 em_initialize_receive_unit(ctx); 1340 1341 /* Use real VLAN Filter support? */ 1342 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1343 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1344 /* Use real VLAN Filter support */ 1345 em_setup_vlan_hw_support(adapter); 1346 else { 1347 u32 ctrl; 1348 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1349 ctrl |= E1000_CTRL_VME; 1350 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1351 } 1352 } else { 1353 u32 ctrl; 1354 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1355 ctrl &= ~E1000_CTRL_VME; 1356 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1357 } 1358 1359 /* Don't lose promiscuous settings */ 1360 em_if_set_promisc(ctx, if_getflags(ifp)); 1361 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1362 1363 /* MSI-X configuration for 82574 */ 1364 if (adapter->hw.mac.type == e1000_82574) { 1365 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1366 1367 tmp |= E1000_CTRL_EXT_PBA_CLR; 1368 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1369 /* Set the IVAR - interrupt vector routing. */ 1370 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1371 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1372 igb_configure_queues(adapter); 1373 1374 /* this clears any pending interrupts */ 1375 E1000_READ_REG(&adapter->hw, E1000_ICR); 1376 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1377 1378 /* AMT based hardware can now take control from firmware */ 1379 if (adapter->has_manage && adapter->has_amt) 1380 em_get_hw_control(adapter); 1381 1382 /* Set Energy Efficient Ethernet */ 1383 if (adapter->hw.mac.type >= igb_mac_min && 1384 adapter->hw.phy.media_type == e1000_media_type_copper) { 1385 if (adapter->hw.mac.type == e1000_i354) 1386 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1387 else 1388 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1389 } 1390 } 1391 1392 /********************************************************************* 1393 * 1394 * Fast Legacy/MSI Combined Interrupt Service routine 1395 * 1396 *********************************************************************/ 1397 int 1398 em_intr(void *arg) 1399 { 1400 struct adapter *adapter = arg; 1401 if_ctx_t ctx = adapter->ctx; 1402 u32 reg_icr; 1403 1404 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1405 1406 /* Hot eject? */ 1407 if (reg_icr == 0xffffffff) 1408 return FILTER_STRAY; 1409 1410 /* Definitely not our interrupt. */ 1411 if (reg_icr == 0x0) 1412 return FILTER_STRAY; 1413 1414 /* 1415 * Starting with the 82571 chip, bit 31 should be used to 1416 * determine whether the interrupt belongs to us. 1417 */ 1418 if (adapter->hw.mac.type >= e1000_82571 && 1419 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1420 return FILTER_STRAY; 1421 1422 /* 1423 * Only MSI-X interrupts have one-shot behavior by taking advantage 1424 * of the EIAC register. Thus, explicitly disable interrupts. This 1425 * also works around the MSI message reordering errata on certain 1426 * systems. 1427 */ 1428 IFDI_INTR_DISABLE(ctx); 1429 1430 /* Link status change */ 1431 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1432 em_handle_link(ctx); 1433 1434 if (reg_icr & E1000_ICR_RXO) 1435 adapter->rx_overruns++; 1436 1437 return (FILTER_SCHEDULE_THREAD); 1438 } 1439 1440 static int 1441 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1442 { 1443 struct adapter *adapter = iflib_get_softc(ctx); 1444 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1445 1446 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1447 return (0); 1448 } 1449 1450 static int 1451 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1452 { 1453 struct adapter *adapter = iflib_get_softc(ctx); 1454 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1455 1456 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1457 return (0); 1458 } 1459 1460 static int 1461 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1462 { 1463 struct adapter *adapter = iflib_get_softc(ctx); 1464 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1465 1466 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1467 return (0); 1468 } 1469 1470 static int 1471 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1472 { 1473 struct adapter *adapter = iflib_get_softc(ctx); 1474 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1475 1476 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1477 return (0); 1478 } 1479 1480 /********************************************************************* 1481 * 1482 * MSI-X RX Interrupt Service routine 1483 * 1484 **********************************************************************/ 1485 static int 1486 em_msix_que(void *arg) 1487 { 1488 struct em_rx_queue *que = arg; 1489 1490 ++que->irqs; 1491 1492 return (FILTER_SCHEDULE_THREAD); 1493 } 1494 1495 /********************************************************************* 1496 * 1497 * MSI-X Link Fast Interrupt Service routine 1498 * 1499 **********************************************************************/ 1500 static int 1501 em_msix_link(void *arg) 1502 { 1503 struct adapter *adapter = arg; 1504 u32 reg_icr; 1505 bool notlink = false; 1506 1507 ++adapter->link_irq; 1508 MPASS(adapter->hw.back != NULL); 1509 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1510 1511 if (reg_icr & E1000_ICR_RXO) 1512 adapter->rx_overruns++; 1513 1514 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1515 em_handle_link(adapter->ctx); 1516 else 1517 notlink = true; 1518 1519 /* Re-arm for other/spurious interrupts */ 1520 if (notlink && adapter->hw.mac.type >= igb_mac_min) { 1521 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1522 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1523 } else if (adapter->hw.mac.type == e1000_82574) { 1524 if (notlink) 1525 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC | 1526 E1000_IMS_OTHER); 1527 /* 1528 * Because we must read the ICR for this interrupt it may 1529 * clear other causes using autoclear, for this reason we 1530 * simply create a soft interrupt for all these vectors. 1531 */ 1532 if (reg_icr) 1533 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims); 1534 } 1535 1536 return (FILTER_HANDLED); 1537 } 1538 1539 static void 1540 em_handle_link(void *context) 1541 { 1542 if_ctx_t ctx = context; 1543 struct adapter *adapter = iflib_get_softc(ctx); 1544 1545 adapter->hw.mac.get_link_status = 1; 1546 iflib_admin_intr_deferred(ctx); 1547 } 1548 1549 /********************************************************************* 1550 * 1551 * Media Ioctl callback 1552 * 1553 * This routine is called whenever the user queries the status of 1554 * the interface using ifconfig. 1555 * 1556 **********************************************************************/ 1557 static void 1558 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1559 { 1560 struct adapter *adapter = iflib_get_softc(ctx); 1561 u_char fiber_type = IFM_1000_SX; 1562 1563 INIT_DEBUGOUT("em_if_media_status: begin"); 1564 1565 iflib_admin_intr_deferred(ctx); 1566 1567 ifmr->ifm_status = IFM_AVALID; 1568 ifmr->ifm_active = IFM_ETHER; 1569 1570 if (!adapter->link_active) { 1571 return; 1572 } 1573 1574 ifmr->ifm_status |= IFM_ACTIVE; 1575 1576 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1577 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1578 if (adapter->hw.mac.type == e1000_82545) 1579 fiber_type = IFM_1000_LX; 1580 ifmr->ifm_active |= fiber_type | IFM_FDX; 1581 } else { 1582 switch (adapter->link_speed) { 1583 case 10: 1584 ifmr->ifm_active |= IFM_10_T; 1585 break; 1586 case 100: 1587 ifmr->ifm_active |= IFM_100_TX; 1588 break; 1589 case 1000: 1590 ifmr->ifm_active |= IFM_1000_T; 1591 break; 1592 } 1593 if (adapter->link_duplex == FULL_DUPLEX) 1594 ifmr->ifm_active |= IFM_FDX; 1595 else 1596 ifmr->ifm_active |= IFM_HDX; 1597 } 1598 } 1599 1600 /********************************************************************* 1601 * 1602 * Media Ioctl callback 1603 * 1604 * This routine is called when the user changes speed/duplex using 1605 * media/mediopt option with ifconfig. 1606 * 1607 **********************************************************************/ 1608 static int 1609 em_if_media_change(if_ctx_t ctx) 1610 { 1611 struct adapter *adapter = iflib_get_softc(ctx); 1612 struct ifmedia *ifm = iflib_get_media(ctx); 1613 1614 INIT_DEBUGOUT("em_if_media_change: begin"); 1615 1616 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1617 return (EINVAL); 1618 1619 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1620 case IFM_AUTO: 1621 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1622 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1623 break; 1624 case IFM_1000_LX: 1625 case IFM_1000_SX: 1626 case IFM_1000_T: 1627 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1628 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1629 break; 1630 case IFM_100_TX: 1631 adapter->hw.mac.autoneg = FALSE; 1632 adapter->hw.phy.autoneg_advertised = 0; 1633 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1634 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1635 else 1636 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1637 break; 1638 case IFM_10_T: 1639 adapter->hw.mac.autoneg = FALSE; 1640 adapter->hw.phy.autoneg_advertised = 0; 1641 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1642 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1643 else 1644 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1645 break; 1646 default: 1647 device_printf(adapter->dev, "Unsupported media type\n"); 1648 } 1649 1650 em_if_init(ctx); 1651 1652 return (0); 1653 } 1654 1655 static int 1656 em_if_set_promisc(if_ctx_t ctx, int flags) 1657 { 1658 struct adapter *adapter = iflib_get_softc(ctx); 1659 struct ifnet *ifp = iflib_get_ifp(ctx); 1660 u32 reg_rctl; 1661 int mcnt = 0; 1662 1663 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1664 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1665 if (flags & IFF_ALLMULTI) 1666 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1667 else 1668 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1669 1670 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1671 reg_rctl &= (~E1000_RCTL_MPE); 1672 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1673 1674 if (flags & IFF_PROMISC) { 1675 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1676 /* Turn this on if you want to see bad packets */ 1677 if (em_debug_sbp) 1678 reg_rctl |= E1000_RCTL_SBP; 1679 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1680 } else if (flags & IFF_ALLMULTI) { 1681 reg_rctl |= E1000_RCTL_MPE; 1682 reg_rctl &= ~E1000_RCTL_UPE; 1683 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1684 } 1685 return (0); 1686 } 1687 1688 static u_int 1689 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1690 { 1691 u8 *mta = arg; 1692 1693 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1694 return (0); 1695 1696 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1697 1698 return (1); 1699 } 1700 1701 /********************************************************************* 1702 * Multicast Update 1703 * 1704 * This routine is called whenever multicast address list is updated. 1705 * 1706 **********************************************************************/ 1707 static void 1708 em_if_multi_set(if_ctx_t ctx) 1709 { 1710 struct adapter *adapter = iflib_get_softc(ctx); 1711 struct ifnet *ifp = iflib_get_ifp(ctx); 1712 u8 *mta; /* Multicast array memory */ 1713 u32 reg_rctl = 0; 1714 int mcnt = 0; 1715 1716 IOCTL_DEBUGOUT("em_set_multi: begin"); 1717 1718 mta = adapter->mta; 1719 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1720 1721 if (adapter->hw.mac.type == e1000_82542 && 1722 adapter->hw.revision_id == E1000_REVISION_2) { 1723 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1724 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1725 e1000_pci_clear_mwi(&adapter->hw); 1726 reg_rctl |= E1000_RCTL_RST; 1727 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1728 msec_delay(5); 1729 } 1730 1731 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1732 1733 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1734 1735 if (if_getflags(ifp) & IFF_PROMISC) 1736 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1737 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1738 if_getflags(ifp) & IFF_ALLMULTI) { 1739 reg_rctl |= E1000_RCTL_MPE; 1740 reg_rctl &= ~E1000_RCTL_UPE; 1741 } else 1742 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1743 1744 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1745 1746 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1747 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1748 1749 if (adapter->hw.mac.type == e1000_82542 && 1750 adapter->hw.revision_id == E1000_REVISION_2) { 1751 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1752 reg_rctl &= ~E1000_RCTL_RST; 1753 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1754 msec_delay(5); 1755 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1756 e1000_pci_set_mwi(&adapter->hw); 1757 } 1758 } 1759 1760 /********************************************************************* 1761 * Timer routine 1762 * 1763 * This routine schedules em_if_update_admin_status() to check for 1764 * link status and to gather statistics as well as to perform some 1765 * controller-specific hardware patting. 1766 * 1767 **********************************************************************/ 1768 static void 1769 em_if_timer(if_ctx_t ctx, uint16_t qid) 1770 { 1771 1772 if (qid != 0) 1773 return; 1774 1775 iflib_admin_intr_deferred(ctx); 1776 } 1777 1778 static void 1779 em_if_update_admin_status(if_ctx_t ctx) 1780 { 1781 struct adapter *adapter = iflib_get_softc(ctx); 1782 struct e1000_hw *hw = &adapter->hw; 1783 device_t dev = iflib_get_dev(ctx); 1784 u32 link_check, thstat, ctrl; 1785 1786 link_check = thstat = ctrl = 0; 1787 /* Get the cached link value or read phy for real */ 1788 switch (hw->phy.media_type) { 1789 case e1000_media_type_copper: 1790 if (hw->mac.get_link_status) { 1791 if (hw->mac.type == e1000_pch_spt) 1792 msec_delay(50); 1793 /* Do the work to read phy */ 1794 e1000_check_for_link(hw); 1795 link_check = !hw->mac.get_link_status; 1796 if (link_check) /* ESB2 fix */ 1797 e1000_cfg_on_link_up(hw); 1798 } else { 1799 link_check = TRUE; 1800 } 1801 break; 1802 case e1000_media_type_fiber: 1803 e1000_check_for_link(hw); 1804 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1805 E1000_STATUS_LU); 1806 break; 1807 case e1000_media_type_internal_serdes: 1808 e1000_check_for_link(hw); 1809 link_check = hw->mac.serdes_has_link; 1810 break; 1811 /* VF device is type_unknown */ 1812 case e1000_media_type_unknown: 1813 e1000_check_for_link(hw); 1814 link_check = !hw->mac.get_link_status; 1815 /* FALLTHROUGH */ 1816 default: 1817 break; 1818 } 1819 1820 /* Check for thermal downshift or shutdown */ 1821 if (hw->mac.type == e1000_i350) { 1822 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1823 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1824 } 1825 1826 /* Now check for a transition */ 1827 if (link_check && (adapter->link_active == 0)) { 1828 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1829 &adapter->link_duplex); 1830 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1831 if ((adapter->link_speed != SPEED_1000) && 1832 ((hw->mac.type == e1000_82571) || 1833 (hw->mac.type == e1000_82572))) { 1834 int tarc0; 1835 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1836 tarc0 &= ~TARC_SPEED_MODE_BIT; 1837 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1838 } 1839 if (bootverbose) 1840 device_printf(dev, "Link is up %d Mbps %s\n", 1841 adapter->link_speed, 1842 ((adapter->link_duplex == FULL_DUPLEX) ? 1843 "Full Duplex" : "Half Duplex")); 1844 adapter->link_active = 1; 1845 adapter->smartspeed = 0; 1846 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1847 E1000_CTRL_EXT_LINK_MODE_GMII && 1848 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1849 device_printf(dev, "Link: thermal downshift\n"); 1850 /* Delay Link Up for Phy update */ 1851 if (((hw->mac.type == e1000_i210) || 1852 (hw->mac.type == e1000_i211)) && 1853 (hw->phy.id == I210_I_PHY_ID)) 1854 msec_delay(I210_LINK_DELAY); 1855 /* Reset if the media type changed. */ 1856 if (hw->dev_spec._82575.media_changed && 1857 hw->mac.type >= igb_mac_min) { 1858 hw->dev_spec._82575.media_changed = false; 1859 adapter->flags |= IGB_MEDIA_RESET; 1860 em_reset(ctx); 1861 } 1862 iflib_link_state_change(ctx, LINK_STATE_UP, 1863 IF_Mbps(adapter->link_speed)); 1864 } else if (!link_check && (adapter->link_active == 1)) { 1865 adapter->link_speed = 0; 1866 adapter->link_duplex = 0; 1867 adapter->link_active = 0; 1868 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1869 } 1870 em_update_stats_counters(adapter); 1871 1872 /* Reset LAA into RAR[0] on 82571 */ 1873 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1874 e1000_rar_set(hw, hw->mac.addr, 0); 1875 1876 if (hw->mac.type < em_mac_min) 1877 lem_smartspeed(adapter); 1878 else if (hw->mac.type >= igb_mac_min && 1879 adapter->intr_type == IFLIB_INTR_MSIX) { 1880 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1881 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1882 } else if (hw->mac.type == e1000_82574 && 1883 adapter->intr_type == IFLIB_INTR_MSIX) 1884 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_OTHER); 1885 } 1886 1887 static void 1888 em_if_watchdog_reset(if_ctx_t ctx) 1889 { 1890 struct adapter *adapter = iflib_get_softc(ctx); 1891 1892 /* 1893 * Just count the event; iflib(4) will already trigger a 1894 * sufficient reset of the controller. 1895 */ 1896 adapter->watchdog_events++; 1897 } 1898 1899 /********************************************************************* 1900 * 1901 * This routine disables all traffic on the adapter by issuing a 1902 * global reset on the MAC. 1903 * 1904 **********************************************************************/ 1905 static void 1906 em_if_stop(if_ctx_t ctx) 1907 { 1908 struct adapter *adapter = iflib_get_softc(ctx); 1909 1910 INIT_DEBUGOUT("em_if_stop: begin"); 1911 1912 e1000_reset_hw(&adapter->hw); 1913 if (adapter->hw.mac.type >= e1000_82544) 1914 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1915 1916 e1000_led_off(&adapter->hw); 1917 e1000_cleanup_led(&adapter->hw); 1918 } 1919 1920 /********************************************************************* 1921 * 1922 * Determine hardware revision. 1923 * 1924 **********************************************************************/ 1925 static void 1926 em_identify_hardware(if_ctx_t ctx) 1927 { 1928 device_t dev = iflib_get_dev(ctx); 1929 struct adapter *adapter = iflib_get_softc(ctx); 1930 1931 /* Make sure our PCI config space has the necessary stuff set */ 1932 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1933 1934 /* Save off the information about this board */ 1935 adapter->hw.vendor_id = pci_get_vendor(dev); 1936 adapter->hw.device_id = pci_get_device(dev); 1937 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1938 adapter->hw.subsystem_vendor_id = 1939 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1940 adapter->hw.subsystem_device_id = 1941 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1942 1943 /* Do Shared Code Init and Setup */ 1944 if (e1000_set_mac_type(&adapter->hw)) { 1945 device_printf(dev, "Setup init failure\n"); 1946 return; 1947 } 1948 1949 /* Are we a VF device? */ 1950 if ((adapter->hw.mac.type == e1000_vfadapt) || 1951 (adapter->hw.mac.type == e1000_vfadapt_i350)) 1952 adapter->vf_ifp = 1; 1953 else 1954 adapter->vf_ifp = 0; 1955 } 1956 1957 static int 1958 em_allocate_pci_resources(if_ctx_t ctx) 1959 { 1960 struct adapter *adapter = iflib_get_softc(ctx); 1961 device_t dev = iflib_get_dev(ctx); 1962 int rid, val; 1963 1964 rid = PCIR_BAR(0); 1965 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1966 &rid, RF_ACTIVE); 1967 if (adapter->memory == NULL) { 1968 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1969 return (ENXIO); 1970 } 1971 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1972 adapter->osdep.mem_bus_space_handle = 1973 rman_get_bushandle(adapter->memory); 1974 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1975 1976 /* Only older adapters use IO mapping */ 1977 if (adapter->hw.mac.type < em_mac_min && 1978 adapter->hw.mac.type > e1000_82543) { 1979 /* Figure our where our IO BAR is ? */ 1980 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1981 val = pci_read_config(dev, rid, 4); 1982 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1983 break; 1984 } 1985 rid += 4; 1986 /* check for 64bit BAR */ 1987 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1988 rid += 4; 1989 } 1990 if (rid >= PCIR_CIS) { 1991 device_printf(dev, "Unable to locate IO BAR\n"); 1992 return (ENXIO); 1993 } 1994 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1995 &rid, RF_ACTIVE); 1996 if (adapter->ioport == NULL) { 1997 device_printf(dev, "Unable to allocate bus resource: " 1998 "ioport\n"); 1999 return (ENXIO); 2000 } 2001 adapter->hw.io_base = 0; 2002 adapter->osdep.io_bus_space_tag = 2003 rman_get_bustag(adapter->ioport); 2004 adapter->osdep.io_bus_space_handle = 2005 rman_get_bushandle(adapter->ioport); 2006 } 2007 2008 adapter->hw.back = &adapter->osdep; 2009 2010 return (0); 2011 } 2012 2013 /********************************************************************* 2014 * 2015 * Set up the MSI-X Interrupt handlers 2016 * 2017 **********************************************************************/ 2018 static int 2019 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2020 { 2021 struct adapter *adapter = iflib_get_softc(ctx); 2022 struct em_rx_queue *rx_que = adapter->rx_queues; 2023 struct em_tx_queue *tx_que = adapter->tx_queues; 2024 int error, rid, i, vector = 0, rx_vectors; 2025 char buf[16]; 2026 2027 /* First set up ring resources */ 2028 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 2029 rid = vector + 1; 2030 snprintf(buf, sizeof(buf), "rxq%d", i); 2031 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2032 if (error) { 2033 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2034 adapter->rx_num_queues = i + 1; 2035 goto fail; 2036 } 2037 2038 rx_que->msix = vector; 2039 2040 /* 2041 * Set the bit to enable interrupt 2042 * in E1000_IMS -- bits 20 and 21 2043 * are for RX0 and RX1, note this has 2044 * NOTHING to do with the MSI-X vector 2045 */ 2046 if (adapter->hw.mac.type == e1000_82574) { 2047 rx_que->eims = 1 << (20 + i); 2048 adapter->ims |= rx_que->eims; 2049 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 2050 } else if (adapter->hw.mac.type == e1000_82575) 2051 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2052 else 2053 rx_que->eims = 1 << vector; 2054 } 2055 rx_vectors = vector; 2056 2057 vector = 0; 2058 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 2059 snprintf(buf, sizeof(buf), "txq%d", i); 2060 tx_que = &adapter->tx_queues[i]; 2061 iflib_softirq_alloc_generic(ctx, 2062 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 2063 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2064 2065 tx_que->msix = (vector % adapter->rx_num_queues); 2066 2067 /* 2068 * Set the bit to enable interrupt 2069 * in E1000_IMS -- bits 22 and 23 2070 * are for TX0 and TX1, note this has 2071 * NOTHING to do with the MSI-X vector 2072 */ 2073 if (adapter->hw.mac.type == e1000_82574) { 2074 tx_que->eims = 1 << (22 + i); 2075 adapter->ims |= tx_que->eims; 2076 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2077 } else if (adapter->hw.mac.type == e1000_82575) { 2078 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2079 } else { 2080 tx_que->eims = 1 << i; 2081 } 2082 } 2083 2084 /* Link interrupt */ 2085 rid = rx_vectors + 1; 2086 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2087 2088 if (error) { 2089 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2090 goto fail; 2091 } 2092 adapter->linkvec = rx_vectors; 2093 if (adapter->hw.mac.type < igb_mac_min) { 2094 adapter->ivars |= (8 | rx_vectors) << 16; 2095 adapter->ivars |= 0x80000000; 2096 /* Enable the "Other" interrupt type for link status change */ 2097 adapter->ims |= E1000_IMS_OTHER; 2098 } 2099 2100 return (0); 2101 fail: 2102 iflib_irq_free(ctx, &adapter->irq); 2103 rx_que = adapter->rx_queues; 2104 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2105 iflib_irq_free(ctx, &rx_que->que_irq); 2106 return (error); 2107 } 2108 2109 static void 2110 igb_configure_queues(struct adapter *adapter) 2111 { 2112 struct e1000_hw *hw = &adapter->hw; 2113 struct em_rx_queue *rx_que; 2114 struct em_tx_queue *tx_que; 2115 u32 tmp, ivar = 0, newitr = 0; 2116 2117 /* First turn on RSS capability */ 2118 if (hw->mac.type != e1000_82575) 2119 E1000_WRITE_REG(hw, E1000_GPIE, 2120 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2121 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2122 2123 /* Turn on MSI-X */ 2124 switch (hw->mac.type) { 2125 case e1000_82580: 2126 case e1000_i350: 2127 case e1000_i354: 2128 case e1000_i210: 2129 case e1000_i211: 2130 case e1000_vfadapt: 2131 case e1000_vfadapt_i350: 2132 /* RX entries */ 2133 for (int i = 0; i < adapter->rx_num_queues; i++) { 2134 u32 index = i >> 1; 2135 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2136 rx_que = &adapter->rx_queues[i]; 2137 if (i & 1) { 2138 ivar &= 0xFF00FFFF; 2139 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2140 } else { 2141 ivar &= 0xFFFFFF00; 2142 ivar |= rx_que->msix | E1000_IVAR_VALID; 2143 } 2144 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2145 } 2146 /* TX entries */ 2147 for (int i = 0; i < adapter->tx_num_queues; i++) { 2148 u32 index = i >> 1; 2149 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2150 tx_que = &adapter->tx_queues[i]; 2151 if (i & 1) { 2152 ivar &= 0x00FFFFFF; 2153 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2154 } else { 2155 ivar &= 0xFFFF00FF; 2156 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2157 } 2158 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2159 adapter->que_mask |= tx_que->eims; 2160 } 2161 2162 /* And for the link interrupt */ 2163 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2164 adapter->link_mask = 1 << adapter->linkvec; 2165 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2166 break; 2167 case e1000_82576: 2168 /* RX entries */ 2169 for (int i = 0; i < adapter->rx_num_queues; i++) { 2170 u32 index = i & 0x7; /* Each IVAR has two entries */ 2171 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2172 rx_que = &adapter->rx_queues[i]; 2173 if (i < 8) { 2174 ivar &= 0xFFFFFF00; 2175 ivar |= rx_que->msix | E1000_IVAR_VALID; 2176 } else { 2177 ivar &= 0xFF00FFFF; 2178 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2179 } 2180 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2181 adapter->que_mask |= rx_que->eims; 2182 } 2183 /* TX entries */ 2184 for (int i = 0; i < adapter->tx_num_queues; i++) { 2185 u32 index = i & 0x7; /* Each IVAR has two entries */ 2186 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2187 tx_que = &adapter->tx_queues[i]; 2188 if (i < 8) { 2189 ivar &= 0xFFFF00FF; 2190 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2191 } else { 2192 ivar &= 0x00FFFFFF; 2193 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2194 } 2195 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2196 adapter->que_mask |= tx_que->eims; 2197 } 2198 2199 /* And for the link interrupt */ 2200 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2201 adapter->link_mask = 1 << adapter->linkvec; 2202 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2203 break; 2204 2205 case e1000_82575: 2206 /* enable MSI-X support*/ 2207 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2208 tmp |= E1000_CTRL_EXT_PBA_CLR; 2209 /* Auto-Mask interrupts upon ICR read. */ 2210 tmp |= E1000_CTRL_EXT_EIAME; 2211 tmp |= E1000_CTRL_EXT_IRCA; 2212 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2213 2214 /* Queues */ 2215 for (int i = 0; i < adapter->rx_num_queues; i++) { 2216 rx_que = &adapter->rx_queues[i]; 2217 tmp = E1000_EICR_RX_QUEUE0 << i; 2218 tmp |= E1000_EICR_TX_QUEUE0 << i; 2219 rx_que->eims = tmp; 2220 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2221 i, rx_que->eims); 2222 adapter->que_mask |= rx_que->eims; 2223 } 2224 2225 /* Link */ 2226 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2227 E1000_EIMS_OTHER); 2228 adapter->link_mask |= E1000_EIMS_OTHER; 2229 default: 2230 break; 2231 } 2232 2233 /* Set the starting interrupt rate */ 2234 if (em_max_interrupt_rate > 0) 2235 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2236 2237 if (hw->mac.type == e1000_82575) 2238 newitr |= newitr << 16; 2239 else 2240 newitr |= E1000_EITR_CNT_IGNR; 2241 2242 for (int i = 0; i < adapter->rx_num_queues; i++) { 2243 rx_que = &adapter->rx_queues[i]; 2244 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2245 } 2246 2247 return; 2248 } 2249 2250 static void 2251 em_free_pci_resources(if_ctx_t ctx) 2252 { 2253 struct adapter *adapter = iflib_get_softc(ctx); 2254 struct em_rx_queue *que = adapter->rx_queues; 2255 device_t dev = iflib_get_dev(ctx); 2256 2257 /* Release all MSI-X queue resources */ 2258 if (adapter->intr_type == IFLIB_INTR_MSIX) 2259 iflib_irq_free(ctx, &adapter->irq); 2260 2261 if (que != NULL) { 2262 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2263 iflib_irq_free(ctx, &que->que_irq); 2264 } 2265 } 2266 2267 if (adapter->memory != NULL) { 2268 bus_release_resource(dev, SYS_RES_MEMORY, 2269 rman_get_rid(adapter->memory), adapter->memory); 2270 adapter->memory = NULL; 2271 } 2272 2273 if (adapter->flash != NULL) { 2274 bus_release_resource(dev, SYS_RES_MEMORY, 2275 rman_get_rid(adapter->flash), adapter->flash); 2276 adapter->flash = NULL; 2277 } 2278 2279 if (adapter->ioport != NULL) { 2280 bus_release_resource(dev, SYS_RES_IOPORT, 2281 rman_get_rid(adapter->ioport), adapter->ioport); 2282 adapter->ioport = NULL; 2283 } 2284 } 2285 2286 /* Set up MSI or MSI-X */ 2287 static int 2288 em_setup_msix(if_ctx_t ctx) 2289 { 2290 struct adapter *adapter = iflib_get_softc(ctx); 2291 2292 if (adapter->hw.mac.type == e1000_82574) { 2293 em_enable_vectors_82574(ctx); 2294 } 2295 return (0); 2296 } 2297 2298 /********************************************************************* 2299 * 2300 * Workaround for SmartSpeed on 82541 and 82547 controllers 2301 * 2302 **********************************************************************/ 2303 static void 2304 lem_smartspeed(struct adapter *adapter) 2305 { 2306 u16 phy_tmp; 2307 2308 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2309 adapter->hw.mac.autoneg == 0 || 2310 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2311 return; 2312 2313 if (adapter->smartspeed == 0) { 2314 /* If Master/Slave config fault is asserted twice, 2315 * we assume back-to-back */ 2316 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2317 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2318 return; 2319 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2320 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2321 e1000_read_phy_reg(&adapter->hw, 2322 PHY_1000T_CTRL, &phy_tmp); 2323 if(phy_tmp & CR_1000T_MS_ENABLE) { 2324 phy_tmp &= ~CR_1000T_MS_ENABLE; 2325 e1000_write_phy_reg(&adapter->hw, 2326 PHY_1000T_CTRL, phy_tmp); 2327 adapter->smartspeed++; 2328 if(adapter->hw.mac.autoneg && 2329 !e1000_copper_link_autoneg(&adapter->hw) && 2330 !e1000_read_phy_reg(&adapter->hw, 2331 PHY_CONTROL, &phy_tmp)) { 2332 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2333 MII_CR_RESTART_AUTO_NEG); 2334 e1000_write_phy_reg(&adapter->hw, 2335 PHY_CONTROL, phy_tmp); 2336 } 2337 } 2338 } 2339 return; 2340 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2341 /* If still no link, perhaps using 2/3 pair cable */ 2342 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2343 phy_tmp |= CR_1000T_MS_ENABLE; 2344 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2345 if(adapter->hw.mac.autoneg && 2346 !e1000_copper_link_autoneg(&adapter->hw) && 2347 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2348 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2349 MII_CR_RESTART_AUTO_NEG); 2350 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2351 } 2352 } 2353 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2354 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2355 adapter->smartspeed = 0; 2356 } 2357 2358 /********************************************************************* 2359 * 2360 * Initialize the DMA Coalescing feature 2361 * 2362 **********************************************************************/ 2363 static void 2364 igb_init_dmac(struct adapter *adapter, u32 pba) 2365 { 2366 device_t dev = adapter->dev; 2367 struct e1000_hw *hw = &adapter->hw; 2368 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2369 u16 hwm; 2370 u16 max_frame_size; 2371 2372 if (hw->mac.type == e1000_i211) 2373 return; 2374 2375 max_frame_size = adapter->shared->isc_max_frame_size; 2376 if (hw->mac.type > e1000_82580) { 2377 2378 if (adapter->dmac == 0) { /* Disabling it */ 2379 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2380 return; 2381 } else 2382 device_printf(dev, "DMA Coalescing enabled\n"); 2383 2384 /* Set starting threshold */ 2385 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2386 2387 hwm = 64 * pba - max_frame_size / 16; 2388 if (hwm < 64 * (pba - 6)) 2389 hwm = 64 * (pba - 6); 2390 reg = E1000_READ_REG(hw, E1000_FCRTC); 2391 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2392 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2393 & E1000_FCRTC_RTH_COAL_MASK); 2394 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2395 2396 2397 dmac = pba - max_frame_size / 512; 2398 if (dmac < pba - 10) 2399 dmac = pba - 10; 2400 reg = E1000_READ_REG(hw, E1000_DMACR); 2401 reg &= ~E1000_DMACR_DMACTHR_MASK; 2402 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2403 & E1000_DMACR_DMACTHR_MASK); 2404 2405 /* transition to L0x or L1 if available..*/ 2406 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2407 2408 /* Check if status is 2.5Gb backplane connection 2409 * before configuration of watchdog timer, which is 2410 * in msec values in 12.8usec intervals 2411 * watchdog timer= msec values in 32usec intervals 2412 * for non 2.5Gb connection 2413 */ 2414 if (hw->mac.type == e1000_i354) { 2415 int status = E1000_READ_REG(hw, E1000_STATUS); 2416 if ((status & E1000_STATUS_2P5_SKU) && 2417 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2418 reg |= ((adapter->dmac * 5) >> 6); 2419 else 2420 reg |= (adapter->dmac >> 5); 2421 } else { 2422 reg |= (adapter->dmac >> 5); 2423 } 2424 2425 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2426 2427 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2428 2429 /* Set the interval before transition */ 2430 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2431 if (hw->mac.type == e1000_i350) 2432 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2433 /* 2434 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2435 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2436 */ 2437 if (hw->mac.type == e1000_i354) { 2438 int status = E1000_READ_REG(hw, E1000_STATUS); 2439 if ((status & E1000_STATUS_2P5_SKU) && 2440 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2441 reg |= 0xA; 2442 else 2443 reg |= 0x4; 2444 } else { 2445 reg |= 0x4; 2446 } 2447 2448 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2449 2450 /* free space in tx packet buffer to wake from DMA coal */ 2451 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2452 (2 * max_frame_size)) >> 6); 2453 2454 /* make low power state decision controlled by DMA coal */ 2455 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2456 reg &= ~E1000_PCIEMISC_LX_DECISION; 2457 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2458 2459 } else if (hw->mac.type == e1000_82580) { 2460 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2461 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2462 reg & ~E1000_PCIEMISC_LX_DECISION); 2463 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2464 } 2465 } 2466 2467 /********************************************************************* 2468 * 2469 * Initialize the hardware to a configuration as specified by the 2470 * adapter structure. 2471 * 2472 **********************************************************************/ 2473 static void 2474 em_reset(if_ctx_t ctx) 2475 { 2476 device_t dev = iflib_get_dev(ctx); 2477 struct adapter *adapter = iflib_get_softc(ctx); 2478 struct ifnet *ifp = iflib_get_ifp(ctx); 2479 struct e1000_hw *hw = &adapter->hw; 2480 u16 rx_buffer_size; 2481 u32 pba; 2482 2483 INIT_DEBUGOUT("em_reset: begin"); 2484 /* Let the firmware know the OS is in control */ 2485 em_get_hw_control(adapter); 2486 2487 /* Set up smart power down as default off on newer adapters. */ 2488 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2489 hw->mac.type == e1000_82572)) { 2490 u16 phy_tmp = 0; 2491 2492 /* Speed up time to link by disabling smart power down. */ 2493 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2494 phy_tmp &= ~IGP02E1000_PM_SPD; 2495 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2496 } 2497 2498 /* 2499 * Packet Buffer Allocation (PBA) 2500 * Writing PBA sets the receive portion of the buffer 2501 * the remainder is used for the transmit buffer. 2502 */ 2503 switch (hw->mac.type) { 2504 /* 82547: Total Packet Buffer is 40K */ 2505 case e1000_82547: 2506 case e1000_82547_rev_2: 2507 if (hw->mac.max_frame_size > 8192) 2508 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2509 else 2510 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2511 break; 2512 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2513 case e1000_82571: 2514 case e1000_82572: 2515 case e1000_80003es2lan: 2516 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2517 break; 2518 /* 82573: Total Packet Buffer is 32K */ 2519 case e1000_82573: 2520 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2521 break; 2522 case e1000_82574: 2523 case e1000_82583: 2524 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2525 break; 2526 case e1000_ich8lan: 2527 pba = E1000_PBA_8K; 2528 break; 2529 case e1000_ich9lan: 2530 case e1000_ich10lan: 2531 /* Boost Receive side for jumbo frames */ 2532 if (hw->mac.max_frame_size > 4096) 2533 pba = E1000_PBA_14K; 2534 else 2535 pba = E1000_PBA_10K; 2536 break; 2537 case e1000_pchlan: 2538 case e1000_pch2lan: 2539 case e1000_pch_lpt: 2540 case e1000_pch_spt: 2541 case e1000_pch_cnp: 2542 case e1000_pch_tgp: 2543 case e1000_pch_adp: 2544 case e1000_pch_mtp: 2545 pba = E1000_PBA_26K; 2546 break; 2547 case e1000_82575: 2548 pba = E1000_PBA_32K; 2549 break; 2550 case e1000_82576: 2551 case e1000_vfadapt: 2552 pba = E1000_READ_REG(hw, E1000_RXPBS); 2553 pba &= E1000_RXPBS_SIZE_MASK_82576; 2554 break; 2555 case e1000_82580: 2556 case e1000_i350: 2557 case e1000_i354: 2558 case e1000_vfadapt_i350: 2559 pba = E1000_READ_REG(hw, E1000_RXPBS); 2560 pba = e1000_rxpbs_adjust_82580(pba); 2561 break; 2562 case e1000_i210: 2563 case e1000_i211: 2564 pba = E1000_PBA_34K; 2565 break; 2566 default: 2567 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2568 if (hw->mac.max_frame_size > 8192) 2569 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2570 else 2571 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2572 } 2573 2574 /* Special needs in case of Jumbo frames */ 2575 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2576 u32 tx_space, min_tx, min_rx; 2577 pba = E1000_READ_REG(hw, E1000_PBA); 2578 tx_space = pba >> 16; 2579 pba &= 0xffff; 2580 min_tx = (hw->mac.max_frame_size + 2581 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2582 min_tx = roundup2(min_tx, 1024); 2583 min_tx >>= 10; 2584 min_rx = hw->mac.max_frame_size; 2585 min_rx = roundup2(min_rx, 1024); 2586 min_rx >>= 10; 2587 if (tx_space < min_tx && 2588 ((min_tx - tx_space) < pba)) { 2589 pba = pba - (min_tx - tx_space); 2590 /* 2591 * if short on rx space, rx wins 2592 * and must trump tx adjustment 2593 */ 2594 if (pba < min_rx) 2595 pba = min_rx; 2596 } 2597 E1000_WRITE_REG(hw, E1000_PBA, pba); 2598 } 2599 2600 if (hw->mac.type < igb_mac_min) 2601 E1000_WRITE_REG(hw, E1000_PBA, pba); 2602 2603 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2604 2605 /* 2606 * These parameters control the automatic generation (Tx) and 2607 * response (Rx) to Ethernet PAUSE frames. 2608 * - High water mark should allow for at least two frames to be 2609 * received after sending an XOFF. 2610 * - Low water mark works best when it is very near the high water mark. 2611 * This allows the receiver to restart by sending XON when it has 2612 * drained a bit. Here we use an arbitrary value of 1500 which will 2613 * restart after one full frame is pulled from the buffer. There 2614 * could be several smaller frames in the buffer and if so they will 2615 * not trigger the XON until their total number reduces the buffer 2616 * by 1500. 2617 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2618 */ 2619 rx_buffer_size = (pba & 0xffff) << 10; 2620 hw->fc.high_water = rx_buffer_size - 2621 roundup2(hw->mac.max_frame_size, 1024); 2622 hw->fc.low_water = hw->fc.high_water - 1500; 2623 2624 if (adapter->fc) /* locally set flow control value? */ 2625 hw->fc.requested_mode = adapter->fc; 2626 else 2627 hw->fc.requested_mode = e1000_fc_full; 2628 2629 if (hw->mac.type == e1000_80003es2lan) 2630 hw->fc.pause_time = 0xFFFF; 2631 else 2632 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2633 2634 hw->fc.send_xon = TRUE; 2635 2636 /* Device specific overrides/settings */ 2637 switch (hw->mac.type) { 2638 case e1000_pchlan: 2639 /* Workaround: no TX flow ctrl for PCH */ 2640 hw->fc.requested_mode = e1000_fc_rx_pause; 2641 hw->fc.pause_time = 0xFFFF; /* override */ 2642 if (if_getmtu(ifp) > ETHERMTU) { 2643 hw->fc.high_water = 0x3500; 2644 hw->fc.low_water = 0x1500; 2645 } else { 2646 hw->fc.high_water = 0x5000; 2647 hw->fc.low_water = 0x3000; 2648 } 2649 hw->fc.refresh_time = 0x1000; 2650 break; 2651 case e1000_pch2lan: 2652 case e1000_pch_lpt: 2653 case e1000_pch_spt: 2654 case e1000_pch_cnp: 2655 case e1000_pch_tgp: 2656 case e1000_pch_adp: 2657 case e1000_pch_mtp: 2658 hw->fc.high_water = 0x5C20; 2659 hw->fc.low_water = 0x5048; 2660 hw->fc.pause_time = 0x0650; 2661 hw->fc.refresh_time = 0x0400; 2662 /* Jumbos need adjusted PBA */ 2663 if (if_getmtu(ifp) > ETHERMTU) 2664 E1000_WRITE_REG(hw, E1000_PBA, 12); 2665 else 2666 E1000_WRITE_REG(hw, E1000_PBA, 26); 2667 break; 2668 case e1000_82575: 2669 case e1000_82576: 2670 /* 8-byte granularity */ 2671 hw->fc.low_water = hw->fc.high_water - 8; 2672 break; 2673 case e1000_82580: 2674 case e1000_i350: 2675 case e1000_i354: 2676 case e1000_i210: 2677 case e1000_i211: 2678 case e1000_vfadapt: 2679 case e1000_vfadapt_i350: 2680 /* 16-byte granularity */ 2681 hw->fc.low_water = hw->fc.high_water - 16; 2682 break; 2683 case e1000_ich9lan: 2684 case e1000_ich10lan: 2685 if (if_getmtu(ifp) > ETHERMTU) { 2686 hw->fc.high_water = 0x2800; 2687 hw->fc.low_water = hw->fc.high_water - 8; 2688 break; 2689 } 2690 /* FALLTHROUGH */ 2691 default: 2692 if (hw->mac.type == e1000_80003es2lan) 2693 hw->fc.pause_time = 0xFFFF; 2694 break; 2695 } 2696 2697 /* Issue a global reset */ 2698 e1000_reset_hw(hw); 2699 if (hw->mac.type >= igb_mac_min) { 2700 E1000_WRITE_REG(hw, E1000_WUC, 0); 2701 } else { 2702 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2703 em_disable_aspm(adapter); 2704 } 2705 if (adapter->flags & IGB_MEDIA_RESET) { 2706 e1000_setup_init_funcs(hw, TRUE); 2707 e1000_get_bus_info(hw); 2708 adapter->flags &= ~IGB_MEDIA_RESET; 2709 } 2710 /* and a re-init */ 2711 if (e1000_init_hw(hw) < 0) { 2712 device_printf(dev, "Hardware Initialization Failed\n"); 2713 return; 2714 } 2715 if (hw->mac.type >= igb_mac_min) 2716 igb_init_dmac(adapter, pba); 2717 2718 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2719 e1000_get_phy_info(hw); 2720 e1000_check_for_link(hw); 2721 } 2722 2723 /* 2724 * Initialise the RSS mapping for NICs that support multiple transmit/ 2725 * receive rings. 2726 */ 2727 2728 #define RSSKEYLEN 10 2729 static void 2730 em_initialize_rss_mapping(struct adapter *adapter) 2731 { 2732 uint8_t rss_key[4 * RSSKEYLEN]; 2733 uint32_t reta = 0; 2734 struct e1000_hw *hw = &adapter->hw; 2735 int i; 2736 2737 /* 2738 * Configure RSS key 2739 */ 2740 arc4rand(rss_key, sizeof(rss_key), 0); 2741 for (i = 0; i < RSSKEYLEN; ++i) { 2742 uint32_t rssrk = 0; 2743 2744 rssrk = EM_RSSRK_VAL(rss_key, i); 2745 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2746 } 2747 2748 /* 2749 * Configure RSS redirect table in following fashion: 2750 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2751 */ 2752 for (i = 0; i < sizeof(reta); ++i) { 2753 uint32_t q; 2754 2755 q = (i % adapter->rx_num_queues) << 7; 2756 reta |= q << (8 * i); 2757 } 2758 2759 for (i = 0; i < 32; ++i) 2760 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2761 2762 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2763 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2764 E1000_MRQC_RSS_FIELD_IPV4 | 2765 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2766 E1000_MRQC_RSS_FIELD_IPV6_EX | 2767 E1000_MRQC_RSS_FIELD_IPV6); 2768 } 2769 2770 static void 2771 igb_initialize_rss_mapping(struct adapter *adapter) 2772 { 2773 struct e1000_hw *hw = &adapter->hw; 2774 int i; 2775 int queue_id; 2776 u32 reta; 2777 u32 rss_key[10], mrqc, shift = 0; 2778 2779 /* XXX? */ 2780 if (hw->mac.type == e1000_82575) 2781 shift = 6; 2782 2783 /* 2784 * The redirection table controls which destination 2785 * queue each bucket redirects traffic to. 2786 * Each DWORD represents four queues, with the LSB 2787 * being the first queue in the DWORD. 2788 * 2789 * This just allocates buckets to queues using round-robin 2790 * allocation. 2791 * 2792 * NOTE: It Just Happens to line up with the default 2793 * RSS allocation method. 2794 */ 2795 2796 /* Warning FM follows */ 2797 reta = 0; 2798 for (i = 0; i < 128; i++) { 2799 #ifdef RSS 2800 queue_id = rss_get_indirection_to_bucket(i); 2801 /* 2802 * If we have more queues than buckets, we'll 2803 * end up mapping buckets to a subset of the 2804 * queues. 2805 * 2806 * If we have more buckets than queues, we'll 2807 * end up instead assigning multiple buckets 2808 * to queues. 2809 * 2810 * Both are suboptimal, but we need to handle 2811 * the case so we don't go out of bounds 2812 * indexing arrays and such. 2813 */ 2814 queue_id = queue_id % adapter->rx_num_queues; 2815 #else 2816 queue_id = (i % adapter->rx_num_queues); 2817 #endif 2818 /* Adjust if required */ 2819 queue_id = queue_id << shift; 2820 2821 /* 2822 * The low 8 bits are for hash value (n+0); 2823 * The next 8 bits are for hash value (n+1), etc. 2824 */ 2825 reta = reta >> 8; 2826 reta = reta | ( ((uint32_t) queue_id) << 24); 2827 if ((i & 3) == 3) { 2828 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2829 reta = 0; 2830 } 2831 } 2832 2833 /* Now fill in hash table */ 2834 2835 /* 2836 * MRQC: Multiple Receive Queues Command 2837 * Set queuing to RSS control, number depends on the device. 2838 */ 2839 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2840 2841 #ifdef RSS 2842 /* XXX ew typecasting */ 2843 rss_getkey((uint8_t *) &rss_key); 2844 #else 2845 arc4rand(&rss_key, sizeof(rss_key), 0); 2846 #endif 2847 for (i = 0; i < 10; i++) 2848 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2849 2850 /* 2851 * Configure the RSS fields to hash upon. 2852 */ 2853 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2854 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2855 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2856 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2857 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2858 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2859 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2860 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2861 2862 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2863 } 2864 2865 /********************************************************************* 2866 * 2867 * Setup networking device structure and register interface media. 2868 * 2869 **********************************************************************/ 2870 static int 2871 em_setup_interface(if_ctx_t ctx) 2872 { 2873 struct ifnet *ifp = iflib_get_ifp(ctx); 2874 struct adapter *adapter = iflib_get_softc(ctx); 2875 if_softc_ctx_t scctx = adapter->shared; 2876 2877 INIT_DEBUGOUT("em_setup_interface: begin"); 2878 2879 /* Single Queue */ 2880 if (adapter->tx_num_queues == 1) { 2881 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2882 if_setsendqready(ifp); 2883 } 2884 2885 /* 2886 * Specify the media types supported by this adapter and register 2887 * callbacks to update media and link information 2888 */ 2889 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2890 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2891 u_char fiber_type = IFM_1000_SX; /* default type */ 2892 2893 if (adapter->hw.mac.type == e1000_82545) 2894 fiber_type = IFM_1000_LX; 2895 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2896 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2897 } else { 2898 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2899 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2900 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2901 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2902 if (adapter->hw.phy.type != e1000_phy_ife) { 2903 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2904 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2905 } 2906 } 2907 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2908 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2909 return (0); 2910 } 2911 2912 static int 2913 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2914 { 2915 struct adapter *adapter = iflib_get_softc(ctx); 2916 if_softc_ctx_t scctx = adapter->shared; 2917 int error = E1000_SUCCESS; 2918 struct em_tx_queue *que; 2919 int i, j; 2920 2921 MPASS(adapter->tx_num_queues > 0); 2922 MPASS(adapter->tx_num_queues == ntxqsets); 2923 2924 /* First allocate the top level queue structs */ 2925 if (!(adapter->tx_queues = 2926 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2927 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2928 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2929 return(ENOMEM); 2930 } 2931 2932 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2933 /* Set up some basics */ 2934 2935 struct tx_ring *txr = &que->txr; 2936 txr->adapter = que->adapter = adapter; 2937 que->me = txr->me = i; 2938 2939 /* Allocate report status array */ 2940 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2941 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2942 error = ENOMEM; 2943 goto fail; 2944 } 2945 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2946 txr->tx_rsq[j] = QIDX_INVALID; 2947 /* get the virtual and physical address of the hardware queues */ 2948 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2949 txr->tx_paddr = paddrs[i*ntxqs]; 2950 } 2951 2952 if (bootverbose) 2953 device_printf(iflib_get_dev(ctx), 2954 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2955 return (0); 2956 fail: 2957 em_if_queues_free(ctx); 2958 return (error); 2959 } 2960 2961 static int 2962 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2963 { 2964 struct adapter *adapter = iflib_get_softc(ctx); 2965 int error = E1000_SUCCESS; 2966 struct em_rx_queue *que; 2967 int i; 2968 2969 MPASS(adapter->rx_num_queues > 0); 2970 MPASS(adapter->rx_num_queues == nrxqsets); 2971 2972 /* First allocate the top level queue structs */ 2973 if (!(adapter->rx_queues = 2974 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2975 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2976 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2977 error = ENOMEM; 2978 goto fail; 2979 } 2980 2981 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2982 /* Set up some basics */ 2983 struct rx_ring *rxr = &que->rxr; 2984 rxr->adapter = que->adapter = adapter; 2985 rxr->que = que; 2986 que->me = rxr->me = i; 2987 2988 /* get the virtual and physical address of the hardware queues */ 2989 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2990 rxr->rx_paddr = paddrs[i*nrxqs]; 2991 } 2992 2993 if (bootverbose) 2994 device_printf(iflib_get_dev(ctx), 2995 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2996 2997 return (0); 2998 fail: 2999 em_if_queues_free(ctx); 3000 return (error); 3001 } 3002 3003 static void 3004 em_if_queues_free(if_ctx_t ctx) 3005 { 3006 struct adapter *adapter = iflib_get_softc(ctx); 3007 struct em_tx_queue *tx_que = adapter->tx_queues; 3008 struct em_rx_queue *rx_que = adapter->rx_queues; 3009 3010 if (tx_que != NULL) { 3011 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 3012 struct tx_ring *txr = &tx_que->txr; 3013 if (txr->tx_rsq == NULL) 3014 break; 3015 3016 free(txr->tx_rsq, M_DEVBUF); 3017 txr->tx_rsq = NULL; 3018 } 3019 free(adapter->tx_queues, M_DEVBUF); 3020 adapter->tx_queues = NULL; 3021 } 3022 3023 if (rx_que != NULL) { 3024 free(adapter->rx_queues, M_DEVBUF); 3025 adapter->rx_queues = NULL; 3026 } 3027 } 3028 3029 /********************************************************************* 3030 * 3031 * Enable transmit unit. 3032 * 3033 **********************************************************************/ 3034 static void 3035 em_initialize_transmit_unit(if_ctx_t ctx) 3036 { 3037 struct adapter *adapter = iflib_get_softc(ctx); 3038 if_softc_ctx_t scctx = adapter->shared; 3039 struct em_tx_queue *que; 3040 struct tx_ring *txr; 3041 struct e1000_hw *hw = &adapter->hw; 3042 u32 tctl, txdctl = 0, tarc, tipg = 0; 3043 3044 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3045 3046 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 3047 u64 bus_addr; 3048 caddr_t offp, endp; 3049 3050 que = &adapter->tx_queues[i]; 3051 txr = &que->txr; 3052 bus_addr = txr->tx_paddr; 3053 3054 /* Clear checksum offload context. */ 3055 offp = (caddr_t)&txr->csum_flags; 3056 endp = (caddr_t)(txr + 1); 3057 bzero(offp, endp - offp); 3058 3059 /* Base and Len of TX Ring */ 3060 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3061 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3062 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3063 (u32)(bus_addr >> 32)); 3064 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3065 (u32)bus_addr); 3066 /* Init the HEAD/TAIL indices */ 3067 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3068 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3069 3070 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3071 E1000_READ_REG(hw, E1000_TDBAL(i)), 3072 E1000_READ_REG(hw, E1000_TDLEN(i))); 3073 3074 txdctl = 0; /* clear txdctl */ 3075 txdctl |= 0x1f; /* PTHRESH */ 3076 txdctl |= 1 << 8; /* HTHRESH */ 3077 txdctl |= 1 << 16;/* WTHRESH */ 3078 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3079 txdctl |= E1000_TXDCTL_GRAN; 3080 txdctl |= 1 << 25; /* LWTHRESH */ 3081 3082 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3083 } 3084 3085 /* Set the default values for the Tx Inter Packet Gap timer */ 3086 switch (hw->mac.type) { 3087 case e1000_80003es2lan: 3088 tipg = DEFAULT_82543_TIPG_IPGR1; 3089 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3090 E1000_TIPG_IPGR2_SHIFT; 3091 break; 3092 case e1000_82542: 3093 tipg = DEFAULT_82542_TIPG_IPGT; 3094 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3095 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3096 break; 3097 default: 3098 if (hw->phy.media_type == e1000_media_type_fiber || 3099 hw->phy.media_type == e1000_media_type_internal_serdes) 3100 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3101 else 3102 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3103 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3104 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3105 } 3106 3107 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3108 E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value); 3109 3110 if(hw->mac.type >= e1000_82540) 3111 E1000_WRITE_REG(hw, E1000_TADV, 3112 adapter->tx_abs_int_delay.value); 3113 3114 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3115 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3116 tarc |= TARC_SPEED_MODE_BIT; 3117 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3118 } else if (hw->mac.type == e1000_80003es2lan) { 3119 /* errata: program both queues to unweighted RR */ 3120 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3121 tarc |= 1; 3122 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3123 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3124 tarc |= 1; 3125 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3126 } else if (hw->mac.type == e1000_82574) { 3127 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3128 tarc |= TARC_ERRATA_BIT; 3129 if ( adapter->tx_num_queues > 1) { 3130 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3131 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3132 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3133 } else 3134 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3135 } 3136 3137 if (adapter->tx_int_delay.value > 0) 3138 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3139 3140 /* Program the Transmit Control Register */ 3141 tctl = E1000_READ_REG(hw, E1000_TCTL); 3142 tctl &= ~E1000_TCTL_CT; 3143 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3144 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3145 3146 if (hw->mac.type >= e1000_82571) 3147 tctl |= E1000_TCTL_MULR; 3148 3149 /* This write will effectively turn on the transmit unit. */ 3150 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3151 3152 /* SPT and KBL errata workarounds */ 3153 if (hw->mac.type == e1000_pch_spt) { 3154 u32 reg; 3155 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3156 reg |= E1000_RCTL_RDMTS_HEX; 3157 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3158 /* i218-i219 Specification Update 1.5.4.5 */ 3159 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3160 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3161 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3162 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3163 } 3164 } 3165 3166 /********************************************************************* 3167 * 3168 * Enable receive unit. 3169 * 3170 **********************************************************************/ 3171 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3172 3173 static void 3174 em_initialize_receive_unit(if_ctx_t ctx) 3175 { 3176 struct adapter *adapter = iflib_get_softc(ctx); 3177 if_softc_ctx_t scctx = adapter->shared; 3178 struct ifnet *ifp = iflib_get_ifp(ctx); 3179 struct e1000_hw *hw = &adapter->hw; 3180 struct em_rx_queue *que; 3181 int i; 3182 uint32_t rctl, rxcsum; 3183 3184 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3185 3186 /* 3187 * Make sure receives are disabled while setting 3188 * up the descriptor ring 3189 */ 3190 rctl = E1000_READ_REG(hw, E1000_RCTL); 3191 /* Do not disable if ever enabled on this hardware */ 3192 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3193 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3194 3195 /* Setup the Receive Control Register */ 3196 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3197 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3198 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3199 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3200 3201 /* Do not store bad packets */ 3202 rctl &= ~E1000_RCTL_SBP; 3203 3204 /* Enable Long Packet receive */ 3205 if (if_getmtu(ifp) > ETHERMTU) 3206 rctl |= E1000_RCTL_LPE; 3207 else 3208 rctl &= ~E1000_RCTL_LPE; 3209 3210 /* Strip the CRC */ 3211 if (!em_disable_crc_stripping) 3212 rctl |= E1000_RCTL_SECRC; 3213 3214 if (hw->mac.type >= e1000_82540) { 3215 E1000_WRITE_REG(hw, E1000_RADV, 3216 adapter->rx_abs_int_delay.value); 3217 3218 /* 3219 * Set the interrupt throttling rate. Value is calculated 3220 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3221 */ 3222 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3223 } 3224 E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value); 3225 3226 if (hw->mac.type >= em_mac_min) { 3227 uint32_t rfctl; 3228 /* Use extended rx descriptor formats */ 3229 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3230 rfctl |= E1000_RFCTL_EXTEN; 3231 3232 /* 3233 * When using MSI-X interrupts we need to throttle 3234 * using the EITR register (82574 only) 3235 */ 3236 if (hw->mac.type == e1000_82574) { 3237 for (int i = 0; i < 4; i++) 3238 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3239 DEFAULT_ITR); 3240 /* Disable accelerated acknowledge */ 3241 rfctl |= E1000_RFCTL_ACK_DIS; 3242 } 3243 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3244 } 3245 3246 /* Set up L3 and L4 csum Rx descriptor offloads */ 3247 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3248 if (scctx->isc_capenable & IFCAP_RXCSUM) { 3249 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3250 if (hw->mac.type > e1000_82575) 3251 rxcsum |= E1000_RXCSUM_CRCOFL; 3252 else if (hw->mac.type < em_mac_min && 3253 scctx->isc_capenable & IFCAP_HWCSUM_IPV6) 3254 rxcsum |= E1000_RXCSUM_IPV6OFL; 3255 } else { 3256 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3257 if (hw->mac.type > e1000_82575) 3258 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3259 else if (hw->mac.type < em_mac_min) 3260 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3261 } 3262 3263 if (adapter->rx_num_queues > 1) { 3264 /* RSS hash needed in the Rx descriptor */ 3265 rxcsum |= E1000_RXCSUM_PCSD; 3266 3267 if (hw->mac.type >= igb_mac_min) 3268 igb_initialize_rss_mapping(adapter); 3269 else 3270 em_initialize_rss_mapping(adapter); 3271 } 3272 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3273 3274 /* 3275 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3276 * long latencies are observed, like Lenovo X60. This 3277 * change eliminates the problem, but since having positive 3278 * values in RDTR is a known source of problems on other 3279 * platforms another solution is being sought. 3280 */ 3281 if (hw->mac.type == e1000_82573) 3282 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3283 3284 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3285 struct rx_ring *rxr = &que->rxr; 3286 /* Setup the Base and Length of the Rx Descriptor Ring */ 3287 u64 bus_addr = rxr->rx_paddr; 3288 #if 0 3289 u32 rdt = adapter->rx_num_queues -1; /* default */ 3290 #endif 3291 3292 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3293 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3294 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3295 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3296 /* Setup the Head and Tail Descriptor Pointers */ 3297 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3298 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3299 } 3300 3301 /* 3302 * Set PTHRESH for improved jumbo performance 3303 * According to 10.2.5.11 of Intel 82574 Datasheet, 3304 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3305 * Only write to RXDCTL(1) if there is a need for different 3306 * settings. 3307 */ 3308 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3309 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3310 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3311 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3312 } else if (hw->mac.type == e1000_82574) { 3313 for (int i = 0; i < adapter->rx_num_queues; i++) { 3314 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3315 rxdctl |= 0x20; /* PTHRESH */ 3316 rxdctl |= 4 << 8; /* HTHRESH */ 3317 rxdctl |= 4 << 16;/* WTHRESH */ 3318 rxdctl |= 1 << 24; /* Switch to granularity */ 3319 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3320 } 3321 } else if (hw->mac.type >= igb_mac_min) { 3322 u32 psize, srrctl = 0; 3323 3324 if (if_getmtu(ifp) > ETHERMTU) { 3325 psize = scctx->isc_max_frame_size; 3326 /* are we on a vlan? */ 3327 if (ifp->if_vlantrunk != NULL) 3328 psize += VLAN_TAG_SIZE; 3329 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3330 } 3331 3332 /* Set maximum packet buffer len */ 3333 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3334 E1000_SRRCTL_BSIZEPKT_SHIFT; 3335 3336 /* 3337 * If TX flow control is disabled and there's >1 queue defined, 3338 * enable DROP. 3339 * 3340 * This drops frames rather than hanging the RX MAC for all queues. 3341 */ 3342 if ((adapter->rx_num_queues > 1) && 3343 (adapter->fc == e1000_fc_none || 3344 adapter->fc == e1000_fc_rx_pause)) { 3345 srrctl |= E1000_SRRCTL_DROP_EN; 3346 } 3347 /* Setup the Base and Length of the Rx Descriptor Rings */ 3348 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3349 struct rx_ring *rxr = &que->rxr; 3350 u64 bus_addr = rxr->rx_paddr; 3351 u32 rxdctl; 3352 3353 #ifdef notyet 3354 /* Configure for header split? -- ignore for now */ 3355 rxr->hdr_split = igb_header_split; 3356 #else 3357 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3358 #endif 3359 3360 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3361 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3362 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3363 (uint32_t)(bus_addr >> 32)); 3364 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3365 (uint32_t)bus_addr); 3366 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3367 /* Enable this Queue */ 3368 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3369 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3370 rxdctl &= 0xFFF00000; 3371 rxdctl |= IGB_RX_PTHRESH; 3372 rxdctl |= IGB_RX_HTHRESH << 8; 3373 rxdctl |= IGB_RX_WTHRESH << 16; 3374 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3375 } 3376 } else if (hw->mac.type >= e1000_pch2lan) { 3377 if (if_getmtu(ifp) > ETHERMTU) 3378 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3379 else 3380 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3381 } 3382 3383 /* Make sure VLAN Filters are off */ 3384 rctl &= ~E1000_RCTL_VFE; 3385 3386 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3387 if (hw->mac.type < igb_mac_min) { 3388 if (adapter->rx_mbuf_sz > 2048 && adapter->rx_mbuf_sz <= 4096) 3389 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3390 else if (adapter->rx_mbuf_sz > 4096 && adapter->rx_mbuf_sz <= 8192) 3391 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3392 else if (adapter->rx_mbuf_sz > 8192) 3393 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3394 else { 3395 rctl |= E1000_RCTL_SZ_2048; 3396 rctl &= ~E1000_RCTL_BSEX; 3397 } 3398 } else 3399 rctl |= E1000_RCTL_SZ_2048; 3400 3401 /* 3402 * rctl bits 11:10 are as follows 3403 * lem: reserved 3404 * em: DTYPE 3405 * igb: reserved 3406 * and should be 00 on all of the above 3407 */ 3408 rctl &= ~0x00000C00; 3409 3410 /* Write out the settings */ 3411 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3412 3413 return; 3414 } 3415 3416 static void 3417 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3418 { 3419 struct adapter *adapter = iflib_get_softc(ctx); 3420 u32 index, bit; 3421 3422 index = (vtag >> 5) & 0x7F; 3423 bit = vtag & 0x1F; 3424 adapter->shadow_vfta[index] |= (1 << bit); 3425 ++adapter->num_vlans; 3426 } 3427 3428 static void 3429 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3430 { 3431 struct adapter *adapter = iflib_get_softc(ctx); 3432 u32 index, bit; 3433 3434 index = (vtag >> 5) & 0x7F; 3435 bit = vtag & 0x1F; 3436 adapter->shadow_vfta[index] &= ~(1 << bit); 3437 --adapter->num_vlans; 3438 } 3439 3440 static void 3441 em_setup_vlan_hw_support(struct adapter *adapter) 3442 { 3443 struct e1000_hw *hw = &adapter->hw; 3444 u32 reg; 3445 3446 /* 3447 * We get here thru init_locked, meaning 3448 * a soft reset, this has already cleared 3449 * the VFTA and other state, so if there 3450 * have been no vlan's registered do nothing. 3451 */ 3452 if (adapter->num_vlans == 0) 3453 return; 3454 3455 /* 3456 * A soft reset zero's out the VFTA, so 3457 * we need to repopulate it now. 3458 */ 3459 for (int i = 0; i < EM_VFTA_SIZE; i++) 3460 if (adapter->shadow_vfta[i] != 0) 3461 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3462 i, adapter->shadow_vfta[i]); 3463 3464 reg = E1000_READ_REG(hw, E1000_CTRL); 3465 reg |= E1000_CTRL_VME; 3466 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3467 3468 /* Enable the Filter Table */ 3469 reg = E1000_READ_REG(hw, E1000_RCTL); 3470 reg &= ~E1000_RCTL_CFIEN; 3471 reg |= E1000_RCTL_VFE; 3472 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3473 } 3474 3475 static void 3476 em_if_intr_enable(if_ctx_t ctx) 3477 { 3478 struct adapter *adapter = iflib_get_softc(ctx); 3479 struct e1000_hw *hw = &adapter->hw; 3480 u32 ims_mask = IMS_ENABLE_MASK; 3481 3482 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3483 E1000_WRITE_REG(hw, EM_EIAC, adapter->ims); 3484 ims_mask |= adapter->ims; 3485 } 3486 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3487 } 3488 3489 static void 3490 em_if_intr_disable(if_ctx_t ctx) 3491 { 3492 struct adapter *adapter = iflib_get_softc(ctx); 3493 struct e1000_hw *hw = &adapter->hw; 3494 3495 if (adapter->intr_type == IFLIB_INTR_MSIX) 3496 E1000_WRITE_REG(hw, EM_EIAC, 0); 3497 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3498 } 3499 3500 static void 3501 igb_if_intr_enable(if_ctx_t ctx) 3502 { 3503 struct adapter *adapter = iflib_get_softc(ctx); 3504 struct e1000_hw *hw = &adapter->hw; 3505 u32 mask; 3506 3507 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3508 mask = (adapter->que_mask | adapter->link_mask); 3509 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3510 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3511 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3512 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3513 } else 3514 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3515 E1000_WRITE_FLUSH(hw); 3516 } 3517 3518 static void 3519 igb_if_intr_disable(if_ctx_t ctx) 3520 { 3521 struct adapter *adapter = iflib_get_softc(ctx); 3522 struct e1000_hw *hw = &adapter->hw; 3523 3524 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3525 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3526 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3527 } 3528 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3529 E1000_WRITE_FLUSH(hw); 3530 } 3531 3532 /* 3533 * Bit of a misnomer, what this really means is 3534 * to enable OS management of the system... aka 3535 * to disable special hardware management features 3536 */ 3537 static void 3538 em_init_manageability(struct adapter *adapter) 3539 { 3540 /* A shared code workaround */ 3541 #define E1000_82542_MANC2H E1000_MANC2H 3542 if (adapter->has_manage) { 3543 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3544 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3545 3546 /* disable hardware interception of ARP */ 3547 manc &= ~(E1000_MANC_ARP_EN); 3548 3549 /* enable receiving management packets to the host */ 3550 manc |= E1000_MANC_EN_MNG2HOST; 3551 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3552 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3553 manc2h |= E1000_MNG2HOST_PORT_623; 3554 manc2h |= E1000_MNG2HOST_PORT_664; 3555 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3556 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3557 } 3558 } 3559 3560 /* 3561 * Give control back to hardware management 3562 * controller if there is one. 3563 */ 3564 static void 3565 em_release_manageability(struct adapter *adapter) 3566 { 3567 if (adapter->has_manage) { 3568 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3569 3570 /* re-enable hardware interception of ARP */ 3571 manc |= E1000_MANC_ARP_EN; 3572 manc &= ~E1000_MANC_EN_MNG2HOST; 3573 3574 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3575 } 3576 } 3577 3578 /* 3579 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3580 * For ASF and Pass Through versions of f/w this means 3581 * that the driver is loaded. For AMT version type f/w 3582 * this means that the network i/f is open. 3583 */ 3584 static void 3585 em_get_hw_control(struct adapter *adapter) 3586 { 3587 u32 ctrl_ext, swsm; 3588 3589 if (adapter->vf_ifp) 3590 return; 3591 3592 if (adapter->hw.mac.type == e1000_82573) { 3593 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3594 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3595 swsm | E1000_SWSM_DRV_LOAD); 3596 return; 3597 } 3598 /* else */ 3599 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3600 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3601 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3602 } 3603 3604 /* 3605 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3606 * For ASF and Pass Through versions of f/w this means that 3607 * the driver is no longer loaded. For AMT versions of the 3608 * f/w this means that the network i/f is closed. 3609 */ 3610 static void 3611 em_release_hw_control(struct adapter *adapter) 3612 { 3613 u32 ctrl_ext, swsm; 3614 3615 if (!adapter->has_manage) 3616 return; 3617 3618 if (adapter->hw.mac.type == e1000_82573) { 3619 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3620 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3621 swsm & ~E1000_SWSM_DRV_LOAD); 3622 return; 3623 } 3624 /* else */ 3625 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3626 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3627 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3628 return; 3629 } 3630 3631 static int 3632 em_is_valid_ether_addr(u8 *addr) 3633 { 3634 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3635 3636 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3637 return (FALSE); 3638 } 3639 3640 return (TRUE); 3641 } 3642 3643 /* 3644 ** Parse the interface capabilities with regard 3645 ** to both system management and wake-on-lan for 3646 ** later use. 3647 */ 3648 static void 3649 em_get_wakeup(if_ctx_t ctx) 3650 { 3651 struct adapter *adapter = iflib_get_softc(ctx); 3652 device_t dev = iflib_get_dev(ctx); 3653 u16 eeprom_data = 0, device_id, apme_mask; 3654 3655 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3656 apme_mask = EM_EEPROM_APME; 3657 3658 switch (adapter->hw.mac.type) { 3659 case e1000_82542: 3660 case e1000_82543: 3661 break; 3662 case e1000_82544: 3663 e1000_read_nvm(&adapter->hw, 3664 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3665 apme_mask = EM_82544_APME; 3666 break; 3667 case e1000_82546: 3668 case e1000_82546_rev_3: 3669 if (adapter->hw.bus.func == 1) { 3670 e1000_read_nvm(&adapter->hw, 3671 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3672 break; 3673 } else 3674 e1000_read_nvm(&adapter->hw, 3675 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3676 break; 3677 case e1000_82573: 3678 case e1000_82583: 3679 adapter->has_amt = TRUE; 3680 /* FALLTHROUGH */ 3681 case e1000_82571: 3682 case e1000_82572: 3683 case e1000_80003es2lan: 3684 if (adapter->hw.bus.func == 1) { 3685 e1000_read_nvm(&adapter->hw, 3686 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3687 break; 3688 } else 3689 e1000_read_nvm(&adapter->hw, 3690 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3691 break; 3692 case e1000_ich8lan: 3693 case e1000_ich9lan: 3694 case e1000_ich10lan: 3695 case e1000_pchlan: 3696 case e1000_pch2lan: 3697 case e1000_pch_lpt: 3698 case e1000_pch_spt: 3699 case e1000_82575: /* listing all igb devices */ 3700 case e1000_82576: 3701 case e1000_82580: 3702 case e1000_i350: 3703 case e1000_i354: 3704 case e1000_i210: 3705 case e1000_i211: 3706 case e1000_vfadapt: 3707 case e1000_vfadapt_i350: 3708 apme_mask = E1000_WUC_APME; 3709 adapter->has_amt = TRUE; 3710 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3711 break; 3712 default: 3713 e1000_read_nvm(&adapter->hw, 3714 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3715 break; 3716 } 3717 if (eeprom_data & apme_mask) 3718 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3719 /* 3720 * We have the eeprom settings, now apply the special cases 3721 * where the eeprom may be wrong or the board won't support 3722 * wake on lan on a particular port 3723 */ 3724 device_id = pci_get_device(dev); 3725 switch (device_id) { 3726 case E1000_DEV_ID_82546GB_PCIE: 3727 adapter->wol = 0; 3728 break; 3729 case E1000_DEV_ID_82546EB_FIBER: 3730 case E1000_DEV_ID_82546GB_FIBER: 3731 /* Wake events only supported on port A for dual fiber 3732 * regardless of eeprom setting */ 3733 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3734 E1000_STATUS_FUNC_1) 3735 adapter->wol = 0; 3736 break; 3737 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3738 /* if quad port adapter, disable WoL on all but port A */ 3739 if (global_quad_port_a != 0) 3740 adapter->wol = 0; 3741 /* Reset for multiple quad port adapters */ 3742 if (++global_quad_port_a == 4) 3743 global_quad_port_a = 0; 3744 break; 3745 case E1000_DEV_ID_82571EB_FIBER: 3746 /* Wake events only supported on port A for dual fiber 3747 * regardless of eeprom setting */ 3748 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3749 E1000_STATUS_FUNC_1) 3750 adapter->wol = 0; 3751 break; 3752 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3753 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3754 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3755 /* if quad port adapter, disable WoL on all but port A */ 3756 if (global_quad_port_a != 0) 3757 adapter->wol = 0; 3758 /* Reset for multiple quad port adapters */ 3759 if (++global_quad_port_a == 4) 3760 global_quad_port_a = 0; 3761 break; 3762 } 3763 return; 3764 } 3765 3766 3767 /* 3768 * Enable PCI Wake On Lan capability 3769 */ 3770 static void 3771 em_enable_wakeup(if_ctx_t ctx) 3772 { 3773 struct adapter *adapter = iflib_get_softc(ctx); 3774 device_t dev = iflib_get_dev(ctx); 3775 if_t ifp = iflib_get_ifp(ctx); 3776 int error = 0; 3777 u32 pmc, ctrl, ctrl_ext, rctl; 3778 u16 status; 3779 3780 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3781 return; 3782 3783 /* 3784 * Determine type of Wakeup: note that wol 3785 * is set with all bits on by default. 3786 */ 3787 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3788 adapter->wol &= ~E1000_WUFC_MAG; 3789 3790 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3791 adapter->wol &= ~E1000_WUFC_EX; 3792 3793 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3794 adapter->wol &= ~E1000_WUFC_MC; 3795 else { 3796 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3797 rctl |= E1000_RCTL_MPE; 3798 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3799 } 3800 3801 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) { 3802 if (adapter->hw.mac.type >= e1000_pch_lpt) { 3803 e1000_enable_ulp_lpt_lp(&adapter->hw, TRUE); 3804 } 3805 goto pme; 3806 } 3807 3808 /* Advertise the wakeup capability */ 3809 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3810 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3811 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3812 3813 /* Keep the laser running on Fiber adapters */ 3814 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3815 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3816 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3817 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3818 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3819 } 3820 3821 if ((adapter->hw.mac.type == e1000_ich8lan) || 3822 (adapter->hw.mac.type == e1000_pchlan) || 3823 (adapter->hw.mac.type == e1000_ich9lan) || 3824 (adapter->hw.mac.type == e1000_ich10lan)) 3825 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3826 3827 if ( adapter->hw.mac.type >= e1000_pchlan) { 3828 error = em_enable_phy_wakeup(adapter); 3829 if (error) 3830 goto pme; 3831 } else { 3832 /* Enable wakeup by the MAC */ 3833 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3834 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3835 } 3836 3837 if (adapter->hw.phy.type == e1000_phy_igp_3) 3838 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3839 3840 pme: 3841 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3842 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3843 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3844 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3845 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3846 3847 return; 3848 } 3849 3850 /* 3851 * WOL in the newer chipset interfaces (pchlan) 3852 * require thing to be copied into the phy 3853 */ 3854 static int 3855 em_enable_phy_wakeup(struct adapter *adapter) 3856 { 3857 struct e1000_hw *hw = &adapter->hw; 3858 u32 mreg, ret = 0; 3859 u16 preg; 3860 3861 /* copy MAC RARs to PHY RARs */ 3862 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3863 3864 /* copy MAC MTA to PHY MTA */ 3865 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3866 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3867 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3868 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3869 (u16)((mreg >> 16) & 0xFFFF)); 3870 } 3871 3872 /* configure PHY Rx Control register */ 3873 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3874 mreg = E1000_READ_REG(hw, E1000_RCTL); 3875 if (mreg & E1000_RCTL_UPE) 3876 preg |= BM_RCTL_UPE; 3877 if (mreg & E1000_RCTL_MPE) 3878 preg |= BM_RCTL_MPE; 3879 preg &= ~(BM_RCTL_MO_MASK); 3880 if (mreg & E1000_RCTL_MO_3) 3881 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3882 << BM_RCTL_MO_SHIFT); 3883 if (mreg & E1000_RCTL_BAM) 3884 preg |= BM_RCTL_BAM; 3885 if (mreg & E1000_RCTL_PMCF) 3886 preg |= BM_RCTL_PMCF; 3887 mreg = E1000_READ_REG(hw, E1000_CTRL); 3888 if (mreg & E1000_CTRL_RFCE) 3889 preg |= BM_RCTL_RFCE; 3890 e1000_write_phy_reg(hw, BM_RCTL, preg); 3891 3892 /* enable PHY wakeup in MAC register */ 3893 E1000_WRITE_REG(hw, E1000_WUC, 3894 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3895 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3896 3897 /* configure and enable PHY wakeup in PHY registers */ 3898 e1000_write_phy_reg(hw, BM_WUFC, adapter->wol); 3899 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3900 3901 /* activate PHY wakeup */ 3902 ret = hw->phy.ops.acquire(hw); 3903 if (ret) { 3904 printf("Could not acquire PHY\n"); 3905 return ret; 3906 } 3907 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3908 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3909 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3910 if (ret) { 3911 printf("Could not read PHY page 769\n"); 3912 goto out; 3913 } 3914 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3915 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3916 if (ret) 3917 printf("Could not set PHY Host Wakeup bit\n"); 3918 out: 3919 hw->phy.ops.release(hw); 3920 3921 return ret; 3922 } 3923 3924 static void 3925 em_if_led_func(if_ctx_t ctx, int onoff) 3926 { 3927 struct adapter *adapter = iflib_get_softc(ctx); 3928 3929 if (onoff) { 3930 e1000_setup_led(&adapter->hw); 3931 e1000_led_on(&adapter->hw); 3932 } else { 3933 e1000_led_off(&adapter->hw); 3934 e1000_cleanup_led(&adapter->hw); 3935 } 3936 } 3937 3938 /* 3939 * Disable the L0S and L1 LINK states 3940 */ 3941 static void 3942 em_disable_aspm(struct adapter *adapter) 3943 { 3944 int base, reg; 3945 u16 link_cap,link_ctrl; 3946 device_t dev = adapter->dev; 3947 3948 switch (adapter->hw.mac.type) { 3949 case e1000_82573: 3950 case e1000_82574: 3951 case e1000_82583: 3952 break; 3953 default: 3954 return; 3955 } 3956 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3957 return; 3958 reg = base + PCIER_LINK_CAP; 3959 link_cap = pci_read_config(dev, reg, 2); 3960 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3961 return; 3962 reg = base + PCIER_LINK_CTL; 3963 link_ctrl = pci_read_config(dev, reg, 2); 3964 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3965 pci_write_config(dev, reg, link_ctrl, 2); 3966 return; 3967 } 3968 3969 /********************************************************************** 3970 * 3971 * Update the board statistics counters. 3972 * 3973 **********************************************************************/ 3974 static void 3975 em_update_stats_counters(struct adapter *adapter) 3976 { 3977 u64 prev_xoffrxc = adapter->stats.xoffrxc; 3978 3979 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3980 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3981 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3982 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3983 } 3984 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3985 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3986 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3987 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3988 3989 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3990 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3991 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3992 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3993 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3994 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3995 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3996 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3997 /* 3998 ** For watchdog management we need to know if we have been 3999 ** paused during the last interval, so capture that here. 4000 */ 4001 if (adapter->stats.xoffrxc != prev_xoffrxc) 4002 adapter->shared->isc_pause_frames = 1; 4003 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4004 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4005 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4006 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4007 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4008 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4009 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4010 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4011 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 4012 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 4013 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 4014 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 4015 4016 /* For the 64-bit byte counters the low dword must be read first. */ 4017 /* Both registers clear on the read of the high dword */ 4018 4019 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 4020 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 4021 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 4022 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 4023 4024 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 4025 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 4026 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 4027 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 4028 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 4029 4030 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 4031 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 4032 4033 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 4034 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 4035 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 4036 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 4037 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 4038 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 4039 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 4040 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 4041 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 4042 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 4043 4044 /* Interrupt Counts */ 4045 4046 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 4047 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 4048 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 4049 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 4050 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 4051 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 4052 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 4053 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 4054 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 4055 4056 if (adapter->hw.mac.type >= e1000_82543) { 4057 adapter->stats.algnerrc += 4058 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4059 adapter->stats.rxerrc += 4060 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4061 adapter->stats.tncrs += 4062 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4063 adapter->stats.cexterr += 4064 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4065 adapter->stats.tsctc += 4066 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4067 adapter->stats.tsctfc += 4068 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4069 } 4070 } 4071 4072 static uint64_t 4073 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4074 { 4075 struct adapter *adapter = iflib_get_softc(ctx); 4076 struct ifnet *ifp = iflib_get_ifp(ctx); 4077 4078 switch (cnt) { 4079 case IFCOUNTER_COLLISIONS: 4080 return (adapter->stats.colc); 4081 case IFCOUNTER_IERRORS: 4082 return (adapter->dropped_pkts + adapter->stats.rxerrc + 4083 adapter->stats.crcerrs + adapter->stats.algnerrc + 4084 adapter->stats.ruc + adapter->stats.roc + 4085 adapter->stats.mpc + adapter->stats.cexterr); 4086 case IFCOUNTER_OERRORS: 4087 return (adapter->stats.ecol + adapter->stats.latecol + 4088 adapter->watchdog_events); 4089 default: 4090 return (if_get_counter_default(ifp, cnt)); 4091 } 4092 } 4093 4094 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4095 * @ctx: iflib context 4096 * @event: event code to check 4097 * 4098 * Defaults to returning true for unknown events. 4099 * 4100 * @returns true if iflib needs to reinit the interface 4101 */ 4102 static bool 4103 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4104 { 4105 switch (event) { 4106 case IFLIB_RESTART_VLAN_CONFIG: 4107 default: 4108 return (true); 4109 } 4110 } 4111 4112 /* Export a single 32-bit register via a read-only sysctl. */ 4113 static int 4114 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4115 { 4116 struct adapter *adapter; 4117 u_int val; 4118 4119 adapter = oidp->oid_arg1; 4120 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 4121 return (sysctl_handle_int(oidp, &val, 0, req)); 4122 } 4123 4124 /* 4125 * Add sysctl variables, one per statistic, to the system. 4126 */ 4127 static void 4128 em_add_hw_stats(struct adapter *adapter) 4129 { 4130 device_t dev = iflib_get_dev(adapter->ctx); 4131 struct em_tx_queue *tx_que = adapter->tx_queues; 4132 struct em_rx_queue *rx_que = adapter->rx_queues; 4133 4134 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4135 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4136 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4137 struct e1000_hw_stats *stats = &adapter->stats; 4138 4139 struct sysctl_oid *stat_node, *queue_node, *int_node; 4140 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4141 4142 #define QUEUE_NAME_LEN 32 4143 char namebuf[QUEUE_NAME_LEN]; 4144 4145 /* Driver Statistics */ 4146 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4147 CTLFLAG_RD, &adapter->dropped_pkts, 4148 "Driver dropped packets"); 4149 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4150 CTLFLAG_RD, &adapter->link_irq, 4151 "Link MSI-X IRQ Handled"); 4152 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4153 CTLFLAG_RD, &adapter->rx_overruns, 4154 "RX overruns"); 4155 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4156 CTLFLAG_RD, &adapter->watchdog_events, 4157 "Watchdog timeouts"); 4158 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4159 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4160 adapter, E1000_CTRL, em_sysctl_reg_handler, "IU", 4161 "Device Control Register"); 4162 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4163 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4164 adapter, E1000_RCTL, em_sysctl_reg_handler, "IU", 4165 "Receiver Control Register"); 4166 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4167 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4168 "Flow Control High Watermark"); 4169 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4170 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4171 "Flow Control Low Watermark"); 4172 4173 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4174 struct tx_ring *txr = &tx_que->txr; 4175 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4176 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4177 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4178 queue_list = SYSCTL_CHILDREN(queue_node); 4179 4180 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4181 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4182 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4183 "Transmit Descriptor Head"); 4184 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4185 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4186 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4187 "Transmit Descriptor Tail"); 4188 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4189 CTLFLAG_RD, &txr->tx_irq, 4190 "Queue MSI-X Transmit Interrupts"); 4191 } 4192 4193 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4194 struct rx_ring *rxr = &rx_que->rxr; 4195 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4196 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4197 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4198 queue_list = SYSCTL_CHILDREN(queue_node); 4199 4200 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4201 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4202 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4203 "Receive Descriptor Head"); 4204 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4205 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4206 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4207 "Receive Descriptor Tail"); 4208 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4209 CTLFLAG_RD, &rxr->rx_irq, 4210 "Queue MSI-X Receive Interrupts"); 4211 } 4212 4213 /* MAC stats get their own sub node */ 4214 4215 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4216 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4217 stat_list = SYSCTL_CHILDREN(stat_node); 4218 4219 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4220 CTLFLAG_RD, &stats->ecol, 4221 "Excessive collisions"); 4222 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4223 CTLFLAG_RD, &stats->scc, 4224 "Single collisions"); 4225 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4226 CTLFLAG_RD, &stats->mcc, 4227 "Multiple collisions"); 4228 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4229 CTLFLAG_RD, &stats->latecol, 4230 "Late collisions"); 4231 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4232 CTLFLAG_RD, &stats->colc, 4233 "Collision Count"); 4234 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4235 CTLFLAG_RD, &adapter->stats.symerrs, 4236 "Symbol Errors"); 4237 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4238 CTLFLAG_RD, &adapter->stats.sec, 4239 "Sequence Errors"); 4240 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4241 CTLFLAG_RD, &adapter->stats.dc, 4242 "Defer Count"); 4243 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4244 CTLFLAG_RD, &adapter->stats.mpc, 4245 "Missed Packets"); 4246 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4247 CTLFLAG_RD, &adapter->stats.rnbc, 4248 "Receive No Buffers"); 4249 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4250 CTLFLAG_RD, &adapter->stats.ruc, 4251 "Receive Undersize"); 4252 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4253 CTLFLAG_RD, &adapter->stats.rfc, 4254 "Fragmented Packets Received "); 4255 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4256 CTLFLAG_RD, &adapter->stats.roc, 4257 "Oversized Packets Received"); 4258 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4259 CTLFLAG_RD, &adapter->stats.rjc, 4260 "Recevied Jabber"); 4261 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4262 CTLFLAG_RD, &adapter->stats.rxerrc, 4263 "Receive Errors"); 4264 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4265 CTLFLAG_RD, &adapter->stats.crcerrs, 4266 "CRC errors"); 4267 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4268 CTLFLAG_RD, &adapter->stats.algnerrc, 4269 "Alignment Errors"); 4270 /* On 82575 these are collision counts */ 4271 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4272 CTLFLAG_RD, &adapter->stats.cexterr, 4273 "Collision/Carrier extension errors"); 4274 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4275 CTLFLAG_RD, &adapter->stats.xonrxc, 4276 "XON Received"); 4277 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4278 CTLFLAG_RD, &adapter->stats.xontxc, 4279 "XON Transmitted"); 4280 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4281 CTLFLAG_RD, &adapter->stats.xoffrxc, 4282 "XOFF Received"); 4283 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4284 CTLFLAG_RD, &adapter->stats.xofftxc, 4285 "XOFF Transmitted"); 4286 4287 /* Packet Reception Stats */ 4288 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4289 CTLFLAG_RD, &adapter->stats.tpr, 4290 "Total Packets Received "); 4291 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4292 CTLFLAG_RD, &adapter->stats.gprc, 4293 "Good Packets Received"); 4294 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4295 CTLFLAG_RD, &adapter->stats.bprc, 4296 "Broadcast Packets Received"); 4297 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4298 CTLFLAG_RD, &adapter->stats.mprc, 4299 "Multicast Packets Received"); 4300 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4301 CTLFLAG_RD, &adapter->stats.prc64, 4302 "64 byte frames received "); 4303 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4304 CTLFLAG_RD, &adapter->stats.prc127, 4305 "65-127 byte frames received"); 4306 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4307 CTLFLAG_RD, &adapter->stats.prc255, 4308 "128-255 byte frames received"); 4309 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4310 CTLFLAG_RD, &adapter->stats.prc511, 4311 "256-511 byte frames received"); 4312 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4313 CTLFLAG_RD, &adapter->stats.prc1023, 4314 "512-1023 byte frames received"); 4315 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4316 CTLFLAG_RD, &adapter->stats.prc1522, 4317 "1023-1522 byte frames received"); 4318 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4319 CTLFLAG_RD, &adapter->stats.gorc, 4320 "Good Octets Received"); 4321 4322 /* Packet Transmission Stats */ 4323 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4324 CTLFLAG_RD, &adapter->stats.gotc, 4325 "Good Octets Transmitted"); 4326 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4327 CTLFLAG_RD, &adapter->stats.tpt, 4328 "Total Packets Transmitted"); 4329 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4330 CTLFLAG_RD, &adapter->stats.gptc, 4331 "Good Packets Transmitted"); 4332 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4333 CTLFLAG_RD, &adapter->stats.bptc, 4334 "Broadcast Packets Transmitted"); 4335 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4336 CTLFLAG_RD, &adapter->stats.mptc, 4337 "Multicast Packets Transmitted"); 4338 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4339 CTLFLAG_RD, &adapter->stats.ptc64, 4340 "64 byte frames transmitted "); 4341 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4342 CTLFLAG_RD, &adapter->stats.ptc127, 4343 "65-127 byte frames transmitted"); 4344 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4345 CTLFLAG_RD, &adapter->stats.ptc255, 4346 "128-255 byte frames transmitted"); 4347 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4348 CTLFLAG_RD, &adapter->stats.ptc511, 4349 "256-511 byte frames transmitted"); 4350 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4351 CTLFLAG_RD, &adapter->stats.ptc1023, 4352 "512-1023 byte frames transmitted"); 4353 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4354 CTLFLAG_RD, &adapter->stats.ptc1522, 4355 "1024-1522 byte frames transmitted"); 4356 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4357 CTLFLAG_RD, &adapter->stats.tsctc, 4358 "TSO Contexts Transmitted"); 4359 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4360 CTLFLAG_RD, &adapter->stats.tsctfc, 4361 "TSO Contexts Failed"); 4362 4363 4364 /* Interrupt Stats */ 4365 4366 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4367 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4368 int_list = SYSCTL_CHILDREN(int_node); 4369 4370 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4371 CTLFLAG_RD, &adapter->stats.iac, 4372 "Interrupt Assertion Count"); 4373 4374 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4375 CTLFLAG_RD, &adapter->stats.icrxptc, 4376 "Interrupt Cause Rx Pkt Timer Expire Count"); 4377 4378 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4379 CTLFLAG_RD, &adapter->stats.icrxatc, 4380 "Interrupt Cause Rx Abs Timer Expire Count"); 4381 4382 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4383 CTLFLAG_RD, &adapter->stats.ictxptc, 4384 "Interrupt Cause Tx Pkt Timer Expire Count"); 4385 4386 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4387 CTLFLAG_RD, &adapter->stats.ictxatc, 4388 "Interrupt Cause Tx Abs Timer Expire Count"); 4389 4390 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4391 CTLFLAG_RD, &adapter->stats.ictxqec, 4392 "Interrupt Cause Tx Queue Empty Count"); 4393 4394 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4395 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4396 "Interrupt Cause Tx Queue Min Thresh Count"); 4397 4398 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4399 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4400 "Interrupt Cause Rx Desc Min Thresh Count"); 4401 4402 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4403 CTLFLAG_RD, &adapter->stats.icrxoc, 4404 "Interrupt Cause Receiver Overrun Count"); 4405 } 4406 4407 /********************************************************************** 4408 * 4409 * This routine provides a way to dump out the adapter eeprom, 4410 * often a useful debug/service tool. This only dumps the first 4411 * 32 words, stuff that matters is in that extent. 4412 * 4413 **********************************************************************/ 4414 static int 4415 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4416 { 4417 struct adapter *adapter = (struct adapter *)arg1; 4418 int error; 4419 int result; 4420 4421 result = -1; 4422 error = sysctl_handle_int(oidp, &result, 0, req); 4423 4424 if (error || !req->newptr) 4425 return (error); 4426 4427 /* 4428 * This value will cause a hex dump of the 4429 * first 32 16-bit words of the EEPROM to 4430 * the screen. 4431 */ 4432 if (result == 1) 4433 em_print_nvm_info(adapter); 4434 4435 return (error); 4436 } 4437 4438 static void 4439 em_print_nvm_info(struct adapter *adapter) 4440 { 4441 u16 eeprom_data; 4442 int i, j, row = 0; 4443 4444 /* Its a bit crude, but it gets the job done */ 4445 printf("\nInterface EEPROM Dump:\n"); 4446 printf("Offset\n0x0000 "); 4447 for (i = 0, j = 0; i < 32; i++, j++) { 4448 if (j == 8) { /* Make the offset block */ 4449 j = 0; ++row; 4450 printf("\n0x00%x0 ",row); 4451 } 4452 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4453 printf("%04x ", eeprom_data); 4454 } 4455 printf("\n"); 4456 } 4457 4458 static int 4459 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4460 { 4461 struct em_int_delay_info *info; 4462 struct adapter *adapter; 4463 u32 regval; 4464 int error, usecs, ticks; 4465 4466 info = (struct em_int_delay_info *) arg1; 4467 usecs = info->value; 4468 error = sysctl_handle_int(oidp, &usecs, 0, req); 4469 if (error != 0 || req->newptr == NULL) 4470 return (error); 4471 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4472 return (EINVAL); 4473 info->value = usecs; 4474 ticks = EM_USECS_TO_TICKS(usecs); 4475 if (info->offset == E1000_ITR) /* units are 256ns here */ 4476 ticks *= 4; 4477 4478 adapter = info->adapter; 4479 4480 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4481 regval = (regval & ~0xffff) | (ticks & 0xffff); 4482 /* Handle a few special cases. */ 4483 switch (info->offset) { 4484 case E1000_RDTR: 4485 break; 4486 case E1000_TIDV: 4487 if (ticks == 0) { 4488 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4489 /* Don't write 0 into the TIDV register. */ 4490 regval++; 4491 } else 4492 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4493 break; 4494 } 4495 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4496 return (0); 4497 } 4498 4499 static void 4500 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4501 const char *description, struct em_int_delay_info *info, 4502 int offset, int value) 4503 { 4504 info->adapter = adapter; 4505 info->offset = offset; 4506 info->value = value; 4507 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4508 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4509 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4510 info, 0, em_sysctl_int_delay, "I", description); 4511 } 4512 4513 /* 4514 * Set flow control using sysctl: 4515 * Flow control values: 4516 * 0 - off 4517 * 1 - rx pause 4518 * 2 - tx pause 4519 * 3 - full 4520 */ 4521 static int 4522 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4523 { 4524 int error; 4525 static int input = 3; /* default is full */ 4526 struct adapter *adapter = (struct adapter *) arg1; 4527 4528 error = sysctl_handle_int(oidp, &input, 0, req); 4529 4530 if ((error) || (req->newptr == NULL)) 4531 return (error); 4532 4533 if (input == adapter->fc) /* no change? */ 4534 return (error); 4535 4536 switch (input) { 4537 case e1000_fc_rx_pause: 4538 case e1000_fc_tx_pause: 4539 case e1000_fc_full: 4540 case e1000_fc_none: 4541 adapter->hw.fc.requested_mode = input; 4542 adapter->fc = input; 4543 break; 4544 default: 4545 /* Do nothing */ 4546 return (error); 4547 } 4548 4549 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4550 e1000_force_mac_fc(&adapter->hw); 4551 return (error); 4552 } 4553 4554 /* 4555 * Manage Energy Efficient Ethernet: 4556 * Control values: 4557 * 0/1 - enabled/disabled 4558 */ 4559 static int 4560 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4561 { 4562 struct adapter *adapter = (struct adapter *) arg1; 4563 int error, value; 4564 4565 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4566 error = sysctl_handle_int(oidp, &value, 0, req); 4567 if (error || req->newptr == NULL) 4568 return (error); 4569 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4570 em_if_init(adapter->ctx); 4571 4572 return (0); 4573 } 4574 4575 static int 4576 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4577 { 4578 struct adapter *adapter; 4579 int error; 4580 int result; 4581 4582 result = -1; 4583 error = sysctl_handle_int(oidp, &result, 0, req); 4584 4585 if (error || !req->newptr) 4586 return (error); 4587 4588 if (result == 1) { 4589 adapter = (struct adapter *) arg1; 4590 em_print_debug_info(adapter); 4591 } 4592 4593 return (error); 4594 } 4595 4596 static int 4597 em_get_rs(SYSCTL_HANDLER_ARGS) 4598 { 4599 struct adapter *adapter = (struct adapter *) arg1; 4600 int error; 4601 int result; 4602 4603 result = 0; 4604 error = sysctl_handle_int(oidp, &result, 0, req); 4605 4606 if (error || !req->newptr || result != 1) 4607 return (error); 4608 em_dump_rs(adapter); 4609 4610 return (error); 4611 } 4612 4613 static void 4614 em_if_debug(if_ctx_t ctx) 4615 { 4616 em_dump_rs(iflib_get_softc(ctx)); 4617 } 4618 4619 /* 4620 * This routine is meant to be fluid, add whatever is 4621 * needed for debugging a problem. -jfv 4622 */ 4623 static void 4624 em_print_debug_info(struct adapter *adapter) 4625 { 4626 device_t dev = iflib_get_dev(adapter->ctx); 4627 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4628 struct tx_ring *txr = &adapter->tx_queues->txr; 4629 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4630 4631 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4632 printf("Interface is RUNNING "); 4633 else 4634 printf("Interface is NOT RUNNING\n"); 4635 4636 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4637 printf("and INACTIVE\n"); 4638 else 4639 printf("and ACTIVE\n"); 4640 4641 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4642 device_printf(dev, "TX Queue %d ------\n", i); 4643 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4644 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4645 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4646 4647 } 4648 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4649 device_printf(dev, "RX Queue %d ------\n", j); 4650 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4651 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4652 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4653 } 4654 } 4655 4656 /* 4657 * 82574 only: 4658 * Write a new value to the EEPROM increasing the number of MSI-X 4659 * vectors from 3 to 5, for proper multiqueue support. 4660 */ 4661 static void 4662 em_enable_vectors_82574(if_ctx_t ctx) 4663 { 4664 struct adapter *adapter = iflib_get_softc(ctx); 4665 struct e1000_hw *hw = &adapter->hw; 4666 device_t dev = iflib_get_dev(ctx); 4667 u16 edata; 4668 4669 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4670 if (bootverbose) 4671 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4672 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4673 device_printf(dev, "Writing to eeprom: increasing " 4674 "reported MSI-X vectors from 3 to 5...\n"); 4675 edata &= ~(EM_NVM_MSIX_N_MASK); 4676 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4677 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4678 e1000_update_nvm_checksum(hw); 4679 device_printf(dev, "Writing to eeprom: done\n"); 4680 } 4681 } 4682