1 /*- 2 * Copyright (c) 2016 Matt Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 #include "if_em.h" 29 #include <sys/sbuf.h> 30 #include <machine/_inttypes.h> 31 32 #define em_mac_min e1000_82547 33 #define igb_mac_min e1000_82575 34 35 /********************************************************************* 36 * Driver version: 37 *********************************************************************/ 38 char em_driver_version[] = "7.6.1-k"; 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last field stores an index into e1000_strings 45 * Last entry must be all 0s 46 * 47 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 48 *********************************************************************/ 49 50 static pci_vendor_info_t em_vendor_info_array[] = 51 { 52 /* Intel(R) PRO/1000 Network Connection - Legacy em*/ 53 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) PRO/1000 Network Connection"), 54 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) PRO/1000 Network Connection"), 55 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) PRO/1000 Network Connection"), 56 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) PRO/1000 Network Connection"), 57 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) PRO/1000 Network Connection"), 58 59 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) PRO/1000 Network Connection"), 60 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) PRO/1000 Network Connection"), 61 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) PRO/1000 Network Connection"), 62 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 63 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) PRO/1000 Network Connection"), 64 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) PRO/1000 Network Connection"), 65 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 66 67 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) PRO/1000 Network Connection"), 68 69 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) PRO/1000 Network Connection"), 70 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 71 72 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 73 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 74 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) PRO/1000 Network Connection"), 75 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) PRO/1000 Network Connection"), 76 77 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) PRO/1000 Network Connection"), 78 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) PRO/1000 Network Connection"), 79 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) PRO/1000 Network Connection"), 80 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) PRO/1000 Network Connection"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) PRO/1000 Network Connection"), 82 83 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 84 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 85 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 86 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) PRO/1000 Network Connection"), 87 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) PRO/1000 Network Connection"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) PRO/1000 Network Connection"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) PRO/1000 Network Connection"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) PRO/1000 Network Connection"), 92 93 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) PRO/1000 Network Connection"), 94 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) PRO/1000 Network Connection"), 95 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) PRO/1000 Network Connection"), 96 97 /* Intel(R) PRO/1000 Network Connection - em */ 98 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 Network Connection"), 99 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 Network Connection"), 100 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 Network Connection"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 Network Connection"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 Network Connection"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 Network Connection"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 Network Connection"), 106 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 Network Connection"), 107 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 Network Connection"), 108 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 Network Connection"), 109 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 Network Connection"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 Network Connection"), 111 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 Network Connection"), 112 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 Network Connection"), 113 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 Network Connection"), 114 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) PRO/1000 Network Connection"), 115 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) PRO/1000 Network Connection"), 116 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) PRO/1000 Network Connection"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) PRO/1000 Network Connection"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) PRO/1000 Network Connection"), 119 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 120 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) PRO/1000 Network Connection"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) PRO/1000 Network Connection"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) PRO/1000 Network Connection"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) PRO/1000 Network Connection"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) PRO/1000 Network Connection"), 127 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) PRO/1000 Network Connection"), 128 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) PRO/1000 Network Connection"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) PRO/1000 Network Connection"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) PRO/1000 Network Connection"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) PRO/1000 Network Connection"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) PRO/1000 Network Connection"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) PRO/1000 Network Connection"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) PRO/1000 Network Connection"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) PRO/1000 Network Connection"), 136 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) PRO/1000 Network Connection"), 137 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) PRO/1000 Network Connection"), 138 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) PRO/1000 Network Connection"), 139 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) PRO/1000 Network Connection"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) PRO/1000 Network Connection"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) PRO/1000 Network Connection"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) PRO/1000 Network Connection"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) PRO/1000 Network Connection"), 144 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) PRO/1000 Network Connection"), 145 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) PRO/1000 Network Connection"), 146 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) PRO/1000 Network Connection"), 147 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) PRO/1000 Network Connection"), 148 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) PRO/1000 Network Connection"), 149 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) PRO/1000 Network Connection"), 150 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) PRO/1000 Network Connection"), 151 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) PRO/1000 Network Connection"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) PRO/1000 Network Connection"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) PRO/1000 Network Connection"), 154 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) PRO/1000 Network Connection"), 155 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) PRO/1000 Network Connection"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) PRO/1000 Network Connection"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) PRO/1000 Network Connection"), 158 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) PRO/1000 Network Connection"), 159 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) PRO/1000 Network Connection"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) PRO/1000 Network Connection"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) PRO/1000 Network Connection"), 162 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) PRO/1000 Network Connection"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) PRO/1000 Network Connection"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) PRO/1000 Network Connection"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) PRO/1000 Network Connection"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) PRO/1000 Network Connection"), 167 /* required last entry */ 168 PVID_END 169 }; 170 171 static pci_vendor_info_t igb_vendor_info_array[] = 172 { 173 /* Intel(R) PRO/1000 Network Connection - igb */ 174 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 175 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 176 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 177 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 PCI-Express Network Driver"), 178 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 179 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 180 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 181 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 182 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 PCI-Express Network Driver"), 183 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 184 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 PCI-Express Network Driver"), 185 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 186 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 187 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 188 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 189 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 190 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) PRO/1000 PCI-Express Network Driver"), 191 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 192 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 193 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 194 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) PRO/1000 PCI-Express Network Driver"), 195 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) PRO/1000 PCI-Express Network Driver"), 196 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 197 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 198 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 199 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 200 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) PRO/1000 PCI-Express Network Driver"), 201 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 202 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) PRO/1000 PCI-Express Network Driver"), 203 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) PRO/1000 PCI-Express Network Driver"), 204 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 205 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 206 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 207 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) PRO/1000 PCI-Express Network Driver"), 208 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 209 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) PRO/1000 PCI-Express Network Driver"), 210 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 211 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) PRO/1000 PCI-Express Network Driver"), 212 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) PRO/1000 PCI-Express Network Driver"), 213 /* required last entry */ 214 PVID_END 215 }; 216 217 /********************************************************************* 218 * Function prototypes 219 *********************************************************************/ 220 static void *em_register(device_t dev); 221 static void *igb_register(device_t dev); 222 static int em_if_attach_pre(if_ctx_t ctx); 223 static int em_if_attach_post(if_ctx_t ctx); 224 static int em_if_detach(if_ctx_t ctx); 225 static int em_if_shutdown(if_ctx_t ctx); 226 static int em_if_suspend(if_ctx_t ctx); 227 static int em_if_resume(if_ctx_t ctx); 228 229 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 230 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 231 static void em_if_queues_free(if_ctx_t ctx); 232 233 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 234 static void em_if_init(if_ctx_t ctx); 235 static void em_if_stop(if_ctx_t ctx); 236 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 237 static int em_if_media_change(if_ctx_t ctx); 238 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 239 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 240 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 241 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 242 243 static void em_identify_hardware(if_ctx_t ctx); 244 static int em_allocate_pci_resources(if_ctx_t ctx); 245 static void em_free_pci_resources(if_ctx_t ctx); 246 static void em_reset(if_ctx_t ctx); 247 static int em_setup_interface(if_ctx_t ctx); 248 static int em_setup_msix(if_ctx_t ctx); 249 250 static void em_initialize_transmit_unit(if_ctx_t ctx); 251 static void em_initialize_receive_unit(if_ctx_t ctx); 252 253 static void em_if_enable_intr(if_ctx_t ctx); 254 static void em_if_disable_intr(if_ctx_t ctx); 255 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 256 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 257 static void em_if_multi_set(if_ctx_t ctx); 258 static void em_if_update_admin_status(if_ctx_t ctx); 259 static void em_if_debug(if_ctx_t ctx); 260 static void em_update_stats_counters(struct adapter *); 261 static void em_add_hw_stats(struct adapter *adapter); 262 static int em_if_set_promisc(if_ctx_t ctx, int flags); 263 static void em_setup_vlan_hw_support(struct adapter *); 264 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 265 static void em_print_nvm_info(struct adapter *); 266 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 267 static int em_get_rs(SYSCTL_HANDLER_ARGS); 268 static void em_print_debug_info(struct adapter *); 269 static int em_is_valid_ether_addr(u8 *); 270 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 271 static void em_add_int_delay_sysctl(struct adapter *, const char *, 272 const char *, struct em_int_delay_info *, int, int); 273 /* Management and WOL Support */ 274 static void em_init_manageability(struct adapter *); 275 static void em_release_manageability(struct adapter *); 276 static void em_get_hw_control(struct adapter *); 277 static void em_release_hw_control(struct adapter *); 278 static void em_get_wakeup(if_ctx_t ctx); 279 static void em_enable_wakeup(if_ctx_t ctx); 280 static int em_enable_phy_wakeup(struct adapter *); 281 static void em_disable_aspm(struct adapter *); 282 283 int em_intr(void *arg); 284 static void em_disable_promisc(if_ctx_t ctx); 285 286 /* MSIX handlers */ 287 static int em_if_msix_intr_assign(if_ctx_t, int); 288 static int em_msix_link(void *); 289 static void em_handle_link(void *context); 290 291 static void em_enable_vectors_82574(if_ctx_t); 292 293 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 294 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 295 static void em_if_led_func(if_ctx_t ctx, int onoff); 296 297 static int em_get_regs(SYSCTL_HANDLER_ARGS); 298 299 static void lem_smartspeed(struct adapter *adapter); 300 static void igb_configure_queues(struct adapter *adapter); 301 302 303 /********************************************************************* 304 * FreeBSD Device Interface Entry Points 305 *********************************************************************/ 306 static device_method_t em_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_register, em_register), 309 DEVMETHOD(device_probe, iflib_device_probe), 310 DEVMETHOD(device_attach, iflib_device_attach), 311 DEVMETHOD(device_detach, iflib_device_detach), 312 DEVMETHOD(device_shutdown, iflib_device_shutdown), 313 DEVMETHOD(device_suspend, iflib_device_suspend), 314 DEVMETHOD(device_resume, iflib_device_resume), 315 DEVMETHOD_END 316 }; 317 318 static device_method_t igb_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_register, igb_register), 321 DEVMETHOD(device_probe, iflib_device_probe), 322 DEVMETHOD(device_attach, iflib_device_attach), 323 DEVMETHOD(device_detach, iflib_device_detach), 324 DEVMETHOD(device_shutdown, iflib_device_shutdown), 325 DEVMETHOD(device_suspend, iflib_device_suspend), 326 DEVMETHOD(device_resume, iflib_device_resume), 327 DEVMETHOD_END 328 }; 329 330 331 static driver_t em_driver = { 332 "em", em_methods, sizeof(struct adapter), 333 }; 334 335 static devclass_t em_devclass; 336 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 337 338 MODULE_DEPEND(em, pci, 1, 1, 1); 339 MODULE_DEPEND(em, ether, 1, 1, 1); 340 MODULE_DEPEND(em, iflib, 1, 1, 1); 341 342 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 343 344 static driver_t igb_driver = { 345 "igb", igb_methods, sizeof(struct adapter), 346 }; 347 348 static devclass_t igb_devclass; 349 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 350 351 MODULE_DEPEND(igb, pci, 1, 1, 1); 352 MODULE_DEPEND(igb, ether, 1, 1, 1); 353 MODULE_DEPEND(igb, iflib, 1, 1, 1); 354 355 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 356 357 static device_method_t em_if_methods[] = { 358 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 359 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 360 DEVMETHOD(ifdi_detach, em_if_detach), 361 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 362 DEVMETHOD(ifdi_suspend, em_if_suspend), 363 DEVMETHOD(ifdi_resume, em_if_resume), 364 DEVMETHOD(ifdi_init, em_if_init), 365 DEVMETHOD(ifdi_stop, em_if_stop), 366 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 367 DEVMETHOD(ifdi_intr_enable, em_if_enable_intr), 368 DEVMETHOD(ifdi_intr_disable, em_if_disable_intr), 369 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 370 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 371 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 372 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 373 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 374 DEVMETHOD(ifdi_media_status, em_if_media_status), 375 DEVMETHOD(ifdi_media_change, em_if_media_change), 376 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 377 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 378 DEVMETHOD(ifdi_timer, em_if_timer), 379 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 380 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 381 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 382 DEVMETHOD(ifdi_led_func, em_if_led_func), 383 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 384 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 385 DEVMETHOD(ifdi_debug, em_if_debug), 386 DEVMETHOD_END 387 }; 388 389 /* 390 * note that if (adapter->msix_mem) is replaced by: 391 * if (adapter->intr_type == IFLIB_INTR_MSIX) 392 */ 393 static driver_t em_if_driver = { 394 "em_if", em_if_methods, sizeof(struct adapter) 395 }; 396 397 /********************************************************************* 398 * Tunable default values. 399 *********************************************************************/ 400 401 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 402 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 403 #define M_TSO_LEN 66 404 405 #define MAX_INTS_PER_SEC 8000 406 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 407 408 /* Allow common code without TSO */ 409 #ifndef CSUM_TSO 410 #define CSUM_TSO 0 411 #endif 412 413 #define TSO_WORKAROUND 4 414 415 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD, 0, "EM driver parameters"); 416 417 static int em_disable_crc_stripping = 0; 418 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 419 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 420 421 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 422 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 423 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 424 0, "Default transmit interrupt delay in usecs"); 425 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 426 0, "Default receive interrupt delay in usecs"); 427 428 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 429 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 430 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 431 &em_tx_abs_int_delay_dflt, 0, 432 "Default transmit interrupt delay limit in usecs"); 433 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 434 &em_rx_abs_int_delay_dflt, 0, 435 "Default receive interrupt delay limit in usecs"); 436 437 static int em_smart_pwr_down = FALSE; 438 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 439 0, "Set to true to leave smart power down enabled on newer adapters"); 440 441 /* Controls whether promiscuous also shows bad packets */ 442 static int em_debug_sbp = TRUE; 443 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 444 "Show bad packets in promiscuous mode"); 445 446 /* How many packets rxeof tries to clean at a time */ 447 static int em_rx_process_limit = 100; 448 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 449 &em_rx_process_limit, 0, 450 "Maximum number of received packets to process " 451 "at a time, -1 means unlimited"); 452 453 /* Energy efficient ethernet - default to OFF */ 454 static int eee_setting = 1; 455 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 456 "Enable Energy Efficient Ethernet"); 457 458 /* 459 ** Tuneable Interrupt rate 460 */ 461 static int em_max_interrupt_rate = 8000; 462 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 463 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 464 465 466 467 /* Global used in WOL setup with multiport cards */ 468 static int global_quad_port_a = 0; 469 470 extern struct if_txrx igb_txrx; 471 extern struct if_txrx em_txrx; 472 extern struct if_txrx lem_txrx; 473 474 static struct if_shared_ctx em_sctx_init = { 475 .isc_magic = IFLIB_MAGIC, 476 .isc_q_align = PAGE_SIZE, 477 .isc_tx_maxsize = EM_TSO_SIZE, 478 .isc_tx_maxsegsize = PAGE_SIZE, 479 .isc_rx_maxsize = MJUM9BYTES, 480 .isc_rx_nsegments = 1, 481 .isc_rx_maxsegsize = MJUM9BYTES, 482 .isc_nfl = 1, 483 .isc_nrxqs = 1, 484 .isc_ntxqs = 1, 485 .isc_admin_intrcnt = 1, 486 .isc_vendor_info = em_vendor_info_array, 487 .isc_driver_version = em_driver_version, 488 .isc_driver = &em_if_driver, 489 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 490 491 .isc_nrxd_min = {EM_MIN_RXD}, 492 .isc_ntxd_min = {EM_MIN_TXD}, 493 .isc_nrxd_max = {EM_MAX_RXD}, 494 .isc_ntxd_max = {EM_MAX_TXD}, 495 .isc_nrxd_default = {EM_DEFAULT_RXD}, 496 .isc_ntxd_default = {EM_DEFAULT_TXD}, 497 }; 498 499 if_shared_ctx_t em_sctx = &em_sctx_init; 500 501 502 static struct if_shared_ctx igb_sctx_init = { 503 .isc_magic = IFLIB_MAGIC, 504 .isc_q_align = PAGE_SIZE, 505 .isc_tx_maxsize = EM_TSO_SIZE, 506 .isc_tx_maxsegsize = PAGE_SIZE, 507 .isc_rx_maxsize = MJUM9BYTES, 508 .isc_rx_nsegments = 1, 509 .isc_rx_maxsegsize = MJUM9BYTES, 510 .isc_nfl = 1, 511 .isc_nrxqs = 1, 512 .isc_ntxqs = 1, 513 .isc_admin_intrcnt = 1, 514 .isc_vendor_info = igb_vendor_info_array, 515 .isc_driver_version = em_driver_version, 516 .isc_driver = &em_if_driver, 517 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 518 519 .isc_nrxd_min = {EM_MIN_RXD}, 520 .isc_ntxd_min = {EM_MIN_TXD}, 521 .isc_nrxd_max = {IGB_MAX_RXD}, 522 .isc_ntxd_max = {IGB_MAX_TXD}, 523 .isc_nrxd_default = {EM_DEFAULT_RXD}, 524 .isc_ntxd_default = {EM_DEFAULT_TXD}, 525 }; 526 527 if_shared_ctx_t igb_sctx = &igb_sctx_init; 528 529 /***************************************************************** 530 * 531 * Dump Registers 532 * 533 ****************************************************************/ 534 #define IGB_REGS_LEN 739 535 536 static int em_get_regs(SYSCTL_HANDLER_ARGS) 537 { 538 struct adapter *adapter = (struct adapter *)arg1; 539 struct e1000_hw *hw = &adapter->hw; 540 struct sbuf *sb; 541 u32 *regs_buff; 542 int rc; 543 544 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 545 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 546 547 rc = sysctl_wire_old_buffer(req, 0); 548 MPASS(rc == 0); 549 if (rc != 0) { 550 free(regs_buff, M_DEVBUF); 551 return (rc); 552 } 553 554 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 555 MPASS(sb != NULL); 556 if (sb == NULL) { 557 free(regs_buff, M_DEVBUF); 558 return (ENOMEM); 559 } 560 561 /* General Registers */ 562 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 563 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 564 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 565 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 566 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 567 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 568 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 569 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 570 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 571 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 572 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 573 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 574 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 575 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 576 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 577 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 578 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 579 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 580 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 581 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 582 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 583 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 584 585 sbuf_printf(sb, "General Registers\n"); 586 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 587 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 588 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 589 590 sbuf_printf(sb, "Interrupt Registers\n"); 591 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 592 593 sbuf_printf(sb, "RX Registers\n"); 594 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 595 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 596 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 597 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 598 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 599 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 600 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 601 602 sbuf_printf(sb, "TX Registers\n"); 603 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 604 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 605 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 606 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 607 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 608 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 609 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 610 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 611 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 612 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 613 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 614 615 free(regs_buff, M_DEVBUF); 616 617 #ifdef DUMP_DESCS 618 { 619 if_softc_ctx_t scctx = adapter->shared; 620 struct rx_ring *rxr = &rx_que->rxr; 621 struct tx_ring *txr = &tx_que->txr; 622 int ntxd = scctx->isc_ntxd[0]; 623 int nrxd = scctx->isc_nrxd[0]; 624 int j; 625 626 for (j = 0; j < nrxd; j++) { 627 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 628 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 629 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 630 } 631 632 for (j = 0; j < min(ntxd, 256); j++) { 633 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 634 635 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 636 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 637 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 638 639 } 640 } 641 #endif 642 643 rc = sbuf_finish(sb); 644 sbuf_delete(sb); 645 return(rc); 646 } 647 648 static void * 649 em_register(device_t dev) 650 { 651 return (em_sctx); 652 } 653 654 static void * 655 igb_register(device_t dev) 656 { 657 return (igb_sctx); 658 } 659 660 static int 661 em_set_num_queues(if_ctx_t ctx) 662 { 663 struct adapter *adapter = iflib_get_softc(ctx); 664 int maxqueues; 665 666 /* Sanity check based on HW */ 667 switch (adapter->hw.mac.type) { 668 case e1000_82576: 669 case e1000_82580: 670 case e1000_i350: 671 case e1000_i354: 672 maxqueues = 8; 673 break; 674 case e1000_i210: 675 case e1000_82575: 676 maxqueues = 4; 677 break; 678 case e1000_i211: 679 case e1000_82574: 680 maxqueues = 2; 681 break; 682 default: 683 maxqueues = 1; 684 break; 685 } 686 687 return (maxqueues); 688 } 689 690 691 #define EM_CAPS \ 692 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 693 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | \ 694 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 695 696 #define IGB_CAPS \ 697 IFCAP_TSO4 | IFCAP_TXCSUM | IFCAP_LRO | IFCAP_RXCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL_MAGIC | \ 698 IFCAP_WOL_MCAST | IFCAP_WOL | IFCAP_VLAN_HWTSO | IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 699 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU | IFCAP_TXCSUM_IPV6 | IFCAP_HWCSUM_IPV6 | IFCAP_JUMBO_MTU; 700 701 /********************************************************************* 702 * Device initialization routine 703 * 704 * The attach entry point is called when the driver is being loaded. 705 * This routine identifies the type of hardware, allocates all resources 706 * and initializes the hardware. 707 * 708 * return 0 on success, positive on failure 709 *********************************************************************/ 710 711 static int 712 em_if_attach_pre(if_ctx_t ctx) 713 { 714 struct adapter *adapter; 715 if_softc_ctx_t scctx; 716 device_t dev; 717 struct e1000_hw *hw; 718 int error = 0; 719 720 INIT_DEBUGOUT("em_if_attach_pre begin"); 721 dev = iflib_get_dev(ctx); 722 adapter = iflib_get_softc(ctx); 723 724 if (resource_disabled("em", device_get_unit(dev))) { 725 device_printf(dev, "Disabled by device hint\n"); 726 return (ENXIO); 727 } 728 729 adapter->ctx = ctx; 730 adapter->dev = adapter->osdep.dev = dev; 731 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 732 adapter->media = iflib_get_media(ctx); 733 hw = &adapter->hw; 734 735 adapter->tx_process_limit = scctx->isc_ntxd[0]; 736 737 /* SYSCTL stuff */ 738 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 739 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 740 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 741 em_sysctl_nvm_info, "I", "NVM Information"); 742 743 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 744 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 745 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 746 em_sysctl_debug_info, "I", "Debug Information"); 747 748 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 749 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 750 OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 751 em_set_flowcntl, "I", "Flow Control"); 752 753 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 754 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 755 OID_AUTO, "reg_dump", CTLTYPE_STRING | CTLFLAG_RD, adapter, 0, 756 em_get_regs, "A", "Dump Registers"); 757 758 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 759 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 760 OID_AUTO, "rs_dump", CTLTYPE_INT | CTLFLAG_RW, adapter, 0, 761 em_get_rs, "I", "Dump RS indexes"); 762 763 /* Determine hardware and mac info */ 764 em_identify_hardware(ctx); 765 766 /* Set isc_msix_bar */ 767 scctx->isc_msix_bar = PCIR_BAR(EM_MSIX_BAR); 768 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 769 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments; 770 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 771 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 772 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 773 device_printf(dev, "attach_pre capping queues at %d\n", scctx->isc_ntxqsets_max); 774 775 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 776 777 778 if (adapter->hw.mac.type >= igb_mac_min) { 779 int try_second_bar; 780 781 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 782 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 783 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 784 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 785 scctx->isc_txrx = &igb_txrx; 786 scctx->isc_capenable = IGB_CAPS; 787 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | CSUM_IP6_TCP \ 788 | CSUM_IP6_UDP | CSUM_IP6_TCP; 789 if (adapter->hw.mac.type != e1000_82575) 790 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 791 792 /* 793 ** Some new devices, as with ixgbe, now may 794 ** use a different BAR, so we need to keep 795 ** track of which is used. 796 */ 797 try_second_bar = pci_read_config(dev, scctx->isc_msix_bar, 4); 798 if (try_second_bar == 0) 799 scctx->isc_msix_bar += 4; 800 801 } else if (adapter->hw.mac.type >= em_mac_min) { 802 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 803 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 804 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 805 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 806 scctx->isc_txrx = &em_txrx; 807 scctx->isc_capenable = EM_CAPS; 808 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 809 } else { 810 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 811 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 812 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 813 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 814 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 815 scctx->isc_txrx = &lem_txrx; 816 scctx->isc_capenable = EM_CAPS; 817 if (adapter->hw.mac.type < e1000_82543) 818 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 819 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 820 scctx->isc_msix_bar = 0; 821 } 822 823 /* Setup PCI resources */ 824 if (em_allocate_pci_resources(ctx)) { 825 device_printf(dev, "Allocation of PCI resources failed\n"); 826 error = ENXIO; 827 goto err_pci; 828 } 829 830 /* 831 ** For ICH8 and family we need to 832 ** map the flash memory, and this 833 ** must happen after the MAC is 834 ** identified 835 */ 836 if ((hw->mac.type == e1000_ich8lan) || 837 (hw->mac.type == e1000_ich9lan) || 838 (hw->mac.type == e1000_ich10lan) || 839 (hw->mac.type == e1000_pchlan) || 840 (hw->mac.type == e1000_pch2lan) || 841 (hw->mac.type == e1000_pch_lpt)) { 842 int rid = EM_BAR_TYPE_FLASH; 843 adapter->flash = bus_alloc_resource_any(dev, 844 SYS_RES_MEMORY, &rid, RF_ACTIVE); 845 if (adapter->flash == NULL) { 846 device_printf(dev, "Mapping of Flash failed\n"); 847 error = ENXIO; 848 goto err_pci; 849 } 850 /* This is used in the shared code */ 851 hw->flash_address = (u8 *)adapter->flash; 852 adapter->osdep.flash_bus_space_tag = 853 rman_get_bustag(adapter->flash); 854 adapter->osdep.flash_bus_space_handle = 855 rman_get_bushandle(adapter->flash); 856 } 857 /* 858 ** In the new SPT device flash is not a 859 ** separate BAR, rather it is also in BAR0, 860 ** so use the same tag and an offset handle for the 861 ** FLASH read/write macros in the shared code. 862 */ 863 else if (hw->mac.type == e1000_pch_spt) { 864 adapter->osdep.flash_bus_space_tag = 865 adapter->osdep.mem_bus_space_tag; 866 adapter->osdep.flash_bus_space_handle = 867 adapter->osdep.mem_bus_space_handle 868 + E1000_FLASH_BASE_ADDR; 869 } 870 871 /* Do Shared Code initialization */ 872 error = e1000_setup_init_funcs(hw, TRUE); 873 if (error) { 874 device_printf(dev, "Setup of Shared code failed, error %d\n", 875 error); 876 error = ENXIO; 877 goto err_pci; 878 } 879 880 em_setup_msix(ctx); 881 e1000_get_bus_info(hw); 882 883 /* Set up some sysctls for the tunable interrupt delays */ 884 em_add_int_delay_sysctl(adapter, "rx_int_delay", 885 "receive interrupt delay in usecs", &adapter->rx_int_delay, 886 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 887 em_add_int_delay_sysctl(adapter, "tx_int_delay", 888 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 889 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 890 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 891 "receive interrupt delay limit in usecs", 892 &adapter->rx_abs_int_delay, 893 E1000_REGISTER(hw, E1000_RADV), 894 em_rx_abs_int_delay_dflt); 895 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 896 "transmit interrupt delay limit in usecs", 897 &adapter->tx_abs_int_delay, 898 E1000_REGISTER(hw, E1000_TADV), 899 em_tx_abs_int_delay_dflt); 900 em_add_int_delay_sysctl(adapter, "itr", 901 "interrupt delay limit in usecs/4", 902 &adapter->tx_itr, 903 E1000_REGISTER(hw, E1000_ITR), 904 DEFAULT_ITR); 905 906 hw->mac.autoneg = DO_AUTO_NEG; 907 hw->phy.autoneg_wait_to_complete = FALSE; 908 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 909 910 if (adapter->hw.mac.type < em_mac_min) { 911 e1000_init_script_state_82541(&adapter->hw, TRUE); 912 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 913 } 914 /* Copper options */ 915 if (hw->phy.media_type == e1000_media_type_copper) { 916 hw->phy.mdix = AUTO_ALL_MODES; 917 hw->phy.disable_polarity_correction = FALSE; 918 hw->phy.ms_type = EM_MASTER_SLAVE; 919 } 920 921 /* 922 * Set the frame limits assuming 923 * standard ethernet sized frames. 924 */ 925 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 926 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 927 928 /* 929 * This controls when hardware reports transmit completion 930 * status. 931 */ 932 hw->mac.report_tx_early = 1; 933 934 /* Allocate multicast array memory. */ 935 adapter->mta = malloc(sizeof(u8) * ETH_ADDR_LEN * 936 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 937 if (adapter->mta == NULL) { 938 device_printf(dev, "Can not allocate multicast setup array\n"); 939 error = ENOMEM; 940 goto err_late; 941 } 942 943 /* Check SOL/IDER usage */ 944 if (e1000_check_reset_block(hw)) 945 device_printf(dev, "PHY reset is blocked" 946 " due to SOL/IDER session.\n"); 947 948 /* Sysctl for setting Energy Efficient Ethernet */ 949 hw->dev_spec.ich8lan.eee_disable = eee_setting; 950 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 951 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 952 OID_AUTO, "eee_control", CTLTYPE_INT|CTLFLAG_RW, 953 adapter, 0, em_sysctl_eee, "I", 954 "Disable Energy Efficient Ethernet"); 955 956 /* 957 ** Start from a known state, this is 958 ** important in reading the nvm and 959 ** mac from that. 960 */ 961 e1000_reset_hw(hw); 962 963 /* Make sure we have a good EEPROM before we read from it */ 964 if (e1000_validate_nvm_checksum(hw) < 0) { 965 /* 966 ** Some PCI-E parts fail the first check due to 967 ** the link being in sleep state, call it again, 968 ** if it fails a second time its a real issue. 969 */ 970 if (e1000_validate_nvm_checksum(hw) < 0) { 971 device_printf(dev, 972 "The EEPROM Checksum Is Not Valid\n"); 973 error = EIO; 974 goto err_late; 975 } 976 } 977 978 /* Copy the permanent MAC address out of the EEPROM */ 979 if (e1000_read_mac_addr(hw) < 0) { 980 device_printf(dev, "EEPROM read error while reading MAC" 981 " address\n"); 982 error = EIO; 983 goto err_late; 984 } 985 986 if (!em_is_valid_ether_addr(hw->mac.addr)) { 987 device_printf(dev, "Invalid MAC address\n"); 988 error = EIO; 989 goto err_late; 990 } 991 992 /* Disable ULP support */ 993 e1000_disable_ulp_lpt_lp(hw, TRUE); 994 995 /* 996 * Get Wake-on-Lan and Management info for later use 997 */ 998 em_get_wakeup(ctx); 999 1000 iflib_set_mac(ctx, hw->mac.addr); 1001 1002 return (0); 1003 1004 err_late: 1005 em_release_hw_control(adapter); 1006 err_pci: 1007 em_free_pci_resources(ctx); 1008 free(adapter->mta, M_DEVBUF); 1009 1010 return (error); 1011 } 1012 1013 static int 1014 em_if_attach_post(if_ctx_t ctx) 1015 { 1016 struct adapter *adapter = iflib_get_softc(ctx); 1017 struct e1000_hw *hw = &adapter->hw; 1018 int error = 0; 1019 1020 /* Setup OS specific network interface */ 1021 error = em_setup_interface(ctx); 1022 if (error != 0) { 1023 goto err_late; 1024 } 1025 1026 em_reset(ctx); 1027 1028 /* Initialize statistics */ 1029 em_update_stats_counters(adapter); 1030 hw->mac.get_link_status = 1; 1031 em_if_update_admin_status(ctx); 1032 em_add_hw_stats(adapter); 1033 1034 /* Non-AMT based hardware can now take control from firmware */ 1035 if (adapter->has_manage && !adapter->has_amt) 1036 em_get_hw_control(adapter); 1037 1038 INIT_DEBUGOUT("em_if_attach_post: end"); 1039 1040 return (error); 1041 1042 err_late: 1043 em_release_hw_control(adapter); 1044 em_free_pci_resources(ctx); 1045 em_if_queues_free(ctx); 1046 free(adapter->mta, M_DEVBUF); 1047 1048 return (error); 1049 } 1050 1051 /********************************************************************* 1052 * Device removal routine 1053 * 1054 * The detach entry point is called when the driver is being removed. 1055 * This routine stops the adapter and deallocates all the resources 1056 * that were allocated for driver operation. 1057 * 1058 * return 0 on success, positive on failure 1059 *********************************************************************/ 1060 1061 static int 1062 em_if_detach(if_ctx_t ctx) 1063 { 1064 struct adapter *adapter = iflib_get_softc(ctx); 1065 1066 INIT_DEBUGOUT("em_detach: begin"); 1067 1068 e1000_phy_hw_reset(&adapter->hw); 1069 1070 em_release_manageability(adapter); 1071 em_release_hw_control(adapter); 1072 em_free_pci_resources(ctx); 1073 1074 return (0); 1075 } 1076 1077 /********************************************************************* 1078 * 1079 * Shutdown entry point 1080 * 1081 **********************************************************************/ 1082 1083 static int 1084 em_if_shutdown(if_ctx_t ctx) 1085 { 1086 return em_if_suspend(ctx); 1087 } 1088 1089 /* 1090 * Suspend/resume device methods. 1091 */ 1092 static int 1093 em_if_suspend(if_ctx_t ctx) 1094 { 1095 struct adapter *adapter = iflib_get_softc(ctx); 1096 1097 em_release_manageability(adapter); 1098 em_release_hw_control(adapter); 1099 em_enable_wakeup(ctx); 1100 return (0); 1101 } 1102 1103 static int 1104 em_if_resume(if_ctx_t ctx) 1105 { 1106 struct adapter *adapter = iflib_get_softc(ctx); 1107 1108 if (adapter->hw.mac.type == e1000_pch2lan) 1109 e1000_resume_workarounds_pchlan(&adapter->hw); 1110 em_if_init(ctx); 1111 em_init_manageability(adapter); 1112 1113 return(0); 1114 } 1115 1116 static int 1117 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1118 { 1119 int max_frame_size; 1120 struct adapter *adapter = iflib_get_softc(ctx); 1121 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1122 1123 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1124 1125 switch (adapter->hw.mac.type) { 1126 case e1000_82571: 1127 case e1000_82572: 1128 case e1000_ich9lan: 1129 case e1000_ich10lan: 1130 case e1000_pch2lan: 1131 case e1000_pch_lpt: 1132 case e1000_pch_spt: 1133 case e1000_82574: 1134 case e1000_82583: 1135 case e1000_80003es2lan: 1136 /* 9K Jumbo Frame size */ 1137 max_frame_size = 9234; 1138 break; 1139 case e1000_pchlan: 1140 max_frame_size = 4096; 1141 break; 1142 case e1000_82542: 1143 case e1000_ich8lan: 1144 /* Adapters that do not support jumbo frames */ 1145 max_frame_size = ETHER_MAX_LEN; 1146 break; 1147 default: 1148 if (adapter->hw.mac.type >= igb_mac_min) 1149 max_frame_size = 9234; 1150 else /* lem */ 1151 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1152 } 1153 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1154 return (EINVAL); 1155 } 1156 1157 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1158 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1159 return (0); 1160 } 1161 1162 /********************************************************************* 1163 * Init entry point 1164 * 1165 * This routine is used in two ways. It is used by the stack as 1166 * init entry point in network interface structure. It is also used 1167 * by the driver as a hw/sw initialization routine to get to a 1168 * consistent state. 1169 * 1170 * return 0 on success, positive on failure 1171 **********************************************************************/ 1172 1173 static void 1174 em_if_init(if_ctx_t ctx) 1175 { 1176 struct adapter *adapter = iflib_get_softc(ctx); 1177 struct ifnet *ifp = iflib_get_ifp(ctx); 1178 struct em_tx_queue *tx_que; 1179 int i; 1180 INIT_DEBUGOUT("em_if_init: begin"); 1181 1182 /* Get the latest mac address, User can use a LAA */ 1183 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1184 ETHER_ADDR_LEN); 1185 1186 /* Put the address into the Receive Address Array */ 1187 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1188 1189 /* 1190 * With the 82571 adapter, RAR[0] may be overwritten 1191 * when the other port is reset, we make a duplicate 1192 * in RAR[14] for that eventuality, this assures 1193 * the interface continues to function. 1194 */ 1195 if (adapter->hw.mac.type == e1000_82571) { 1196 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1197 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1198 E1000_RAR_ENTRIES - 1); 1199 } 1200 1201 1202 /* Initialize the hardware */ 1203 em_reset(ctx); 1204 em_if_update_admin_status(ctx); 1205 1206 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1207 struct tx_ring *txr = &tx_que->txr; 1208 1209 txr->tx_rs_cidx = txr->tx_rs_pidx = txr->tx_cidx_processed = 0; 1210 } 1211 1212 /* Setup VLAN support, basic and offload if available */ 1213 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1214 1215 /* Clear bad data from Rx FIFOs */ 1216 if (adapter->hw.mac.type >= igb_mac_min) 1217 e1000_rx_fifo_flush_82575(&adapter->hw); 1218 1219 /* Configure for OS presence */ 1220 em_init_manageability(adapter); 1221 1222 /* Prepare transmit descriptors and buffers */ 1223 em_initialize_transmit_unit(ctx); 1224 1225 /* Setup Multicast table */ 1226 em_if_multi_set(ctx); 1227 1228 /* 1229 * Figure out the desired mbuf 1230 * pool for doing jumbos 1231 */ 1232 if (adapter->hw.mac.max_frame_size <= 2048) 1233 adapter->rx_mbuf_sz = MCLBYTES; 1234 #ifndef CONTIGMALLOC_WORKS 1235 else 1236 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1237 #else 1238 else if (adapter->hw.mac.max_frame_size <= 4096) 1239 adapter->rx_mbuf_sz = MJUMPAGESIZE; 1240 else 1241 adapter->rx_mbuf_sz = MJUM9BYTES; 1242 #endif 1243 em_initialize_receive_unit(ctx); 1244 1245 /* Use real VLAN Filter support? */ 1246 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1247 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1248 /* Use real VLAN Filter support */ 1249 em_setup_vlan_hw_support(adapter); 1250 else { 1251 u32 ctrl; 1252 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1253 ctrl |= E1000_CTRL_VME; 1254 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1255 } 1256 } 1257 1258 /* Don't lose promiscuous settings */ 1259 em_if_set_promisc(ctx, IFF_PROMISC); 1260 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1261 1262 /* MSI/X configuration for 82574 */ 1263 if (adapter->hw.mac.type == e1000_82574) { 1264 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1265 1266 tmp |= E1000_CTRL_EXT_PBA_CLR; 1267 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1268 /* Set the IVAR - interrupt vector routing. */ 1269 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1270 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1271 igb_configure_queues(adapter); 1272 1273 /* this clears any pending interrupts */ 1274 E1000_READ_REG(&adapter->hw, E1000_ICR); 1275 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1276 1277 /* AMT based hardware can now take control from firmware */ 1278 if (adapter->has_manage && adapter->has_amt) 1279 em_get_hw_control(adapter); 1280 1281 /* Set Energy Efficient Ethernet */ 1282 if (adapter->hw.mac.type >= igb_mac_min && 1283 adapter->hw.phy.media_type == e1000_media_type_copper) { 1284 if (adapter->hw.mac.type == e1000_i354) 1285 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1286 else 1287 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1288 } 1289 } 1290 1291 /********************************************************************* 1292 * 1293 * Fast Legacy/MSI Combined Interrupt Service routine 1294 * 1295 *********************************************************************/ 1296 int 1297 em_intr(void *arg) 1298 { 1299 struct adapter *adapter = arg; 1300 if_ctx_t ctx = adapter->ctx; 1301 u32 reg_icr; 1302 1303 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1304 1305 if (adapter->intr_type != IFLIB_INTR_LEGACY) 1306 goto skip_stray; 1307 /* Hot eject? */ 1308 if (reg_icr == 0xffffffff) 1309 return FILTER_STRAY; 1310 1311 /* Definitely not our interrupt. */ 1312 if (reg_icr == 0x0) 1313 return FILTER_STRAY; 1314 1315 /* 1316 * Starting with the 82571 chip, bit 31 should be used to 1317 * determine whether the interrupt belongs to us. 1318 */ 1319 if (adapter->hw.mac.type >= e1000_82571 && 1320 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1321 return FILTER_STRAY; 1322 1323 skip_stray: 1324 /* Link status change */ 1325 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1326 adapter->hw.mac.get_link_status = 1; 1327 iflib_admin_intr_deferred(ctx); 1328 } 1329 1330 if (reg_icr & E1000_ICR_RXO) 1331 adapter->rx_overruns++; 1332 1333 return (FILTER_SCHEDULE_THREAD); 1334 } 1335 1336 static void 1337 igb_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1338 { 1339 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1340 } 1341 1342 static void 1343 em_rx_enable_queue(struct adapter *adapter, struct em_rx_queue *rxq) 1344 { 1345 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1346 } 1347 1348 static void 1349 igb_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1350 { 1351 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1352 } 1353 1354 static void 1355 em_tx_enable_queue(struct adapter *adapter, struct em_tx_queue *txq) 1356 { 1357 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1358 } 1359 1360 static int 1361 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1362 { 1363 struct adapter *adapter = iflib_get_softc(ctx); 1364 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1365 1366 if (adapter->hw.mac.type >= igb_mac_min) 1367 igb_rx_enable_queue(adapter, rxq); 1368 else 1369 em_rx_enable_queue(adapter, rxq); 1370 return (0); 1371 } 1372 1373 static int 1374 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1375 { 1376 struct adapter *adapter = iflib_get_softc(ctx); 1377 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1378 1379 if (adapter->hw.mac.type >= igb_mac_min) 1380 igb_tx_enable_queue(adapter, txq); 1381 else 1382 em_tx_enable_queue(adapter, txq); 1383 return (0); 1384 } 1385 1386 /********************************************************************* 1387 * 1388 * MSIX RX Interrupt Service routine 1389 * 1390 **********************************************************************/ 1391 static int 1392 em_msix_que(void *arg) 1393 { 1394 struct em_rx_queue *que = arg; 1395 1396 ++que->irqs; 1397 1398 return (FILTER_SCHEDULE_THREAD); 1399 } 1400 1401 /********************************************************************* 1402 * 1403 * MSIX Link Fast Interrupt Service routine 1404 * 1405 **********************************************************************/ 1406 static int 1407 em_msix_link(void *arg) 1408 { 1409 struct adapter *adapter = arg; 1410 u32 reg_icr; 1411 1412 ++adapter->link_irq; 1413 MPASS(adapter->hw.back != NULL); 1414 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1415 1416 if (reg_icr & E1000_ICR_RXO) 1417 adapter->rx_overruns++; 1418 1419 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1420 em_handle_link(adapter->ctx); 1421 } else { 1422 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 1423 EM_MSIX_LINK | E1000_IMS_LSC); 1424 if (adapter->hw.mac.type >= igb_mac_min) 1425 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1426 } 1427 1428 /* 1429 * Because we must read the ICR for this interrupt 1430 * it may clear other causes using autoclear, for 1431 * this reason we simply create a soft interrupt 1432 * for all these vectors. 1433 */ 1434 if (reg_icr && adapter->hw.mac.type < igb_mac_min) { 1435 E1000_WRITE_REG(&adapter->hw, 1436 E1000_ICS, adapter->ims); 1437 } 1438 1439 return (FILTER_HANDLED); 1440 } 1441 1442 static void 1443 em_handle_link(void *context) 1444 { 1445 if_ctx_t ctx = context; 1446 struct adapter *adapter = iflib_get_softc(ctx); 1447 1448 adapter->hw.mac.get_link_status = 1; 1449 iflib_admin_intr_deferred(ctx); 1450 } 1451 1452 1453 /********************************************************************* 1454 * 1455 * Media Ioctl callback 1456 * 1457 * This routine is called whenever the user queries the status of 1458 * the interface using ifconfig. 1459 * 1460 **********************************************************************/ 1461 static void 1462 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1463 { 1464 struct adapter *adapter = iflib_get_softc(ctx); 1465 u_char fiber_type = IFM_1000_SX; 1466 1467 INIT_DEBUGOUT("em_if_media_status: begin"); 1468 1469 iflib_admin_intr_deferred(ctx); 1470 1471 ifmr->ifm_status = IFM_AVALID; 1472 ifmr->ifm_active = IFM_ETHER; 1473 1474 if (!adapter->link_active) { 1475 return; 1476 } 1477 1478 ifmr->ifm_status |= IFM_ACTIVE; 1479 1480 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1481 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1482 if (adapter->hw.mac.type == e1000_82545) 1483 fiber_type = IFM_1000_LX; 1484 ifmr->ifm_active |= fiber_type | IFM_FDX; 1485 } else { 1486 switch (adapter->link_speed) { 1487 case 10: 1488 ifmr->ifm_active |= IFM_10_T; 1489 break; 1490 case 100: 1491 ifmr->ifm_active |= IFM_100_TX; 1492 break; 1493 case 1000: 1494 ifmr->ifm_active |= IFM_1000_T; 1495 break; 1496 } 1497 if (adapter->link_duplex == FULL_DUPLEX) 1498 ifmr->ifm_active |= IFM_FDX; 1499 else 1500 ifmr->ifm_active |= IFM_HDX; 1501 } 1502 } 1503 1504 /********************************************************************* 1505 * 1506 * Media Ioctl callback 1507 * 1508 * This routine is called when the user changes speed/duplex using 1509 * media/mediopt option with ifconfig. 1510 * 1511 **********************************************************************/ 1512 static int 1513 em_if_media_change(if_ctx_t ctx) 1514 { 1515 struct adapter *adapter = iflib_get_softc(ctx); 1516 struct ifmedia *ifm = iflib_get_media(ctx); 1517 1518 INIT_DEBUGOUT("em_if_media_change: begin"); 1519 1520 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1521 return (EINVAL); 1522 1523 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1524 case IFM_AUTO: 1525 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1526 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1527 break; 1528 case IFM_1000_LX: 1529 case IFM_1000_SX: 1530 case IFM_1000_T: 1531 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1532 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1533 break; 1534 case IFM_100_TX: 1535 adapter->hw.mac.autoneg = FALSE; 1536 adapter->hw.phy.autoneg_advertised = 0; 1537 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1538 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1539 else 1540 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1541 break; 1542 case IFM_10_T: 1543 adapter->hw.mac.autoneg = FALSE; 1544 adapter->hw.phy.autoneg_advertised = 0; 1545 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1546 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1547 else 1548 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1549 break; 1550 default: 1551 device_printf(adapter->dev, "Unsupported media type\n"); 1552 } 1553 1554 em_if_init(ctx); 1555 1556 return (0); 1557 } 1558 1559 static int 1560 em_if_set_promisc(if_ctx_t ctx, int flags) 1561 { 1562 struct adapter *adapter = iflib_get_softc(ctx); 1563 u32 reg_rctl; 1564 1565 em_disable_promisc(ctx); 1566 1567 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1568 1569 if (flags & IFF_PROMISC) { 1570 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1571 /* Turn this on if you want to see bad packets */ 1572 if (em_debug_sbp) 1573 reg_rctl |= E1000_RCTL_SBP; 1574 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1575 } else if (flags & IFF_ALLMULTI) { 1576 reg_rctl |= E1000_RCTL_MPE; 1577 reg_rctl &= ~E1000_RCTL_UPE; 1578 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1579 } 1580 return (0); 1581 } 1582 1583 static void 1584 em_disable_promisc(if_ctx_t ctx) 1585 { 1586 struct adapter *adapter = iflib_get_softc(ctx); 1587 struct ifnet *ifp = iflib_get_ifp(ctx); 1588 u32 reg_rctl; 1589 int mcnt = 0; 1590 1591 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1592 reg_rctl &= (~E1000_RCTL_UPE); 1593 if (if_getflags(ifp) & IFF_ALLMULTI) 1594 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1595 else 1596 mcnt = if_multiaddr_count(ifp, MAX_NUM_MULTICAST_ADDRESSES); 1597 /* Don't disable if in MAX groups */ 1598 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1599 reg_rctl &= (~E1000_RCTL_MPE); 1600 reg_rctl &= (~E1000_RCTL_SBP); 1601 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1602 } 1603 1604 1605 /********************************************************************* 1606 * Multicast Update 1607 * 1608 * This routine is called whenever multicast address list is updated. 1609 * 1610 **********************************************************************/ 1611 1612 static void 1613 em_if_multi_set(if_ctx_t ctx) 1614 { 1615 struct adapter *adapter = iflib_get_softc(ctx); 1616 struct ifnet *ifp = iflib_get_ifp(ctx); 1617 u32 reg_rctl = 0; 1618 u8 *mta; /* Multicast array memory */ 1619 int mcnt = 0; 1620 1621 IOCTL_DEBUGOUT("em_set_multi: begin"); 1622 1623 mta = adapter->mta; 1624 bzero(mta, sizeof(u8) * ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1625 1626 if (adapter->hw.mac.type == e1000_82542 && 1627 adapter->hw.revision_id == E1000_REVISION_2) { 1628 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1629 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1630 e1000_pci_clear_mwi(&adapter->hw); 1631 reg_rctl |= E1000_RCTL_RST; 1632 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1633 msec_delay(5); 1634 } 1635 1636 if_multiaddr_array(ifp, mta, &mcnt, MAX_NUM_MULTICAST_ADDRESSES); 1637 1638 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1639 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1640 reg_rctl |= E1000_RCTL_MPE; 1641 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1642 } else 1643 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1644 1645 if (adapter->hw.mac.type == e1000_82542 && 1646 adapter->hw.revision_id == E1000_REVISION_2) { 1647 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1648 reg_rctl &= ~E1000_RCTL_RST; 1649 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1650 msec_delay(5); 1651 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1652 e1000_pci_set_mwi(&adapter->hw); 1653 } 1654 } 1655 1656 1657 /********************************************************************* 1658 * Timer routine 1659 * 1660 * This routine checks for link status and updates statistics. 1661 * 1662 **********************************************************************/ 1663 1664 static void 1665 em_if_timer(if_ctx_t ctx, uint16_t qid) 1666 { 1667 struct adapter *adapter = iflib_get_softc(ctx); 1668 struct em_rx_queue *que; 1669 int i; 1670 int trigger = 0; 1671 1672 if (qid != 0) 1673 return; 1674 1675 iflib_admin_intr_deferred(ctx); 1676 /* Reset LAA into RAR[0] on 82571 */ 1677 if ((adapter->hw.mac.type == e1000_82571) && 1678 e1000_get_laa_state_82571(&adapter->hw)) 1679 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1680 1681 if (adapter->hw.mac.type < em_mac_min) 1682 lem_smartspeed(adapter); 1683 1684 /* Mask to use in the irq trigger */ 1685 if (adapter->intr_type == IFLIB_INTR_MSIX) { 1686 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) 1687 trigger |= que->eims; 1688 } else { 1689 trigger = E1000_ICS_RXDMT0; 1690 } 1691 } 1692 1693 1694 static void 1695 em_if_update_admin_status(if_ctx_t ctx) 1696 { 1697 struct adapter *adapter = iflib_get_softc(ctx); 1698 struct e1000_hw *hw = &adapter->hw; 1699 struct ifnet *ifp = iflib_get_ifp(ctx); 1700 device_t dev = iflib_get_dev(ctx); 1701 u32 link_check, thstat, ctrl; 1702 1703 link_check = thstat = ctrl = 0; 1704 /* Get the cached link value or read phy for real */ 1705 switch (hw->phy.media_type) { 1706 case e1000_media_type_copper: 1707 if (hw->mac.get_link_status) { 1708 if (hw->mac.type == e1000_pch_spt) 1709 msec_delay(50); 1710 /* Do the work to read phy */ 1711 e1000_check_for_link(hw); 1712 link_check = !hw->mac.get_link_status; 1713 if (link_check) /* ESB2 fix */ 1714 e1000_cfg_on_link_up(hw); 1715 } else { 1716 link_check = TRUE; 1717 } 1718 break; 1719 case e1000_media_type_fiber: 1720 e1000_check_for_link(hw); 1721 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1722 E1000_STATUS_LU); 1723 break; 1724 case e1000_media_type_internal_serdes: 1725 e1000_check_for_link(hw); 1726 link_check = adapter->hw.mac.serdes_has_link; 1727 break; 1728 /* VF device is type_unknown */ 1729 case e1000_media_type_unknown: 1730 e1000_check_for_link(hw); 1731 link_check = !hw->mac.get_link_status; 1732 /* FALLTHROUGH */ 1733 default: 1734 break; 1735 } 1736 1737 /* Check for thermal downshift or shutdown */ 1738 if (hw->mac.type == e1000_i350) { 1739 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1740 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1741 } 1742 1743 /* Now check for a transition */ 1744 if (link_check && (adapter->link_active == 0)) { 1745 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1746 &adapter->link_duplex); 1747 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1748 if ((adapter->link_speed != SPEED_1000) && 1749 ((hw->mac.type == e1000_82571) || 1750 (hw->mac.type == e1000_82572))) { 1751 int tarc0; 1752 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1753 tarc0 &= ~TARC_SPEED_MODE_BIT; 1754 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1755 } 1756 if (bootverbose) 1757 device_printf(dev, "Link is up %d Mbps %s\n", 1758 adapter->link_speed, 1759 ((adapter->link_duplex == FULL_DUPLEX) ? 1760 "Full Duplex" : "Half Duplex")); 1761 adapter->link_active = 1; 1762 adapter->smartspeed = 0; 1763 if_setbaudrate(ifp, adapter->link_speed * 1000000); 1764 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) && 1765 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1766 device_printf(dev, "Link: thermal downshift\n"); 1767 /* Delay Link Up for Phy update */ 1768 if (((hw->mac.type == e1000_i210) || 1769 (hw->mac.type == e1000_i211)) && 1770 (hw->phy.id == I210_I_PHY_ID)) 1771 msec_delay(I210_LINK_DELAY); 1772 /* Reset if the media type changed. */ 1773 if ((hw->dev_spec._82575.media_changed) && 1774 (adapter->hw.mac.type >= igb_mac_min)) { 1775 hw->dev_spec._82575.media_changed = false; 1776 adapter->flags |= IGB_MEDIA_RESET; 1777 em_reset(ctx); 1778 } 1779 iflib_link_state_change(ctx, LINK_STATE_UP, ifp->if_baudrate); 1780 printf("Link state changed to up\n"); 1781 } else if (!link_check && (adapter->link_active == 1)) { 1782 if_setbaudrate(ifp, 0); 1783 adapter->link_speed = 0; 1784 adapter->link_duplex = 0; 1785 if (bootverbose) 1786 device_printf(dev, "Link is Down\n"); 1787 adapter->link_active = 0; 1788 iflib_link_state_change(ctx, LINK_STATE_DOWN, ifp->if_baudrate); 1789 printf("link state changed to down\n"); 1790 } 1791 em_update_stats_counters(adapter); 1792 1793 E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | E1000_IMS_LSC); 1794 } 1795 1796 /********************************************************************* 1797 * 1798 * This routine disables all traffic on the adapter by issuing a 1799 * global reset on the MAC and deallocates TX/RX buffers. 1800 * 1801 * This routine should always be called with BOTH the CORE 1802 * and TX locks. 1803 **********************************************************************/ 1804 1805 static void 1806 em_if_stop(if_ctx_t ctx) 1807 { 1808 struct adapter *adapter = iflib_get_softc(ctx); 1809 1810 INIT_DEBUGOUT("em_stop: begin"); 1811 1812 e1000_reset_hw(&adapter->hw); 1813 if (adapter->hw.mac.type >= e1000_82544) 1814 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1815 1816 e1000_led_off(&adapter->hw); 1817 e1000_cleanup_led(&adapter->hw); 1818 } 1819 1820 1821 /********************************************************************* 1822 * 1823 * Determine hardware revision. 1824 * 1825 **********************************************************************/ 1826 static void 1827 em_identify_hardware(if_ctx_t ctx) 1828 { 1829 device_t dev = iflib_get_dev(ctx); 1830 struct adapter *adapter = iflib_get_softc(ctx); 1831 1832 /* Make sure our PCI config space has the necessary stuff set */ 1833 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1834 1835 /* Save off the information about this board */ 1836 adapter->hw.vendor_id = pci_get_vendor(dev); 1837 adapter->hw.device_id = pci_get_device(dev); 1838 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1839 adapter->hw.subsystem_vendor_id = 1840 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1841 adapter->hw.subsystem_device_id = 1842 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1843 1844 /* Do Shared Code Init and Setup */ 1845 if (e1000_set_mac_type(&adapter->hw)) { 1846 device_printf(dev, "Setup init failure\n"); 1847 return; 1848 } 1849 } 1850 1851 static int 1852 em_allocate_pci_resources(if_ctx_t ctx) 1853 { 1854 struct adapter *adapter = iflib_get_softc(ctx); 1855 device_t dev = iflib_get_dev(ctx); 1856 int rid, val; 1857 1858 rid = PCIR_BAR(0); 1859 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1860 &rid, RF_ACTIVE); 1861 if (adapter->memory == NULL) { 1862 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1863 return (ENXIO); 1864 } 1865 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1866 adapter->osdep.mem_bus_space_handle = 1867 rman_get_bushandle(adapter->memory); 1868 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1869 1870 /* Only older adapters use IO mapping */ 1871 if (adapter->hw.mac.type < em_mac_min && 1872 adapter->hw.mac.type > e1000_82543) { 1873 /* Figure our where our IO BAR is ? */ 1874 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1875 val = pci_read_config(dev, rid, 4); 1876 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1877 adapter->io_rid = rid; 1878 break; 1879 } 1880 rid += 4; 1881 /* check for 64bit BAR */ 1882 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1883 rid += 4; 1884 } 1885 if (rid >= PCIR_CIS) { 1886 device_printf(dev, "Unable to locate IO BAR\n"); 1887 return (ENXIO); 1888 } 1889 adapter->ioport = bus_alloc_resource_any(dev, 1890 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 1891 if (adapter->ioport == NULL) { 1892 device_printf(dev, "Unable to allocate bus resource: " 1893 "ioport\n"); 1894 return (ENXIO); 1895 } 1896 adapter->hw.io_base = 0; 1897 adapter->osdep.io_bus_space_tag = 1898 rman_get_bustag(adapter->ioport); 1899 adapter->osdep.io_bus_space_handle = 1900 rman_get_bushandle(adapter->ioport); 1901 } 1902 1903 adapter->hw.back = &adapter->osdep; 1904 1905 return (0); 1906 } 1907 1908 /********************************************************************* 1909 * 1910 * Setup the MSIX Interrupt handlers 1911 * 1912 **********************************************************************/ 1913 static int 1914 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 1915 { 1916 struct adapter *adapter = iflib_get_softc(ctx); 1917 struct em_rx_queue *rx_que = adapter->rx_queues; 1918 struct em_tx_queue *tx_que = adapter->tx_queues; 1919 int error, rid, i, vector = 0, rx_vectors; 1920 char buf[16]; 1921 1922 /* First set up ring resources */ 1923 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1924 rid = vector + 1; 1925 snprintf(buf, sizeof(buf), "rxq%d", i); 1926 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 1927 if (error) { 1928 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1929 adapter->rx_num_queues = i + 1; 1930 goto fail; 1931 } 1932 1933 rx_que->msix = vector; 1934 1935 /* 1936 * Set the bit to enable interrupt 1937 * in E1000_IMS -- bits 20 and 21 1938 * are for RX0 and RX1, note this has 1939 * NOTHING to do with the MSIX vector 1940 */ 1941 if (adapter->hw.mac.type == e1000_82574) { 1942 rx_que->eims = 1 << (20 + i); 1943 adapter->ims |= rx_que->eims; 1944 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 1945 } else if (adapter->hw.mac.type == e1000_82575) 1946 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 1947 else 1948 rx_que->eims = 1 << vector; 1949 } 1950 rx_vectors = vector; 1951 1952 vector = 0; 1953 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1954 rid = vector + 1; 1955 snprintf(buf, sizeof(buf), "txq%d", i); 1956 tx_que = &adapter->tx_queues[i]; 1957 iflib_softirq_alloc_generic(ctx, 1958 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1959 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1960 1961 tx_que->msix = (vector % adapter->tx_num_queues); 1962 1963 /* 1964 * Set the bit to enable interrupt 1965 * in E1000_IMS -- bits 22 and 23 1966 * are for TX0 and TX1, note this has 1967 * NOTHING to do with the MSIX vector 1968 */ 1969 if (adapter->hw.mac.type == e1000_82574) { 1970 tx_que->eims = 1 << (22 + i); 1971 adapter->ims |= tx_que->eims; 1972 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 1973 } else if (adapter->hw.mac.type == e1000_82575) { 1974 tx_que->eims = E1000_EICR_TX_QUEUE0 << (i % adapter->tx_num_queues); 1975 } else { 1976 tx_que->eims = 1 << (i % adapter->tx_num_queues); 1977 } 1978 } 1979 1980 /* Link interrupt */ 1981 rid = rx_vectors + 1; 1982 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 1983 1984 if (error) { 1985 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1986 goto fail; 1987 } 1988 adapter->linkvec = rx_vectors; 1989 if (adapter->hw.mac.type < igb_mac_min) { 1990 adapter->ivars |= (8 | rx_vectors) << 16; 1991 adapter->ivars |= 0x80000000; 1992 } 1993 return (0); 1994 fail: 1995 iflib_irq_free(ctx, &adapter->irq); 1996 rx_que = adapter->rx_queues; 1997 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1998 iflib_irq_free(ctx, &rx_que->que_irq); 1999 return (error); 2000 } 2001 2002 static void 2003 igb_configure_queues(struct adapter *adapter) 2004 { 2005 struct e1000_hw *hw = &adapter->hw; 2006 struct em_rx_queue *rx_que; 2007 struct em_tx_queue *tx_que; 2008 u32 tmp, ivar = 0, newitr = 0; 2009 2010 /* First turn on RSS capability */ 2011 if (adapter->hw.mac.type != e1000_82575) 2012 E1000_WRITE_REG(hw, E1000_GPIE, 2013 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2014 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2015 2016 /* Turn on MSIX */ 2017 switch (adapter->hw.mac.type) { 2018 case e1000_82580: 2019 case e1000_i350: 2020 case e1000_i354: 2021 case e1000_i210: 2022 case e1000_i211: 2023 case e1000_vfadapt: 2024 case e1000_vfadapt_i350: 2025 /* RX entries */ 2026 for (int i = 0; i < adapter->rx_num_queues; i++) { 2027 u32 index = i >> 1; 2028 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2029 rx_que = &adapter->rx_queues[i]; 2030 if (i & 1) { 2031 ivar &= 0xFF00FFFF; 2032 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2033 } else { 2034 ivar &= 0xFFFFFF00; 2035 ivar |= rx_que->msix | E1000_IVAR_VALID; 2036 } 2037 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2038 } 2039 /* TX entries */ 2040 for (int i = 0; i < adapter->tx_num_queues; i++) { 2041 u32 index = i >> 1; 2042 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2043 tx_que = &adapter->tx_queues[i]; 2044 if (i & 1) { 2045 ivar &= 0x00FFFFFF; 2046 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2047 } else { 2048 ivar &= 0xFFFF00FF; 2049 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2050 } 2051 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2052 adapter->que_mask |= tx_que->eims; 2053 } 2054 2055 /* And for the link interrupt */ 2056 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2057 adapter->link_mask = 1 << adapter->linkvec; 2058 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2059 break; 2060 case e1000_82576: 2061 /* RX entries */ 2062 for (int i = 0; i < adapter->rx_num_queues; i++) { 2063 u32 index = i & 0x7; /* Each IVAR has two entries */ 2064 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2065 rx_que = &adapter->rx_queues[i]; 2066 if (i < 8) { 2067 ivar &= 0xFFFFFF00; 2068 ivar |= rx_que->msix | E1000_IVAR_VALID; 2069 } else { 2070 ivar &= 0xFF00FFFF; 2071 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2072 } 2073 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2074 adapter->que_mask |= rx_que->eims; 2075 } 2076 /* TX entries */ 2077 for (int i = 0; i < adapter->tx_num_queues; i++) { 2078 u32 index = i & 0x7; /* Each IVAR has two entries */ 2079 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2080 tx_que = &adapter->tx_queues[i]; 2081 if (i < 8) { 2082 ivar &= 0xFFFF00FF; 2083 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2084 } else { 2085 ivar &= 0x00FFFFFF; 2086 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2087 } 2088 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2089 adapter->que_mask |= tx_que->eims; 2090 } 2091 2092 /* And for the link interrupt */ 2093 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2094 adapter->link_mask = 1 << adapter->linkvec; 2095 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2096 break; 2097 2098 case e1000_82575: 2099 /* enable MSI-X support*/ 2100 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2101 tmp |= E1000_CTRL_EXT_PBA_CLR; 2102 /* Auto-Mask interrupts upon ICR read. */ 2103 tmp |= E1000_CTRL_EXT_EIAME; 2104 tmp |= E1000_CTRL_EXT_IRCA; 2105 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2106 2107 /* Queues */ 2108 for (int i = 0; i < adapter->rx_num_queues; i++) { 2109 rx_que = &adapter->rx_queues[i]; 2110 tmp = E1000_EICR_RX_QUEUE0 << i; 2111 tmp |= E1000_EICR_TX_QUEUE0 << i; 2112 rx_que->eims = tmp; 2113 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2114 i, rx_que->eims); 2115 adapter->que_mask |= rx_que->eims; 2116 } 2117 2118 /* Link */ 2119 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2120 E1000_EIMS_OTHER); 2121 adapter->link_mask |= E1000_EIMS_OTHER; 2122 default: 2123 break; 2124 } 2125 2126 /* Set the starting interrupt rate */ 2127 if (em_max_interrupt_rate > 0) 2128 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2129 2130 if (hw->mac.type == e1000_82575) 2131 newitr |= newitr << 16; 2132 else 2133 newitr |= E1000_EITR_CNT_IGNR; 2134 2135 for (int i = 0; i < adapter->rx_num_queues; i++) { 2136 rx_que = &adapter->rx_queues[i]; 2137 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2138 } 2139 2140 return; 2141 } 2142 2143 static void 2144 em_free_pci_resources(if_ctx_t ctx) 2145 { 2146 struct adapter *adapter = iflib_get_softc(ctx); 2147 struct em_rx_queue *que = adapter->rx_queues; 2148 device_t dev = iflib_get_dev(ctx); 2149 2150 /* Release all msix queue resources */ 2151 if (adapter->intr_type == IFLIB_INTR_MSIX) 2152 iflib_irq_free(ctx, &adapter->irq); 2153 2154 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2155 iflib_irq_free(ctx, &que->que_irq); 2156 } 2157 2158 /* First release all the interrupt resources */ 2159 if (adapter->memory != NULL) { 2160 bus_release_resource(dev, SYS_RES_MEMORY, 2161 PCIR_BAR(0), adapter->memory); 2162 adapter->memory = NULL; 2163 } 2164 2165 if (adapter->flash != NULL) { 2166 bus_release_resource(dev, SYS_RES_MEMORY, 2167 EM_FLASH, adapter->flash); 2168 adapter->flash = NULL; 2169 } 2170 if (adapter->ioport != NULL) 2171 bus_release_resource(dev, SYS_RES_IOPORT, 2172 adapter->io_rid, adapter->ioport); 2173 } 2174 2175 /* Setup MSI or MSI/X */ 2176 static int 2177 em_setup_msix(if_ctx_t ctx) 2178 { 2179 struct adapter *adapter = iflib_get_softc(ctx); 2180 2181 if (adapter->hw.mac.type == e1000_82574) { 2182 em_enable_vectors_82574(ctx); 2183 } 2184 return (0); 2185 } 2186 2187 /********************************************************************* 2188 * 2189 * Initialize the hardware to a configuration 2190 * as specified by the adapter structure. 2191 * 2192 **********************************************************************/ 2193 2194 static void 2195 lem_smartspeed(struct adapter *adapter) 2196 { 2197 u16 phy_tmp; 2198 2199 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2200 adapter->hw.mac.autoneg == 0 || 2201 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2202 return; 2203 2204 if (adapter->smartspeed == 0) { 2205 /* If Master/Slave config fault is asserted twice, 2206 * we assume back-to-back */ 2207 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2208 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2209 return; 2210 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2211 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2212 e1000_read_phy_reg(&adapter->hw, 2213 PHY_1000T_CTRL, &phy_tmp); 2214 if(phy_tmp & CR_1000T_MS_ENABLE) { 2215 phy_tmp &= ~CR_1000T_MS_ENABLE; 2216 e1000_write_phy_reg(&adapter->hw, 2217 PHY_1000T_CTRL, phy_tmp); 2218 adapter->smartspeed++; 2219 if(adapter->hw.mac.autoneg && 2220 !e1000_copper_link_autoneg(&adapter->hw) && 2221 !e1000_read_phy_reg(&adapter->hw, 2222 PHY_CONTROL, &phy_tmp)) { 2223 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2224 MII_CR_RESTART_AUTO_NEG); 2225 e1000_write_phy_reg(&adapter->hw, 2226 PHY_CONTROL, phy_tmp); 2227 } 2228 } 2229 } 2230 return; 2231 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2232 /* If still no link, perhaps using 2/3 pair cable */ 2233 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2234 phy_tmp |= CR_1000T_MS_ENABLE; 2235 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2236 if(adapter->hw.mac.autoneg && 2237 !e1000_copper_link_autoneg(&adapter->hw) && 2238 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2239 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2240 MII_CR_RESTART_AUTO_NEG); 2241 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2242 } 2243 } 2244 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2245 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2246 adapter->smartspeed = 0; 2247 } 2248 2249 /********************************************************************* 2250 * 2251 * Initialize the DMA Coalescing feature 2252 * 2253 **********************************************************************/ 2254 static void 2255 igb_init_dmac(struct adapter *adapter, u32 pba) 2256 { 2257 device_t dev = adapter->dev; 2258 struct e1000_hw *hw = &adapter->hw; 2259 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2260 u16 hwm; 2261 u16 max_frame_size; 2262 2263 if (hw->mac.type == e1000_i211) 2264 return; 2265 2266 max_frame_size = adapter->shared->isc_max_frame_size; 2267 if (hw->mac.type > e1000_82580) { 2268 2269 if (adapter->dmac == 0) { /* Disabling it */ 2270 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2271 return; 2272 } else 2273 device_printf(dev, "DMA Coalescing enabled\n"); 2274 2275 /* Set starting threshold */ 2276 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2277 2278 hwm = 64 * pba - max_frame_size / 16; 2279 if (hwm < 64 * (pba - 6)) 2280 hwm = 64 * (pba - 6); 2281 reg = E1000_READ_REG(hw, E1000_FCRTC); 2282 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2283 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2284 & E1000_FCRTC_RTH_COAL_MASK); 2285 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2286 2287 2288 dmac = pba - max_frame_size / 512; 2289 if (dmac < pba - 10) 2290 dmac = pba - 10; 2291 reg = E1000_READ_REG(hw, E1000_DMACR); 2292 reg &= ~E1000_DMACR_DMACTHR_MASK; 2293 reg = ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2294 & E1000_DMACR_DMACTHR_MASK); 2295 2296 /* transition to L0x or L1 if available..*/ 2297 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2298 2299 /* Check if status is 2.5Gb backplane connection 2300 * before configuration of watchdog timer, which is 2301 * in msec values in 12.8usec intervals 2302 * watchdog timer= msec values in 32usec intervals 2303 * for non 2.5Gb connection 2304 */ 2305 if (hw->mac.type == e1000_i354) { 2306 int status = E1000_READ_REG(hw, E1000_STATUS); 2307 if ((status & E1000_STATUS_2P5_SKU) && 2308 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2309 reg |= ((adapter->dmac * 5) >> 6); 2310 else 2311 reg |= (adapter->dmac >> 5); 2312 } else { 2313 reg |= (adapter->dmac >> 5); 2314 } 2315 2316 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2317 2318 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2319 2320 /* Set the interval before transition */ 2321 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2322 if (hw->mac.type == e1000_i350) 2323 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2324 /* 2325 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2326 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2327 */ 2328 if (hw->mac.type == e1000_i354) { 2329 int status = E1000_READ_REG(hw, E1000_STATUS); 2330 if ((status & E1000_STATUS_2P5_SKU) && 2331 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2332 reg |= 0xA; 2333 else 2334 reg |= 0x4; 2335 } else { 2336 reg |= 0x4; 2337 } 2338 2339 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2340 2341 /* free space in tx packet buffer to wake from DMA coal */ 2342 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2343 (2 * max_frame_size)) >> 6); 2344 2345 /* make low power state decision controlled by DMA coal */ 2346 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2347 reg &= ~E1000_PCIEMISC_LX_DECISION; 2348 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2349 2350 } else if (hw->mac.type == e1000_82580) { 2351 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2352 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2353 reg & ~E1000_PCIEMISC_LX_DECISION); 2354 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2355 } 2356 } 2357 2358 static void 2359 em_reset(if_ctx_t ctx) 2360 { 2361 device_t dev = iflib_get_dev(ctx); 2362 struct adapter *adapter = iflib_get_softc(ctx); 2363 struct ifnet *ifp = iflib_get_ifp(ctx); 2364 struct e1000_hw *hw = &adapter->hw; 2365 u16 rx_buffer_size; 2366 u32 pba; 2367 2368 INIT_DEBUGOUT("em_reset: begin"); 2369 /* Let the firmware know the OS is in control */ 2370 em_get_hw_control(adapter); 2371 2372 /* Set up smart power down as default off on newer adapters. */ 2373 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2374 hw->mac.type == e1000_82572)) { 2375 u16 phy_tmp = 0; 2376 2377 /* Speed up time to link by disabling smart power down. */ 2378 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2379 phy_tmp &= ~IGP02E1000_PM_SPD; 2380 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2381 } 2382 2383 /* 2384 * Packet Buffer Allocation (PBA) 2385 * Writing PBA sets the receive portion of the buffer 2386 * the remainder is used for the transmit buffer. 2387 */ 2388 switch (hw->mac.type) { 2389 /* Total Packet Buffer on these is 48K */ 2390 case e1000_82571: 2391 case e1000_82572: 2392 case e1000_80003es2lan: 2393 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2394 break; 2395 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 2396 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2397 break; 2398 case e1000_82574: 2399 case e1000_82583: 2400 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2401 break; 2402 case e1000_ich8lan: 2403 pba = E1000_PBA_8K; 2404 break; 2405 case e1000_ich9lan: 2406 case e1000_ich10lan: 2407 /* Boost Receive side for jumbo frames */ 2408 if (adapter->hw.mac.max_frame_size > 4096) 2409 pba = E1000_PBA_14K; 2410 else 2411 pba = E1000_PBA_10K; 2412 break; 2413 case e1000_pchlan: 2414 case e1000_pch2lan: 2415 case e1000_pch_lpt: 2416 case e1000_pch_spt: 2417 pba = E1000_PBA_26K; 2418 break; 2419 case e1000_82575: 2420 pba = E1000_PBA_32K; 2421 break; 2422 case e1000_82576: 2423 case e1000_vfadapt: 2424 pba = E1000_READ_REG(hw, E1000_RXPBS); 2425 pba &= E1000_RXPBS_SIZE_MASK_82576; 2426 break; 2427 case e1000_82580: 2428 case e1000_i350: 2429 case e1000_i354: 2430 case e1000_vfadapt_i350: 2431 pba = E1000_READ_REG(hw, E1000_RXPBS); 2432 pba = e1000_rxpbs_adjust_82580(pba); 2433 break; 2434 case e1000_i210: 2435 case e1000_i211: 2436 pba = E1000_PBA_34K; 2437 break; 2438 default: 2439 if (adapter->hw.mac.max_frame_size > 8192) 2440 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2441 else 2442 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2443 } 2444 2445 /* Special needs in case of Jumbo frames */ 2446 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2447 u32 tx_space, min_tx, min_rx; 2448 pba = E1000_READ_REG(hw, E1000_PBA); 2449 tx_space = pba >> 16; 2450 pba &= 0xffff; 2451 min_tx = (adapter->hw.mac.max_frame_size + 2452 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2453 min_tx = roundup2(min_tx, 1024); 2454 min_tx >>= 10; 2455 min_rx = adapter->hw.mac.max_frame_size; 2456 min_rx = roundup2(min_rx, 1024); 2457 min_rx >>= 10; 2458 if (tx_space < min_tx && 2459 ((min_tx - tx_space) < pba)) { 2460 pba = pba - (min_tx - tx_space); 2461 /* 2462 * if short on rx space, rx wins 2463 * and must trump tx adjustment 2464 */ 2465 if (pba < min_rx) 2466 pba = min_rx; 2467 } 2468 E1000_WRITE_REG(hw, E1000_PBA, pba); 2469 } 2470 2471 if (hw->mac.type < igb_mac_min) 2472 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 2473 2474 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2475 2476 /* 2477 * These parameters control the automatic generation (Tx) and 2478 * response (Rx) to Ethernet PAUSE frames. 2479 * - High water mark should allow for at least two frames to be 2480 * received after sending an XOFF. 2481 * - Low water mark works best when it is very near the high water mark. 2482 * This allows the receiver to restart by sending XON when it has 2483 * drained a bit. Here we use an arbitrary value of 1500 which will 2484 * restart after one full frame is pulled from the buffer. There 2485 * could be several smaller frames in the buffer and if so they will 2486 * not trigger the XON until their total number reduces the buffer 2487 * by 1500. 2488 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2489 */ 2490 rx_buffer_size = (pba & 0xffff) << 10; 2491 hw->fc.high_water = rx_buffer_size - 2492 roundup2(adapter->hw.mac.max_frame_size, 1024); 2493 hw->fc.low_water = hw->fc.high_water - 1500; 2494 2495 if (adapter->fc) /* locally set flow control value? */ 2496 hw->fc.requested_mode = adapter->fc; 2497 else 2498 hw->fc.requested_mode = e1000_fc_full; 2499 2500 if (hw->mac.type == e1000_80003es2lan) 2501 hw->fc.pause_time = 0xFFFF; 2502 else 2503 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2504 2505 hw->fc.send_xon = TRUE; 2506 2507 /* Device specific overrides/settings */ 2508 switch (hw->mac.type) { 2509 case e1000_pchlan: 2510 /* Workaround: no TX flow ctrl for PCH */ 2511 hw->fc.requested_mode = e1000_fc_rx_pause; 2512 hw->fc.pause_time = 0xFFFF; /* override */ 2513 if (if_getmtu(ifp) > ETHERMTU) { 2514 hw->fc.high_water = 0x3500; 2515 hw->fc.low_water = 0x1500; 2516 } else { 2517 hw->fc.high_water = 0x5000; 2518 hw->fc.low_water = 0x3000; 2519 } 2520 hw->fc.refresh_time = 0x1000; 2521 break; 2522 case e1000_pch2lan: 2523 case e1000_pch_lpt: 2524 case e1000_pch_spt: 2525 hw->fc.high_water = 0x5C20; 2526 hw->fc.low_water = 0x5048; 2527 hw->fc.pause_time = 0x0650; 2528 hw->fc.refresh_time = 0x0400; 2529 /* Jumbos need adjusted PBA */ 2530 if (if_getmtu(ifp) > ETHERMTU) 2531 E1000_WRITE_REG(hw, E1000_PBA, 12); 2532 else 2533 E1000_WRITE_REG(hw, E1000_PBA, 26); 2534 break; 2535 case e1000_82575: 2536 case e1000_82576: 2537 /* 8-byte granularity */ 2538 hw->fc.low_water = hw->fc.high_water - 8; 2539 break; 2540 case e1000_82580: 2541 case e1000_i350: 2542 case e1000_i354: 2543 case e1000_i210: 2544 case e1000_i211: 2545 case e1000_vfadapt: 2546 case e1000_vfadapt_i350: 2547 /* 16-byte granularity */ 2548 hw->fc.low_water = hw->fc.high_water - 16; 2549 break; 2550 case e1000_ich9lan: 2551 case e1000_ich10lan: 2552 if (if_getmtu(ifp) > ETHERMTU) { 2553 hw->fc.high_water = 0x2800; 2554 hw->fc.low_water = hw->fc.high_water - 8; 2555 break; 2556 } 2557 /* FALLTHROUGH */ 2558 default: 2559 if (hw->mac.type == e1000_80003es2lan) 2560 hw->fc.pause_time = 0xFFFF; 2561 break; 2562 } 2563 2564 /* Issue a global reset */ 2565 e1000_reset_hw(hw); 2566 if (adapter->hw.mac.type >= igb_mac_min) { 2567 E1000_WRITE_REG(hw, E1000_WUC, 0); 2568 } else { 2569 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2570 em_disable_aspm(adapter); 2571 } 2572 if (adapter->flags & IGB_MEDIA_RESET) { 2573 e1000_setup_init_funcs(hw, TRUE); 2574 e1000_get_bus_info(hw); 2575 adapter->flags &= ~IGB_MEDIA_RESET; 2576 } 2577 /* and a re-init */ 2578 if (e1000_init_hw(hw) < 0) { 2579 device_printf(dev, "Hardware Initialization Failed\n"); 2580 return; 2581 } 2582 if (adapter->hw.mac.type >= igb_mac_min) 2583 igb_init_dmac(adapter, pba); 2584 2585 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2586 e1000_get_phy_info(hw); 2587 e1000_check_for_link(hw); 2588 } 2589 2590 #define RSSKEYLEN 10 2591 static void 2592 em_initialize_rss_mapping(struct adapter *adapter) 2593 { 2594 uint8_t rss_key[4 * RSSKEYLEN]; 2595 uint32_t reta = 0; 2596 struct e1000_hw *hw = &adapter->hw; 2597 int i; 2598 2599 /* 2600 * Configure RSS key 2601 */ 2602 arc4rand(rss_key, sizeof(rss_key), 0); 2603 for (i = 0; i < RSSKEYLEN; ++i) { 2604 uint32_t rssrk = 0; 2605 2606 rssrk = EM_RSSRK_VAL(rss_key, i); 2607 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2608 } 2609 2610 /* 2611 * Configure RSS redirect table in following fashion: 2612 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2613 */ 2614 for (i = 0; i < sizeof(reta); ++i) { 2615 uint32_t q; 2616 2617 q = (i % adapter->rx_num_queues) << 7; 2618 reta |= q << (8 * i); 2619 } 2620 2621 for (i = 0; i < 32; ++i) 2622 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2623 2624 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2625 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2626 E1000_MRQC_RSS_FIELD_IPV4 | 2627 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2628 E1000_MRQC_RSS_FIELD_IPV6_EX | 2629 E1000_MRQC_RSS_FIELD_IPV6); 2630 2631 } 2632 2633 static void 2634 igb_initialize_rss_mapping(struct adapter *adapter) 2635 { 2636 struct e1000_hw *hw = &adapter->hw; 2637 int i; 2638 int queue_id; 2639 u32 reta; 2640 u32 rss_key[10], mrqc, shift = 0; 2641 2642 /* XXX? */ 2643 if (adapter->hw.mac.type == e1000_82575) 2644 shift = 6; 2645 2646 /* 2647 * The redirection table controls which destination 2648 * queue each bucket redirects traffic to. 2649 * Each DWORD represents four queues, with the LSB 2650 * being the first queue in the DWORD. 2651 * 2652 * This just allocates buckets to queues using round-robin 2653 * allocation. 2654 * 2655 * NOTE: It Just Happens to line up with the default 2656 * RSS allocation method. 2657 */ 2658 2659 /* Warning FM follows */ 2660 reta = 0; 2661 for (i = 0; i < 128; i++) { 2662 #ifdef RSS 2663 queue_id = rss_get_indirection_to_bucket(i); 2664 /* 2665 * If we have more queues than buckets, we'll 2666 * end up mapping buckets to a subset of the 2667 * queues. 2668 * 2669 * If we have more buckets than queues, we'll 2670 * end up instead assigning multiple buckets 2671 * to queues. 2672 * 2673 * Both are suboptimal, but we need to handle 2674 * the case so we don't go out of bounds 2675 * indexing arrays and such. 2676 */ 2677 queue_id = queue_id % adapter->rx_num_queues; 2678 #else 2679 queue_id = (i % adapter->rx_num_queues); 2680 #endif 2681 /* Adjust if required */ 2682 queue_id = queue_id << shift; 2683 2684 /* 2685 * The low 8 bits are for hash value (n+0); 2686 * The next 8 bits are for hash value (n+1), etc. 2687 */ 2688 reta = reta >> 8; 2689 reta = reta | ( ((uint32_t) queue_id) << 24); 2690 if ((i & 3) == 3) { 2691 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2692 reta = 0; 2693 } 2694 } 2695 2696 /* Now fill in hash table */ 2697 2698 /* 2699 * MRQC: Multiple Receive Queues Command 2700 * Set queuing to RSS control, number depends on the device. 2701 */ 2702 mrqc = E1000_MRQC_ENABLE_RSS_8Q; 2703 2704 #ifdef RSS 2705 /* XXX ew typecasting */ 2706 rss_getkey((uint8_t *) &rss_key); 2707 #else 2708 arc4rand(&rss_key, sizeof(rss_key), 0); 2709 #endif 2710 for (i = 0; i < 10; i++) 2711 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2712 2713 /* 2714 * Configure the RSS fields to hash upon. 2715 */ 2716 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2717 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2718 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2719 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2720 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2721 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2722 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2723 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2724 2725 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2726 } 2727 2728 /********************************************************************* 2729 * 2730 * Setup networking device structure and register an interface. 2731 * 2732 **********************************************************************/ 2733 static int 2734 em_setup_interface(if_ctx_t ctx) 2735 { 2736 struct ifnet *ifp = iflib_get_ifp(ctx); 2737 struct adapter *adapter = iflib_get_softc(ctx); 2738 if_softc_ctx_t scctx = adapter->shared; 2739 uint64_t cap = 0; 2740 2741 INIT_DEBUGOUT("em_setup_interface: begin"); 2742 2743 /* TSO parameters */ 2744 if_sethwtsomax(ifp, IP_MAXPACKET); 2745 /* Take m_pullup(9)'s in em_xmit() w/ TSO into acount. */ 2746 if_sethwtsomaxsegcount(ifp, EM_MAX_SCATTER - 5); 2747 if_sethwtsomaxsegsize(ifp, EM_TSO_SEG_SIZE); 2748 2749 /* Single Queue */ 2750 if (adapter->tx_num_queues == 1) { 2751 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2752 if_setsendqready(ifp); 2753 } 2754 2755 cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4; 2756 cap |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU; 2757 2758 /* 2759 * Tell the upper layer(s) we 2760 * support full VLAN capability 2761 */ 2762 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 2763 if_setcapabilitiesbit(ifp, cap, 0); 2764 2765 /* 2766 * Don't turn this on by default, if vlans are 2767 * created on another pseudo device (eg. lagg) 2768 * then vlan events are not passed thru, breaking 2769 * operation, but with HW FILTER off it works. If 2770 * using vlans directly on the em driver you can 2771 * enable this and get full hardware tag filtering. 2772 */ 2773 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER,0); 2774 2775 /* Enable only WOL MAGIC by default */ 2776 if (adapter->wol) { 2777 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 2778 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2779 } else { 2780 if_setcapenablebit(ifp, 0, IFCAP_WOL_MAGIC | 2781 IFCAP_WOL_MCAST| IFCAP_WOL_UCAST); 2782 } 2783 2784 /* 2785 * Specify the media types supported by this adapter and register 2786 * callbacks to update media and link information 2787 */ 2788 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2789 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2790 u_char fiber_type = IFM_1000_SX; /* default type */ 2791 2792 if (adapter->hw.mac.type == e1000_82545) 2793 fiber_type = IFM_1000_LX; 2794 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2795 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2796 } else { 2797 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2798 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2799 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2800 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2801 if (adapter->hw.phy.type != e1000_phy_ife) { 2802 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2803 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2804 } 2805 } 2806 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2807 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2808 return (0); 2809 } 2810 2811 static int 2812 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2813 { 2814 struct adapter *adapter = iflib_get_softc(ctx); 2815 if_softc_ctx_t scctx = adapter->shared; 2816 int error = E1000_SUCCESS; 2817 struct em_tx_queue *que; 2818 int i, j; 2819 2820 MPASS(adapter->tx_num_queues > 0); 2821 MPASS(adapter->tx_num_queues == ntxqsets); 2822 2823 /* First allocate the top level queue structs */ 2824 if (!(adapter->tx_queues = 2825 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2826 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2827 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2828 return(ENOMEM); 2829 } 2830 2831 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2832 /* Set up some basics */ 2833 2834 struct tx_ring *txr = &que->txr; 2835 txr->adapter = que->adapter = adapter; 2836 que->me = txr->me = i; 2837 2838 /* Allocate report status array */ 2839 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2840 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2841 error = ENOMEM; 2842 goto fail; 2843 } 2844 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2845 txr->tx_rsq[j] = QIDX_INVALID; 2846 /* get the virtual and physical address of the hardware queues */ 2847 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2848 txr->tx_paddr = paddrs[i*ntxqs]; 2849 } 2850 2851 device_printf(iflib_get_dev(ctx), "allocated for %d tx_queues\n", adapter->tx_num_queues); 2852 return (0); 2853 fail: 2854 em_if_queues_free(ctx); 2855 return (error); 2856 } 2857 2858 static int 2859 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2860 { 2861 struct adapter *adapter = iflib_get_softc(ctx); 2862 int error = E1000_SUCCESS; 2863 struct em_rx_queue *que; 2864 int i; 2865 2866 MPASS(adapter->rx_num_queues > 0); 2867 MPASS(adapter->rx_num_queues == nrxqsets); 2868 2869 /* First allocate the top level queue structs */ 2870 if (!(adapter->rx_queues = 2871 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2872 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2873 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2874 error = ENOMEM; 2875 goto fail; 2876 } 2877 2878 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2879 /* Set up some basics */ 2880 struct rx_ring *rxr = &que->rxr; 2881 rxr->adapter = que->adapter = adapter; 2882 rxr->que = que; 2883 que->me = rxr->me = i; 2884 2885 /* get the virtual and physical address of the hardware queues */ 2886 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2887 rxr->rx_paddr = paddrs[i*nrxqs]; 2888 } 2889 2890 device_printf(iflib_get_dev(ctx), "allocated for %d rx_queues\n", adapter->rx_num_queues); 2891 2892 return (0); 2893 fail: 2894 em_if_queues_free(ctx); 2895 return (error); 2896 } 2897 2898 static void 2899 em_if_queues_free(if_ctx_t ctx) 2900 { 2901 struct adapter *adapter = iflib_get_softc(ctx); 2902 struct em_tx_queue *tx_que = adapter->tx_queues; 2903 struct em_rx_queue *rx_que = adapter->rx_queues; 2904 2905 if (tx_que != NULL) { 2906 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2907 struct tx_ring *txr = &tx_que->txr; 2908 if (txr->tx_rsq == NULL) 2909 break; 2910 2911 free(txr->tx_rsq, M_DEVBUF); 2912 txr->tx_rsq = NULL; 2913 } 2914 free(adapter->tx_queues, M_DEVBUF); 2915 adapter->tx_queues = NULL; 2916 } 2917 2918 if (rx_que != NULL) { 2919 free(adapter->rx_queues, M_DEVBUF); 2920 adapter->rx_queues = NULL; 2921 } 2922 2923 em_release_hw_control(adapter); 2924 2925 if (adapter->mta != NULL) { 2926 free(adapter->mta, M_DEVBUF); 2927 } 2928 } 2929 2930 /********************************************************************* 2931 * 2932 * Enable transmit unit. 2933 * 2934 **********************************************************************/ 2935 static void 2936 em_initialize_transmit_unit(if_ctx_t ctx) 2937 { 2938 struct adapter *adapter = iflib_get_softc(ctx); 2939 if_softc_ctx_t scctx = adapter->shared; 2940 struct em_tx_queue *que; 2941 struct tx_ring *txr; 2942 struct e1000_hw *hw = &adapter->hw; 2943 u32 tctl, txdctl = 0, tarc, tipg = 0; 2944 2945 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2946 2947 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2948 u64 bus_addr; 2949 caddr_t offp, endp; 2950 2951 que = &adapter->tx_queues[i]; 2952 txr = &que->txr; 2953 bus_addr = txr->tx_paddr; 2954 2955 /* Clear checksum offload context. */ 2956 offp = (caddr_t)&txr->csum_flags; 2957 endp = (caddr_t)(txr + 1); 2958 bzero(offp, endp - offp); 2959 2960 /* Base and Len of TX Ring */ 2961 E1000_WRITE_REG(hw, E1000_TDLEN(i), 2962 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 2963 E1000_WRITE_REG(hw, E1000_TDBAH(i), 2964 (u32)(bus_addr >> 32)); 2965 E1000_WRITE_REG(hw, E1000_TDBAL(i), 2966 (u32)bus_addr); 2967 /* Init the HEAD/TAIL indices */ 2968 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 2969 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 2970 2971 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2972 E1000_READ_REG(&adapter->hw, E1000_TDBAL(i)), 2973 E1000_READ_REG(&adapter->hw, E1000_TDLEN(i))); 2974 2975 txdctl = 0; /* clear txdctl */ 2976 txdctl |= 0x1f; /* PTHRESH */ 2977 txdctl |= 1 << 8; /* HTHRESH */ 2978 txdctl |= 1 << 16;/* WTHRESH */ 2979 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 2980 txdctl |= E1000_TXDCTL_GRAN; 2981 txdctl |= 1 << 25; /* LWTHRESH */ 2982 2983 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 2984 } 2985 2986 /* Set the default values for the Tx Inter Packet Gap timer */ 2987 switch (adapter->hw.mac.type) { 2988 case e1000_80003es2lan: 2989 tipg = DEFAULT_82543_TIPG_IPGR1; 2990 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2991 E1000_TIPG_IPGR2_SHIFT; 2992 break; 2993 case e1000_82542: 2994 tipg = DEFAULT_82542_TIPG_IPGT; 2995 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2996 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2997 break; 2998 default: 2999 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3000 (adapter->hw.phy.media_type == 3001 e1000_media_type_internal_serdes)) 3002 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3003 else 3004 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3005 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3006 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3007 } 3008 3009 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3010 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3011 3012 if(adapter->hw.mac.type >= e1000_82540) 3013 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3014 adapter->tx_abs_int_delay.value); 3015 3016 if ((adapter->hw.mac.type == e1000_82571) || 3017 (adapter->hw.mac.type == e1000_82572)) { 3018 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3019 tarc |= TARC_SPEED_MODE_BIT; 3020 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3021 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3022 /* errata: program both queues to unweighted RR */ 3023 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3024 tarc |= 1; 3025 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3026 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3027 tarc |= 1; 3028 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3029 } else if (adapter->hw.mac.type == e1000_82574) { 3030 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3031 tarc |= TARC_ERRATA_BIT; 3032 if ( adapter->tx_num_queues > 1) { 3033 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3034 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3035 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3036 } else 3037 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3038 } 3039 3040 if (adapter->tx_int_delay.value > 0) 3041 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3042 3043 /* Program the Transmit Control Register */ 3044 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3045 tctl &= ~E1000_TCTL_CT; 3046 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3047 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3048 3049 if (adapter->hw.mac.type >= e1000_82571) 3050 tctl |= E1000_TCTL_MULR; 3051 3052 /* This write will effectively turn on the transmit unit. */ 3053 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3054 3055 if (hw->mac.type == e1000_pch_spt) { 3056 u32 reg; 3057 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3058 reg |= E1000_RCTL_RDMTS_HEX; 3059 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3060 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3061 reg |= E1000_TARC0_CB_MULTIQ_3_REQ; 3062 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3063 } 3064 } 3065 3066 /********************************************************************* 3067 * 3068 * Enable receive unit. 3069 * 3070 **********************************************************************/ 3071 3072 static void 3073 em_initialize_receive_unit(if_ctx_t ctx) 3074 { 3075 struct adapter *adapter = iflib_get_softc(ctx); 3076 if_softc_ctx_t scctx = adapter->shared; 3077 struct ifnet *ifp = iflib_get_ifp(ctx); 3078 struct e1000_hw *hw = &adapter->hw; 3079 struct em_rx_queue *que; 3080 int i; 3081 u32 rctl, rxcsum, rfctl; 3082 3083 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3084 3085 /* 3086 * Make sure receives are disabled while setting 3087 * up the descriptor ring 3088 */ 3089 rctl = E1000_READ_REG(hw, E1000_RCTL); 3090 /* Do not disable if ever enabled on this hardware */ 3091 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3092 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3093 3094 /* Setup the Receive Control Register */ 3095 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3096 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3097 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3098 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3099 3100 /* Do not store bad packets */ 3101 rctl &= ~E1000_RCTL_SBP; 3102 3103 /* Enable Long Packet receive */ 3104 if (if_getmtu(ifp) > ETHERMTU) 3105 rctl |= E1000_RCTL_LPE; 3106 else 3107 rctl &= ~E1000_RCTL_LPE; 3108 3109 /* Strip the CRC */ 3110 if (!em_disable_crc_stripping) 3111 rctl |= E1000_RCTL_SECRC; 3112 3113 if (adapter->hw.mac.type >= e1000_82540) { 3114 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 3115 adapter->rx_abs_int_delay.value); 3116 3117 /* 3118 * Set the interrupt throttling rate. Value is calculated 3119 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3120 */ 3121 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3122 } 3123 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 3124 adapter->rx_int_delay.value); 3125 3126 /* Use extended rx descriptor formats */ 3127 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3128 rfctl |= E1000_RFCTL_EXTEN; 3129 /* 3130 * When using MSIX interrupts we need to throttle 3131 * using the EITR register (82574 only) 3132 */ 3133 if (hw->mac.type == e1000_82574) { 3134 for (int i = 0; i < 4; i++) 3135 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3136 DEFAULT_ITR); 3137 /* Disable accelerated acknowledge */ 3138 rfctl |= E1000_RFCTL_ACK_DIS; 3139 } 3140 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3141 3142 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3143 if (if_getcapenable(ifp) & IFCAP_RXCSUM && 3144 adapter->hw.mac.type >= e1000_82543) { 3145 if (adapter->tx_num_queues > 1) { 3146 if (adapter->hw.mac.type >= igb_mac_min) { 3147 rxcsum |= E1000_RXCSUM_PCSD; 3148 if (hw->mac.type != e1000_82575) 3149 rxcsum |= E1000_RXCSUM_CRCOFL; 3150 } else 3151 rxcsum |= E1000_RXCSUM_TUOFL | 3152 E1000_RXCSUM_IPOFL | 3153 E1000_RXCSUM_PCSD; 3154 } else { 3155 if (adapter->hw.mac.type >= igb_mac_min) 3156 rxcsum |= E1000_RXCSUM_IPPCSE; 3157 else 3158 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3159 if (adapter->hw.mac.type > e1000_82575) 3160 rxcsum |= E1000_RXCSUM_CRCOFL; 3161 } 3162 } else 3163 rxcsum &= ~E1000_RXCSUM_TUOFL; 3164 3165 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3166 3167 if (adapter->rx_num_queues > 1) { 3168 if (adapter->hw.mac.type >= igb_mac_min) 3169 igb_initialize_rss_mapping(adapter); 3170 else 3171 em_initialize_rss_mapping(adapter); 3172 } 3173 3174 /* 3175 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3176 * long latencies are observed, like Lenovo X60. This 3177 * change eliminates the problem, but since having positive 3178 * values in RDTR is a known source of problems on other 3179 * platforms another solution is being sought. 3180 */ 3181 if (hw->mac.type == e1000_82573) 3182 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3183 3184 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3185 struct rx_ring *rxr = &que->rxr; 3186 /* Setup the Base and Length of the Rx Descriptor Ring */ 3187 u64 bus_addr = rxr->rx_paddr; 3188 #if 0 3189 u32 rdt = adapter->rx_num_queues -1; /* default */ 3190 #endif 3191 3192 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3193 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3194 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3195 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3196 /* Setup the Head and Tail Descriptor Pointers */ 3197 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3198 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3199 } 3200 3201 /* 3202 * Set PTHRESH for improved jumbo performance 3203 * According to 10.2.5.11 of Intel 82574 Datasheet, 3204 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3205 * Only write to RXDCTL(1) if there is a need for different 3206 * settings. 3207 */ 3208 3209 if (((adapter->hw.mac.type == e1000_ich9lan) || 3210 (adapter->hw.mac.type == e1000_pch2lan) || 3211 (adapter->hw.mac.type == e1000_ich10lan)) && 3212 (if_getmtu(ifp) > ETHERMTU)) { 3213 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3214 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3215 } else if (adapter->hw.mac.type == e1000_82574) { 3216 for (int i = 0; i < adapter->rx_num_queues; i++) { 3217 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3218 rxdctl |= 0x20; /* PTHRESH */ 3219 rxdctl |= 4 << 8; /* HTHRESH */ 3220 rxdctl |= 4 << 16;/* WTHRESH */ 3221 rxdctl |= 1 << 24; /* Switch to granularity */ 3222 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3223 } 3224 } else if (adapter->hw.mac.type >= igb_mac_min) { 3225 u32 psize, srrctl = 0; 3226 3227 if (if_getmtu(ifp) > ETHERMTU) { 3228 /* Set maximum packet len */ 3229 if (adapter->rx_mbuf_sz <= 4096) { 3230 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3231 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3232 } else if (adapter->rx_mbuf_sz > 4096) { 3233 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3234 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3235 } 3236 psize = scctx->isc_max_frame_size; 3237 /* are we on a vlan? */ 3238 if (ifp->if_vlantrunk != NULL) 3239 psize += VLAN_TAG_SIZE; 3240 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize); 3241 } else { 3242 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3243 rctl |= E1000_RCTL_SZ_2048; 3244 } 3245 3246 /* 3247 * If TX flow control is disabled and there's >1 queue defined, 3248 * enable DROP. 3249 * 3250 * This drops frames rather than hanging the RX MAC for all queues. 3251 */ 3252 if ((adapter->rx_num_queues > 1) && 3253 (adapter->fc == e1000_fc_none || 3254 adapter->fc == e1000_fc_rx_pause)) { 3255 srrctl |= E1000_SRRCTL_DROP_EN; 3256 } 3257 /* Setup the Base and Length of the Rx Descriptor Rings */ 3258 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3259 struct rx_ring *rxr = &que->rxr; 3260 u64 bus_addr = rxr->rx_paddr; 3261 u32 rxdctl; 3262 3263 #ifdef notyet 3264 /* Configure for header split? -- ignore for now */ 3265 rxr->hdr_split = igb_header_split; 3266 #else 3267 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3268 #endif 3269 3270 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3271 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3272 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3273 (uint32_t)(bus_addr >> 32)); 3274 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3275 (uint32_t)bus_addr); 3276 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3277 /* Enable this Queue */ 3278 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3279 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3280 rxdctl &= 0xFFF00000; 3281 rxdctl |= IGB_RX_PTHRESH; 3282 rxdctl |= IGB_RX_HTHRESH << 8; 3283 rxdctl |= IGB_RX_WTHRESH << 16; 3284 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3285 } 3286 } else if (adapter->hw.mac.type >= e1000_pch2lan) { 3287 if (if_getmtu(ifp) > ETHERMTU) 3288 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3289 else 3290 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3291 } 3292 3293 /* Make sure VLAN Filters are off */ 3294 rctl &= ~E1000_RCTL_VFE; 3295 3296 if (adapter->hw.mac.type < igb_mac_min) { 3297 if (adapter->rx_mbuf_sz == MCLBYTES) 3298 rctl |= E1000_RCTL_SZ_2048; 3299 else if (adapter->rx_mbuf_sz == MJUMPAGESIZE) 3300 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3301 else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) 3302 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3303 3304 /* ensure we clear use DTYPE of 00 here */ 3305 rctl &= ~0x00000C00; 3306 } 3307 3308 /* Write out the settings */ 3309 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3310 3311 return; 3312 } 3313 3314 static void 3315 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3316 { 3317 struct adapter *adapter = iflib_get_softc(ctx); 3318 u32 index, bit; 3319 3320 index = (vtag >> 5) & 0x7F; 3321 bit = vtag & 0x1F; 3322 adapter->shadow_vfta[index] |= (1 << bit); 3323 ++adapter->num_vlans; 3324 } 3325 3326 static void 3327 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3328 { 3329 struct adapter *adapter = iflib_get_softc(ctx); 3330 u32 index, bit; 3331 3332 index = (vtag >> 5) & 0x7F; 3333 bit = vtag & 0x1F; 3334 adapter->shadow_vfta[index] &= ~(1 << bit); 3335 --adapter->num_vlans; 3336 } 3337 3338 static void 3339 em_setup_vlan_hw_support(struct adapter *adapter) 3340 { 3341 struct e1000_hw *hw = &adapter->hw; 3342 u32 reg; 3343 3344 /* 3345 * We get here thru init_locked, meaning 3346 * a soft reset, this has already cleared 3347 * the VFTA and other state, so if there 3348 * have been no vlan's registered do nothing. 3349 */ 3350 if (adapter->num_vlans == 0) 3351 return; 3352 3353 /* 3354 * A soft reset zero's out the VFTA, so 3355 * we need to repopulate it now. 3356 */ 3357 for (int i = 0; i < EM_VFTA_SIZE; i++) 3358 if (adapter->shadow_vfta[i] != 0) 3359 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3360 i, adapter->shadow_vfta[i]); 3361 3362 reg = E1000_READ_REG(hw, E1000_CTRL); 3363 reg |= E1000_CTRL_VME; 3364 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3365 3366 /* Enable the Filter Table */ 3367 reg = E1000_READ_REG(hw, E1000_RCTL); 3368 reg &= ~E1000_RCTL_CFIEN; 3369 reg |= E1000_RCTL_VFE; 3370 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3371 } 3372 3373 static void 3374 em_if_enable_intr(if_ctx_t ctx) 3375 { 3376 struct adapter *adapter = iflib_get_softc(ctx); 3377 struct e1000_hw *hw = &adapter->hw; 3378 u32 ims_mask = IMS_ENABLE_MASK; 3379 3380 if (hw->mac.type == e1000_82574) { 3381 E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); 3382 ims_mask |= adapter->ims; 3383 } else if (adapter->intr_type == IFLIB_INTR_MSIX && hw->mac.type >= igb_mac_min) { 3384 u32 mask = (adapter->que_mask | adapter->link_mask); 3385 3386 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, mask); 3387 E1000_WRITE_REG(&adapter->hw, E1000_EIAM, mask); 3388 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, mask); 3389 ims_mask = E1000_IMS_LSC; 3390 } 3391 3392 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3393 } 3394 3395 static void 3396 em_if_disable_intr(if_ctx_t ctx) 3397 { 3398 struct adapter *adapter = iflib_get_softc(ctx); 3399 struct e1000_hw *hw = &adapter->hw; 3400 3401 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3402 if (hw->mac.type >= igb_mac_min) 3403 E1000_WRITE_REG(&adapter->hw, E1000_EIMC, ~0); 3404 E1000_WRITE_REG(&adapter->hw, E1000_EIAC, 0); 3405 } 3406 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 3407 } 3408 3409 /* 3410 * Bit of a misnomer, what this really means is 3411 * to enable OS management of the system... aka 3412 * to disable special hardware management features 3413 */ 3414 static void 3415 em_init_manageability(struct adapter *adapter) 3416 { 3417 /* A shared code workaround */ 3418 #define E1000_82542_MANC2H E1000_MANC2H 3419 if (adapter->has_manage) { 3420 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3421 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3422 3423 /* disable hardware interception of ARP */ 3424 manc &= ~(E1000_MANC_ARP_EN); 3425 3426 /* enable receiving management packets to the host */ 3427 manc |= E1000_MANC_EN_MNG2HOST; 3428 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3429 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3430 manc2h |= E1000_MNG2HOST_PORT_623; 3431 manc2h |= E1000_MNG2HOST_PORT_664; 3432 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3433 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3434 } 3435 } 3436 3437 /* 3438 * Give control back to hardware management 3439 * controller if there is one. 3440 */ 3441 static void 3442 em_release_manageability(struct adapter *adapter) 3443 { 3444 if (adapter->has_manage) { 3445 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3446 3447 /* re-enable hardware interception of ARP */ 3448 manc |= E1000_MANC_ARP_EN; 3449 manc &= ~E1000_MANC_EN_MNG2HOST; 3450 3451 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3452 } 3453 } 3454 3455 /* 3456 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3457 * For ASF and Pass Through versions of f/w this means 3458 * that the driver is loaded. For AMT version type f/w 3459 * this means that the network i/f is open. 3460 */ 3461 static void 3462 em_get_hw_control(struct adapter *adapter) 3463 { 3464 u32 ctrl_ext, swsm; 3465 3466 if (adapter->vf_ifp) 3467 return; 3468 3469 if (adapter->hw.mac.type == e1000_82573) { 3470 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3471 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3472 swsm | E1000_SWSM_DRV_LOAD); 3473 return; 3474 } 3475 /* else */ 3476 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3477 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3478 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3479 } 3480 3481 /* 3482 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3483 * For ASF and Pass Through versions of f/w this means that 3484 * the driver is no longer loaded. For AMT versions of the 3485 * f/w this means that the network i/f is closed. 3486 */ 3487 static void 3488 em_release_hw_control(struct adapter *adapter) 3489 { 3490 u32 ctrl_ext, swsm; 3491 3492 if (!adapter->has_manage) 3493 return; 3494 3495 if (adapter->hw.mac.type == e1000_82573) { 3496 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3497 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3498 swsm & ~E1000_SWSM_DRV_LOAD); 3499 return; 3500 } 3501 /* else */ 3502 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3503 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3504 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3505 return; 3506 } 3507 3508 static int 3509 em_is_valid_ether_addr(u8 *addr) 3510 { 3511 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3512 3513 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3514 return (FALSE); 3515 } 3516 3517 return (TRUE); 3518 } 3519 3520 /* 3521 ** Parse the interface capabilities with regard 3522 ** to both system management and wake-on-lan for 3523 ** later use. 3524 */ 3525 static void 3526 em_get_wakeup(if_ctx_t ctx) 3527 { 3528 struct adapter *adapter = iflib_get_softc(ctx); 3529 device_t dev = iflib_get_dev(ctx); 3530 u16 eeprom_data = 0, device_id, apme_mask; 3531 3532 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3533 apme_mask = EM_EEPROM_APME; 3534 3535 switch (adapter->hw.mac.type) { 3536 case e1000_82542: 3537 case e1000_82543: 3538 break; 3539 case e1000_82544: 3540 e1000_read_nvm(&adapter->hw, 3541 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3542 apme_mask = EM_82544_APME; 3543 break; 3544 case e1000_82546: 3545 case e1000_82546_rev_3: 3546 if (adapter->hw.bus.func == 1) { 3547 e1000_read_nvm(&adapter->hw, 3548 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3549 break; 3550 } else 3551 e1000_read_nvm(&adapter->hw, 3552 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3553 break; 3554 case e1000_82573: 3555 case e1000_82583: 3556 adapter->has_amt = TRUE; 3557 /* FALLTHROUGH */ 3558 case e1000_82571: 3559 case e1000_82572: 3560 case e1000_80003es2lan: 3561 if (adapter->hw.bus.func == 1) { 3562 e1000_read_nvm(&adapter->hw, 3563 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3564 break; 3565 } else 3566 e1000_read_nvm(&adapter->hw, 3567 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3568 break; 3569 case e1000_ich8lan: 3570 case e1000_ich9lan: 3571 case e1000_ich10lan: 3572 case e1000_pchlan: 3573 case e1000_pch2lan: 3574 case e1000_pch_lpt: 3575 case e1000_pch_spt: 3576 case e1000_82575: /* listing all igb devices */ 3577 case e1000_82576: 3578 case e1000_82580: 3579 case e1000_i350: 3580 case e1000_i354: 3581 case e1000_i210: 3582 case e1000_i211: 3583 case e1000_vfadapt: 3584 case e1000_vfadapt_i350: 3585 apme_mask = E1000_WUC_APME; 3586 adapter->has_amt = TRUE; 3587 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3588 break; 3589 default: 3590 e1000_read_nvm(&adapter->hw, 3591 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3592 break; 3593 } 3594 if (eeprom_data & apme_mask) 3595 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3596 /* 3597 * We have the eeprom settings, now apply the special cases 3598 * where the eeprom may be wrong or the board won't support 3599 * wake on lan on a particular port 3600 */ 3601 device_id = pci_get_device(dev); 3602 switch (device_id) { 3603 case E1000_DEV_ID_82546GB_PCIE: 3604 adapter->wol = 0; 3605 break; 3606 case E1000_DEV_ID_82546EB_FIBER: 3607 case E1000_DEV_ID_82546GB_FIBER: 3608 /* Wake events only supported on port A for dual fiber 3609 * regardless of eeprom setting */ 3610 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3611 E1000_STATUS_FUNC_1) 3612 adapter->wol = 0; 3613 break; 3614 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3615 /* if quad port adapter, disable WoL on all but port A */ 3616 if (global_quad_port_a != 0) 3617 adapter->wol = 0; 3618 /* Reset for multiple quad port adapters */ 3619 if (++global_quad_port_a == 4) 3620 global_quad_port_a = 0; 3621 break; 3622 case E1000_DEV_ID_82571EB_FIBER: 3623 /* Wake events only supported on port A for dual fiber 3624 * regardless of eeprom setting */ 3625 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3626 E1000_STATUS_FUNC_1) 3627 adapter->wol = 0; 3628 break; 3629 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3630 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3631 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3632 /* if quad port adapter, disable WoL on all but port A */ 3633 if (global_quad_port_a != 0) 3634 adapter->wol = 0; 3635 /* Reset for multiple quad port adapters */ 3636 if (++global_quad_port_a == 4) 3637 global_quad_port_a = 0; 3638 break; 3639 } 3640 return; 3641 } 3642 3643 3644 /* 3645 * Enable PCI Wake On Lan capability 3646 */ 3647 static void 3648 em_enable_wakeup(if_ctx_t ctx) 3649 { 3650 struct adapter *adapter = iflib_get_softc(ctx); 3651 device_t dev = iflib_get_dev(ctx); 3652 if_t ifp = iflib_get_ifp(ctx); 3653 int error = 0; 3654 u32 pmc, ctrl, ctrl_ext, rctl; 3655 u16 status; 3656 3657 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3658 return; 3659 3660 /* 3661 * Determine type of Wakeup: note that wol 3662 * is set with all bits on by default. 3663 */ 3664 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3665 adapter->wol &= ~E1000_WUFC_MAG; 3666 3667 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3668 adapter->wol &= ~E1000_WUFC_EX; 3669 3670 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3671 adapter->wol &= ~E1000_WUFC_MC; 3672 else { 3673 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3674 rctl |= E1000_RCTL_MPE; 3675 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3676 } 3677 3678 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 3679 goto pme; 3680 3681 /* Advertise the wakeup capability */ 3682 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3683 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3684 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3685 3686 /* Keep the laser running on Fiber adapters */ 3687 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3688 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3689 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3690 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3691 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3692 } 3693 3694 if ((adapter->hw.mac.type == e1000_ich8lan) || 3695 (adapter->hw.mac.type == e1000_pchlan) || 3696 (adapter->hw.mac.type == e1000_ich9lan) || 3697 (adapter->hw.mac.type == e1000_ich10lan)) 3698 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3699 3700 if ( adapter->hw.mac.type >= e1000_pchlan) { 3701 error = em_enable_phy_wakeup(adapter); 3702 if (error) 3703 goto pme; 3704 } else { 3705 /* Enable wakeup by the MAC */ 3706 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3707 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3708 } 3709 3710 if (adapter->hw.phy.type == e1000_phy_igp_3) 3711 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3712 3713 pme: 3714 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3715 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3716 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3717 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3718 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3719 3720 return; 3721 } 3722 3723 /* 3724 * WOL in the newer chipset interfaces (pchlan) 3725 * require thing to be copied into the phy 3726 */ 3727 static int 3728 em_enable_phy_wakeup(struct adapter *adapter) 3729 { 3730 struct e1000_hw *hw = &adapter->hw; 3731 u32 mreg, ret = 0; 3732 u16 preg; 3733 3734 /* copy MAC RARs to PHY RARs */ 3735 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3736 3737 /* copy MAC MTA to PHY MTA */ 3738 for (int i = 0; i < adapter->hw.mac.mta_reg_count; i++) { 3739 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3740 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3741 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3742 (u16)((mreg >> 16) & 0xFFFF)); 3743 } 3744 3745 /* configure PHY Rx Control register */ 3746 e1000_read_phy_reg(&adapter->hw, BM_RCTL, &preg); 3747 mreg = E1000_READ_REG(hw, E1000_RCTL); 3748 if (mreg & E1000_RCTL_UPE) 3749 preg |= BM_RCTL_UPE; 3750 if (mreg & E1000_RCTL_MPE) 3751 preg |= BM_RCTL_MPE; 3752 preg &= ~(BM_RCTL_MO_MASK); 3753 if (mreg & E1000_RCTL_MO_3) 3754 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3755 << BM_RCTL_MO_SHIFT); 3756 if (mreg & E1000_RCTL_BAM) 3757 preg |= BM_RCTL_BAM; 3758 if (mreg & E1000_RCTL_PMCF) 3759 preg |= BM_RCTL_PMCF; 3760 mreg = E1000_READ_REG(hw, E1000_CTRL); 3761 if (mreg & E1000_CTRL_RFCE) 3762 preg |= BM_RCTL_RFCE; 3763 e1000_write_phy_reg(&adapter->hw, BM_RCTL, preg); 3764 3765 /* enable PHY wakeup in MAC register */ 3766 E1000_WRITE_REG(hw, E1000_WUC, 3767 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3768 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3769 3770 /* configure and enable PHY wakeup in PHY registers */ 3771 e1000_write_phy_reg(&adapter->hw, BM_WUFC, adapter->wol); 3772 e1000_write_phy_reg(&adapter->hw, BM_WUC, E1000_WUC_PME_EN); 3773 3774 /* activate PHY wakeup */ 3775 ret = hw->phy.ops.acquire(hw); 3776 if (ret) { 3777 printf("Could not acquire PHY\n"); 3778 return ret; 3779 } 3780 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3781 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3782 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3783 if (ret) { 3784 printf("Could not read PHY page 769\n"); 3785 goto out; 3786 } 3787 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3788 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3789 if (ret) 3790 printf("Could not set PHY Host Wakeup bit\n"); 3791 out: 3792 hw->phy.ops.release(hw); 3793 3794 return ret; 3795 } 3796 3797 static void 3798 em_if_led_func(if_ctx_t ctx, int onoff) 3799 { 3800 struct adapter *adapter = iflib_get_softc(ctx); 3801 3802 if (onoff) { 3803 e1000_setup_led(&adapter->hw); 3804 e1000_led_on(&adapter->hw); 3805 } else { 3806 e1000_led_off(&adapter->hw); 3807 e1000_cleanup_led(&adapter->hw); 3808 } 3809 } 3810 3811 /* 3812 * Disable the L0S and L1 LINK states 3813 */ 3814 static void 3815 em_disable_aspm(struct adapter *adapter) 3816 { 3817 int base, reg; 3818 u16 link_cap,link_ctrl; 3819 device_t dev = adapter->dev; 3820 3821 switch (adapter->hw.mac.type) { 3822 case e1000_82573: 3823 case e1000_82574: 3824 case e1000_82583: 3825 break; 3826 default: 3827 return; 3828 } 3829 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3830 return; 3831 reg = base + PCIER_LINK_CAP; 3832 link_cap = pci_read_config(dev, reg, 2); 3833 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3834 return; 3835 reg = base + PCIER_LINK_CTL; 3836 link_ctrl = pci_read_config(dev, reg, 2); 3837 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3838 pci_write_config(dev, reg, link_ctrl, 2); 3839 return; 3840 } 3841 3842 /********************************************************************** 3843 * 3844 * Update the board statistics counters. 3845 * 3846 **********************************************************************/ 3847 static void 3848 em_update_stats_counters(struct adapter *adapter) 3849 { 3850 3851 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3852 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3853 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3854 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3855 } 3856 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3857 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3858 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3859 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3860 3861 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3862 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3863 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3864 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3865 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3866 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3867 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3868 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3869 /* 3870 ** For watchdog management we need to know if we have been 3871 ** paused during the last interval, so capture that here. 3872 */ 3873 adapter->shared->isc_pause_frames = adapter->stats.xoffrxc; 3874 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 3875 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 3876 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 3877 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 3878 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 3879 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 3880 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 3881 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 3882 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 3883 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 3884 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 3885 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 3886 3887 /* For the 64-bit byte counters the low dword must be read first. */ 3888 /* Both registers clear on the read of the high dword */ 3889 3890 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 3891 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 3892 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 3893 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 3894 3895 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 3896 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 3897 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 3898 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 3899 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 3900 3901 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 3902 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 3903 3904 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 3905 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 3906 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 3907 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 3908 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 3909 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 3910 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 3911 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 3912 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 3913 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 3914 3915 /* Interrupt Counts */ 3916 3917 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 3918 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 3919 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 3920 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 3921 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 3922 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 3923 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 3924 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 3925 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 3926 3927 if (adapter->hw.mac.type >= e1000_82543) { 3928 adapter->stats.algnerrc += 3929 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 3930 adapter->stats.rxerrc += 3931 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 3932 adapter->stats.tncrs += 3933 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 3934 adapter->stats.cexterr += 3935 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 3936 adapter->stats.tsctc += 3937 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 3938 adapter->stats.tsctfc += 3939 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 3940 } 3941 } 3942 3943 static uint64_t 3944 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3945 { 3946 struct adapter *adapter = iflib_get_softc(ctx); 3947 struct ifnet *ifp = iflib_get_ifp(ctx); 3948 3949 switch (cnt) { 3950 case IFCOUNTER_COLLISIONS: 3951 return (adapter->stats.colc); 3952 case IFCOUNTER_IERRORS: 3953 return (adapter->dropped_pkts + adapter->stats.rxerrc + 3954 adapter->stats.crcerrs + adapter->stats.algnerrc + 3955 adapter->stats.ruc + adapter->stats.roc + 3956 adapter->stats.mpc + adapter->stats.cexterr); 3957 case IFCOUNTER_OERRORS: 3958 return (adapter->stats.ecol + adapter->stats.latecol + 3959 adapter->watchdog_events); 3960 default: 3961 return (if_get_counter_default(ifp, cnt)); 3962 } 3963 } 3964 3965 /* Export a single 32-bit register via a read-only sysctl. */ 3966 static int 3967 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3968 { 3969 struct adapter *adapter; 3970 u_int val; 3971 3972 adapter = oidp->oid_arg1; 3973 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 3974 return (sysctl_handle_int(oidp, &val, 0, req)); 3975 } 3976 3977 /* 3978 * Add sysctl variables, one per statistic, to the system. 3979 */ 3980 static void 3981 em_add_hw_stats(struct adapter *adapter) 3982 { 3983 device_t dev = iflib_get_dev(adapter->ctx); 3984 struct em_tx_queue *tx_que = adapter->tx_queues; 3985 struct em_rx_queue *rx_que = adapter->rx_queues; 3986 3987 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3988 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3989 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3990 struct e1000_hw_stats *stats = &adapter->stats; 3991 3992 struct sysctl_oid *stat_node, *queue_node, *int_node; 3993 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 3994 3995 #define QUEUE_NAME_LEN 32 3996 char namebuf[QUEUE_NAME_LEN]; 3997 3998 /* Driver Statistics */ 3999 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4000 CTLFLAG_RD, &adapter->dropped_pkts, 4001 "Driver dropped packets"); 4002 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4003 CTLFLAG_RD, &adapter->link_irq, 4004 "Link MSIX IRQ Handled"); 4005 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "mbuf_defrag_fail", 4006 CTLFLAG_RD, &adapter->mbuf_defrag_failed, 4007 "Defragmenting mbuf chain failed"); 4008 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "tx_dma_fail", 4009 CTLFLAG_RD, &adapter->no_tx_dma_setup, 4010 "Driver tx dma failure in xmit"); 4011 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4012 CTLFLAG_RD, &adapter->rx_overruns, 4013 "RX overruns"); 4014 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4015 CTLFLAG_RD, &adapter->watchdog_events, 4016 "Watchdog timeouts"); 4017 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4018 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_CTRL, 4019 em_sysctl_reg_handler, "IU", 4020 "Device Control Register"); 4021 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4022 CTLTYPE_UINT | CTLFLAG_RD, adapter, E1000_RCTL, 4023 em_sysctl_reg_handler, "IU", 4024 "Receiver Control Register"); 4025 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4026 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4027 "Flow Control High Watermark"); 4028 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4029 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4030 "Flow Control Low Watermark"); 4031 4032 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4033 struct tx_ring *txr = &tx_que->txr; 4034 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4035 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4036 CTLFLAG_RD, NULL, "TX Queue Name"); 4037 queue_list = SYSCTL_CHILDREN(queue_node); 4038 4039 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4040 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4041 E1000_TDH(txr->me), 4042 em_sysctl_reg_handler, "IU", 4043 "Transmit Descriptor Head"); 4044 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4045 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4046 E1000_TDT(txr->me), 4047 em_sysctl_reg_handler, "IU", 4048 "Transmit Descriptor Tail"); 4049 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4050 CTLFLAG_RD, &txr->tx_irq, 4051 "Queue MSI-X Transmit Interrupts"); 4052 } 4053 4054 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4055 struct rx_ring *rxr = &rx_que->rxr; 4056 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4057 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4058 CTLFLAG_RD, NULL, "RX Queue Name"); 4059 queue_list = SYSCTL_CHILDREN(queue_node); 4060 4061 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4062 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4063 E1000_RDH(rxr->me), 4064 em_sysctl_reg_handler, "IU", 4065 "Receive Descriptor Head"); 4066 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4067 CTLTYPE_UINT | CTLFLAG_RD, adapter, 4068 E1000_RDT(rxr->me), 4069 em_sysctl_reg_handler, "IU", 4070 "Receive Descriptor Tail"); 4071 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4072 CTLFLAG_RD, &rxr->rx_irq, 4073 "Queue MSI-X Receive Interrupts"); 4074 } 4075 4076 /* MAC stats get their own sub node */ 4077 4078 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4079 CTLFLAG_RD, NULL, "Statistics"); 4080 stat_list = SYSCTL_CHILDREN(stat_node); 4081 4082 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4083 CTLFLAG_RD, &stats->ecol, 4084 "Excessive collisions"); 4085 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4086 CTLFLAG_RD, &stats->scc, 4087 "Single collisions"); 4088 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4089 CTLFLAG_RD, &stats->mcc, 4090 "Multiple collisions"); 4091 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4092 CTLFLAG_RD, &stats->latecol, 4093 "Late collisions"); 4094 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4095 CTLFLAG_RD, &stats->colc, 4096 "Collision Count"); 4097 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4098 CTLFLAG_RD, &adapter->stats.symerrs, 4099 "Symbol Errors"); 4100 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4101 CTLFLAG_RD, &adapter->stats.sec, 4102 "Sequence Errors"); 4103 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4104 CTLFLAG_RD, &adapter->stats.dc, 4105 "Defer Count"); 4106 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4107 CTLFLAG_RD, &adapter->stats.mpc, 4108 "Missed Packets"); 4109 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4110 CTLFLAG_RD, &adapter->stats.rnbc, 4111 "Receive No Buffers"); 4112 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4113 CTLFLAG_RD, &adapter->stats.ruc, 4114 "Receive Undersize"); 4115 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4116 CTLFLAG_RD, &adapter->stats.rfc, 4117 "Fragmented Packets Received "); 4118 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4119 CTLFLAG_RD, &adapter->stats.roc, 4120 "Oversized Packets Received"); 4121 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4122 CTLFLAG_RD, &adapter->stats.rjc, 4123 "Recevied Jabber"); 4124 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4125 CTLFLAG_RD, &adapter->stats.rxerrc, 4126 "Receive Errors"); 4127 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4128 CTLFLAG_RD, &adapter->stats.crcerrs, 4129 "CRC errors"); 4130 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4131 CTLFLAG_RD, &adapter->stats.algnerrc, 4132 "Alignment Errors"); 4133 /* On 82575 these are collision counts */ 4134 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4135 CTLFLAG_RD, &adapter->stats.cexterr, 4136 "Collision/Carrier extension errors"); 4137 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4138 CTLFLAG_RD, &adapter->stats.xonrxc, 4139 "XON Received"); 4140 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4141 CTLFLAG_RD, &adapter->stats.xontxc, 4142 "XON Transmitted"); 4143 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4144 CTLFLAG_RD, &adapter->stats.xoffrxc, 4145 "XOFF Received"); 4146 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4147 CTLFLAG_RD, &adapter->stats.xofftxc, 4148 "XOFF Transmitted"); 4149 4150 /* Packet Reception Stats */ 4151 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4152 CTLFLAG_RD, &adapter->stats.tpr, 4153 "Total Packets Received "); 4154 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4155 CTLFLAG_RD, &adapter->stats.gprc, 4156 "Good Packets Received"); 4157 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4158 CTLFLAG_RD, &adapter->stats.bprc, 4159 "Broadcast Packets Received"); 4160 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4161 CTLFLAG_RD, &adapter->stats.mprc, 4162 "Multicast Packets Received"); 4163 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4164 CTLFLAG_RD, &adapter->stats.prc64, 4165 "64 byte frames received "); 4166 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4167 CTLFLAG_RD, &adapter->stats.prc127, 4168 "65-127 byte frames received"); 4169 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4170 CTLFLAG_RD, &adapter->stats.prc255, 4171 "128-255 byte frames received"); 4172 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4173 CTLFLAG_RD, &adapter->stats.prc511, 4174 "256-511 byte frames received"); 4175 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4176 CTLFLAG_RD, &adapter->stats.prc1023, 4177 "512-1023 byte frames received"); 4178 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4179 CTLFLAG_RD, &adapter->stats.prc1522, 4180 "1023-1522 byte frames received"); 4181 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4182 CTLFLAG_RD, &adapter->stats.gorc, 4183 "Good Octets Received"); 4184 4185 /* Packet Transmission Stats */ 4186 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4187 CTLFLAG_RD, &adapter->stats.gotc, 4188 "Good Octets Transmitted"); 4189 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4190 CTLFLAG_RD, &adapter->stats.tpt, 4191 "Total Packets Transmitted"); 4192 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4193 CTLFLAG_RD, &adapter->stats.gptc, 4194 "Good Packets Transmitted"); 4195 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4196 CTLFLAG_RD, &adapter->stats.bptc, 4197 "Broadcast Packets Transmitted"); 4198 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4199 CTLFLAG_RD, &adapter->stats.mptc, 4200 "Multicast Packets Transmitted"); 4201 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4202 CTLFLAG_RD, &adapter->stats.ptc64, 4203 "64 byte frames transmitted "); 4204 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4205 CTLFLAG_RD, &adapter->stats.ptc127, 4206 "65-127 byte frames transmitted"); 4207 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4208 CTLFLAG_RD, &adapter->stats.ptc255, 4209 "128-255 byte frames transmitted"); 4210 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4211 CTLFLAG_RD, &adapter->stats.ptc511, 4212 "256-511 byte frames transmitted"); 4213 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4214 CTLFLAG_RD, &adapter->stats.ptc1023, 4215 "512-1023 byte frames transmitted"); 4216 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4217 CTLFLAG_RD, &adapter->stats.ptc1522, 4218 "1024-1522 byte frames transmitted"); 4219 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4220 CTLFLAG_RD, &adapter->stats.tsctc, 4221 "TSO Contexts Transmitted"); 4222 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4223 CTLFLAG_RD, &adapter->stats.tsctfc, 4224 "TSO Contexts Failed"); 4225 4226 4227 /* Interrupt Stats */ 4228 4229 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4230 CTLFLAG_RD, NULL, "Interrupt Statistics"); 4231 int_list = SYSCTL_CHILDREN(int_node); 4232 4233 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4234 CTLFLAG_RD, &adapter->stats.iac, 4235 "Interrupt Assertion Count"); 4236 4237 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4238 CTLFLAG_RD, &adapter->stats.icrxptc, 4239 "Interrupt Cause Rx Pkt Timer Expire Count"); 4240 4241 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4242 CTLFLAG_RD, &adapter->stats.icrxatc, 4243 "Interrupt Cause Rx Abs Timer Expire Count"); 4244 4245 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4246 CTLFLAG_RD, &adapter->stats.ictxptc, 4247 "Interrupt Cause Tx Pkt Timer Expire Count"); 4248 4249 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4250 CTLFLAG_RD, &adapter->stats.ictxatc, 4251 "Interrupt Cause Tx Abs Timer Expire Count"); 4252 4253 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4254 CTLFLAG_RD, &adapter->stats.ictxqec, 4255 "Interrupt Cause Tx Queue Empty Count"); 4256 4257 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4258 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4259 "Interrupt Cause Tx Queue Min Thresh Count"); 4260 4261 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4262 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4263 "Interrupt Cause Rx Desc Min Thresh Count"); 4264 4265 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4266 CTLFLAG_RD, &adapter->stats.icrxoc, 4267 "Interrupt Cause Receiver Overrun Count"); 4268 } 4269 4270 /********************************************************************** 4271 * 4272 * This routine provides a way to dump out the adapter eeprom, 4273 * often a useful debug/service tool. This only dumps the first 4274 * 32 words, stuff that matters is in that extent. 4275 * 4276 **********************************************************************/ 4277 static int 4278 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4279 { 4280 struct adapter *adapter = (struct adapter *)arg1; 4281 int error; 4282 int result; 4283 4284 result = -1; 4285 error = sysctl_handle_int(oidp, &result, 0, req); 4286 4287 if (error || !req->newptr) 4288 return (error); 4289 4290 /* 4291 * This value will cause a hex dump of the 4292 * first 32 16-bit words of the EEPROM to 4293 * the screen. 4294 */ 4295 if (result == 1) 4296 em_print_nvm_info(adapter); 4297 4298 return (error); 4299 } 4300 4301 static void 4302 em_print_nvm_info(struct adapter *adapter) 4303 { 4304 u16 eeprom_data; 4305 int i, j, row = 0; 4306 4307 /* Its a bit crude, but it gets the job done */ 4308 printf("\nInterface EEPROM Dump:\n"); 4309 printf("Offset\n0x0000 "); 4310 for (i = 0, j = 0; i < 32; i++, j++) { 4311 if (j == 8) { /* Make the offset block */ 4312 j = 0; ++row; 4313 printf("\n0x00%x0 ",row); 4314 } 4315 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4316 printf("%04x ", eeprom_data); 4317 } 4318 printf("\n"); 4319 } 4320 4321 static int 4322 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4323 { 4324 struct em_int_delay_info *info; 4325 struct adapter *adapter; 4326 u32 regval; 4327 int error, usecs, ticks; 4328 4329 info = (struct em_int_delay_info *) arg1; 4330 usecs = info->value; 4331 error = sysctl_handle_int(oidp, &usecs, 0, req); 4332 if (error != 0 || req->newptr == NULL) 4333 return (error); 4334 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4335 return (EINVAL); 4336 info->value = usecs; 4337 ticks = EM_USECS_TO_TICKS(usecs); 4338 if (info->offset == E1000_ITR) /* units are 256ns here */ 4339 ticks *= 4; 4340 4341 adapter = info->adapter; 4342 4343 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4344 regval = (regval & ~0xffff) | (ticks & 0xffff); 4345 /* Handle a few special cases. */ 4346 switch (info->offset) { 4347 case E1000_RDTR: 4348 break; 4349 case E1000_TIDV: 4350 if (ticks == 0) { 4351 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4352 /* Don't write 0 into the TIDV register. */ 4353 regval++; 4354 } else 4355 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4356 break; 4357 } 4358 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4359 return (0); 4360 } 4361 4362 static void 4363 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4364 const char *description, struct em_int_delay_info *info, 4365 int offset, int value) 4366 { 4367 info->adapter = adapter; 4368 info->offset = offset; 4369 info->value = value; 4370 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4371 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4372 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4373 info, 0, em_sysctl_int_delay, "I", description); 4374 } 4375 4376 /* 4377 * Set flow control using sysctl: 4378 * Flow control values: 4379 * 0 - off 4380 * 1 - rx pause 4381 * 2 - tx pause 4382 * 3 - full 4383 */ 4384 static int 4385 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4386 { 4387 int error; 4388 static int input = 3; /* default is full */ 4389 struct adapter *adapter = (struct adapter *) arg1; 4390 4391 error = sysctl_handle_int(oidp, &input, 0, req); 4392 4393 if ((error) || (req->newptr == NULL)) 4394 return (error); 4395 4396 if (input == adapter->fc) /* no change? */ 4397 return (error); 4398 4399 switch (input) { 4400 case e1000_fc_rx_pause: 4401 case e1000_fc_tx_pause: 4402 case e1000_fc_full: 4403 case e1000_fc_none: 4404 adapter->hw.fc.requested_mode = input; 4405 adapter->fc = input; 4406 break; 4407 default: 4408 /* Do nothing */ 4409 return (error); 4410 } 4411 4412 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4413 e1000_force_mac_fc(&adapter->hw); 4414 return (error); 4415 } 4416 4417 /* 4418 * Manage Energy Efficient Ethernet: 4419 * Control values: 4420 * 0/1 - enabled/disabled 4421 */ 4422 static int 4423 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4424 { 4425 struct adapter *adapter = (struct adapter *) arg1; 4426 int error, value; 4427 4428 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4429 error = sysctl_handle_int(oidp, &value, 0, req); 4430 if (error || req->newptr == NULL) 4431 return (error); 4432 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4433 em_if_init(adapter->ctx); 4434 4435 return (0); 4436 } 4437 4438 static int 4439 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4440 { 4441 struct adapter *adapter; 4442 int error; 4443 int result; 4444 4445 result = -1; 4446 error = sysctl_handle_int(oidp, &result, 0, req); 4447 4448 if (error || !req->newptr) 4449 return (error); 4450 4451 if (result == 1) { 4452 adapter = (struct adapter *) arg1; 4453 em_print_debug_info(adapter); 4454 } 4455 4456 return (error); 4457 } 4458 4459 static int 4460 em_get_rs(SYSCTL_HANDLER_ARGS) 4461 { 4462 struct adapter *adapter = (struct adapter *) arg1; 4463 int error; 4464 int result; 4465 4466 result = 0; 4467 error = sysctl_handle_int(oidp, &result, 0, req); 4468 4469 if (error || !req->newptr || result != 1) 4470 return (error); 4471 em_dump_rs(adapter); 4472 4473 return (error); 4474 } 4475 4476 static void 4477 em_if_debug(if_ctx_t ctx) 4478 { 4479 em_dump_rs(iflib_get_softc(ctx)); 4480 } 4481 4482 /* 4483 * This routine is meant to be fluid, add whatever is 4484 * needed for debugging a problem. -jfv 4485 */ 4486 static void 4487 em_print_debug_info(struct adapter *adapter) 4488 { 4489 device_t dev = iflib_get_dev(adapter->ctx); 4490 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4491 struct tx_ring *txr = &adapter->tx_queues->txr; 4492 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4493 4494 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4495 printf("Interface is RUNNING "); 4496 else 4497 printf("Interface is NOT RUNNING\n"); 4498 4499 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4500 printf("and INACTIVE\n"); 4501 else 4502 printf("and ACTIVE\n"); 4503 4504 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4505 device_printf(dev, "TX Queue %d ------\n", i); 4506 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4507 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4508 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4509 4510 } 4511 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4512 device_printf(dev, "RX Queue %d ------\n", j); 4513 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4514 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4515 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4516 } 4517 } 4518 4519 /* 4520 * 82574 only: 4521 * Write a new value to the EEPROM increasing the number of MSIX 4522 * vectors from 3 to 5, for proper multiqueue support. 4523 */ 4524 static void 4525 em_enable_vectors_82574(if_ctx_t ctx) 4526 { 4527 struct adapter *adapter = iflib_get_softc(ctx); 4528 struct e1000_hw *hw = &adapter->hw; 4529 device_t dev = iflib_get_dev(ctx); 4530 u16 edata; 4531 4532 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4533 printf("Current cap: %#06x\n", edata); 4534 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4535 device_printf(dev, "Writing to eeprom: increasing " 4536 "reported MSIX vectors from 3 to 5...\n"); 4537 edata &= ~(EM_NVM_MSIX_N_MASK); 4538 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4539 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4540 e1000_update_nvm_checksum(hw); 4541 device_printf(dev, "Writing to eeprom: done\n"); 4542 } 4543 } 4544