1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.6.1-k"; 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last field stores an index into e1000_strings 47 * Last entry must be all 0s 48 * 49 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 50 *********************************************************************/ 51 52 static pci_vendor_info_t em_vendor_info_array[] = 53 { 54 /* Intel(R) - lem-class legacy devices */ 55 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 56 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 57 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 58 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 60 61 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 62 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 63 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 65 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 66 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 68 69 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 70 71 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 72 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 73 74 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 75 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 76 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 78 79 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 80 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 81 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 84 85 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 86 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 88 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 95 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 96 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 97 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 98 99 /* Intel(R) - em-class devices */ 100 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 108 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 109 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 113 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 114 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 116 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 117 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 121 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 139 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 140 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 148 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 150 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 152 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 197 /* required last entry */ 198 PVID_END 199 }; 200 201 static pci_vendor_info_t igb_vendor_info_array[] = 202 { 203 /* Intel(R) - igb-class devices */ 204 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 205 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 206 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 207 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 208 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 209 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 210 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 211 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 212 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 213 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 214 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 215 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 216 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 217 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 218 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 219 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 220 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 221 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 222 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 224 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 225 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 226 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 227 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 230 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 231 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 232 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 233 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 234 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 235 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 238 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 239 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 240 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 241 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 242 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 244 /* required last entry */ 245 PVID_END 246 }; 247 248 /********************************************************************* 249 * Function prototypes 250 *********************************************************************/ 251 static void *em_register(device_t dev); 252 static void *igb_register(device_t dev); 253 static int em_if_attach_pre(if_ctx_t ctx); 254 static int em_if_attach_post(if_ctx_t ctx); 255 static int em_if_detach(if_ctx_t ctx); 256 static int em_if_shutdown(if_ctx_t ctx); 257 static int em_if_suspend(if_ctx_t ctx); 258 static int em_if_resume(if_ctx_t ctx); 259 260 static int em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 261 static int em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 262 static void em_if_queues_free(if_ctx_t ctx); 263 264 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 265 static void em_if_init(if_ctx_t ctx); 266 static void em_if_stop(if_ctx_t ctx); 267 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 268 static int em_if_media_change(if_ctx_t ctx); 269 static int em_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 270 static void em_if_timer(if_ctx_t ctx, uint16_t qid); 271 static void em_if_vlan_register(if_ctx_t ctx, u16 vtag); 272 static void em_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 273 static void em_if_watchdog_reset(if_ctx_t ctx); 274 static bool em_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 275 276 static void em_identify_hardware(if_ctx_t ctx); 277 static int em_allocate_pci_resources(if_ctx_t ctx); 278 static void em_free_pci_resources(if_ctx_t ctx); 279 static void em_reset(if_ctx_t ctx); 280 static int em_setup_interface(if_ctx_t ctx); 281 static int em_setup_msix(if_ctx_t ctx); 282 283 static void em_initialize_transmit_unit(if_ctx_t ctx); 284 static void em_initialize_receive_unit(if_ctx_t ctx); 285 286 static void em_if_intr_enable(if_ctx_t ctx); 287 static void em_if_intr_disable(if_ctx_t ctx); 288 static void igb_if_intr_enable(if_ctx_t ctx); 289 static void igb_if_intr_disable(if_ctx_t ctx); 290 static int em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 291 static int em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 292 static int igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 293 static int igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 294 static void em_if_multi_set(if_ctx_t ctx); 295 static void em_if_update_admin_status(if_ctx_t ctx); 296 static void em_if_debug(if_ctx_t ctx); 297 static void em_update_stats_counters(struct adapter *); 298 static void em_add_hw_stats(struct adapter *adapter); 299 static int em_if_set_promisc(if_ctx_t ctx, int flags); 300 static void em_setup_vlan_hw_support(struct adapter *); 301 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 302 static void em_print_nvm_info(struct adapter *); 303 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 304 static int em_get_rs(SYSCTL_HANDLER_ARGS); 305 static void em_print_debug_info(struct adapter *); 306 static int em_is_valid_ether_addr(u8 *); 307 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 308 static void em_add_int_delay_sysctl(struct adapter *, const char *, 309 const char *, struct em_int_delay_info *, int, int); 310 /* Management and WOL Support */ 311 static void em_init_manageability(struct adapter *); 312 static void em_release_manageability(struct adapter *); 313 static void em_get_hw_control(struct adapter *); 314 static void em_release_hw_control(struct adapter *); 315 static void em_get_wakeup(if_ctx_t ctx); 316 static void em_enable_wakeup(if_ctx_t ctx); 317 static int em_enable_phy_wakeup(struct adapter *); 318 static void em_disable_aspm(struct adapter *); 319 320 int em_intr(void *arg); 321 322 /* MSI-X handlers */ 323 static int em_if_msix_intr_assign(if_ctx_t, int); 324 static int em_msix_link(void *); 325 static void em_handle_link(void *context); 326 327 static void em_enable_vectors_82574(if_ctx_t); 328 329 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 330 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 331 static void em_if_led_func(if_ctx_t ctx, int onoff); 332 333 static int em_get_regs(SYSCTL_HANDLER_ARGS); 334 335 static void lem_smartspeed(struct adapter *adapter); 336 static void igb_configure_queues(struct adapter *adapter); 337 338 339 /********************************************************************* 340 * FreeBSD Device Interface Entry Points 341 *********************************************************************/ 342 static device_method_t em_methods[] = { 343 /* Device interface */ 344 DEVMETHOD(device_register, em_register), 345 DEVMETHOD(device_probe, iflib_device_probe), 346 DEVMETHOD(device_attach, iflib_device_attach), 347 DEVMETHOD(device_detach, iflib_device_detach), 348 DEVMETHOD(device_shutdown, iflib_device_shutdown), 349 DEVMETHOD(device_suspend, iflib_device_suspend), 350 DEVMETHOD(device_resume, iflib_device_resume), 351 DEVMETHOD_END 352 }; 353 354 static device_method_t igb_methods[] = { 355 /* Device interface */ 356 DEVMETHOD(device_register, igb_register), 357 DEVMETHOD(device_probe, iflib_device_probe), 358 DEVMETHOD(device_attach, iflib_device_attach), 359 DEVMETHOD(device_detach, iflib_device_detach), 360 DEVMETHOD(device_shutdown, iflib_device_shutdown), 361 DEVMETHOD(device_suspend, iflib_device_suspend), 362 DEVMETHOD(device_resume, iflib_device_resume), 363 DEVMETHOD_END 364 }; 365 366 367 static driver_t em_driver = { 368 "em", em_methods, sizeof(struct adapter), 369 }; 370 371 static devclass_t em_devclass; 372 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 373 374 MODULE_DEPEND(em, pci, 1, 1, 1); 375 MODULE_DEPEND(em, ether, 1, 1, 1); 376 MODULE_DEPEND(em, iflib, 1, 1, 1); 377 378 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 379 380 static driver_t igb_driver = { 381 "igb", igb_methods, sizeof(struct adapter), 382 }; 383 384 static devclass_t igb_devclass; 385 DRIVER_MODULE(igb, pci, igb_driver, igb_devclass, 0, 0); 386 387 MODULE_DEPEND(igb, pci, 1, 1, 1); 388 MODULE_DEPEND(igb, ether, 1, 1, 1); 389 MODULE_DEPEND(igb, iflib, 1, 1, 1); 390 391 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 392 393 static device_method_t em_if_methods[] = { 394 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 395 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 396 DEVMETHOD(ifdi_detach, em_if_detach), 397 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 398 DEVMETHOD(ifdi_suspend, em_if_suspend), 399 DEVMETHOD(ifdi_resume, em_if_resume), 400 DEVMETHOD(ifdi_init, em_if_init), 401 DEVMETHOD(ifdi_stop, em_if_stop), 402 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 403 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 404 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 405 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 406 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 407 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 408 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 409 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 410 DEVMETHOD(ifdi_media_status, em_if_media_status), 411 DEVMETHOD(ifdi_media_change, em_if_media_change), 412 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 413 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 414 DEVMETHOD(ifdi_timer, em_if_timer), 415 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 416 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 417 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 418 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 419 DEVMETHOD(ifdi_led_func, em_if_led_func), 420 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 421 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 422 DEVMETHOD(ifdi_debug, em_if_debug), 423 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 424 DEVMETHOD_END 425 }; 426 427 static driver_t em_if_driver = { 428 "em_if", em_if_methods, sizeof(struct adapter) 429 }; 430 431 static device_method_t igb_if_methods[] = { 432 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 433 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 434 DEVMETHOD(ifdi_detach, em_if_detach), 435 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 436 DEVMETHOD(ifdi_suspend, em_if_suspend), 437 DEVMETHOD(ifdi_resume, em_if_resume), 438 DEVMETHOD(ifdi_init, em_if_init), 439 DEVMETHOD(ifdi_stop, em_if_stop), 440 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 441 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 442 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 443 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 444 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 445 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 446 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 447 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 448 DEVMETHOD(ifdi_media_status, em_if_media_status), 449 DEVMETHOD(ifdi_media_change, em_if_media_change), 450 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 451 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 452 DEVMETHOD(ifdi_timer, em_if_timer), 453 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 454 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 455 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 456 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 457 DEVMETHOD(ifdi_led_func, em_if_led_func), 458 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 459 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 460 DEVMETHOD(ifdi_debug, em_if_debug), 461 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 462 DEVMETHOD_END 463 }; 464 465 static driver_t igb_if_driver = { 466 "igb_if", igb_if_methods, sizeof(struct adapter) 467 }; 468 469 /********************************************************************* 470 * Tunable default values. 471 *********************************************************************/ 472 473 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 474 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 475 476 #define MAX_INTS_PER_SEC 8000 477 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 478 479 /* Allow common code without TSO */ 480 #ifndef CSUM_TSO 481 #define CSUM_TSO 0 482 #endif 483 484 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 485 "EM driver parameters"); 486 487 static int em_disable_crc_stripping = 0; 488 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 489 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 490 491 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 492 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 493 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 494 0, "Default transmit interrupt delay in usecs"); 495 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 496 0, "Default receive interrupt delay in usecs"); 497 498 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 499 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 500 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 501 &em_tx_abs_int_delay_dflt, 0, 502 "Default transmit interrupt delay limit in usecs"); 503 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 504 &em_rx_abs_int_delay_dflt, 0, 505 "Default receive interrupt delay limit in usecs"); 506 507 static int em_smart_pwr_down = FALSE; 508 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 509 0, "Set to true to leave smart power down enabled on newer adapters"); 510 511 /* Controls whether promiscuous also shows bad packets */ 512 static int em_debug_sbp = FALSE; 513 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 514 "Show bad packets in promiscuous mode"); 515 516 /* How many packets rxeof tries to clean at a time */ 517 static int em_rx_process_limit = 100; 518 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 519 &em_rx_process_limit, 0, 520 "Maximum number of received packets to process " 521 "at a time, -1 means unlimited"); 522 523 /* Energy efficient ethernet - default to OFF */ 524 static int eee_setting = 1; 525 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 526 "Enable Energy Efficient Ethernet"); 527 528 /* 529 ** Tuneable Interrupt rate 530 */ 531 static int em_max_interrupt_rate = 8000; 532 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 533 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 534 535 536 537 /* Global used in WOL setup with multiport cards */ 538 static int global_quad_port_a = 0; 539 540 extern struct if_txrx igb_txrx; 541 extern struct if_txrx em_txrx; 542 extern struct if_txrx lem_txrx; 543 544 static struct if_shared_ctx em_sctx_init = { 545 .isc_magic = IFLIB_MAGIC, 546 .isc_q_align = PAGE_SIZE, 547 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 548 .isc_tx_maxsegsize = PAGE_SIZE, 549 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 550 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 551 .isc_rx_maxsize = MJUM9BYTES, 552 .isc_rx_nsegments = 1, 553 .isc_rx_maxsegsize = MJUM9BYTES, 554 .isc_nfl = 1, 555 .isc_nrxqs = 1, 556 .isc_ntxqs = 1, 557 .isc_admin_intrcnt = 1, 558 .isc_vendor_info = em_vendor_info_array, 559 .isc_driver_version = em_driver_version, 560 .isc_driver = &em_if_driver, 561 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 562 563 .isc_nrxd_min = {EM_MIN_RXD}, 564 .isc_ntxd_min = {EM_MIN_TXD}, 565 .isc_nrxd_max = {EM_MAX_RXD}, 566 .isc_ntxd_max = {EM_MAX_TXD}, 567 .isc_nrxd_default = {EM_DEFAULT_RXD}, 568 .isc_ntxd_default = {EM_DEFAULT_TXD}, 569 }; 570 571 static struct if_shared_ctx igb_sctx_init = { 572 .isc_magic = IFLIB_MAGIC, 573 .isc_q_align = PAGE_SIZE, 574 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 575 .isc_tx_maxsegsize = PAGE_SIZE, 576 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 577 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 578 .isc_rx_maxsize = MJUM9BYTES, 579 .isc_rx_nsegments = 1, 580 .isc_rx_maxsegsize = MJUM9BYTES, 581 .isc_nfl = 1, 582 .isc_nrxqs = 1, 583 .isc_ntxqs = 1, 584 .isc_admin_intrcnt = 1, 585 .isc_vendor_info = igb_vendor_info_array, 586 .isc_driver_version = em_driver_version, 587 .isc_driver = &igb_if_driver, 588 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 589 590 .isc_nrxd_min = {EM_MIN_RXD}, 591 .isc_ntxd_min = {EM_MIN_TXD}, 592 .isc_nrxd_max = {IGB_MAX_RXD}, 593 .isc_ntxd_max = {IGB_MAX_TXD}, 594 .isc_nrxd_default = {EM_DEFAULT_RXD}, 595 .isc_ntxd_default = {EM_DEFAULT_TXD}, 596 }; 597 598 /***************************************************************** 599 * 600 * Dump Registers 601 * 602 ****************************************************************/ 603 #define IGB_REGS_LEN 739 604 605 static int em_get_regs(SYSCTL_HANDLER_ARGS) 606 { 607 struct adapter *adapter = (struct adapter *)arg1; 608 struct e1000_hw *hw = &adapter->hw; 609 struct sbuf *sb; 610 u32 *regs_buff; 611 int rc; 612 613 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 614 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 615 616 rc = sysctl_wire_old_buffer(req, 0); 617 MPASS(rc == 0); 618 if (rc != 0) { 619 free(regs_buff, M_DEVBUF); 620 return (rc); 621 } 622 623 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 624 MPASS(sb != NULL); 625 if (sb == NULL) { 626 free(regs_buff, M_DEVBUF); 627 return (ENOMEM); 628 } 629 630 /* General Registers */ 631 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 632 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 633 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 634 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 635 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 636 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 637 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 638 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 639 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 640 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 641 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 642 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 643 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 644 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 645 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 646 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 647 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 648 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 649 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 650 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 651 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 652 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 653 654 sbuf_printf(sb, "General Registers\n"); 655 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 656 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 657 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 658 659 sbuf_printf(sb, "Interrupt Registers\n"); 660 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 661 662 sbuf_printf(sb, "RX Registers\n"); 663 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 664 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 665 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 666 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 667 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 668 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 669 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 670 671 sbuf_printf(sb, "TX Registers\n"); 672 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 673 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 674 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 675 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 676 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 677 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 678 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 679 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 680 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 681 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 682 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 683 684 free(regs_buff, M_DEVBUF); 685 686 #ifdef DUMP_DESCS 687 { 688 if_softc_ctx_t scctx = adapter->shared; 689 struct rx_ring *rxr = &rx_que->rxr; 690 struct tx_ring *txr = &tx_que->txr; 691 int ntxd = scctx->isc_ntxd[0]; 692 int nrxd = scctx->isc_nrxd[0]; 693 int j; 694 695 for (j = 0; j < nrxd; j++) { 696 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 697 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 698 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 699 } 700 701 for (j = 0; j < min(ntxd, 256); j++) { 702 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 703 704 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 705 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 706 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 707 708 } 709 } 710 #endif 711 712 rc = sbuf_finish(sb); 713 sbuf_delete(sb); 714 return(rc); 715 } 716 717 static void * 718 em_register(device_t dev) 719 { 720 return (&em_sctx_init); 721 } 722 723 static void * 724 igb_register(device_t dev) 725 { 726 return (&igb_sctx_init); 727 } 728 729 static int 730 em_set_num_queues(if_ctx_t ctx) 731 { 732 struct adapter *adapter = iflib_get_softc(ctx); 733 int maxqueues; 734 735 /* Sanity check based on HW */ 736 switch (adapter->hw.mac.type) { 737 case e1000_82576: 738 case e1000_82580: 739 case e1000_i350: 740 case e1000_i354: 741 maxqueues = 8; 742 break; 743 case e1000_i210: 744 case e1000_82575: 745 maxqueues = 4; 746 break; 747 case e1000_i211: 748 case e1000_82574: 749 maxqueues = 2; 750 break; 751 default: 752 maxqueues = 1; 753 break; 754 } 755 756 return (maxqueues); 757 } 758 759 #define LEM_CAPS \ 760 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 761 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER 762 763 #define EM_CAPS \ 764 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 765 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 766 IFCAP_LRO | IFCAP_VLAN_HWTSO 767 768 #define IGB_CAPS \ 769 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 770 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 771 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 772 IFCAP_TSO6 773 774 /********************************************************************* 775 * Device initialization routine 776 * 777 * The attach entry point is called when the driver is being loaded. 778 * This routine identifies the type of hardware, allocates all resources 779 * and initializes the hardware. 780 * 781 * return 0 on success, positive on failure 782 *********************************************************************/ 783 static int 784 em_if_attach_pre(if_ctx_t ctx) 785 { 786 struct adapter *adapter; 787 if_softc_ctx_t scctx; 788 device_t dev; 789 struct e1000_hw *hw; 790 int error = 0; 791 792 INIT_DEBUGOUT("em_if_attach_pre: begin"); 793 dev = iflib_get_dev(ctx); 794 adapter = iflib_get_softc(ctx); 795 796 adapter->ctx = adapter->osdep.ctx = ctx; 797 adapter->dev = adapter->osdep.dev = dev; 798 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 799 adapter->media = iflib_get_media(ctx); 800 hw = &adapter->hw; 801 802 adapter->tx_process_limit = scctx->isc_ntxd[0]; 803 804 /* SYSCTL stuff */ 805 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 806 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 807 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 808 adapter, 0, em_sysctl_nvm_info, "I", "NVM Information"); 809 810 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 811 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 812 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 813 adapter, 0, em_sysctl_debug_info, "I", "Debug Information"); 814 815 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 817 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 818 adapter, 0, em_set_flowcntl, "I", "Flow Control"); 819 820 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 821 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 822 OID_AUTO, "reg_dump", 823 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 824 em_get_regs, "A", "Dump Registers"); 825 826 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 827 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 828 OID_AUTO, "rs_dump", 829 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 830 em_get_rs, "I", "Dump RS indexes"); 831 832 /* Determine hardware and mac info */ 833 em_identify_hardware(ctx); 834 835 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 836 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 837 if (bootverbose) 838 device_printf(dev, "attach_pre capping queues at %d\n", 839 scctx->isc_ntxqsets_max); 840 841 if (hw->mac.type >= igb_mac_min) { 842 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 843 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 844 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 845 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 846 scctx->isc_txrx = &igb_txrx; 847 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 848 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 849 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 850 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 851 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 852 CSUM_IP6_TCP | CSUM_IP6_UDP; 853 if (hw->mac.type != e1000_82575) 854 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 855 /* 856 ** Some new devices, as with ixgbe, now may 857 ** use a different BAR, so we need to keep 858 ** track of which is used. 859 */ 860 scctx->isc_msix_bar = pci_msix_table_bar(dev); 861 } else if (hw->mac.type >= em_mac_min) { 862 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 863 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 864 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 865 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 866 scctx->isc_txrx = &em_txrx; 867 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 868 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 869 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 870 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 871 /* 872 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO} 873 * by default as we don't have workarounds for all associated 874 * silicon errata. E. g., with several MACs such as 82573E, 875 * TSO only works at Gigabit speed and otherwise can cause the 876 * hardware to hang (which also would be next to impossible to 877 * work around given that already queued TSO-using descriptors 878 * would need to be flushed and vlan(4) reconfigured at runtime 879 * in case of a link speed change). Moreover, MACs like 82579 880 * still can hang at Gigabit even with all publicly documented 881 * TSO workarounds implemented. Generally, the penality of 882 * these workarounds is rather high and may involve copying 883 * mbuf data around so advantages of TSO lapse. Still, TSO may 884 * work for a few MACs of this class - at least when sticking 885 * with Gigabit - in which case users may enable TSO manually. 886 */ 887 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 888 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO; 889 /* 890 * We support MSI-X with 82574 only, but indicate to iflib(4) 891 * that it shall give MSI at least a try with other devices. 892 */ 893 if (hw->mac.type == e1000_82574) { 894 scctx->isc_msix_bar = pci_msix_table_bar(dev);; 895 } else { 896 scctx->isc_msix_bar = -1; 897 scctx->isc_disable_msix = 1; 898 } 899 } else { 900 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 901 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 902 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 903 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 904 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 905 scctx->isc_txrx = &lem_txrx; 906 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 907 if (hw->mac.type < e1000_82543) 908 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 909 /* INTx only */ 910 scctx->isc_msix_bar = 0; 911 } 912 913 /* Setup PCI resources */ 914 if (em_allocate_pci_resources(ctx)) { 915 device_printf(dev, "Allocation of PCI resources failed\n"); 916 error = ENXIO; 917 goto err_pci; 918 } 919 920 /* 921 ** For ICH8 and family we need to 922 ** map the flash memory, and this 923 ** must happen after the MAC is 924 ** identified 925 */ 926 if ((hw->mac.type == e1000_ich8lan) || 927 (hw->mac.type == e1000_ich9lan) || 928 (hw->mac.type == e1000_ich10lan) || 929 (hw->mac.type == e1000_pchlan) || 930 (hw->mac.type == e1000_pch2lan) || 931 (hw->mac.type == e1000_pch_lpt)) { 932 int rid = EM_BAR_TYPE_FLASH; 933 adapter->flash = bus_alloc_resource_any(dev, 934 SYS_RES_MEMORY, &rid, RF_ACTIVE); 935 if (adapter->flash == NULL) { 936 device_printf(dev, "Mapping of Flash failed\n"); 937 error = ENXIO; 938 goto err_pci; 939 } 940 /* This is used in the shared code */ 941 hw->flash_address = (u8 *)adapter->flash; 942 adapter->osdep.flash_bus_space_tag = 943 rman_get_bustag(adapter->flash); 944 adapter->osdep.flash_bus_space_handle = 945 rman_get_bushandle(adapter->flash); 946 } 947 /* 948 ** In the new SPT device flash is not a 949 ** separate BAR, rather it is also in BAR0, 950 ** so use the same tag and an offset handle for the 951 ** FLASH read/write macros in the shared code. 952 */ 953 else if (hw->mac.type >= e1000_pch_spt) { 954 adapter->osdep.flash_bus_space_tag = 955 adapter->osdep.mem_bus_space_tag; 956 adapter->osdep.flash_bus_space_handle = 957 adapter->osdep.mem_bus_space_handle 958 + E1000_FLASH_BASE_ADDR; 959 } 960 961 /* Do Shared Code initialization */ 962 error = e1000_setup_init_funcs(hw, TRUE); 963 if (error) { 964 device_printf(dev, "Setup of Shared code failed, error %d\n", 965 error); 966 error = ENXIO; 967 goto err_pci; 968 } 969 970 em_setup_msix(ctx); 971 e1000_get_bus_info(hw); 972 973 /* Set up some sysctls for the tunable interrupt delays */ 974 em_add_int_delay_sysctl(adapter, "rx_int_delay", 975 "receive interrupt delay in usecs", &adapter->rx_int_delay, 976 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 977 em_add_int_delay_sysctl(adapter, "tx_int_delay", 978 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 979 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 980 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 981 "receive interrupt delay limit in usecs", 982 &adapter->rx_abs_int_delay, 983 E1000_REGISTER(hw, E1000_RADV), 984 em_rx_abs_int_delay_dflt); 985 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 986 "transmit interrupt delay limit in usecs", 987 &adapter->tx_abs_int_delay, 988 E1000_REGISTER(hw, E1000_TADV), 989 em_tx_abs_int_delay_dflt); 990 em_add_int_delay_sysctl(adapter, "itr", 991 "interrupt delay limit in usecs/4", 992 &adapter->tx_itr, 993 E1000_REGISTER(hw, E1000_ITR), 994 DEFAULT_ITR); 995 996 hw->mac.autoneg = DO_AUTO_NEG; 997 hw->phy.autoneg_wait_to_complete = FALSE; 998 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 999 1000 if (hw->mac.type < em_mac_min) { 1001 e1000_init_script_state_82541(hw, TRUE); 1002 e1000_set_tbi_compatibility_82543(hw, TRUE); 1003 } 1004 /* Copper options */ 1005 if (hw->phy.media_type == e1000_media_type_copper) { 1006 hw->phy.mdix = AUTO_ALL_MODES; 1007 hw->phy.disable_polarity_correction = FALSE; 1008 hw->phy.ms_type = EM_MASTER_SLAVE; 1009 } 1010 1011 /* 1012 * Set the frame limits assuming 1013 * standard ethernet sized frames. 1014 */ 1015 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1016 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1017 1018 /* 1019 * This controls when hardware reports transmit completion 1020 * status. 1021 */ 1022 hw->mac.report_tx_early = 1; 1023 1024 /* Allocate multicast array memory. */ 1025 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1026 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1027 if (adapter->mta == NULL) { 1028 device_printf(dev, "Can not allocate multicast setup array\n"); 1029 error = ENOMEM; 1030 goto err_late; 1031 } 1032 1033 /* Check SOL/IDER usage */ 1034 if (e1000_check_reset_block(hw)) 1035 device_printf(dev, "PHY reset is blocked" 1036 " due to SOL/IDER session.\n"); 1037 1038 /* Sysctl for setting Energy Efficient Ethernet */ 1039 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1040 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1041 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1042 OID_AUTO, "eee_control", 1043 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1044 adapter, 0, em_sysctl_eee, "I", 1045 "Disable Energy Efficient Ethernet"); 1046 1047 /* 1048 ** Start from a known state, this is 1049 ** important in reading the nvm and 1050 ** mac from that. 1051 */ 1052 e1000_reset_hw(hw); 1053 1054 /* Make sure we have a good EEPROM before we read from it */ 1055 if (e1000_validate_nvm_checksum(hw) < 0) { 1056 /* 1057 ** Some PCI-E parts fail the first check due to 1058 ** the link being in sleep state, call it again, 1059 ** if it fails a second time its a real issue. 1060 */ 1061 if (e1000_validate_nvm_checksum(hw) < 0) { 1062 device_printf(dev, 1063 "The EEPROM Checksum Is Not Valid\n"); 1064 error = EIO; 1065 goto err_late; 1066 } 1067 } 1068 1069 /* Copy the permanent MAC address out of the EEPROM */ 1070 if (e1000_read_mac_addr(hw) < 0) { 1071 device_printf(dev, "EEPROM read error while reading MAC" 1072 " address\n"); 1073 error = EIO; 1074 goto err_late; 1075 } 1076 1077 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1078 if (adapter->vf_ifp) { 1079 ether_gen_addr(iflib_get_ifp(ctx), 1080 (struct ether_addr *)hw->mac.addr); 1081 } else { 1082 device_printf(dev, "Invalid MAC address\n"); 1083 error = EIO; 1084 goto err_late; 1085 } 1086 } 1087 1088 /* 1089 * Get Wake-on-Lan and Management info for later use 1090 */ 1091 em_get_wakeup(ctx); 1092 1093 /* Enable only WOL MAGIC by default */ 1094 scctx->isc_capenable &= ~IFCAP_WOL; 1095 if (adapter->wol != 0) 1096 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1097 1098 iflib_set_mac(ctx, hw->mac.addr); 1099 1100 return (0); 1101 1102 err_late: 1103 em_release_hw_control(adapter); 1104 err_pci: 1105 em_free_pci_resources(ctx); 1106 free(adapter->mta, M_DEVBUF); 1107 1108 return (error); 1109 } 1110 1111 static int 1112 em_if_attach_post(if_ctx_t ctx) 1113 { 1114 struct adapter *adapter = iflib_get_softc(ctx); 1115 struct e1000_hw *hw = &adapter->hw; 1116 int error = 0; 1117 1118 /* Setup OS specific network interface */ 1119 error = em_setup_interface(ctx); 1120 if (error != 0) { 1121 device_printf(adapter->dev, "Interface setup failed: %d\n", error); 1122 goto err_late; 1123 } 1124 1125 em_reset(ctx); 1126 1127 /* Initialize statistics */ 1128 em_update_stats_counters(adapter); 1129 hw->mac.get_link_status = 1; 1130 em_if_update_admin_status(ctx); 1131 em_add_hw_stats(adapter); 1132 1133 /* Non-AMT based hardware can now take control from firmware */ 1134 if (adapter->has_manage && !adapter->has_amt) 1135 em_get_hw_control(adapter); 1136 1137 INIT_DEBUGOUT("em_if_attach_post: end"); 1138 1139 return (0); 1140 1141 err_late: 1142 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1143 return (error); 1144 } 1145 1146 /********************************************************************* 1147 * Device removal routine 1148 * 1149 * The detach entry point is called when the driver is being removed. 1150 * This routine stops the adapter and deallocates all the resources 1151 * that were allocated for driver operation. 1152 * 1153 * return 0 on success, positive on failure 1154 *********************************************************************/ 1155 static int 1156 em_if_detach(if_ctx_t ctx) 1157 { 1158 struct adapter *adapter = iflib_get_softc(ctx); 1159 1160 INIT_DEBUGOUT("em_if_detach: begin"); 1161 1162 e1000_phy_hw_reset(&adapter->hw); 1163 1164 em_release_manageability(adapter); 1165 em_release_hw_control(adapter); 1166 em_free_pci_resources(ctx); 1167 free(adapter->mta, M_DEVBUF); 1168 adapter->mta = NULL; 1169 1170 return (0); 1171 } 1172 1173 /********************************************************************* 1174 * 1175 * Shutdown entry point 1176 * 1177 **********************************************************************/ 1178 1179 static int 1180 em_if_shutdown(if_ctx_t ctx) 1181 { 1182 return em_if_suspend(ctx); 1183 } 1184 1185 /* 1186 * Suspend/resume device methods. 1187 */ 1188 static int 1189 em_if_suspend(if_ctx_t ctx) 1190 { 1191 struct adapter *adapter = iflib_get_softc(ctx); 1192 1193 em_release_manageability(adapter); 1194 em_release_hw_control(adapter); 1195 em_enable_wakeup(ctx); 1196 return (0); 1197 } 1198 1199 static int 1200 em_if_resume(if_ctx_t ctx) 1201 { 1202 struct adapter *adapter = iflib_get_softc(ctx); 1203 1204 if (adapter->hw.mac.type == e1000_pch2lan) 1205 e1000_resume_workarounds_pchlan(&adapter->hw); 1206 em_if_init(ctx); 1207 em_init_manageability(adapter); 1208 1209 return(0); 1210 } 1211 1212 static int 1213 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1214 { 1215 int max_frame_size; 1216 struct adapter *adapter = iflib_get_softc(ctx); 1217 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1218 1219 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1220 1221 switch (adapter->hw.mac.type) { 1222 case e1000_82571: 1223 case e1000_82572: 1224 case e1000_ich9lan: 1225 case e1000_ich10lan: 1226 case e1000_pch2lan: 1227 case e1000_pch_lpt: 1228 case e1000_pch_spt: 1229 case e1000_pch_cnp: 1230 case e1000_pch_tgp: 1231 case e1000_pch_adp: 1232 case e1000_pch_mtp: 1233 case e1000_82574: 1234 case e1000_82583: 1235 case e1000_80003es2lan: 1236 /* 9K Jumbo Frame size */ 1237 max_frame_size = 9234; 1238 break; 1239 case e1000_pchlan: 1240 max_frame_size = 4096; 1241 break; 1242 case e1000_82542: 1243 case e1000_ich8lan: 1244 /* Adapters that do not support jumbo frames */ 1245 max_frame_size = ETHER_MAX_LEN; 1246 break; 1247 default: 1248 if (adapter->hw.mac.type >= igb_mac_min) 1249 max_frame_size = 9234; 1250 else /* lem */ 1251 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1252 } 1253 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1254 return (EINVAL); 1255 } 1256 1257 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 1258 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1259 return (0); 1260 } 1261 1262 /********************************************************************* 1263 * Init entry point 1264 * 1265 * This routine is used in two ways. It is used by the stack as 1266 * init entry point in network interface structure. It is also used 1267 * by the driver as a hw/sw initialization routine to get to a 1268 * consistent state. 1269 * 1270 **********************************************************************/ 1271 static void 1272 em_if_init(if_ctx_t ctx) 1273 { 1274 struct adapter *adapter = iflib_get_softc(ctx); 1275 if_softc_ctx_t scctx = adapter->shared; 1276 struct ifnet *ifp = iflib_get_ifp(ctx); 1277 struct em_tx_queue *tx_que; 1278 int i; 1279 1280 INIT_DEBUGOUT("em_if_init: begin"); 1281 1282 /* Get the latest mac address, User can use a LAA */ 1283 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 1284 ETHER_ADDR_LEN); 1285 1286 /* Put the address into the Receive Address Array */ 1287 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1288 1289 /* 1290 * With the 82571 adapter, RAR[0] may be overwritten 1291 * when the other port is reset, we make a duplicate 1292 * in RAR[14] for that eventuality, this assures 1293 * the interface continues to function. 1294 */ 1295 if (adapter->hw.mac.type == e1000_82571) { 1296 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1297 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1298 E1000_RAR_ENTRIES - 1); 1299 } 1300 1301 1302 /* Initialize the hardware */ 1303 em_reset(ctx); 1304 em_if_update_admin_status(ctx); 1305 1306 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 1307 struct tx_ring *txr = &tx_que->txr; 1308 1309 txr->tx_rs_cidx = txr->tx_rs_pidx; 1310 1311 /* Initialize the last processed descriptor to be the end of 1312 * the ring, rather than the start, so that we avoid an 1313 * off-by-one error when calculating how many descriptors are 1314 * done in the credits_update function. 1315 */ 1316 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1317 } 1318 1319 /* Setup VLAN support, basic and offload if available */ 1320 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1321 1322 /* Clear bad data from Rx FIFOs */ 1323 if (adapter->hw.mac.type >= igb_mac_min) 1324 e1000_rx_fifo_flush_82575(&adapter->hw); 1325 1326 /* Configure for OS presence */ 1327 em_init_manageability(adapter); 1328 1329 /* Prepare transmit descriptors and buffers */ 1330 em_initialize_transmit_unit(ctx); 1331 1332 /* Setup Multicast table */ 1333 em_if_multi_set(ctx); 1334 1335 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1336 em_initialize_receive_unit(ctx); 1337 1338 /* Use real VLAN Filter support? */ 1339 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1340 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 1341 /* Use real VLAN Filter support */ 1342 em_setup_vlan_hw_support(adapter); 1343 else { 1344 u32 ctrl; 1345 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1346 ctrl |= E1000_CTRL_VME; 1347 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1348 } 1349 } else { 1350 u32 ctrl; 1351 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 1352 ctrl &= ~E1000_CTRL_VME; 1353 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 1354 } 1355 1356 /* Don't lose promiscuous settings */ 1357 em_if_set_promisc(ctx, if_getflags(ifp)); 1358 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1359 1360 /* MSI-X configuration for 82574 */ 1361 if (adapter->hw.mac.type == e1000_82574) { 1362 int tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 1363 1364 tmp |= E1000_CTRL_EXT_PBA_CLR; 1365 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp); 1366 /* Set the IVAR - interrupt vector routing. */ 1367 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, adapter->ivars); 1368 } else if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1369 igb_configure_queues(adapter); 1370 1371 /* this clears any pending interrupts */ 1372 E1000_READ_REG(&adapter->hw, E1000_ICR); 1373 E1000_WRITE_REG(&adapter->hw, E1000_ICS, E1000_ICS_LSC); 1374 1375 /* AMT based hardware can now take control from firmware */ 1376 if (adapter->has_manage && adapter->has_amt) 1377 em_get_hw_control(adapter); 1378 1379 /* Set Energy Efficient Ethernet */ 1380 if (adapter->hw.mac.type >= igb_mac_min && 1381 adapter->hw.phy.media_type == e1000_media_type_copper) { 1382 if (adapter->hw.mac.type == e1000_i354) 1383 e1000_set_eee_i354(&adapter->hw, TRUE, TRUE); 1384 else 1385 e1000_set_eee_i350(&adapter->hw, TRUE, TRUE); 1386 } 1387 } 1388 1389 /********************************************************************* 1390 * 1391 * Fast Legacy/MSI Combined Interrupt Service routine 1392 * 1393 *********************************************************************/ 1394 int 1395 em_intr(void *arg) 1396 { 1397 struct adapter *adapter = arg; 1398 if_ctx_t ctx = adapter->ctx; 1399 u32 reg_icr; 1400 1401 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1402 1403 /* Hot eject? */ 1404 if (reg_icr == 0xffffffff) 1405 return FILTER_STRAY; 1406 1407 /* Definitely not our interrupt. */ 1408 if (reg_icr == 0x0) 1409 return FILTER_STRAY; 1410 1411 /* 1412 * Starting with the 82571 chip, bit 31 should be used to 1413 * determine whether the interrupt belongs to us. 1414 */ 1415 if (adapter->hw.mac.type >= e1000_82571 && 1416 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1417 return FILTER_STRAY; 1418 1419 /* 1420 * Only MSI-X interrupts have one-shot behavior by taking advantage 1421 * of the EIAC register. Thus, explicitly disable interrupts. This 1422 * also works around the MSI message reordering errata on certain 1423 * systems. 1424 */ 1425 IFDI_INTR_DISABLE(ctx); 1426 1427 /* Link status change */ 1428 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1429 em_handle_link(ctx); 1430 1431 if (reg_icr & E1000_ICR_RXO) 1432 adapter->rx_overruns++; 1433 1434 return (FILTER_SCHEDULE_THREAD); 1435 } 1436 1437 static int 1438 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1439 { 1440 struct adapter *adapter = iflib_get_softc(ctx); 1441 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1442 1443 E1000_WRITE_REG(&adapter->hw, E1000_IMS, rxq->eims); 1444 return (0); 1445 } 1446 1447 static int 1448 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1449 { 1450 struct adapter *adapter = iflib_get_softc(ctx); 1451 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1452 1453 E1000_WRITE_REG(&adapter->hw, E1000_IMS, txq->eims); 1454 return (0); 1455 } 1456 1457 static int 1458 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1459 { 1460 struct adapter *adapter = iflib_get_softc(ctx); 1461 struct em_rx_queue *rxq = &adapter->rx_queues[rxqid]; 1462 1463 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, rxq->eims); 1464 return (0); 1465 } 1466 1467 static int 1468 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1469 { 1470 struct adapter *adapter = iflib_get_softc(ctx); 1471 struct em_tx_queue *txq = &adapter->tx_queues[txqid]; 1472 1473 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, txq->eims); 1474 return (0); 1475 } 1476 1477 /********************************************************************* 1478 * 1479 * MSI-X RX Interrupt Service routine 1480 * 1481 **********************************************************************/ 1482 static int 1483 em_msix_que(void *arg) 1484 { 1485 struct em_rx_queue *que = arg; 1486 1487 ++que->irqs; 1488 1489 return (FILTER_SCHEDULE_THREAD); 1490 } 1491 1492 /********************************************************************* 1493 * 1494 * MSI-X Link Fast Interrupt Service routine 1495 * 1496 **********************************************************************/ 1497 static int 1498 em_msix_link(void *arg) 1499 { 1500 struct adapter *adapter = arg; 1501 u32 reg_icr; 1502 bool notlink = false; 1503 1504 ++adapter->link_irq; 1505 MPASS(adapter->hw.back != NULL); 1506 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1507 1508 if (reg_icr & E1000_ICR_RXO) 1509 adapter->rx_overruns++; 1510 1511 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1512 em_handle_link(adapter->ctx); 1513 else 1514 notlink = true; 1515 1516 /* Re-arm for other/spurious interrupts */ 1517 if (notlink && adapter->hw.mac.type >= igb_mac_min) { 1518 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1519 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1520 } else if (adapter->hw.mac.type == e1000_82574) { 1521 if (notlink) 1522 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC | 1523 E1000_IMS_OTHER); 1524 /* 1525 * Because we must read the ICR for this interrupt it may 1526 * clear other causes using autoclear, for this reason we 1527 * simply create a soft interrupt for all these vectors. 1528 */ 1529 if (reg_icr) 1530 E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims); 1531 } 1532 1533 return (FILTER_HANDLED); 1534 } 1535 1536 static void 1537 em_handle_link(void *context) 1538 { 1539 if_ctx_t ctx = context; 1540 struct adapter *adapter = iflib_get_softc(ctx); 1541 1542 adapter->hw.mac.get_link_status = 1; 1543 iflib_admin_intr_deferred(ctx); 1544 } 1545 1546 /********************************************************************* 1547 * 1548 * Media Ioctl callback 1549 * 1550 * This routine is called whenever the user queries the status of 1551 * the interface using ifconfig. 1552 * 1553 **********************************************************************/ 1554 static void 1555 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1556 { 1557 struct adapter *adapter = iflib_get_softc(ctx); 1558 u_char fiber_type = IFM_1000_SX; 1559 1560 INIT_DEBUGOUT("em_if_media_status: begin"); 1561 1562 iflib_admin_intr_deferred(ctx); 1563 1564 ifmr->ifm_status = IFM_AVALID; 1565 ifmr->ifm_active = IFM_ETHER; 1566 1567 if (!adapter->link_active) { 1568 return; 1569 } 1570 1571 ifmr->ifm_status |= IFM_ACTIVE; 1572 1573 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1574 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1575 if (adapter->hw.mac.type == e1000_82545) 1576 fiber_type = IFM_1000_LX; 1577 ifmr->ifm_active |= fiber_type | IFM_FDX; 1578 } else { 1579 switch (adapter->link_speed) { 1580 case 10: 1581 ifmr->ifm_active |= IFM_10_T; 1582 break; 1583 case 100: 1584 ifmr->ifm_active |= IFM_100_TX; 1585 break; 1586 case 1000: 1587 ifmr->ifm_active |= IFM_1000_T; 1588 break; 1589 } 1590 if (adapter->link_duplex == FULL_DUPLEX) 1591 ifmr->ifm_active |= IFM_FDX; 1592 else 1593 ifmr->ifm_active |= IFM_HDX; 1594 } 1595 } 1596 1597 /********************************************************************* 1598 * 1599 * Media Ioctl callback 1600 * 1601 * This routine is called when the user changes speed/duplex using 1602 * media/mediopt option with ifconfig. 1603 * 1604 **********************************************************************/ 1605 static int 1606 em_if_media_change(if_ctx_t ctx) 1607 { 1608 struct adapter *adapter = iflib_get_softc(ctx); 1609 struct ifmedia *ifm = iflib_get_media(ctx); 1610 1611 INIT_DEBUGOUT("em_if_media_change: begin"); 1612 1613 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1614 return (EINVAL); 1615 1616 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1617 case IFM_AUTO: 1618 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1619 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1620 break; 1621 case IFM_1000_LX: 1622 case IFM_1000_SX: 1623 case IFM_1000_T: 1624 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1625 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1626 break; 1627 case IFM_100_TX: 1628 adapter->hw.mac.autoneg = FALSE; 1629 adapter->hw.phy.autoneg_advertised = 0; 1630 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1631 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1632 else 1633 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1634 break; 1635 case IFM_10_T: 1636 adapter->hw.mac.autoneg = FALSE; 1637 adapter->hw.phy.autoneg_advertised = 0; 1638 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1639 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1640 else 1641 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1642 break; 1643 default: 1644 device_printf(adapter->dev, "Unsupported media type\n"); 1645 } 1646 1647 em_if_init(ctx); 1648 1649 return (0); 1650 } 1651 1652 static int 1653 em_if_set_promisc(if_ctx_t ctx, int flags) 1654 { 1655 struct adapter *adapter = iflib_get_softc(ctx); 1656 struct ifnet *ifp = iflib_get_ifp(ctx); 1657 u32 reg_rctl; 1658 int mcnt = 0; 1659 1660 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1661 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1662 if (flags & IFF_ALLMULTI) 1663 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1664 else 1665 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1666 1667 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1668 reg_rctl &= (~E1000_RCTL_MPE); 1669 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1670 1671 if (flags & IFF_PROMISC) { 1672 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1673 /* Turn this on if you want to see bad packets */ 1674 if (em_debug_sbp) 1675 reg_rctl |= E1000_RCTL_SBP; 1676 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1677 } else if (flags & IFF_ALLMULTI) { 1678 reg_rctl |= E1000_RCTL_MPE; 1679 reg_rctl &= ~E1000_RCTL_UPE; 1680 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1681 } 1682 return (0); 1683 } 1684 1685 static u_int 1686 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1687 { 1688 u8 *mta = arg; 1689 1690 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1691 return (0); 1692 1693 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1694 1695 return (1); 1696 } 1697 1698 /********************************************************************* 1699 * Multicast Update 1700 * 1701 * This routine is called whenever multicast address list is updated. 1702 * 1703 **********************************************************************/ 1704 static void 1705 em_if_multi_set(if_ctx_t ctx) 1706 { 1707 struct adapter *adapter = iflib_get_softc(ctx); 1708 struct ifnet *ifp = iflib_get_ifp(ctx); 1709 u8 *mta; /* Multicast array memory */ 1710 u32 reg_rctl = 0; 1711 int mcnt = 0; 1712 1713 IOCTL_DEBUGOUT("em_set_multi: begin"); 1714 1715 mta = adapter->mta; 1716 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1717 1718 if (adapter->hw.mac.type == e1000_82542 && 1719 adapter->hw.revision_id == E1000_REVISION_2) { 1720 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1721 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1722 e1000_pci_clear_mwi(&adapter->hw); 1723 reg_rctl |= E1000_RCTL_RST; 1724 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1725 msec_delay(5); 1726 } 1727 1728 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1729 1730 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1731 1732 if (if_getflags(ifp) & IFF_PROMISC) 1733 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1734 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1735 if_getflags(ifp) & IFF_ALLMULTI) { 1736 reg_rctl |= E1000_RCTL_MPE; 1737 reg_rctl &= ~E1000_RCTL_UPE; 1738 } else 1739 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1740 1741 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1742 1743 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1744 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt); 1745 1746 if (adapter->hw.mac.type == e1000_82542 && 1747 adapter->hw.revision_id == E1000_REVISION_2) { 1748 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 1749 reg_rctl &= ~E1000_RCTL_RST; 1750 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 1751 msec_delay(5); 1752 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1753 e1000_pci_set_mwi(&adapter->hw); 1754 } 1755 } 1756 1757 /********************************************************************* 1758 * Timer routine 1759 * 1760 * This routine schedules em_if_update_admin_status() to check for 1761 * link status and to gather statistics as well as to perform some 1762 * controller-specific hardware patting. 1763 * 1764 **********************************************************************/ 1765 static void 1766 em_if_timer(if_ctx_t ctx, uint16_t qid) 1767 { 1768 1769 if (qid != 0) 1770 return; 1771 1772 iflib_admin_intr_deferred(ctx); 1773 } 1774 1775 static void 1776 em_if_update_admin_status(if_ctx_t ctx) 1777 { 1778 struct adapter *adapter = iflib_get_softc(ctx); 1779 struct e1000_hw *hw = &adapter->hw; 1780 device_t dev = iflib_get_dev(ctx); 1781 u32 link_check, thstat, ctrl; 1782 1783 link_check = thstat = ctrl = 0; 1784 /* Get the cached link value or read phy for real */ 1785 switch (hw->phy.media_type) { 1786 case e1000_media_type_copper: 1787 if (hw->mac.get_link_status) { 1788 if (hw->mac.type == e1000_pch_spt) 1789 msec_delay(50); 1790 /* Do the work to read phy */ 1791 e1000_check_for_link(hw); 1792 link_check = !hw->mac.get_link_status; 1793 if (link_check) /* ESB2 fix */ 1794 e1000_cfg_on_link_up(hw); 1795 } else { 1796 link_check = TRUE; 1797 } 1798 break; 1799 case e1000_media_type_fiber: 1800 e1000_check_for_link(hw); 1801 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1802 E1000_STATUS_LU); 1803 break; 1804 case e1000_media_type_internal_serdes: 1805 e1000_check_for_link(hw); 1806 link_check = hw->mac.serdes_has_link; 1807 break; 1808 /* VF device is type_unknown */ 1809 case e1000_media_type_unknown: 1810 e1000_check_for_link(hw); 1811 link_check = !hw->mac.get_link_status; 1812 /* FALLTHROUGH */ 1813 default: 1814 break; 1815 } 1816 1817 /* Check for thermal downshift or shutdown */ 1818 if (hw->mac.type == e1000_i350) { 1819 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1820 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1821 } 1822 1823 /* Now check for a transition */ 1824 if (link_check && (adapter->link_active == 0)) { 1825 e1000_get_speed_and_duplex(hw, &adapter->link_speed, 1826 &adapter->link_duplex); 1827 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1828 if ((adapter->link_speed != SPEED_1000) && 1829 ((hw->mac.type == e1000_82571) || 1830 (hw->mac.type == e1000_82572))) { 1831 int tarc0; 1832 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1833 tarc0 &= ~TARC_SPEED_MODE_BIT; 1834 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1835 } 1836 if (bootverbose) 1837 device_printf(dev, "Link is up %d Mbps %s\n", 1838 adapter->link_speed, 1839 ((adapter->link_duplex == FULL_DUPLEX) ? 1840 "Full Duplex" : "Half Duplex")); 1841 adapter->link_active = 1; 1842 adapter->smartspeed = 0; 1843 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1844 E1000_CTRL_EXT_LINK_MODE_GMII && 1845 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1846 device_printf(dev, "Link: thermal downshift\n"); 1847 /* Delay Link Up for Phy update */ 1848 if (((hw->mac.type == e1000_i210) || 1849 (hw->mac.type == e1000_i211)) && 1850 (hw->phy.id == I210_I_PHY_ID)) 1851 msec_delay(I210_LINK_DELAY); 1852 /* Reset if the media type changed. */ 1853 if (hw->dev_spec._82575.media_changed && 1854 hw->mac.type >= igb_mac_min) { 1855 hw->dev_spec._82575.media_changed = false; 1856 adapter->flags |= IGB_MEDIA_RESET; 1857 em_reset(ctx); 1858 } 1859 iflib_link_state_change(ctx, LINK_STATE_UP, 1860 IF_Mbps(adapter->link_speed)); 1861 } else if (!link_check && (adapter->link_active == 1)) { 1862 adapter->link_speed = 0; 1863 adapter->link_duplex = 0; 1864 adapter->link_active = 0; 1865 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1866 } 1867 em_update_stats_counters(adapter); 1868 1869 /* Reset LAA into RAR[0] on 82571 */ 1870 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1871 e1000_rar_set(hw, hw->mac.addr, 0); 1872 1873 if (hw->mac.type < em_mac_min) 1874 lem_smartspeed(adapter); 1875 else if (hw->mac.type >= igb_mac_min && 1876 adapter->intr_type == IFLIB_INTR_MSIX) { 1877 E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); 1878 E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); 1879 } else if (hw->mac.type == e1000_82574 && 1880 adapter->intr_type == IFLIB_INTR_MSIX) 1881 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_OTHER); 1882 } 1883 1884 static void 1885 em_if_watchdog_reset(if_ctx_t ctx) 1886 { 1887 struct adapter *adapter = iflib_get_softc(ctx); 1888 1889 /* 1890 * Just count the event; iflib(4) will already trigger a 1891 * sufficient reset of the controller. 1892 */ 1893 adapter->watchdog_events++; 1894 } 1895 1896 /********************************************************************* 1897 * 1898 * This routine disables all traffic on the adapter by issuing a 1899 * global reset on the MAC. 1900 * 1901 **********************************************************************/ 1902 static void 1903 em_if_stop(if_ctx_t ctx) 1904 { 1905 struct adapter *adapter = iflib_get_softc(ctx); 1906 1907 INIT_DEBUGOUT("em_if_stop: begin"); 1908 1909 e1000_reset_hw(&adapter->hw); 1910 if (adapter->hw.mac.type >= e1000_82544) 1911 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, 0); 1912 1913 e1000_led_off(&adapter->hw); 1914 e1000_cleanup_led(&adapter->hw); 1915 } 1916 1917 /********************************************************************* 1918 * 1919 * Determine hardware revision. 1920 * 1921 **********************************************************************/ 1922 static void 1923 em_identify_hardware(if_ctx_t ctx) 1924 { 1925 device_t dev = iflib_get_dev(ctx); 1926 struct adapter *adapter = iflib_get_softc(ctx); 1927 1928 /* Make sure our PCI config space has the necessary stuff set */ 1929 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1930 1931 /* Save off the information about this board */ 1932 adapter->hw.vendor_id = pci_get_vendor(dev); 1933 adapter->hw.device_id = pci_get_device(dev); 1934 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1935 adapter->hw.subsystem_vendor_id = 1936 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1937 adapter->hw.subsystem_device_id = 1938 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1939 1940 /* Do Shared Code Init and Setup */ 1941 if (e1000_set_mac_type(&adapter->hw)) { 1942 device_printf(dev, "Setup init failure\n"); 1943 return; 1944 } 1945 1946 /* Are we a VF device? */ 1947 if ((adapter->hw.mac.type == e1000_vfadapt) || 1948 (adapter->hw.mac.type == e1000_vfadapt_i350)) 1949 adapter->vf_ifp = 1; 1950 else 1951 adapter->vf_ifp = 0; 1952 } 1953 1954 static int 1955 em_allocate_pci_resources(if_ctx_t ctx) 1956 { 1957 struct adapter *adapter = iflib_get_softc(ctx); 1958 device_t dev = iflib_get_dev(ctx); 1959 int rid, val; 1960 1961 rid = PCIR_BAR(0); 1962 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1963 &rid, RF_ACTIVE); 1964 if (adapter->memory == NULL) { 1965 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1966 return (ENXIO); 1967 } 1968 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1969 adapter->osdep.mem_bus_space_handle = 1970 rman_get_bushandle(adapter->memory); 1971 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1972 1973 /* Only older adapters use IO mapping */ 1974 if (adapter->hw.mac.type < em_mac_min && 1975 adapter->hw.mac.type > e1000_82543) { 1976 /* Figure our where our IO BAR is ? */ 1977 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 1978 val = pci_read_config(dev, rid, 4); 1979 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 1980 break; 1981 } 1982 rid += 4; 1983 /* check for 64bit BAR */ 1984 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 1985 rid += 4; 1986 } 1987 if (rid >= PCIR_CIS) { 1988 device_printf(dev, "Unable to locate IO BAR\n"); 1989 return (ENXIO); 1990 } 1991 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 1992 &rid, RF_ACTIVE); 1993 if (adapter->ioport == NULL) { 1994 device_printf(dev, "Unable to allocate bus resource: " 1995 "ioport\n"); 1996 return (ENXIO); 1997 } 1998 adapter->hw.io_base = 0; 1999 adapter->osdep.io_bus_space_tag = 2000 rman_get_bustag(adapter->ioport); 2001 adapter->osdep.io_bus_space_handle = 2002 rman_get_bushandle(adapter->ioport); 2003 } 2004 2005 adapter->hw.back = &adapter->osdep; 2006 2007 return (0); 2008 } 2009 2010 /********************************************************************* 2011 * 2012 * Set up the MSI-X Interrupt handlers 2013 * 2014 **********************************************************************/ 2015 static int 2016 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2017 { 2018 struct adapter *adapter = iflib_get_softc(ctx); 2019 struct em_rx_queue *rx_que = adapter->rx_queues; 2020 struct em_tx_queue *tx_que = adapter->tx_queues; 2021 int error, rid, i, vector = 0, rx_vectors; 2022 char buf[16]; 2023 2024 /* First set up ring resources */ 2025 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 2026 rid = vector + 1; 2027 snprintf(buf, sizeof(buf), "rxq%d", i); 2028 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2029 if (error) { 2030 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2031 adapter->rx_num_queues = i + 1; 2032 goto fail; 2033 } 2034 2035 rx_que->msix = vector; 2036 2037 /* 2038 * Set the bit to enable interrupt 2039 * in E1000_IMS -- bits 20 and 21 2040 * are for RX0 and RX1, note this has 2041 * NOTHING to do with the MSI-X vector 2042 */ 2043 if (adapter->hw.mac.type == e1000_82574) { 2044 rx_que->eims = 1 << (20 + i); 2045 adapter->ims |= rx_que->eims; 2046 adapter->ivars |= (8 | rx_que->msix) << (i * 4); 2047 } else if (adapter->hw.mac.type == e1000_82575) 2048 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2049 else 2050 rx_que->eims = 1 << vector; 2051 } 2052 rx_vectors = vector; 2053 2054 vector = 0; 2055 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 2056 snprintf(buf, sizeof(buf), "txq%d", i); 2057 tx_que = &adapter->tx_queues[i]; 2058 iflib_softirq_alloc_generic(ctx, 2059 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 2060 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2061 2062 tx_que->msix = (vector % adapter->rx_num_queues); 2063 2064 /* 2065 * Set the bit to enable interrupt 2066 * in E1000_IMS -- bits 22 and 23 2067 * are for TX0 and TX1, note this has 2068 * NOTHING to do with the MSI-X vector 2069 */ 2070 if (adapter->hw.mac.type == e1000_82574) { 2071 tx_que->eims = 1 << (22 + i); 2072 adapter->ims |= tx_que->eims; 2073 adapter->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2074 } else if (adapter->hw.mac.type == e1000_82575) { 2075 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2076 } else { 2077 tx_que->eims = 1 << i; 2078 } 2079 } 2080 2081 /* Link interrupt */ 2082 rid = rx_vectors + 1; 2083 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, adapter, 0, "aq"); 2084 2085 if (error) { 2086 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2087 goto fail; 2088 } 2089 adapter->linkvec = rx_vectors; 2090 if (adapter->hw.mac.type < igb_mac_min) { 2091 adapter->ivars |= (8 | rx_vectors) << 16; 2092 adapter->ivars |= 0x80000000; 2093 /* Enable the "Other" interrupt type for link status change */ 2094 adapter->ims |= E1000_IMS_OTHER; 2095 } 2096 2097 return (0); 2098 fail: 2099 iflib_irq_free(ctx, &adapter->irq); 2100 rx_que = adapter->rx_queues; 2101 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 2102 iflib_irq_free(ctx, &rx_que->que_irq); 2103 return (error); 2104 } 2105 2106 static void 2107 igb_configure_queues(struct adapter *adapter) 2108 { 2109 struct e1000_hw *hw = &adapter->hw; 2110 struct em_rx_queue *rx_que; 2111 struct em_tx_queue *tx_que; 2112 u32 tmp, ivar = 0, newitr = 0; 2113 2114 /* First turn on RSS capability */ 2115 if (hw->mac.type != e1000_82575) 2116 E1000_WRITE_REG(hw, E1000_GPIE, 2117 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2118 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2119 2120 /* Turn on MSI-X */ 2121 switch (hw->mac.type) { 2122 case e1000_82580: 2123 case e1000_i350: 2124 case e1000_i354: 2125 case e1000_i210: 2126 case e1000_i211: 2127 case e1000_vfadapt: 2128 case e1000_vfadapt_i350: 2129 /* RX entries */ 2130 for (int i = 0; i < adapter->rx_num_queues; i++) { 2131 u32 index = i >> 1; 2132 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2133 rx_que = &adapter->rx_queues[i]; 2134 if (i & 1) { 2135 ivar &= 0xFF00FFFF; 2136 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2137 } else { 2138 ivar &= 0xFFFFFF00; 2139 ivar |= rx_que->msix | E1000_IVAR_VALID; 2140 } 2141 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2142 } 2143 /* TX entries */ 2144 for (int i = 0; i < adapter->tx_num_queues; i++) { 2145 u32 index = i >> 1; 2146 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2147 tx_que = &adapter->tx_queues[i]; 2148 if (i & 1) { 2149 ivar &= 0x00FFFFFF; 2150 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2151 } else { 2152 ivar &= 0xFFFF00FF; 2153 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2154 } 2155 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2156 adapter->que_mask |= tx_que->eims; 2157 } 2158 2159 /* And for the link interrupt */ 2160 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2161 adapter->link_mask = 1 << adapter->linkvec; 2162 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2163 break; 2164 case e1000_82576: 2165 /* RX entries */ 2166 for (int i = 0; i < adapter->rx_num_queues; i++) { 2167 u32 index = i & 0x7; /* Each IVAR has two entries */ 2168 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2169 rx_que = &adapter->rx_queues[i]; 2170 if (i < 8) { 2171 ivar &= 0xFFFFFF00; 2172 ivar |= rx_que->msix | E1000_IVAR_VALID; 2173 } else { 2174 ivar &= 0xFF00FFFF; 2175 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2176 } 2177 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2178 adapter->que_mask |= rx_que->eims; 2179 } 2180 /* TX entries */ 2181 for (int i = 0; i < adapter->tx_num_queues; i++) { 2182 u32 index = i & 0x7; /* Each IVAR has two entries */ 2183 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2184 tx_que = &adapter->tx_queues[i]; 2185 if (i < 8) { 2186 ivar &= 0xFFFF00FF; 2187 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2188 } else { 2189 ivar &= 0x00FFFFFF; 2190 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2191 } 2192 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2193 adapter->que_mask |= tx_que->eims; 2194 } 2195 2196 /* And for the link interrupt */ 2197 ivar = (adapter->linkvec | E1000_IVAR_VALID) << 8; 2198 adapter->link_mask = 1 << adapter->linkvec; 2199 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2200 break; 2201 2202 case e1000_82575: 2203 /* enable MSI-X support*/ 2204 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2205 tmp |= E1000_CTRL_EXT_PBA_CLR; 2206 /* Auto-Mask interrupts upon ICR read. */ 2207 tmp |= E1000_CTRL_EXT_EIAME; 2208 tmp |= E1000_CTRL_EXT_IRCA; 2209 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2210 2211 /* Queues */ 2212 for (int i = 0; i < adapter->rx_num_queues; i++) { 2213 rx_que = &adapter->rx_queues[i]; 2214 tmp = E1000_EICR_RX_QUEUE0 << i; 2215 tmp |= E1000_EICR_TX_QUEUE0 << i; 2216 rx_que->eims = tmp; 2217 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2218 i, rx_que->eims); 2219 adapter->que_mask |= rx_que->eims; 2220 } 2221 2222 /* Link */ 2223 E1000_WRITE_REG(hw, E1000_MSIXBM(adapter->linkvec), 2224 E1000_EIMS_OTHER); 2225 adapter->link_mask |= E1000_EIMS_OTHER; 2226 default: 2227 break; 2228 } 2229 2230 /* Set the starting interrupt rate */ 2231 if (em_max_interrupt_rate > 0) 2232 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2233 2234 if (hw->mac.type == e1000_82575) 2235 newitr |= newitr << 16; 2236 else 2237 newitr |= E1000_EITR_CNT_IGNR; 2238 2239 for (int i = 0; i < adapter->rx_num_queues; i++) { 2240 rx_que = &adapter->rx_queues[i]; 2241 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2242 } 2243 2244 return; 2245 } 2246 2247 static void 2248 em_free_pci_resources(if_ctx_t ctx) 2249 { 2250 struct adapter *adapter = iflib_get_softc(ctx); 2251 struct em_rx_queue *que = adapter->rx_queues; 2252 device_t dev = iflib_get_dev(ctx); 2253 2254 /* Release all MSI-X queue resources */ 2255 if (adapter->intr_type == IFLIB_INTR_MSIX) 2256 iflib_irq_free(ctx, &adapter->irq); 2257 2258 if (que != NULL) { 2259 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 2260 iflib_irq_free(ctx, &que->que_irq); 2261 } 2262 } 2263 2264 if (adapter->memory != NULL) { 2265 bus_release_resource(dev, SYS_RES_MEMORY, 2266 rman_get_rid(adapter->memory), adapter->memory); 2267 adapter->memory = NULL; 2268 } 2269 2270 if (adapter->flash != NULL) { 2271 bus_release_resource(dev, SYS_RES_MEMORY, 2272 rman_get_rid(adapter->flash), adapter->flash); 2273 adapter->flash = NULL; 2274 } 2275 2276 if (adapter->ioport != NULL) { 2277 bus_release_resource(dev, SYS_RES_IOPORT, 2278 rman_get_rid(adapter->ioport), adapter->ioport); 2279 adapter->ioport = NULL; 2280 } 2281 } 2282 2283 /* Set up MSI or MSI-X */ 2284 static int 2285 em_setup_msix(if_ctx_t ctx) 2286 { 2287 struct adapter *adapter = iflib_get_softc(ctx); 2288 2289 if (adapter->hw.mac.type == e1000_82574) { 2290 em_enable_vectors_82574(ctx); 2291 } 2292 return (0); 2293 } 2294 2295 /********************************************************************* 2296 * 2297 * Workaround for SmartSpeed on 82541 and 82547 controllers 2298 * 2299 **********************************************************************/ 2300 static void 2301 lem_smartspeed(struct adapter *adapter) 2302 { 2303 u16 phy_tmp; 2304 2305 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 2306 adapter->hw.mac.autoneg == 0 || 2307 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2308 return; 2309 2310 if (adapter->smartspeed == 0) { 2311 /* If Master/Slave config fault is asserted twice, 2312 * we assume back-to-back */ 2313 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2314 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2315 return; 2316 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2317 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2318 e1000_read_phy_reg(&adapter->hw, 2319 PHY_1000T_CTRL, &phy_tmp); 2320 if(phy_tmp & CR_1000T_MS_ENABLE) { 2321 phy_tmp &= ~CR_1000T_MS_ENABLE; 2322 e1000_write_phy_reg(&adapter->hw, 2323 PHY_1000T_CTRL, phy_tmp); 2324 adapter->smartspeed++; 2325 if(adapter->hw.mac.autoneg && 2326 !e1000_copper_link_autoneg(&adapter->hw) && 2327 !e1000_read_phy_reg(&adapter->hw, 2328 PHY_CONTROL, &phy_tmp)) { 2329 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2330 MII_CR_RESTART_AUTO_NEG); 2331 e1000_write_phy_reg(&adapter->hw, 2332 PHY_CONTROL, phy_tmp); 2333 } 2334 } 2335 } 2336 return; 2337 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2338 /* If still no link, perhaps using 2/3 pair cable */ 2339 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2340 phy_tmp |= CR_1000T_MS_ENABLE; 2341 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2342 if(adapter->hw.mac.autoneg && 2343 !e1000_copper_link_autoneg(&adapter->hw) && 2344 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 2345 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2346 MII_CR_RESTART_AUTO_NEG); 2347 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 2348 } 2349 } 2350 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2351 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2352 adapter->smartspeed = 0; 2353 } 2354 2355 /********************************************************************* 2356 * 2357 * Initialize the DMA Coalescing feature 2358 * 2359 **********************************************************************/ 2360 static void 2361 igb_init_dmac(struct adapter *adapter, u32 pba) 2362 { 2363 device_t dev = adapter->dev; 2364 struct e1000_hw *hw = &adapter->hw; 2365 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2366 u16 hwm; 2367 u16 max_frame_size; 2368 2369 if (hw->mac.type == e1000_i211) 2370 return; 2371 2372 max_frame_size = adapter->shared->isc_max_frame_size; 2373 if (hw->mac.type > e1000_82580) { 2374 2375 if (adapter->dmac == 0) { /* Disabling it */ 2376 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2377 return; 2378 } else 2379 device_printf(dev, "DMA Coalescing enabled\n"); 2380 2381 /* Set starting threshold */ 2382 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2383 2384 hwm = 64 * pba - max_frame_size / 16; 2385 if (hwm < 64 * (pba - 6)) 2386 hwm = 64 * (pba - 6); 2387 reg = E1000_READ_REG(hw, E1000_FCRTC); 2388 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2389 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2390 & E1000_FCRTC_RTH_COAL_MASK); 2391 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2392 2393 2394 dmac = pba - max_frame_size / 512; 2395 if (dmac < pba - 10) 2396 dmac = pba - 10; 2397 reg = E1000_READ_REG(hw, E1000_DMACR); 2398 reg &= ~E1000_DMACR_DMACTHR_MASK; 2399 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2400 & E1000_DMACR_DMACTHR_MASK); 2401 2402 /* transition to L0x or L1 if available..*/ 2403 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2404 2405 /* Check if status is 2.5Gb backplane connection 2406 * before configuration of watchdog timer, which is 2407 * in msec values in 12.8usec intervals 2408 * watchdog timer= msec values in 32usec intervals 2409 * for non 2.5Gb connection 2410 */ 2411 if (hw->mac.type == e1000_i354) { 2412 int status = E1000_READ_REG(hw, E1000_STATUS); 2413 if ((status & E1000_STATUS_2P5_SKU) && 2414 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2415 reg |= ((adapter->dmac * 5) >> 6); 2416 else 2417 reg |= (adapter->dmac >> 5); 2418 } else { 2419 reg |= (adapter->dmac >> 5); 2420 } 2421 2422 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2423 2424 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2425 2426 /* Set the interval before transition */ 2427 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2428 if (hw->mac.type == e1000_i350) 2429 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2430 /* 2431 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2432 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2433 */ 2434 if (hw->mac.type == e1000_i354) { 2435 int status = E1000_READ_REG(hw, E1000_STATUS); 2436 if ((status & E1000_STATUS_2P5_SKU) && 2437 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2438 reg |= 0xA; 2439 else 2440 reg |= 0x4; 2441 } else { 2442 reg |= 0x4; 2443 } 2444 2445 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2446 2447 /* free space in tx packet buffer to wake from DMA coal */ 2448 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2449 (2 * max_frame_size)) >> 6); 2450 2451 /* make low power state decision controlled by DMA coal */ 2452 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2453 reg &= ~E1000_PCIEMISC_LX_DECISION; 2454 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2455 2456 } else if (hw->mac.type == e1000_82580) { 2457 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2458 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2459 reg & ~E1000_PCIEMISC_LX_DECISION); 2460 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2461 } 2462 } 2463 2464 /********************************************************************* 2465 * 2466 * Initialize the hardware to a configuration as specified by the 2467 * adapter structure. 2468 * 2469 **********************************************************************/ 2470 static void 2471 em_reset(if_ctx_t ctx) 2472 { 2473 device_t dev = iflib_get_dev(ctx); 2474 struct adapter *adapter = iflib_get_softc(ctx); 2475 struct ifnet *ifp = iflib_get_ifp(ctx); 2476 struct e1000_hw *hw = &adapter->hw; 2477 u16 rx_buffer_size; 2478 u32 pba; 2479 2480 INIT_DEBUGOUT("em_reset: begin"); 2481 /* Let the firmware know the OS is in control */ 2482 em_get_hw_control(adapter); 2483 2484 /* Set up smart power down as default off on newer adapters. */ 2485 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2486 hw->mac.type == e1000_82572)) { 2487 u16 phy_tmp = 0; 2488 2489 /* Speed up time to link by disabling smart power down. */ 2490 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2491 phy_tmp &= ~IGP02E1000_PM_SPD; 2492 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2493 } 2494 2495 /* 2496 * Packet Buffer Allocation (PBA) 2497 * Writing PBA sets the receive portion of the buffer 2498 * the remainder is used for the transmit buffer. 2499 */ 2500 switch (hw->mac.type) { 2501 /* 82547: Total Packet Buffer is 40K */ 2502 case e1000_82547: 2503 case e1000_82547_rev_2: 2504 if (hw->mac.max_frame_size > 8192) 2505 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2506 else 2507 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2508 break; 2509 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2510 case e1000_82571: 2511 case e1000_82572: 2512 case e1000_80003es2lan: 2513 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2514 break; 2515 /* 82573: Total Packet Buffer is 32K */ 2516 case e1000_82573: 2517 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2518 break; 2519 case e1000_82574: 2520 case e1000_82583: 2521 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2522 break; 2523 case e1000_ich8lan: 2524 pba = E1000_PBA_8K; 2525 break; 2526 case e1000_ich9lan: 2527 case e1000_ich10lan: 2528 /* Boost Receive side for jumbo frames */ 2529 if (hw->mac.max_frame_size > 4096) 2530 pba = E1000_PBA_14K; 2531 else 2532 pba = E1000_PBA_10K; 2533 break; 2534 case e1000_pchlan: 2535 case e1000_pch2lan: 2536 case e1000_pch_lpt: 2537 case e1000_pch_spt: 2538 case e1000_pch_cnp: 2539 case e1000_pch_tgp: 2540 case e1000_pch_adp: 2541 case e1000_pch_mtp: 2542 pba = E1000_PBA_26K; 2543 break; 2544 case e1000_82575: 2545 pba = E1000_PBA_32K; 2546 break; 2547 case e1000_82576: 2548 case e1000_vfadapt: 2549 pba = E1000_READ_REG(hw, E1000_RXPBS); 2550 pba &= E1000_RXPBS_SIZE_MASK_82576; 2551 break; 2552 case e1000_82580: 2553 case e1000_i350: 2554 case e1000_i354: 2555 case e1000_vfadapt_i350: 2556 pba = E1000_READ_REG(hw, E1000_RXPBS); 2557 pba = e1000_rxpbs_adjust_82580(pba); 2558 break; 2559 case e1000_i210: 2560 case e1000_i211: 2561 pba = E1000_PBA_34K; 2562 break; 2563 default: 2564 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2565 if (hw->mac.max_frame_size > 8192) 2566 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2567 else 2568 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2569 } 2570 2571 /* Special needs in case of Jumbo frames */ 2572 if ((hw->mac.type == e1000_82575) && (ifp->if_mtu > ETHERMTU)) { 2573 u32 tx_space, min_tx, min_rx; 2574 pba = E1000_READ_REG(hw, E1000_PBA); 2575 tx_space = pba >> 16; 2576 pba &= 0xffff; 2577 min_tx = (hw->mac.max_frame_size + 2578 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2579 min_tx = roundup2(min_tx, 1024); 2580 min_tx >>= 10; 2581 min_rx = hw->mac.max_frame_size; 2582 min_rx = roundup2(min_rx, 1024); 2583 min_rx >>= 10; 2584 if (tx_space < min_tx && 2585 ((min_tx - tx_space) < pba)) { 2586 pba = pba - (min_tx - tx_space); 2587 /* 2588 * if short on rx space, rx wins 2589 * and must trump tx adjustment 2590 */ 2591 if (pba < min_rx) 2592 pba = min_rx; 2593 } 2594 E1000_WRITE_REG(hw, E1000_PBA, pba); 2595 } 2596 2597 if (hw->mac.type < igb_mac_min) 2598 E1000_WRITE_REG(hw, E1000_PBA, pba); 2599 2600 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2601 2602 /* 2603 * These parameters control the automatic generation (Tx) and 2604 * response (Rx) to Ethernet PAUSE frames. 2605 * - High water mark should allow for at least two frames to be 2606 * received after sending an XOFF. 2607 * - Low water mark works best when it is very near the high water mark. 2608 * This allows the receiver to restart by sending XON when it has 2609 * drained a bit. Here we use an arbitrary value of 1500 which will 2610 * restart after one full frame is pulled from the buffer. There 2611 * could be several smaller frames in the buffer and if so they will 2612 * not trigger the XON until their total number reduces the buffer 2613 * by 1500. 2614 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2615 */ 2616 rx_buffer_size = (pba & 0xffff) << 10; 2617 hw->fc.high_water = rx_buffer_size - 2618 roundup2(hw->mac.max_frame_size, 1024); 2619 hw->fc.low_water = hw->fc.high_water - 1500; 2620 2621 if (adapter->fc) /* locally set flow control value? */ 2622 hw->fc.requested_mode = adapter->fc; 2623 else 2624 hw->fc.requested_mode = e1000_fc_full; 2625 2626 if (hw->mac.type == e1000_80003es2lan) 2627 hw->fc.pause_time = 0xFFFF; 2628 else 2629 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2630 2631 hw->fc.send_xon = TRUE; 2632 2633 /* Device specific overrides/settings */ 2634 switch (hw->mac.type) { 2635 case e1000_pchlan: 2636 /* Workaround: no TX flow ctrl for PCH */ 2637 hw->fc.requested_mode = e1000_fc_rx_pause; 2638 hw->fc.pause_time = 0xFFFF; /* override */ 2639 if (if_getmtu(ifp) > ETHERMTU) { 2640 hw->fc.high_water = 0x3500; 2641 hw->fc.low_water = 0x1500; 2642 } else { 2643 hw->fc.high_water = 0x5000; 2644 hw->fc.low_water = 0x3000; 2645 } 2646 hw->fc.refresh_time = 0x1000; 2647 break; 2648 case e1000_pch2lan: 2649 case e1000_pch_lpt: 2650 case e1000_pch_spt: 2651 case e1000_pch_cnp: 2652 case e1000_pch_tgp: 2653 case e1000_pch_adp: 2654 case e1000_pch_mtp: 2655 hw->fc.high_water = 0x5C20; 2656 hw->fc.low_water = 0x5048; 2657 hw->fc.pause_time = 0x0650; 2658 hw->fc.refresh_time = 0x0400; 2659 /* Jumbos need adjusted PBA */ 2660 if (if_getmtu(ifp) > ETHERMTU) 2661 E1000_WRITE_REG(hw, E1000_PBA, 12); 2662 else 2663 E1000_WRITE_REG(hw, E1000_PBA, 26); 2664 break; 2665 case e1000_82575: 2666 case e1000_82576: 2667 /* 8-byte granularity */ 2668 hw->fc.low_water = hw->fc.high_water - 8; 2669 break; 2670 case e1000_82580: 2671 case e1000_i350: 2672 case e1000_i354: 2673 case e1000_i210: 2674 case e1000_i211: 2675 case e1000_vfadapt: 2676 case e1000_vfadapt_i350: 2677 /* 16-byte granularity */ 2678 hw->fc.low_water = hw->fc.high_water - 16; 2679 break; 2680 case e1000_ich9lan: 2681 case e1000_ich10lan: 2682 if (if_getmtu(ifp) > ETHERMTU) { 2683 hw->fc.high_water = 0x2800; 2684 hw->fc.low_water = hw->fc.high_water - 8; 2685 break; 2686 } 2687 /* FALLTHROUGH */ 2688 default: 2689 if (hw->mac.type == e1000_80003es2lan) 2690 hw->fc.pause_time = 0xFFFF; 2691 break; 2692 } 2693 2694 /* Issue a global reset */ 2695 e1000_reset_hw(hw); 2696 if (hw->mac.type >= igb_mac_min) { 2697 E1000_WRITE_REG(hw, E1000_WUC, 0); 2698 } else { 2699 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2700 em_disable_aspm(adapter); 2701 } 2702 if (adapter->flags & IGB_MEDIA_RESET) { 2703 e1000_setup_init_funcs(hw, TRUE); 2704 e1000_get_bus_info(hw); 2705 adapter->flags &= ~IGB_MEDIA_RESET; 2706 } 2707 /* and a re-init */ 2708 if (e1000_init_hw(hw) < 0) { 2709 device_printf(dev, "Hardware Initialization Failed\n"); 2710 return; 2711 } 2712 if (hw->mac.type >= igb_mac_min) 2713 igb_init_dmac(adapter, pba); 2714 2715 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2716 e1000_get_phy_info(hw); 2717 e1000_check_for_link(hw); 2718 } 2719 2720 /* 2721 * Initialise the RSS mapping for NICs that support multiple transmit/ 2722 * receive rings. 2723 */ 2724 2725 #define RSSKEYLEN 10 2726 static void 2727 em_initialize_rss_mapping(struct adapter *adapter) 2728 { 2729 uint8_t rss_key[4 * RSSKEYLEN]; 2730 uint32_t reta = 0; 2731 struct e1000_hw *hw = &adapter->hw; 2732 int i; 2733 2734 /* 2735 * Configure RSS key 2736 */ 2737 arc4rand(rss_key, sizeof(rss_key), 0); 2738 for (i = 0; i < RSSKEYLEN; ++i) { 2739 uint32_t rssrk = 0; 2740 2741 rssrk = EM_RSSRK_VAL(rss_key, i); 2742 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2743 } 2744 2745 /* 2746 * Configure RSS redirect table in following fashion: 2747 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2748 */ 2749 for (i = 0; i < sizeof(reta); ++i) { 2750 uint32_t q; 2751 2752 q = (i % adapter->rx_num_queues) << 7; 2753 reta |= q << (8 * i); 2754 } 2755 2756 for (i = 0; i < 32; ++i) 2757 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2758 2759 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2760 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2761 E1000_MRQC_RSS_FIELD_IPV4 | 2762 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2763 E1000_MRQC_RSS_FIELD_IPV6_EX | 2764 E1000_MRQC_RSS_FIELD_IPV6); 2765 } 2766 2767 static void 2768 igb_initialize_rss_mapping(struct adapter *adapter) 2769 { 2770 struct e1000_hw *hw = &adapter->hw; 2771 int i; 2772 int queue_id; 2773 u32 reta; 2774 u32 rss_key[10], mrqc, shift = 0; 2775 2776 /* XXX? */ 2777 if (hw->mac.type == e1000_82575) 2778 shift = 6; 2779 2780 /* 2781 * The redirection table controls which destination 2782 * queue each bucket redirects traffic to. 2783 * Each DWORD represents four queues, with the LSB 2784 * being the first queue in the DWORD. 2785 * 2786 * This just allocates buckets to queues using round-robin 2787 * allocation. 2788 * 2789 * NOTE: It Just Happens to line up with the default 2790 * RSS allocation method. 2791 */ 2792 2793 /* Warning FM follows */ 2794 reta = 0; 2795 for (i = 0; i < 128; i++) { 2796 #ifdef RSS 2797 queue_id = rss_get_indirection_to_bucket(i); 2798 /* 2799 * If we have more queues than buckets, we'll 2800 * end up mapping buckets to a subset of the 2801 * queues. 2802 * 2803 * If we have more buckets than queues, we'll 2804 * end up instead assigning multiple buckets 2805 * to queues. 2806 * 2807 * Both are suboptimal, but we need to handle 2808 * the case so we don't go out of bounds 2809 * indexing arrays and such. 2810 */ 2811 queue_id = queue_id % adapter->rx_num_queues; 2812 #else 2813 queue_id = (i % adapter->rx_num_queues); 2814 #endif 2815 /* Adjust if required */ 2816 queue_id = queue_id << shift; 2817 2818 /* 2819 * The low 8 bits are for hash value (n+0); 2820 * The next 8 bits are for hash value (n+1), etc. 2821 */ 2822 reta = reta >> 8; 2823 reta = reta | ( ((uint32_t) queue_id) << 24); 2824 if ((i & 3) == 3) { 2825 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2826 reta = 0; 2827 } 2828 } 2829 2830 /* Now fill in hash table */ 2831 2832 /* 2833 * MRQC: Multiple Receive Queues Command 2834 * Set queuing to RSS control, number depends on the device. 2835 */ 2836 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2837 2838 #ifdef RSS 2839 /* XXX ew typecasting */ 2840 rss_getkey((uint8_t *) &rss_key); 2841 #else 2842 arc4rand(&rss_key, sizeof(rss_key), 0); 2843 #endif 2844 for (i = 0; i < 10; i++) 2845 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2846 2847 /* 2848 * Configure the RSS fields to hash upon. 2849 */ 2850 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2851 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2852 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 2853 E1000_MRQC_RSS_FIELD_IPV6_TCP); 2854 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 2855 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2856 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2857 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2858 2859 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2860 } 2861 2862 /********************************************************************* 2863 * 2864 * Setup networking device structure and register interface media. 2865 * 2866 **********************************************************************/ 2867 static int 2868 em_setup_interface(if_ctx_t ctx) 2869 { 2870 struct ifnet *ifp = iflib_get_ifp(ctx); 2871 struct adapter *adapter = iflib_get_softc(ctx); 2872 if_softc_ctx_t scctx = adapter->shared; 2873 2874 INIT_DEBUGOUT("em_setup_interface: begin"); 2875 2876 /* Single Queue */ 2877 if (adapter->tx_num_queues == 1) { 2878 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2879 if_setsendqready(ifp); 2880 } 2881 2882 /* 2883 * Specify the media types supported by this adapter and register 2884 * callbacks to update media and link information 2885 */ 2886 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 2887 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 2888 u_char fiber_type = IFM_1000_SX; /* default type */ 2889 2890 if (adapter->hw.mac.type == e1000_82545) 2891 fiber_type = IFM_1000_LX; 2892 ifmedia_add(adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 2893 ifmedia_add(adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2894 } else { 2895 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2896 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2897 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2898 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2899 if (adapter->hw.phy.type != e1000_phy_ife) { 2900 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2901 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2902 } 2903 } 2904 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2905 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 2906 return (0); 2907 } 2908 2909 static int 2910 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 2911 { 2912 struct adapter *adapter = iflib_get_softc(ctx); 2913 if_softc_ctx_t scctx = adapter->shared; 2914 int error = E1000_SUCCESS; 2915 struct em_tx_queue *que; 2916 int i, j; 2917 2918 MPASS(adapter->tx_num_queues > 0); 2919 MPASS(adapter->tx_num_queues == ntxqsets); 2920 2921 /* First allocate the top level queue structs */ 2922 if (!(adapter->tx_queues = 2923 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 2924 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2925 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2926 return(ENOMEM); 2927 } 2928 2929 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 2930 /* Set up some basics */ 2931 2932 struct tx_ring *txr = &que->txr; 2933 txr->adapter = que->adapter = adapter; 2934 que->me = txr->me = i; 2935 2936 /* Allocate report status array */ 2937 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2938 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 2939 error = ENOMEM; 2940 goto fail; 2941 } 2942 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2943 txr->tx_rsq[j] = QIDX_INVALID; 2944 /* get the virtual and physical address of the hardware queues */ 2945 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 2946 txr->tx_paddr = paddrs[i*ntxqs]; 2947 } 2948 2949 if (bootverbose) 2950 device_printf(iflib_get_dev(ctx), 2951 "allocated for %d tx_queues\n", adapter->tx_num_queues); 2952 return (0); 2953 fail: 2954 em_if_queues_free(ctx); 2955 return (error); 2956 } 2957 2958 static int 2959 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 2960 { 2961 struct adapter *adapter = iflib_get_softc(ctx); 2962 int error = E1000_SUCCESS; 2963 struct em_rx_queue *que; 2964 int i; 2965 2966 MPASS(adapter->rx_num_queues > 0); 2967 MPASS(adapter->rx_num_queues == nrxqsets); 2968 2969 /* First allocate the top level queue structs */ 2970 if (!(adapter->rx_queues = 2971 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 2972 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2973 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 2974 error = ENOMEM; 2975 goto fail; 2976 } 2977 2978 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 2979 /* Set up some basics */ 2980 struct rx_ring *rxr = &que->rxr; 2981 rxr->adapter = que->adapter = adapter; 2982 rxr->que = que; 2983 que->me = rxr->me = i; 2984 2985 /* get the virtual and physical address of the hardware queues */ 2986 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 2987 rxr->rx_paddr = paddrs[i*nrxqs]; 2988 } 2989 2990 if (bootverbose) 2991 device_printf(iflib_get_dev(ctx), 2992 "allocated for %d rx_queues\n", adapter->rx_num_queues); 2993 2994 return (0); 2995 fail: 2996 em_if_queues_free(ctx); 2997 return (error); 2998 } 2999 3000 static void 3001 em_if_queues_free(if_ctx_t ctx) 3002 { 3003 struct adapter *adapter = iflib_get_softc(ctx); 3004 struct em_tx_queue *tx_que = adapter->tx_queues; 3005 struct em_rx_queue *rx_que = adapter->rx_queues; 3006 3007 if (tx_que != NULL) { 3008 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 3009 struct tx_ring *txr = &tx_que->txr; 3010 if (txr->tx_rsq == NULL) 3011 break; 3012 3013 free(txr->tx_rsq, M_DEVBUF); 3014 txr->tx_rsq = NULL; 3015 } 3016 free(adapter->tx_queues, M_DEVBUF); 3017 adapter->tx_queues = NULL; 3018 } 3019 3020 if (rx_que != NULL) { 3021 free(adapter->rx_queues, M_DEVBUF); 3022 adapter->rx_queues = NULL; 3023 } 3024 } 3025 3026 /********************************************************************* 3027 * 3028 * Enable transmit unit. 3029 * 3030 **********************************************************************/ 3031 static void 3032 em_initialize_transmit_unit(if_ctx_t ctx) 3033 { 3034 struct adapter *adapter = iflib_get_softc(ctx); 3035 if_softc_ctx_t scctx = adapter->shared; 3036 struct em_tx_queue *que; 3037 struct tx_ring *txr; 3038 struct e1000_hw *hw = &adapter->hw; 3039 u32 tctl, txdctl = 0, tarc, tipg = 0; 3040 3041 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3042 3043 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 3044 u64 bus_addr; 3045 caddr_t offp, endp; 3046 3047 que = &adapter->tx_queues[i]; 3048 txr = &que->txr; 3049 bus_addr = txr->tx_paddr; 3050 3051 /* Clear checksum offload context. */ 3052 offp = (caddr_t)&txr->csum_flags; 3053 endp = (caddr_t)(txr + 1); 3054 bzero(offp, endp - offp); 3055 3056 /* Base and Len of TX Ring */ 3057 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3058 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3059 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3060 (u32)(bus_addr >> 32)); 3061 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3062 (u32)bus_addr); 3063 /* Init the HEAD/TAIL indices */ 3064 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3065 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3066 3067 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3068 E1000_READ_REG(hw, E1000_TDBAL(i)), 3069 E1000_READ_REG(hw, E1000_TDLEN(i))); 3070 3071 txdctl = 0; /* clear txdctl */ 3072 txdctl |= 0x1f; /* PTHRESH */ 3073 txdctl |= 1 << 8; /* HTHRESH */ 3074 txdctl |= 1 << 16;/* WTHRESH */ 3075 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3076 txdctl |= E1000_TXDCTL_GRAN; 3077 txdctl |= 1 << 25; /* LWTHRESH */ 3078 3079 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3080 } 3081 3082 /* Set the default values for the Tx Inter Packet Gap timer */ 3083 switch (hw->mac.type) { 3084 case e1000_80003es2lan: 3085 tipg = DEFAULT_82543_TIPG_IPGR1; 3086 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3087 E1000_TIPG_IPGR2_SHIFT; 3088 break; 3089 case e1000_82542: 3090 tipg = DEFAULT_82542_TIPG_IPGT; 3091 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3092 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3093 break; 3094 default: 3095 if (hw->phy.media_type == e1000_media_type_fiber || 3096 hw->phy.media_type == e1000_media_type_internal_serdes) 3097 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3098 else 3099 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3100 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3101 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3102 } 3103 3104 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3105 E1000_WRITE_REG(hw, E1000_TIDV, adapter->tx_int_delay.value); 3106 3107 if(hw->mac.type >= e1000_82540) 3108 E1000_WRITE_REG(hw, E1000_TADV, 3109 adapter->tx_abs_int_delay.value); 3110 3111 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3112 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3113 tarc |= TARC_SPEED_MODE_BIT; 3114 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3115 } else if (hw->mac.type == e1000_80003es2lan) { 3116 /* errata: program both queues to unweighted RR */ 3117 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3118 tarc |= 1; 3119 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3120 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3121 tarc |= 1; 3122 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3123 } else if (hw->mac.type == e1000_82574) { 3124 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3125 tarc |= TARC_ERRATA_BIT; 3126 if ( adapter->tx_num_queues > 1) { 3127 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3128 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3129 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3130 } else 3131 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3132 } 3133 3134 if (adapter->tx_int_delay.value > 0) 3135 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3136 3137 /* Program the Transmit Control Register */ 3138 tctl = E1000_READ_REG(hw, E1000_TCTL); 3139 tctl &= ~E1000_TCTL_CT; 3140 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3141 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3142 3143 if (hw->mac.type >= e1000_82571) 3144 tctl |= E1000_TCTL_MULR; 3145 3146 /* This write will effectively turn on the transmit unit. */ 3147 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3148 3149 /* SPT and KBL errata workarounds */ 3150 if (hw->mac.type == e1000_pch_spt) { 3151 u32 reg; 3152 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3153 reg |= E1000_RCTL_RDMTS_HEX; 3154 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3155 /* i218-i219 Specification Update 1.5.4.5 */ 3156 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3157 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3158 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3159 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3160 } 3161 } 3162 3163 /********************************************************************* 3164 * 3165 * Enable receive unit. 3166 * 3167 **********************************************************************/ 3168 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3169 3170 static void 3171 em_initialize_receive_unit(if_ctx_t ctx) 3172 { 3173 struct adapter *adapter = iflib_get_softc(ctx); 3174 if_softc_ctx_t scctx = adapter->shared; 3175 struct ifnet *ifp = iflib_get_ifp(ctx); 3176 struct e1000_hw *hw = &adapter->hw; 3177 struct em_rx_queue *que; 3178 int i; 3179 uint32_t rctl, rxcsum; 3180 3181 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3182 3183 /* 3184 * Make sure receives are disabled while setting 3185 * up the descriptor ring 3186 */ 3187 rctl = E1000_READ_REG(hw, E1000_RCTL); 3188 /* Do not disable if ever enabled on this hardware */ 3189 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3190 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3191 3192 /* Setup the Receive Control Register */ 3193 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3194 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3195 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3196 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3197 3198 /* Do not store bad packets */ 3199 rctl &= ~E1000_RCTL_SBP; 3200 3201 /* Enable Long Packet receive */ 3202 if (if_getmtu(ifp) > ETHERMTU) 3203 rctl |= E1000_RCTL_LPE; 3204 else 3205 rctl &= ~E1000_RCTL_LPE; 3206 3207 /* Strip the CRC */ 3208 if (!em_disable_crc_stripping) 3209 rctl |= E1000_RCTL_SECRC; 3210 3211 if (hw->mac.type >= e1000_82540) { 3212 E1000_WRITE_REG(hw, E1000_RADV, 3213 adapter->rx_abs_int_delay.value); 3214 3215 /* 3216 * Set the interrupt throttling rate. Value is calculated 3217 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3218 */ 3219 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3220 } 3221 E1000_WRITE_REG(hw, E1000_RDTR, adapter->rx_int_delay.value); 3222 3223 if (hw->mac.type >= em_mac_min) { 3224 uint32_t rfctl; 3225 /* Use extended rx descriptor formats */ 3226 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3227 rfctl |= E1000_RFCTL_EXTEN; 3228 3229 /* 3230 * When using MSI-X interrupts we need to throttle 3231 * using the EITR register (82574 only) 3232 */ 3233 if (hw->mac.type == e1000_82574) { 3234 for (int i = 0; i < 4; i++) 3235 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3236 DEFAULT_ITR); 3237 /* Disable accelerated acknowledge */ 3238 rfctl |= E1000_RFCTL_ACK_DIS; 3239 } 3240 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3241 } 3242 3243 /* Set up L3 and L4 csum Rx descriptor offloads */ 3244 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3245 if (scctx->isc_capenable & IFCAP_RXCSUM) { 3246 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3247 if (hw->mac.type > e1000_82575) 3248 rxcsum |= E1000_RXCSUM_CRCOFL; 3249 else if (hw->mac.type < em_mac_min && 3250 scctx->isc_capenable & IFCAP_HWCSUM_IPV6) 3251 rxcsum |= E1000_RXCSUM_IPV6OFL; 3252 } else { 3253 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3254 if (hw->mac.type > e1000_82575) 3255 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3256 else if (hw->mac.type < em_mac_min) 3257 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3258 } 3259 3260 if (adapter->rx_num_queues > 1) { 3261 /* RSS hash needed in the Rx descriptor */ 3262 rxcsum |= E1000_RXCSUM_PCSD; 3263 3264 if (hw->mac.type >= igb_mac_min) 3265 igb_initialize_rss_mapping(adapter); 3266 else 3267 em_initialize_rss_mapping(adapter); 3268 } 3269 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3270 3271 /* 3272 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3273 * long latencies are observed, like Lenovo X60. This 3274 * change eliminates the problem, but since having positive 3275 * values in RDTR is a known source of problems on other 3276 * platforms another solution is being sought. 3277 */ 3278 if (hw->mac.type == e1000_82573) 3279 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3280 3281 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3282 struct rx_ring *rxr = &que->rxr; 3283 /* Setup the Base and Length of the Rx Descriptor Ring */ 3284 u64 bus_addr = rxr->rx_paddr; 3285 #if 0 3286 u32 rdt = adapter->rx_num_queues -1; /* default */ 3287 #endif 3288 3289 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3290 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3291 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3292 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3293 /* Setup the Head and Tail Descriptor Pointers */ 3294 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3295 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3296 } 3297 3298 /* 3299 * Set PTHRESH for improved jumbo performance 3300 * According to 10.2.5.11 of Intel 82574 Datasheet, 3301 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3302 * Only write to RXDCTL(1) if there is a need for different 3303 * settings. 3304 */ 3305 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3306 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3307 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3308 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3309 } else if (hw->mac.type == e1000_82574) { 3310 for (int i = 0; i < adapter->rx_num_queues; i++) { 3311 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3312 rxdctl |= 0x20; /* PTHRESH */ 3313 rxdctl |= 4 << 8; /* HTHRESH */ 3314 rxdctl |= 4 << 16;/* WTHRESH */ 3315 rxdctl |= 1 << 24; /* Switch to granularity */ 3316 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3317 } 3318 } else if (hw->mac.type >= igb_mac_min) { 3319 u32 psize, srrctl = 0; 3320 3321 if (if_getmtu(ifp) > ETHERMTU) { 3322 psize = scctx->isc_max_frame_size; 3323 /* are we on a vlan? */ 3324 if (ifp->if_vlantrunk != NULL) 3325 psize += VLAN_TAG_SIZE; 3326 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3327 } 3328 3329 /* Set maximum packet buffer len */ 3330 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3331 E1000_SRRCTL_BSIZEPKT_SHIFT; 3332 3333 /* 3334 * If TX flow control is disabled and there's >1 queue defined, 3335 * enable DROP. 3336 * 3337 * This drops frames rather than hanging the RX MAC for all queues. 3338 */ 3339 if ((adapter->rx_num_queues > 1) && 3340 (adapter->fc == e1000_fc_none || 3341 adapter->fc == e1000_fc_rx_pause)) { 3342 srrctl |= E1000_SRRCTL_DROP_EN; 3343 } 3344 /* Setup the Base and Length of the Rx Descriptor Rings */ 3345 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 3346 struct rx_ring *rxr = &que->rxr; 3347 u64 bus_addr = rxr->rx_paddr; 3348 u32 rxdctl; 3349 3350 #ifdef notyet 3351 /* Configure for header split? -- ignore for now */ 3352 rxr->hdr_split = igb_header_split; 3353 #else 3354 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3355 #endif 3356 3357 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3358 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3359 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3360 (uint32_t)(bus_addr >> 32)); 3361 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3362 (uint32_t)bus_addr); 3363 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3364 /* Enable this Queue */ 3365 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3366 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3367 rxdctl &= 0xFFF00000; 3368 rxdctl |= IGB_RX_PTHRESH; 3369 rxdctl |= IGB_RX_HTHRESH << 8; 3370 rxdctl |= IGB_RX_WTHRESH << 16; 3371 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3372 } 3373 } else if (hw->mac.type >= e1000_pch2lan) { 3374 if (if_getmtu(ifp) > ETHERMTU) 3375 e1000_lv_jumbo_workaround_ich8lan(hw, TRUE); 3376 else 3377 e1000_lv_jumbo_workaround_ich8lan(hw, FALSE); 3378 } 3379 3380 /* Make sure VLAN Filters are off */ 3381 rctl &= ~E1000_RCTL_VFE; 3382 3383 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3384 if (hw->mac.type < igb_mac_min) { 3385 if (adapter->rx_mbuf_sz > 2048 && adapter->rx_mbuf_sz <= 4096) 3386 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3387 else if (adapter->rx_mbuf_sz > 4096 && adapter->rx_mbuf_sz <= 8192) 3388 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3389 else if (adapter->rx_mbuf_sz > 8192) 3390 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3391 else { 3392 rctl |= E1000_RCTL_SZ_2048; 3393 rctl &= ~E1000_RCTL_BSEX; 3394 } 3395 } else 3396 rctl |= E1000_RCTL_SZ_2048; 3397 3398 /* 3399 * rctl bits 11:10 are as follows 3400 * lem: reserved 3401 * em: DTYPE 3402 * igb: reserved 3403 * and should be 00 on all of the above 3404 */ 3405 rctl &= ~0x00000C00; 3406 3407 /* Write out the settings */ 3408 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3409 3410 return; 3411 } 3412 3413 static void 3414 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3415 { 3416 struct adapter *adapter = iflib_get_softc(ctx); 3417 u32 index, bit; 3418 3419 index = (vtag >> 5) & 0x7F; 3420 bit = vtag & 0x1F; 3421 adapter->shadow_vfta[index] |= (1 << bit); 3422 ++adapter->num_vlans; 3423 } 3424 3425 static void 3426 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3427 { 3428 struct adapter *adapter = iflib_get_softc(ctx); 3429 u32 index, bit; 3430 3431 index = (vtag >> 5) & 0x7F; 3432 bit = vtag & 0x1F; 3433 adapter->shadow_vfta[index] &= ~(1 << bit); 3434 --adapter->num_vlans; 3435 } 3436 3437 static void 3438 em_setup_vlan_hw_support(struct adapter *adapter) 3439 { 3440 struct e1000_hw *hw = &adapter->hw; 3441 u32 reg; 3442 3443 /* 3444 * We get here thru init_locked, meaning 3445 * a soft reset, this has already cleared 3446 * the VFTA and other state, so if there 3447 * have been no vlan's registered do nothing. 3448 */ 3449 if (adapter->num_vlans == 0) 3450 return; 3451 3452 /* 3453 * A soft reset zero's out the VFTA, so 3454 * we need to repopulate it now. 3455 */ 3456 for (int i = 0; i < EM_VFTA_SIZE; i++) 3457 if (adapter->shadow_vfta[i] != 0) 3458 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, 3459 i, adapter->shadow_vfta[i]); 3460 3461 reg = E1000_READ_REG(hw, E1000_CTRL); 3462 reg |= E1000_CTRL_VME; 3463 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3464 3465 /* Enable the Filter Table */ 3466 reg = E1000_READ_REG(hw, E1000_RCTL); 3467 reg &= ~E1000_RCTL_CFIEN; 3468 reg |= E1000_RCTL_VFE; 3469 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3470 } 3471 3472 static void 3473 em_if_intr_enable(if_ctx_t ctx) 3474 { 3475 struct adapter *adapter = iflib_get_softc(ctx); 3476 struct e1000_hw *hw = &adapter->hw; 3477 u32 ims_mask = IMS_ENABLE_MASK; 3478 3479 if (adapter->intr_type == IFLIB_INTR_MSIX) { 3480 E1000_WRITE_REG(hw, EM_EIAC, adapter->ims); 3481 ims_mask |= adapter->ims; 3482 } 3483 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3484 } 3485 3486 static void 3487 em_if_intr_disable(if_ctx_t ctx) 3488 { 3489 struct adapter *adapter = iflib_get_softc(ctx); 3490 struct e1000_hw *hw = &adapter->hw; 3491 3492 if (adapter->intr_type == IFLIB_INTR_MSIX) 3493 E1000_WRITE_REG(hw, EM_EIAC, 0); 3494 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3495 } 3496 3497 static void 3498 igb_if_intr_enable(if_ctx_t ctx) 3499 { 3500 struct adapter *adapter = iflib_get_softc(ctx); 3501 struct e1000_hw *hw = &adapter->hw; 3502 u32 mask; 3503 3504 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3505 mask = (adapter->que_mask | adapter->link_mask); 3506 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3507 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3508 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3509 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3510 } else 3511 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3512 E1000_WRITE_FLUSH(hw); 3513 } 3514 3515 static void 3516 igb_if_intr_disable(if_ctx_t ctx) 3517 { 3518 struct adapter *adapter = iflib_get_softc(ctx); 3519 struct e1000_hw *hw = &adapter->hw; 3520 3521 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 3522 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3523 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3524 } 3525 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3526 E1000_WRITE_FLUSH(hw); 3527 } 3528 3529 /* 3530 * Bit of a misnomer, what this really means is 3531 * to enable OS management of the system... aka 3532 * to disable special hardware management features 3533 */ 3534 static void 3535 em_init_manageability(struct adapter *adapter) 3536 { 3537 /* A shared code workaround */ 3538 #define E1000_82542_MANC2H E1000_MANC2H 3539 if (adapter->has_manage) { 3540 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 3541 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3542 3543 /* disable hardware interception of ARP */ 3544 manc &= ~(E1000_MANC_ARP_EN); 3545 3546 /* enable receiving management packets to the host */ 3547 manc |= E1000_MANC_EN_MNG2HOST; 3548 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3549 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3550 manc2h |= E1000_MNG2HOST_PORT_623; 3551 manc2h |= E1000_MNG2HOST_PORT_664; 3552 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 3553 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3554 } 3555 } 3556 3557 /* 3558 * Give control back to hardware management 3559 * controller if there is one. 3560 */ 3561 static void 3562 em_release_manageability(struct adapter *adapter) 3563 { 3564 if (adapter->has_manage) { 3565 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 3566 3567 /* re-enable hardware interception of ARP */ 3568 manc |= E1000_MANC_ARP_EN; 3569 manc &= ~E1000_MANC_EN_MNG2HOST; 3570 3571 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 3572 } 3573 } 3574 3575 /* 3576 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3577 * For ASF and Pass Through versions of f/w this means 3578 * that the driver is loaded. For AMT version type f/w 3579 * this means that the network i/f is open. 3580 */ 3581 static void 3582 em_get_hw_control(struct adapter *adapter) 3583 { 3584 u32 ctrl_ext, swsm; 3585 3586 if (adapter->vf_ifp) 3587 return; 3588 3589 if (adapter->hw.mac.type == e1000_82573) { 3590 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3591 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3592 swsm | E1000_SWSM_DRV_LOAD); 3593 return; 3594 } 3595 /* else */ 3596 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3597 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3598 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3599 } 3600 3601 /* 3602 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3603 * For ASF and Pass Through versions of f/w this means that 3604 * the driver is no longer loaded. For AMT versions of the 3605 * f/w this means that the network i/f is closed. 3606 */ 3607 static void 3608 em_release_hw_control(struct adapter *adapter) 3609 { 3610 u32 ctrl_ext, swsm; 3611 3612 if (!adapter->has_manage) 3613 return; 3614 3615 if (adapter->hw.mac.type == e1000_82573) { 3616 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 3617 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 3618 swsm & ~E1000_SWSM_DRV_LOAD); 3619 return; 3620 } 3621 /* else */ 3622 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3623 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 3624 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3625 return; 3626 } 3627 3628 static int 3629 em_is_valid_ether_addr(u8 *addr) 3630 { 3631 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3632 3633 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3634 return (FALSE); 3635 } 3636 3637 return (TRUE); 3638 } 3639 3640 /* 3641 ** Parse the interface capabilities with regard 3642 ** to both system management and wake-on-lan for 3643 ** later use. 3644 */ 3645 static void 3646 em_get_wakeup(if_ctx_t ctx) 3647 { 3648 struct adapter *adapter = iflib_get_softc(ctx); 3649 device_t dev = iflib_get_dev(ctx); 3650 u16 eeprom_data = 0, device_id, apme_mask; 3651 3652 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 3653 apme_mask = EM_EEPROM_APME; 3654 3655 switch (adapter->hw.mac.type) { 3656 case e1000_82542: 3657 case e1000_82543: 3658 break; 3659 case e1000_82544: 3660 e1000_read_nvm(&adapter->hw, 3661 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3662 apme_mask = EM_82544_APME; 3663 break; 3664 case e1000_82546: 3665 case e1000_82546_rev_3: 3666 if (adapter->hw.bus.func == 1) { 3667 e1000_read_nvm(&adapter->hw, 3668 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3669 break; 3670 } else 3671 e1000_read_nvm(&adapter->hw, 3672 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3673 break; 3674 case e1000_82573: 3675 case e1000_82583: 3676 adapter->has_amt = TRUE; 3677 /* FALLTHROUGH */ 3678 case e1000_82571: 3679 case e1000_82572: 3680 case e1000_80003es2lan: 3681 if (adapter->hw.bus.func == 1) { 3682 e1000_read_nvm(&adapter->hw, 3683 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3684 break; 3685 } else 3686 e1000_read_nvm(&adapter->hw, 3687 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3688 break; 3689 case e1000_ich8lan: 3690 case e1000_ich9lan: 3691 case e1000_ich10lan: 3692 case e1000_pchlan: 3693 case e1000_pch2lan: 3694 case e1000_pch_lpt: 3695 case e1000_pch_spt: 3696 case e1000_82575: /* listing all igb devices */ 3697 case e1000_82576: 3698 case e1000_82580: 3699 case e1000_i350: 3700 case e1000_i354: 3701 case e1000_i210: 3702 case e1000_i211: 3703 case e1000_vfadapt: 3704 case e1000_vfadapt_i350: 3705 apme_mask = E1000_WUC_APME; 3706 adapter->has_amt = TRUE; 3707 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC); 3708 break; 3709 default: 3710 e1000_read_nvm(&adapter->hw, 3711 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3712 break; 3713 } 3714 if (eeprom_data & apme_mask) 3715 adapter->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3716 /* 3717 * We have the eeprom settings, now apply the special cases 3718 * where the eeprom may be wrong or the board won't support 3719 * wake on lan on a particular port 3720 */ 3721 device_id = pci_get_device(dev); 3722 switch (device_id) { 3723 case E1000_DEV_ID_82546GB_PCIE: 3724 adapter->wol = 0; 3725 break; 3726 case E1000_DEV_ID_82546EB_FIBER: 3727 case E1000_DEV_ID_82546GB_FIBER: 3728 /* Wake events only supported on port A for dual fiber 3729 * regardless of eeprom setting */ 3730 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3731 E1000_STATUS_FUNC_1) 3732 adapter->wol = 0; 3733 break; 3734 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3735 /* if quad port adapter, disable WoL on all but port A */ 3736 if (global_quad_port_a != 0) 3737 adapter->wol = 0; 3738 /* Reset for multiple quad port adapters */ 3739 if (++global_quad_port_a == 4) 3740 global_quad_port_a = 0; 3741 break; 3742 case E1000_DEV_ID_82571EB_FIBER: 3743 /* Wake events only supported on port A for dual fiber 3744 * regardless of eeprom setting */ 3745 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 3746 E1000_STATUS_FUNC_1) 3747 adapter->wol = 0; 3748 break; 3749 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3750 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3751 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3752 /* if quad port adapter, disable WoL on all but port A */ 3753 if (global_quad_port_a != 0) 3754 adapter->wol = 0; 3755 /* Reset for multiple quad port adapters */ 3756 if (++global_quad_port_a == 4) 3757 global_quad_port_a = 0; 3758 break; 3759 } 3760 return; 3761 } 3762 3763 3764 /* 3765 * Enable PCI Wake On Lan capability 3766 */ 3767 static void 3768 em_enable_wakeup(if_ctx_t ctx) 3769 { 3770 struct adapter *adapter = iflib_get_softc(ctx); 3771 device_t dev = iflib_get_dev(ctx); 3772 if_t ifp = iflib_get_ifp(ctx); 3773 int error = 0; 3774 u32 pmc, ctrl, ctrl_ext, rctl; 3775 u16 status; 3776 3777 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 3778 return; 3779 3780 /* 3781 * Determine type of Wakeup: note that wol 3782 * is set with all bits on by default. 3783 */ 3784 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 3785 adapter->wol &= ~E1000_WUFC_MAG; 3786 3787 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 3788 adapter->wol &= ~E1000_WUFC_EX; 3789 3790 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 3791 adapter->wol &= ~E1000_WUFC_MC; 3792 else { 3793 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 3794 rctl |= E1000_RCTL_MPE; 3795 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl); 3796 } 3797 3798 if (!(adapter->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) { 3799 if (adapter->hw.mac.type >= e1000_pch_lpt) { 3800 e1000_enable_ulp_lpt_lp(&adapter->hw, TRUE); 3801 } 3802 goto pme; 3803 } 3804 3805 /* Advertise the wakeup capability */ 3806 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 3807 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 3808 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 3809 3810 /* Keep the laser running on Fiber adapters */ 3811 if (adapter->hw.phy.media_type == e1000_media_type_fiber || 3812 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 3813 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 3814 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 3815 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, ctrl_ext); 3816 } 3817 3818 if ((adapter->hw.mac.type == e1000_ich8lan) || 3819 (adapter->hw.mac.type == e1000_pchlan) || 3820 (adapter->hw.mac.type == e1000_ich9lan) || 3821 (adapter->hw.mac.type == e1000_ich10lan)) 3822 e1000_suspend_workarounds_ich8lan(&adapter->hw); 3823 3824 if ( adapter->hw.mac.type >= e1000_pchlan) { 3825 error = em_enable_phy_wakeup(adapter); 3826 if (error) 3827 goto pme; 3828 } else { 3829 /* Enable wakeup by the MAC */ 3830 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 3831 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 3832 } 3833 3834 if (adapter->hw.phy.type == e1000_phy_igp_3) 3835 e1000_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 3836 3837 pme: 3838 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 3839 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3840 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 3841 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3842 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 3843 3844 return; 3845 } 3846 3847 /* 3848 * WOL in the newer chipset interfaces (pchlan) 3849 * require thing to be copied into the phy 3850 */ 3851 static int 3852 em_enable_phy_wakeup(struct adapter *adapter) 3853 { 3854 struct e1000_hw *hw = &adapter->hw; 3855 u32 mreg, ret = 0; 3856 u16 preg; 3857 3858 /* copy MAC RARs to PHY RARs */ 3859 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 3860 3861 /* copy MAC MTA to PHY MTA */ 3862 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 3863 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 3864 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 3865 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 3866 (u16)((mreg >> 16) & 0xFFFF)); 3867 } 3868 3869 /* configure PHY Rx Control register */ 3870 e1000_read_phy_reg(hw, BM_RCTL, &preg); 3871 mreg = E1000_READ_REG(hw, E1000_RCTL); 3872 if (mreg & E1000_RCTL_UPE) 3873 preg |= BM_RCTL_UPE; 3874 if (mreg & E1000_RCTL_MPE) 3875 preg |= BM_RCTL_MPE; 3876 preg &= ~(BM_RCTL_MO_MASK); 3877 if (mreg & E1000_RCTL_MO_3) 3878 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 3879 << BM_RCTL_MO_SHIFT); 3880 if (mreg & E1000_RCTL_BAM) 3881 preg |= BM_RCTL_BAM; 3882 if (mreg & E1000_RCTL_PMCF) 3883 preg |= BM_RCTL_PMCF; 3884 mreg = E1000_READ_REG(hw, E1000_CTRL); 3885 if (mreg & E1000_CTRL_RFCE) 3886 preg |= BM_RCTL_RFCE; 3887 e1000_write_phy_reg(hw, BM_RCTL, preg); 3888 3889 /* enable PHY wakeup in MAC register */ 3890 E1000_WRITE_REG(hw, E1000_WUC, 3891 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 3892 E1000_WRITE_REG(hw, E1000_WUFC, adapter->wol); 3893 3894 /* configure and enable PHY wakeup in PHY registers */ 3895 e1000_write_phy_reg(hw, BM_WUFC, adapter->wol); 3896 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 3897 3898 /* activate PHY wakeup */ 3899 ret = hw->phy.ops.acquire(hw); 3900 if (ret) { 3901 printf("Could not acquire PHY\n"); 3902 return ret; 3903 } 3904 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 3905 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 3906 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 3907 if (ret) { 3908 printf("Could not read PHY page 769\n"); 3909 goto out; 3910 } 3911 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 3912 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 3913 if (ret) 3914 printf("Could not set PHY Host Wakeup bit\n"); 3915 out: 3916 hw->phy.ops.release(hw); 3917 3918 return ret; 3919 } 3920 3921 static void 3922 em_if_led_func(if_ctx_t ctx, int onoff) 3923 { 3924 struct adapter *adapter = iflib_get_softc(ctx); 3925 3926 if (onoff) { 3927 e1000_setup_led(&adapter->hw); 3928 e1000_led_on(&adapter->hw); 3929 } else { 3930 e1000_led_off(&adapter->hw); 3931 e1000_cleanup_led(&adapter->hw); 3932 } 3933 } 3934 3935 /* 3936 * Disable the L0S and L1 LINK states 3937 */ 3938 static void 3939 em_disable_aspm(struct adapter *adapter) 3940 { 3941 int base, reg; 3942 u16 link_cap,link_ctrl; 3943 device_t dev = adapter->dev; 3944 3945 switch (adapter->hw.mac.type) { 3946 case e1000_82573: 3947 case e1000_82574: 3948 case e1000_82583: 3949 break; 3950 default: 3951 return; 3952 } 3953 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 3954 return; 3955 reg = base + PCIER_LINK_CAP; 3956 link_cap = pci_read_config(dev, reg, 2); 3957 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 3958 return; 3959 reg = base + PCIER_LINK_CTL; 3960 link_ctrl = pci_read_config(dev, reg, 2); 3961 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 3962 pci_write_config(dev, reg, link_ctrl, 2); 3963 return; 3964 } 3965 3966 /********************************************************************** 3967 * 3968 * Update the board statistics counters. 3969 * 3970 **********************************************************************/ 3971 static void 3972 em_update_stats_counters(struct adapter *adapter) 3973 { 3974 u64 prev_xoffrxc = adapter->stats.xoffrxc; 3975 3976 if(adapter->hw.phy.media_type == e1000_media_type_copper || 3977 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 3978 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 3979 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 3980 } 3981 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 3982 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 3983 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 3984 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 3985 3986 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 3987 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 3988 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 3989 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 3990 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 3991 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 3992 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 3993 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 3994 /* 3995 ** For watchdog management we need to know if we have been 3996 ** paused during the last interval, so capture that here. 3997 */ 3998 if (adapter->stats.xoffrxc != prev_xoffrxc) 3999 adapter->shared->isc_pause_frames = 1; 4000 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4001 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4002 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4003 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4004 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4005 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4006 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4007 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4008 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 4009 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 4010 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 4011 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 4012 4013 /* For the 64-bit byte counters the low dword must be read first. */ 4014 /* Both registers clear on the read of the high dword */ 4015 4016 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCL) + 4017 ((u64)E1000_READ_REG(&adapter->hw, E1000_GORCH) << 32); 4018 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCL) + 4019 ((u64)E1000_READ_REG(&adapter->hw, E1000_GOTCH) << 32); 4020 4021 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 4022 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 4023 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 4024 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 4025 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 4026 4027 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 4028 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 4029 4030 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 4031 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 4032 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 4033 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 4034 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 4035 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 4036 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 4037 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 4038 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 4039 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 4040 4041 /* Interrupt Counts */ 4042 4043 adapter->stats.iac += E1000_READ_REG(&adapter->hw, E1000_IAC); 4044 adapter->stats.icrxptc += E1000_READ_REG(&adapter->hw, E1000_ICRXPTC); 4045 adapter->stats.icrxatc += E1000_READ_REG(&adapter->hw, E1000_ICRXATC); 4046 adapter->stats.ictxptc += E1000_READ_REG(&adapter->hw, E1000_ICTXPTC); 4047 adapter->stats.ictxatc += E1000_READ_REG(&adapter->hw, E1000_ICTXATC); 4048 adapter->stats.ictxqec += E1000_READ_REG(&adapter->hw, E1000_ICTXQEC); 4049 adapter->stats.ictxqmtc += E1000_READ_REG(&adapter->hw, E1000_ICTXQMTC); 4050 adapter->stats.icrxdmtc += E1000_READ_REG(&adapter->hw, E1000_ICRXDMTC); 4051 adapter->stats.icrxoc += E1000_READ_REG(&adapter->hw, E1000_ICRXOC); 4052 4053 if (adapter->hw.mac.type >= e1000_82543) { 4054 adapter->stats.algnerrc += 4055 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 4056 adapter->stats.rxerrc += 4057 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 4058 adapter->stats.tncrs += 4059 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 4060 adapter->stats.cexterr += 4061 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 4062 adapter->stats.tsctc += 4063 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 4064 adapter->stats.tsctfc += 4065 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 4066 } 4067 } 4068 4069 static uint64_t 4070 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4071 { 4072 struct adapter *adapter = iflib_get_softc(ctx); 4073 struct ifnet *ifp = iflib_get_ifp(ctx); 4074 4075 switch (cnt) { 4076 case IFCOUNTER_COLLISIONS: 4077 return (adapter->stats.colc); 4078 case IFCOUNTER_IERRORS: 4079 return (adapter->dropped_pkts + adapter->stats.rxerrc + 4080 adapter->stats.crcerrs + adapter->stats.algnerrc + 4081 adapter->stats.ruc + adapter->stats.roc + 4082 adapter->stats.mpc + adapter->stats.cexterr); 4083 case IFCOUNTER_OERRORS: 4084 return (adapter->stats.ecol + adapter->stats.latecol + 4085 adapter->watchdog_events); 4086 default: 4087 return (if_get_counter_default(ifp, cnt)); 4088 } 4089 } 4090 4091 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4092 * @ctx: iflib context 4093 * @event: event code to check 4094 * 4095 * Defaults to returning true for unknown events. 4096 * 4097 * @returns true if iflib needs to reinit the interface 4098 */ 4099 static bool 4100 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4101 { 4102 switch (event) { 4103 case IFLIB_RESTART_VLAN_CONFIG: 4104 default: 4105 return (true); 4106 } 4107 } 4108 4109 /* Export a single 32-bit register via a read-only sysctl. */ 4110 static int 4111 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4112 { 4113 struct adapter *adapter; 4114 u_int val; 4115 4116 adapter = oidp->oid_arg1; 4117 val = E1000_READ_REG(&adapter->hw, oidp->oid_arg2); 4118 return (sysctl_handle_int(oidp, &val, 0, req)); 4119 } 4120 4121 /* 4122 * Add sysctl variables, one per statistic, to the system. 4123 */ 4124 static void 4125 em_add_hw_stats(struct adapter *adapter) 4126 { 4127 device_t dev = iflib_get_dev(adapter->ctx); 4128 struct em_tx_queue *tx_que = adapter->tx_queues; 4129 struct em_rx_queue *rx_que = adapter->rx_queues; 4130 4131 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4132 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4133 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4134 struct e1000_hw_stats *stats = &adapter->stats; 4135 4136 struct sysctl_oid *stat_node, *queue_node, *int_node; 4137 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4138 4139 #define QUEUE_NAME_LEN 32 4140 char namebuf[QUEUE_NAME_LEN]; 4141 4142 /* Driver Statistics */ 4143 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4144 CTLFLAG_RD, &adapter->dropped_pkts, 4145 "Driver dropped packets"); 4146 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4147 CTLFLAG_RD, &adapter->link_irq, 4148 "Link MSI-X IRQ Handled"); 4149 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4150 CTLFLAG_RD, &adapter->rx_overruns, 4151 "RX overruns"); 4152 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4153 CTLFLAG_RD, &adapter->watchdog_events, 4154 "Watchdog timeouts"); 4155 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4156 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4157 adapter, E1000_CTRL, em_sysctl_reg_handler, "IU", 4158 "Device Control Register"); 4159 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4160 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4161 adapter, E1000_RCTL, em_sysctl_reg_handler, "IU", 4162 "Receiver Control Register"); 4163 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4164 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 4165 "Flow Control High Watermark"); 4166 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4167 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 4168 "Flow Control Low Watermark"); 4169 4170 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 4171 struct tx_ring *txr = &tx_que->txr; 4172 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4173 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4174 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4175 queue_list = SYSCTL_CHILDREN(queue_node); 4176 4177 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4178 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4179 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4180 "Transmit Descriptor Head"); 4181 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4182 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4183 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4184 "Transmit Descriptor Tail"); 4185 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4186 CTLFLAG_RD, &txr->tx_irq, 4187 "Queue MSI-X Transmit Interrupts"); 4188 } 4189 4190 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 4191 struct rx_ring *rxr = &rx_que->rxr; 4192 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4193 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4194 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4195 queue_list = SYSCTL_CHILDREN(queue_node); 4196 4197 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4198 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4199 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4200 "Receive Descriptor Head"); 4201 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4202 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 4203 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4204 "Receive Descriptor Tail"); 4205 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4206 CTLFLAG_RD, &rxr->rx_irq, 4207 "Queue MSI-X Receive Interrupts"); 4208 } 4209 4210 /* MAC stats get their own sub node */ 4211 4212 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4213 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4214 stat_list = SYSCTL_CHILDREN(stat_node); 4215 4216 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4217 CTLFLAG_RD, &stats->ecol, 4218 "Excessive collisions"); 4219 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4220 CTLFLAG_RD, &stats->scc, 4221 "Single collisions"); 4222 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4223 CTLFLAG_RD, &stats->mcc, 4224 "Multiple collisions"); 4225 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4226 CTLFLAG_RD, &stats->latecol, 4227 "Late collisions"); 4228 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4229 CTLFLAG_RD, &stats->colc, 4230 "Collision Count"); 4231 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4232 CTLFLAG_RD, &adapter->stats.symerrs, 4233 "Symbol Errors"); 4234 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4235 CTLFLAG_RD, &adapter->stats.sec, 4236 "Sequence Errors"); 4237 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4238 CTLFLAG_RD, &adapter->stats.dc, 4239 "Defer Count"); 4240 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4241 CTLFLAG_RD, &adapter->stats.mpc, 4242 "Missed Packets"); 4243 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4244 CTLFLAG_RD, &adapter->stats.rnbc, 4245 "Receive No Buffers"); 4246 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4247 CTLFLAG_RD, &adapter->stats.ruc, 4248 "Receive Undersize"); 4249 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4250 CTLFLAG_RD, &adapter->stats.rfc, 4251 "Fragmented Packets Received "); 4252 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4253 CTLFLAG_RD, &adapter->stats.roc, 4254 "Oversized Packets Received"); 4255 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4256 CTLFLAG_RD, &adapter->stats.rjc, 4257 "Recevied Jabber"); 4258 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4259 CTLFLAG_RD, &adapter->stats.rxerrc, 4260 "Receive Errors"); 4261 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4262 CTLFLAG_RD, &adapter->stats.crcerrs, 4263 "CRC errors"); 4264 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4265 CTLFLAG_RD, &adapter->stats.algnerrc, 4266 "Alignment Errors"); 4267 /* On 82575 these are collision counts */ 4268 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4269 CTLFLAG_RD, &adapter->stats.cexterr, 4270 "Collision/Carrier extension errors"); 4271 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4272 CTLFLAG_RD, &adapter->stats.xonrxc, 4273 "XON Received"); 4274 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4275 CTLFLAG_RD, &adapter->stats.xontxc, 4276 "XON Transmitted"); 4277 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4278 CTLFLAG_RD, &adapter->stats.xoffrxc, 4279 "XOFF Received"); 4280 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4281 CTLFLAG_RD, &adapter->stats.xofftxc, 4282 "XOFF Transmitted"); 4283 4284 /* Packet Reception Stats */ 4285 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4286 CTLFLAG_RD, &adapter->stats.tpr, 4287 "Total Packets Received "); 4288 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4289 CTLFLAG_RD, &adapter->stats.gprc, 4290 "Good Packets Received"); 4291 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4292 CTLFLAG_RD, &adapter->stats.bprc, 4293 "Broadcast Packets Received"); 4294 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4295 CTLFLAG_RD, &adapter->stats.mprc, 4296 "Multicast Packets Received"); 4297 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4298 CTLFLAG_RD, &adapter->stats.prc64, 4299 "64 byte frames received "); 4300 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4301 CTLFLAG_RD, &adapter->stats.prc127, 4302 "65-127 byte frames received"); 4303 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4304 CTLFLAG_RD, &adapter->stats.prc255, 4305 "128-255 byte frames received"); 4306 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4307 CTLFLAG_RD, &adapter->stats.prc511, 4308 "256-511 byte frames received"); 4309 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4310 CTLFLAG_RD, &adapter->stats.prc1023, 4311 "512-1023 byte frames received"); 4312 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4313 CTLFLAG_RD, &adapter->stats.prc1522, 4314 "1023-1522 byte frames received"); 4315 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4316 CTLFLAG_RD, &adapter->stats.gorc, 4317 "Good Octets Received"); 4318 4319 /* Packet Transmission Stats */ 4320 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4321 CTLFLAG_RD, &adapter->stats.gotc, 4322 "Good Octets Transmitted"); 4323 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4324 CTLFLAG_RD, &adapter->stats.tpt, 4325 "Total Packets Transmitted"); 4326 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4327 CTLFLAG_RD, &adapter->stats.gptc, 4328 "Good Packets Transmitted"); 4329 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4330 CTLFLAG_RD, &adapter->stats.bptc, 4331 "Broadcast Packets Transmitted"); 4332 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4333 CTLFLAG_RD, &adapter->stats.mptc, 4334 "Multicast Packets Transmitted"); 4335 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4336 CTLFLAG_RD, &adapter->stats.ptc64, 4337 "64 byte frames transmitted "); 4338 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4339 CTLFLAG_RD, &adapter->stats.ptc127, 4340 "65-127 byte frames transmitted"); 4341 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4342 CTLFLAG_RD, &adapter->stats.ptc255, 4343 "128-255 byte frames transmitted"); 4344 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4345 CTLFLAG_RD, &adapter->stats.ptc511, 4346 "256-511 byte frames transmitted"); 4347 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4348 CTLFLAG_RD, &adapter->stats.ptc1023, 4349 "512-1023 byte frames transmitted"); 4350 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4351 CTLFLAG_RD, &adapter->stats.ptc1522, 4352 "1024-1522 byte frames transmitted"); 4353 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4354 CTLFLAG_RD, &adapter->stats.tsctc, 4355 "TSO Contexts Transmitted"); 4356 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4357 CTLFLAG_RD, &adapter->stats.tsctfc, 4358 "TSO Contexts Failed"); 4359 4360 4361 /* Interrupt Stats */ 4362 4363 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4364 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4365 int_list = SYSCTL_CHILDREN(int_node); 4366 4367 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4368 CTLFLAG_RD, &adapter->stats.iac, 4369 "Interrupt Assertion Count"); 4370 4371 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4372 CTLFLAG_RD, &adapter->stats.icrxptc, 4373 "Interrupt Cause Rx Pkt Timer Expire Count"); 4374 4375 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4376 CTLFLAG_RD, &adapter->stats.icrxatc, 4377 "Interrupt Cause Rx Abs Timer Expire Count"); 4378 4379 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4380 CTLFLAG_RD, &adapter->stats.ictxptc, 4381 "Interrupt Cause Tx Pkt Timer Expire Count"); 4382 4383 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4384 CTLFLAG_RD, &adapter->stats.ictxatc, 4385 "Interrupt Cause Tx Abs Timer Expire Count"); 4386 4387 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4388 CTLFLAG_RD, &adapter->stats.ictxqec, 4389 "Interrupt Cause Tx Queue Empty Count"); 4390 4391 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4392 CTLFLAG_RD, &adapter->stats.ictxqmtc, 4393 "Interrupt Cause Tx Queue Min Thresh Count"); 4394 4395 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4396 CTLFLAG_RD, &adapter->stats.icrxdmtc, 4397 "Interrupt Cause Rx Desc Min Thresh Count"); 4398 4399 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4400 CTLFLAG_RD, &adapter->stats.icrxoc, 4401 "Interrupt Cause Receiver Overrun Count"); 4402 } 4403 4404 /********************************************************************** 4405 * 4406 * This routine provides a way to dump out the adapter eeprom, 4407 * often a useful debug/service tool. This only dumps the first 4408 * 32 words, stuff that matters is in that extent. 4409 * 4410 **********************************************************************/ 4411 static int 4412 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4413 { 4414 struct adapter *adapter = (struct adapter *)arg1; 4415 int error; 4416 int result; 4417 4418 result = -1; 4419 error = sysctl_handle_int(oidp, &result, 0, req); 4420 4421 if (error || !req->newptr) 4422 return (error); 4423 4424 /* 4425 * This value will cause a hex dump of the 4426 * first 32 16-bit words of the EEPROM to 4427 * the screen. 4428 */ 4429 if (result == 1) 4430 em_print_nvm_info(adapter); 4431 4432 return (error); 4433 } 4434 4435 static void 4436 em_print_nvm_info(struct adapter *adapter) 4437 { 4438 u16 eeprom_data; 4439 int i, j, row = 0; 4440 4441 /* Its a bit crude, but it gets the job done */ 4442 printf("\nInterface EEPROM Dump:\n"); 4443 printf("Offset\n0x0000 "); 4444 for (i = 0, j = 0; i < 32; i++, j++) { 4445 if (j == 8) { /* Make the offset block */ 4446 j = 0; ++row; 4447 printf("\n0x00%x0 ",row); 4448 } 4449 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 4450 printf("%04x ", eeprom_data); 4451 } 4452 printf("\n"); 4453 } 4454 4455 static int 4456 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4457 { 4458 struct em_int_delay_info *info; 4459 struct adapter *adapter; 4460 u32 regval; 4461 int error, usecs, ticks; 4462 4463 info = (struct em_int_delay_info *) arg1; 4464 usecs = info->value; 4465 error = sysctl_handle_int(oidp, &usecs, 0, req); 4466 if (error != 0 || req->newptr == NULL) 4467 return (error); 4468 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4469 return (EINVAL); 4470 info->value = usecs; 4471 ticks = EM_USECS_TO_TICKS(usecs); 4472 if (info->offset == E1000_ITR) /* units are 256ns here */ 4473 ticks *= 4; 4474 4475 adapter = info->adapter; 4476 4477 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4478 regval = (regval & ~0xffff) | (ticks & 0xffff); 4479 /* Handle a few special cases. */ 4480 switch (info->offset) { 4481 case E1000_RDTR: 4482 break; 4483 case E1000_TIDV: 4484 if (ticks == 0) { 4485 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4486 /* Don't write 0 into the TIDV register. */ 4487 regval++; 4488 } else 4489 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4490 break; 4491 } 4492 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4493 return (0); 4494 } 4495 4496 static void 4497 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4498 const char *description, struct em_int_delay_info *info, 4499 int offset, int value) 4500 { 4501 info->adapter = adapter; 4502 info->offset = offset; 4503 info->value = value; 4504 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4505 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4506 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4507 info, 0, em_sysctl_int_delay, "I", description); 4508 } 4509 4510 /* 4511 * Set flow control using sysctl: 4512 * Flow control values: 4513 * 0 - off 4514 * 1 - rx pause 4515 * 2 - tx pause 4516 * 3 - full 4517 */ 4518 static int 4519 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4520 { 4521 int error; 4522 static int input = 3; /* default is full */ 4523 struct adapter *adapter = (struct adapter *) arg1; 4524 4525 error = sysctl_handle_int(oidp, &input, 0, req); 4526 4527 if ((error) || (req->newptr == NULL)) 4528 return (error); 4529 4530 if (input == adapter->fc) /* no change? */ 4531 return (error); 4532 4533 switch (input) { 4534 case e1000_fc_rx_pause: 4535 case e1000_fc_tx_pause: 4536 case e1000_fc_full: 4537 case e1000_fc_none: 4538 adapter->hw.fc.requested_mode = input; 4539 adapter->fc = input; 4540 break; 4541 default: 4542 /* Do nothing */ 4543 return (error); 4544 } 4545 4546 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 4547 e1000_force_mac_fc(&adapter->hw); 4548 return (error); 4549 } 4550 4551 /* 4552 * Manage Energy Efficient Ethernet: 4553 * Control values: 4554 * 0/1 - enabled/disabled 4555 */ 4556 static int 4557 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4558 { 4559 struct adapter *adapter = (struct adapter *) arg1; 4560 int error, value; 4561 4562 value = adapter->hw.dev_spec.ich8lan.eee_disable; 4563 error = sysctl_handle_int(oidp, &value, 0, req); 4564 if (error || req->newptr == NULL) 4565 return (error); 4566 adapter->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4567 em_if_init(adapter->ctx); 4568 4569 return (0); 4570 } 4571 4572 static int 4573 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4574 { 4575 struct adapter *adapter; 4576 int error; 4577 int result; 4578 4579 result = -1; 4580 error = sysctl_handle_int(oidp, &result, 0, req); 4581 4582 if (error || !req->newptr) 4583 return (error); 4584 4585 if (result == 1) { 4586 adapter = (struct adapter *) arg1; 4587 em_print_debug_info(adapter); 4588 } 4589 4590 return (error); 4591 } 4592 4593 static int 4594 em_get_rs(SYSCTL_HANDLER_ARGS) 4595 { 4596 struct adapter *adapter = (struct adapter *) arg1; 4597 int error; 4598 int result; 4599 4600 result = 0; 4601 error = sysctl_handle_int(oidp, &result, 0, req); 4602 4603 if (error || !req->newptr || result != 1) 4604 return (error); 4605 em_dump_rs(adapter); 4606 4607 return (error); 4608 } 4609 4610 static void 4611 em_if_debug(if_ctx_t ctx) 4612 { 4613 em_dump_rs(iflib_get_softc(ctx)); 4614 } 4615 4616 /* 4617 * This routine is meant to be fluid, add whatever is 4618 * needed for debugging a problem. -jfv 4619 */ 4620 static void 4621 em_print_debug_info(struct adapter *adapter) 4622 { 4623 device_t dev = iflib_get_dev(adapter->ctx); 4624 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 4625 struct tx_ring *txr = &adapter->tx_queues->txr; 4626 struct rx_ring *rxr = &adapter->rx_queues->rxr; 4627 4628 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4629 printf("Interface is RUNNING "); 4630 else 4631 printf("Interface is NOT RUNNING\n"); 4632 4633 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4634 printf("and INACTIVE\n"); 4635 else 4636 printf("and ACTIVE\n"); 4637 4638 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 4639 device_printf(dev, "TX Queue %d ------\n", i); 4640 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 4641 E1000_READ_REG(&adapter->hw, E1000_TDH(i)), 4642 E1000_READ_REG(&adapter->hw, E1000_TDT(i))); 4643 4644 } 4645 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 4646 device_printf(dev, "RX Queue %d ------\n", j); 4647 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 4648 E1000_READ_REG(&adapter->hw, E1000_RDH(j)), 4649 E1000_READ_REG(&adapter->hw, E1000_RDT(j))); 4650 } 4651 } 4652 4653 /* 4654 * 82574 only: 4655 * Write a new value to the EEPROM increasing the number of MSI-X 4656 * vectors from 3 to 5, for proper multiqueue support. 4657 */ 4658 static void 4659 em_enable_vectors_82574(if_ctx_t ctx) 4660 { 4661 struct adapter *adapter = iflib_get_softc(ctx); 4662 struct e1000_hw *hw = &adapter->hw; 4663 device_t dev = iflib_get_dev(ctx); 4664 u16 edata; 4665 4666 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4667 if (bootverbose) 4668 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 4669 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 4670 device_printf(dev, "Writing to eeprom: increasing " 4671 "reported MSI-X vectors from 3 to 5...\n"); 4672 edata &= ~(EM_NVM_MSIX_N_MASK); 4673 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 4674 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 4675 e1000_update_nvm_checksum(hw); 4676 device_printf(dev, "Writing to eeprom: done\n"); 4677 } 4678 } 4679