1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static const pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, 57 "Intel(R) Legacy PRO/1000 MT 82540EM"), 58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, 59 "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP, 61 "Intel(R) Legacy PRO/1000 MT 82540EP"), 62 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, 63 "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 64 PVID(0x8086, E1000_DEV_ID_82540EP_LP, 65 "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 66 67 PVID(0x8086, E1000_DEV_ID_82541EI, 68 "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 69 PVID(0x8086, E1000_DEV_ID_82541ER, 70 "Intel(R) Legacy PRO/1000 82541ER"), 71 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, 72 "Intel(R) Legacy PRO/1000 MT 82541ER"), 73 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, 74 "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 75 PVID(0x8086, E1000_DEV_ID_82541GI, 76 "Intel(R) Legacy PRO/1000 MT 82541GI"), 77 PVID(0x8086, E1000_DEV_ID_82541GI_LF, 78 "Intel(R) Legacy PRO/1000 GT 82541PI"), 79 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, 80 "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 81 82 PVID(0x8086, E1000_DEV_ID_82542, 83 "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 84 85 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, 86 "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, 88 "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 89 90 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, 91 "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 92 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, 93 "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 94 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, 95 "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 96 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, 97 "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 98 99 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, 100 "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, 102 "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, 104 "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 105 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, 106 "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 107 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, 108 "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 109 110 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, 111 "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, 113 "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 114 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, 115 "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 116 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, 117 "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, 119 "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 120 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, 121 "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, 123 "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 124 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, 125 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 126 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 127 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 128 129 PVID(0x8086, E1000_DEV_ID_82547EI, 130 "Intel(R) Legacy PRO/1000 CT 82547EI"), 131 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, 132 "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 133 PVID(0x8086, E1000_DEV_ID_82547GI, 134 "Intel(R) Legacy PRO/1000 CT 82547GI"), 135 136 /* Intel(R) - em-class devices */ 137 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, 138 "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 139 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, 140 "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 141 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, 142 "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 143 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, 144 "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 145 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, 146 "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 147 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 148 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 149 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 150 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 151 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 152 "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 153 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 154 "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 155 PVID(0x8086, E1000_DEV_ID_82572EI, 156 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 157 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, 158 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 159 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, 160 "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 161 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, 162 "Intel(R) PRO/1000 82572EI (SERDES)"), 163 PVID(0x8086, E1000_DEV_ID_82573E, 164 "Intel(R) PRO/1000 82573E (Copper)"), 165 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, 166 "Intel(R) PRO/1000 82573E AMT (Copper)"), 167 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 168 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 169 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 170 "Intel(R) 80003ES2LAN (Copper)"), 171 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 172 "Intel(R) 80003ES2LAN (SERDES)"), 173 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 174 "Intel(R) 80003ES2LAN (Dual Copper)"), 175 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 176 "Intel(R) 80003ES2LAN (Dual SERDES)"), 177 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, 178 "Intel(R) 82566MM ICH8 AMT (Mobile)"), 179 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 180 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 181 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 182 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 183 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 184 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 186 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, 187 "Intel(R) 82567LM ICH9 AMT"), 188 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, 189 "Intel(R) 82566DM-2 ICH9 AMT"), 190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 192 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 197 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 205 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 206 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 207 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 208 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 209 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 210 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 213 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, 214 "Intel(R) I218-LM LPTLP"), 215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 222 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, 223 "Intel(R) I219-LM SPT-H(2)"), 224 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, 225 "Intel(R) I219-V SPT-H(2)"), 226 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, 227 "Intel(R) I219-LM LBG(3)"), 228 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, 229 "Intel(R) I219-LM SPT(4)"), 230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 231 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, 232 "Intel(R) I219-LM SPT(5)"), 233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 234 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, 235 "Intel(R) I219-LM CNP(6)"), 236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 237 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, 238 "Intel(R) I219-LM CNP(7)"), 239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 240 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, 241 "Intel(R) I219-LM ICP(8)"), 242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 243 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, 244 "Intel(R) I219-LM ICP(9)"), 245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 246 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, 247 "Intel(R) I219-LM CMP(10)"), 248 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, 249 "Intel(R) I219-V CMP(10)"), 250 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, 251 "Intel(R) I219-LM CMP(11)"), 252 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, 253 "Intel(R) I219-V CMP(11)"), 254 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, 255 "Intel(R) I219-LM CMP(12)"), 256 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, 257 "Intel(R) I219-V CMP(12)"), 258 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, 259 "Intel(R) I219-LM TGP(13)"), 260 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, 261 "Intel(R) I219-V TGP(13)"), 262 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, 263 "Intel(R) I219-LM TGP(14)"), 264 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, 265 "Intel(R) I219-V GTP(14)"), 266 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, 267 "Intel(R) I219-LM TGP(15)"), 268 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, 269 "Intel(R) I219-V TGP(15)"), 270 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, 271 "Intel(R) I219-LM ADL(16)"), 272 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, 273 "Intel(R) I219-V ADL(16)"), 274 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, 275 "Intel(R) I219-LM ADL(17)"), 276 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, 277 "Intel(R) I219-V ADL(17)"), 278 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, 279 "Intel(R) I219-LM MTP(18)"), 280 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, 281 "Intel(R) I219-V MTP(18)"), 282 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19, 283 "Intel(R) I219-LM ADL(19)"), 284 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19, 285 "Intel(R) I219-V ADL(19)"), 286 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, 287 "Intel(R) I219-LM LNL(20)"), 288 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, 289 "Intel(R) I219-V LNL(20)"), 290 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, 291 "Intel(R) I219-LM LNL(21)"), 292 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, 293 "Intel(R) I219-V LNL(21)"), 294 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, 295 "Intel(R) I219-LM RPL(22)"), 296 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, 297 "Intel(R) I219-V RPL(22)"), 298 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, 299 "Intel(R) I219-LM RPL(23)"), 300 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, 301 "Intel(R) I219-V RPL(23)"), 302 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, 303 "Intel(R) I219-LM ARL(24)"), 304 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, 305 "Intel(R) I219-V ARL(24)"), 306 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, 307 "Intel(R) I219-LM PTP(25)"), 308 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, 309 "Intel(R) I219-V PTP(25)"), 310 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, 311 "Intel(R) I219-LM PTP(26)"), 312 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, 313 "Intel(R) I219-V PTP(26)"), 314 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, 315 "Intel(R) I219-LM PTP(27)"), 316 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, 317 "Intel(R) I219-V PTP(27)"), 318 /* required last entry */ 319 PVID_END 320 }; 321 322 static const pci_vendor_info_t igb_vendor_info_array[] = 323 { 324 /* Intel(R) - igb-class devices */ 325 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, 326 "Intel(R) PRO/1000 82575EB (Copper)"), 327 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 328 "Intel(R) PRO/1000 82575EB (SERDES)"), 329 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 330 "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 331 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 332 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 333 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, 334 "Intel(R) PRO/1000 82576NS (SERDES)"), 335 PVID(0x8086, E1000_DEV_ID_82576_FIBER, 336 "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 337 PVID(0x8086, E1000_DEV_ID_82576_SERDES, 338 "Intel(R) PRO/1000 82576 (Dual SERDES)"), 339 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, 340 "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 341 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, 342 "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 343 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, 344 "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 345 PVID(0x8086, E1000_DEV_ID_82576_VF, 346 "Intel(R) PRO/1000 82576 Virtual Function"), 347 PVID(0x8086, E1000_DEV_ID_82580_COPPER, 348 "Intel(R) I340 82580 (Copper)"), 349 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 350 PVID(0x8086, E1000_DEV_ID_82580_SERDES, 351 "Intel(R) I340 82580 (SERDES)"), 352 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 353 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, 354 "Intel(R) I340-T2 82580 (Dual Copper)"), 355 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, 356 "Intel(R) I340-F4 82580 (Quad Fiber)"), 357 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, 358 "Intel(R) DH89XXCC (SERDES)"), 359 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, 360 "Intel(R) I347-AT4 DH89XXCC"), 361 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 362 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, 363 "Intel(R) DH89XXCC (Backplane)"), 364 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 365 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 366 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 367 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 368 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 369 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 370 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, 371 "Intel(R) I210 IT (Copper)"), 372 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 373 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, 374 "Intel(R) I210 Flashless (Copper)"), 375 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, 376 "Intel(R) I210 Flashless (SERDES)"), 377 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, 378 "Intel(R) I210 Flashless (SGMII)"), 379 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 380 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 381 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 382 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 383 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, 384 "Intel(R) I354 (1.0 GbE Backplane)"), 385 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, 386 "Intel(R) I354 (2.5 GbE Backplane)"), 387 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 388 /* required last entry */ 389 PVID_END 390 }; 391 392 /********************************************************************* 393 * Function prototypes 394 *********************************************************************/ 395 static void *em_register(device_t); 396 static void *igb_register(device_t); 397 static int em_if_attach_pre(if_ctx_t); 398 static int em_if_attach_post(if_ctx_t); 399 static int em_if_detach(if_ctx_t); 400 static int em_if_shutdown(if_ctx_t); 401 static int em_if_suspend(if_ctx_t); 402 static int em_if_resume(if_ctx_t); 403 404 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 405 int); 406 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 407 int); 408 static void em_if_queues_free(if_ctx_t); 409 410 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 411 static void em_if_init(if_ctx_t); 412 static void em_if_stop(if_ctx_t); 413 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 414 static int em_if_media_change(if_ctx_t); 415 static int em_if_mtu_set(if_ctx_t, uint32_t); 416 static void em_if_timer(if_ctx_t, uint16_t); 417 static void em_if_vlan_register(if_ctx_t, u16); 418 static void em_if_vlan_unregister(if_ctx_t, u16); 419 static void em_if_watchdog_reset(if_ctx_t); 420 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 421 422 static void em_identify_hardware(if_ctx_t); 423 static int em_allocate_pci_resources(if_ctx_t); 424 static void em_free_pci_resources(if_ctx_t); 425 static void em_reset(if_ctx_t); 426 static int em_setup_interface(if_ctx_t); 427 static int em_setup_msix(if_ctx_t); 428 429 static void em_initialize_transmit_unit(if_ctx_t); 430 static void em_initialize_receive_unit(if_ctx_t); 431 432 static void em_if_intr_enable(if_ctx_t); 433 static void em_if_intr_disable(if_ctx_t); 434 static void igb_if_intr_enable(if_ctx_t); 435 static void igb_if_intr_disable(if_ctx_t); 436 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 437 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 438 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 439 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 440 static void em_if_multi_set(if_ctx_t); 441 static void em_if_update_admin_status(if_ctx_t); 442 static void em_if_debug(if_ctx_t); 443 static void em_update_stats_counters(struct e1000_softc *); 444 static void em_add_hw_stats(struct e1000_softc *); 445 static int em_if_set_promisc(if_ctx_t, int); 446 static bool em_if_vlan_filter_capable(if_ctx_t); 447 static bool em_if_vlan_filter_used(if_ctx_t); 448 static void em_if_vlan_filter_enable(struct e1000_softc *); 449 static void em_if_vlan_filter_disable(struct e1000_softc *); 450 static void em_if_vlan_filter_write(struct e1000_softc *); 451 static void em_setup_vlan_hw_support(if_ctx_t ctx); 452 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 453 static void em_print_nvm_info(struct e1000_softc *); 454 static void em_fw_version_locked(if_ctx_t); 455 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 456 static void em_print_fw_version(struct e1000_softc *); 457 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 458 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 459 static int em_get_rs(SYSCTL_HANDLER_ARGS); 460 static void em_print_debug_info(struct e1000_softc *); 461 static int em_is_valid_ether_addr(u8 *); 462 static void em_newitr(struct e1000_softc *, struct em_rx_queue *, 463 struct tx_ring *, struct rx_ring *); 464 static bool em_automask_tso(if_ctx_t); 465 static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 466 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 467 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 468 const char *, struct em_int_delay_info *, int, int); 469 /* Management and WOL Support */ 470 static void em_init_manageability(struct e1000_softc *); 471 static void em_release_manageability(struct e1000_softc *); 472 static void em_get_hw_control(struct e1000_softc *); 473 static void em_release_hw_control(struct e1000_softc *); 474 static void em_get_wakeup(if_ctx_t); 475 static void em_enable_wakeup(if_ctx_t); 476 static int em_enable_phy_wakeup(struct e1000_softc *); 477 static void em_disable_aspm(struct e1000_softc *); 478 479 int em_intr(void *); 480 481 /* MSI-X handlers */ 482 static int em_if_msix_intr_assign(if_ctx_t, int); 483 static int em_msix_link(void *); 484 static void em_handle_link(void *); 485 486 static void em_enable_vectors_82574(if_ctx_t); 487 488 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 489 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 490 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 491 static void em_if_led_func(if_ctx_t, int); 492 493 static int em_get_regs(SYSCTL_HANDLER_ARGS); 494 495 static void lem_smartspeed(struct e1000_softc *); 496 static void igb_configure_queues(struct e1000_softc *); 497 static void em_flush_desc_rings(struct e1000_softc *); 498 499 500 /********************************************************************* 501 * FreeBSD Device Interface Entry Points 502 *********************************************************************/ 503 static device_method_t em_methods[] = { 504 /* Device interface */ 505 DEVMETHOD(device_register, em_register), 506 DEVMETHOD(device_probe, iflib_device_probe), 507 DEVMETHOD(device_attach, iflib_device_attach), 508 DEVMETHOD(device_detach, iflib_device_detach), 509 DEVMETHOD(device_shutdown, iflib_device_shutdown), 510 DEVMETHOD(device_suspend, iflib_device_suspend), 511 DEVMETHOD(device_resume, iflib_device_resume), 512 DEVMETHOD_END 513 }; 514 515 static device_method_t igb_methods[] = { 516 /* Device interface */ 517 DEVMETHOD(device_register, igb_register), 518 DEVMETHOD(device_probe, iflib_device_probe), 519 DEVMETHOD(device_attach, iflib_device_attach), 520 DEVMETHOD(device_detach, iflib_device_detach), 521 DEVMETHOD(device_shutdown, iflib_device_shutdown), 522 DEVMETHOD(device_suspend, iflib_device_suspend), 523 DEVMETHOD(device_resume, iflib_device_resume), 524 DEVMETHOD_END 525 }; 526 527 528 static driver_t em_driver = { 529 "em", em_methods, sizeof(struct e1000_softc), 530 }; 531 532 DRIVER_MODULE(em, pci, em_driver, 0, 0); 533 534 MODULE_DEPEND(em, pci, 1, 1, 1); 535 MODULE_DEPEND(em, ether, 1, 1, 1); 536 MODULE_DEPEND(em, iflib, 1, 1, 1); 537 538 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 539 540 static driver_t igb_driver = { 541 "igb", igb_methods, sizeof(struct e1000_softc), 542 }; 543 544 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 545 546 MODULE_DEPEND(igb, pci, 1, 1, 1); 547 MODULE_DEPEND(igb, ether, 1, 1, 1); 548 MODULE_DEPEND(igb, iflib, 1, 1, 1); 549 550 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 551 552 static device_method_t em_if_methods[] = { 553 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 554 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 555 DEVMETHOD(ifdi_detach, em_if_detach), 556 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 557 DEVMETHOD(ifdi_suspend, em_if_suspend), 558 DEVMETHOD(ifdi_resume, em_if_resume), 559 DEVMETHOD(ifdi_init, em_if_init), 560 DEVMETHOD(ifdi_stop, em_if_stop), 561 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 562 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 563 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 564 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 565 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 566 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 567 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 568 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 569 DEVMETHOD(ifdi_media_status, em_if_media_status), 570 DEVMETHOD(ifdi_media_change, em_if_media_change), 571 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 572 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 573 DEVMETHOD(ifdi_timer, em_if_timer), 574 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 575 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 576 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 577 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 578 DEVMETHOD(ifdi_led_func, em_if_led_func), 579 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 580 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 581 DEVMETHOD(ifdi_debug, em_if_debug), 582 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 583 DEVMETHOD_END 584 }; 585 586 static driver_t em_if_driver = { 587 "em_if", em_if_methods, sizeof(struct e1000_softc) 588 }; 589 590 static device_method_t igb_if_methods[] = { 591 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 592 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 593 DEVMETHOD(ifdi_detach, em_if_detach), 594 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 595 DEVMETHOD(ifdi_suspend, em_if_suspend), 596 DEVMETHOD(ifdi_resume, em_if_resume), 597 DEVMETHOD(ifdi_init, em_if_init), 598 DEVMETHOD(ifdi_stop, em_if_stop), 599 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 600 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 601 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 602 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 603 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 604 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 605 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 606 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 607 DEVMETHOD(ifdi_media_status, em_if_media_status), 608 DEVMETHOD(ifdi_media_change, em_if_media_change), 609 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 610 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 611 DEVMETHOD(ifdi_timer, em_if_timer), 612 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 613 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 614 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 615 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 616 DEVMETHOD(ifdi_led_func, em_if_led_func), 617 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 618 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 619 DEVMETHOD(ifdi_debug, em_if_debug), 620 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 621 DEVMETHOD_END 622 }; 623 624 static driver_t igb_if_driver = { 625 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 626 }; 627 628 /********************************************************************* 629 * Tunable default values. 630 *********************************************************************/ 631 632 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 633 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 634 635 /* Allow common code without TSO */ 636 #ifndef CSUM_TSO 637 #define CSUM_TSO 0 638 #endif 639 640 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 641 "EM driver parameters"); 642 643 static int em_disable_crc_stripping = 0; 644 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 645 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 646 647 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 648 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 649 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, 650 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs"); 651 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, 652 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs"); 653 654 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 655 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 656 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 657 &em_tx_abs_int_delay_dflt, 0, 658 "Default transmit interrupt delay limit in usecs"); 659 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 660 &em_rx_abs_int_delay_dflt, 0, 661 "Default receive interrupt delay limit in usecs"); 662 663 static int em_smart_pwr_down = false; 664 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, 665 &em_smart_pwr_down, 666 0, "Set to true to leave smart power down enabled on newer adapters"); 667 668 static bool em_unsupported_tso = false; 669 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 670 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 671 672 /* Controls whether promiscuous also shows bad packets */ 673 static int em_debug_sbp = false; 674 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 675 "Show bad packets in promiscuous mode"); 676 677 /* Energy efficient ethernet - default to OFF */ 678 static int eee_setting = 1; 679 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 680 "Enable Energy Efficient Ethernet"); 681 682 /* 683 * AIM: Adaptive Interrupt Moderation 684 * which means that the interrupt rate is varied over time based on the 685 * traffic for that interrupt vector 686 */ 687 static int em_enable_aim = 1; 688 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim, 689 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 690 691 /* 692 ** Tuneable Interrupt rate 693 */ 694 static int em_max_interrupt_rate = EM_INTS_DEFAULT; 695 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 696 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 697 698 /* Global used in WOL setup with multiport cards */ 699 static int global_quad_port_a = 0; 700 701 extern struct if_txrx igb_txrx; 702 extern struct if_txrx em_txrx; 703 extern struct if_txrx lem_txrx; 704 705 static struct if_shared_ctx em_sctx_init = { 706 .isc_magic = IFLIB_MAGIC, 707 .isc_q_align = PAGE_SIZE, 708 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 709 .isc_tx_maxsegsize = PAGE_SIZE, 710 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 711 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 712 .isc_rx_maxsize = MJUM9BYTES, 713 .isc_rx_nsegments = 1, 714 .isc_rx_maxsegsize = MJUM9BYTES, 715 .isc_nfl = 1, 716 .isc_nrxqs = 1, 717 .isc_ntxqs = 1, 718 .isc_admin_intrcnt = 1, 719 .isc_vendor_info = em_vendor_info_array, 720 .isc_driver_version = em_driver_version, 721 .isc_driver = &em_if_driver, 722 .isc_flags = 723 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 724 725 .isc_nrxd_min = {EM_MIN_RXD}, 726 .isc_ntxd_min = {EM_MIN_TXD}, 727 .isc_nrxd_max = {EM_MAX_RXD}, 728 .isc_ntxd_max = {EM_MAX_TXD}, 729 .isc_nrxd_default = {EM_DEFAULT_RXD}, 730 .isc_ntxd_default = {EM_DEFAULT_TXD}, 731 }; 732 733 static struct if_shared_ctx igb_sctx_init = { 734 .isc_magic = IFLIB_MAGIC, 735 .isc_q_align = PAGE_SIZE, 736 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 737 .isc_tx_maxsegsize = PAGE_SIZE, 738 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 739 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 740 .isc_rx_maxsize = MJUM9BYTES, 741 .isc_rx_nsegments = 1, 742 .isc_rx_maxsegsize = MJUM9BYTES, 743 .isc_nfl = 1, 744 .isc_nrxqs = 1, 745 .isc_ntxqs = 1, 746 .isc_admin_intrcnt = 1, 747 .isc_vendor_info = igb_vendor_info_array, 748 .isc_driver_version = igb_driver_version, 749 .isc_driver = &igb_if_driver, 750 .isc_flags = 751 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 752 753 .isc_nrxd_min = {EM_MIN_RXD}, 754 .isc_ntxd_min = {EM_MIN_TXD}, 755 .isc_nrxd_max = {IGB_MAX_RXD}, 756 .isc_ntxd_max = {IGB_MAX_TXD}, 757 .isc_nrxd_default = {EM_DEFAULT_RXD}, 758 .isc_ntxd_default = {EM_DEFAULT_TXD}, 759 }; 760 761 /***************************************************************** 762 * 763 * Dump Registers 764 * 765 ****************************************************************/ 766 #define IGB_REGS_LEN 739 767 768 static int em_get_regs(SYSCTL_HANDLER_ARGS) 769 { 770 struct e1000_softc *sc = (struct e1000_softc *)arg1; 771 struct e1000_hw *hw = &sc->hw; 772 struct sbuf *sb; 773 u32 *regs_buff; 774 int rc; 775 776 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 777 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 778 779 rc = sysctl_wire_old_buffer(req, 0); 780 MPASS(rc == 0); 781 if (rc != 0) { 782 free(regs_buff, M_DEVBUF); 783 return (rc); 784 } 785 786 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 787 MPASS(sb != NULL); 788 if (sb == NULL) { 789 free(regs_buff, M_DEVBUF); 790 return (ENOMEM); 791 } 792 793 /* General Registers */ 794 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 795 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 796 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 797 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 798 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 799 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 800 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 801 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 802 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 803 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 804 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 805 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 806 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 807 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 808 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 809 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 810 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 811 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 812 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 813 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 814 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 815 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 816 817 sbuf_printf(sb, "General Registers\n"); 818 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 819 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 820 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 821 822 sbuf_printf(sb, "Interrupt Registers\n"); 823 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 824 825 sbuf_printf(sb, "RX Registers\n"); 826 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 827 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 828 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 829 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 830 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 831 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 832 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 833 834 sbuf_printf(sb, "TX Registers\n"); 835 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 836 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 837 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 838 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 839 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 840 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 841 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 842 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 843 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 844 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 845 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 846 847 free(regs_buff, M_DEVBUF); 848 849 #ifdef DUMP_DESCS 850 { 851 if_softc_ctx_t scctx = sc->shared; 852 struct rx_ring *rxr = &rx_que->rxr; 853 struct tx_ring *txr = &tx_que->txr; 854 int ntxd = scctx->isc_ntxd[0]; 855 int nrxd = scctx->isc_nrxd[0]; 856 int j; 857 858 for (j = 0; j < nrxd; j++) { 859 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 860 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 861 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" 862 PRIx64 " Error:%d Length:%d\n", 863 j, rxr->rx_base[j].read.buffer_addr, staterr, length); 864 } 865 866 for (j = 0; j < min(ntxd, 256); j++) { 867 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 868 869 sbuf_printf(sb, 870 "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x" 871 " eop: %d DD=%d\n", 872 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 873 buf->eop != -1 ? 874 txr->tx_base[buf->eop].upper.fields.status & 875 E1000_TXD_STAT_DD : 0); 876 877 } 878 } 879 #endif 880 881 rc = sbuf_finish(sb); 882 sbuf_delete(sb); 883 return(rc); 884 } 885 886 static void * 887 em_register(device_t dev) 888 { 889 return (&em_sctx_init); 890 } 891 892 static void * 893 igb_register(device_t dev) 894 { 895 return (&igb_sctx_init); 896 } 897 898 static int 899 em_set_num_queues(if_ctx_t ctx) 900 { 901 struct e1000_softc *sc = iflib_get_softc(ctx); 902 int maxqueues; 903 904 /* Sanity check based on HW */ 905 switch (sc->hw.mac.type) { 906 case e1000_82576: 907 case e1000_82580: 908 case e1000_i350: 909 case e1000_i354: 910 maxqueues = 8; 911 break; 912 case e1000_i210: 913 case e1000_82575: 914 maxqueues = 4; 915 break; 916 case e1000_i211: 917 case e1000_82574: 918 maxqueues = 2; 919 break; 920 default: 921 maxqueues = 1; 922 break; 923 } 924 925 return (maxqueues); 926 } 927 928 #define LEM_CAPS \ 929 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 930 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 931 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 932 933 #define EM_CAPS \ 934 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 935 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 936 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 937 IFCAP_TSO6 938 939 #define IGB_CAPS \ 940 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 941 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 942 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 943 IFCAP_TSO6 944 945 /********************************************************************* 946 * Device initialization routine 947 * 948 * The attach entry point is called when the driver is being loaded. 949 * This routine identifies the type of hardware, allocates all resources 950 * and initializes the hardware. 951 * 952 * return 0 on success, positive on failure 953 *********************************************************************/ 954 static int 955 em_if_attach_pre(if_ctx_t ctx) 956 { 957 struct e1000_softc *sc; 958 if_softc_ctx_t scctx; 959 device_t dev; 960 struct e1000_hw *hw; 961 struct sysctl_oid_list *child; 962 struct sysctl_ctx_list *ctx_list; 963 int error = 0; 964 965 INIT_DEBUGOUT("em_if_attach_pre: begin"); 966 dev = iflib_get_dev(ctx); 967 sc = iflib_get_softc(ctx); 968 969 sc->ctx = sc->osdep.ctx = ctx; 970 sc->dev = sc->osdep.dev = dev; 971 scctx = sc->shared = iflib_get_softc_ctx(ctx); 972 sc->media = iflib_get_media(ctx); 973 hw = &sc->hw; 974 975 /* Determine hardware and mac info */ 976 em_identify_hardware(ctx); 977 978 /* SYSCTL stuff */ 979 ctx_list = device_get_sysctl_ctx(dev); 980 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 981 982 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 983 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 984 em_sysctl_nvm_info, "I", "NVM Information"); 985 986 sc->enable_aim = em_enable_aim; 987 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", 988 CTLFLAG_RW, &sc->enable_aim, 0, 989 "Interrupt Moderation (1=normal, 2=lowlatency)"); 990 991 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 992 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 993 em_sysctl_print_fw_version, "A", 994 "Prints FW/NVM Versions"); 995 996 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 997 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 998 em_sysctl_debug_info, "I", "Debug Information"); 999 1000 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 1001 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1002 em_set_flowcntl, "I", "Flow Control"); 1003 1004 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 1005 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 1006 em_get_regs, "A", "Dump Registers"); 1007 1008 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 1009 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1010 em_get_rs, "I", "Dump RS indexes"); 1011 1012 if (hw->mac.type >= e1000_i350) { 1013 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 1014 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1015 igb_sysctl_dmac, "I", "DMA Coalesce"); 1016 } 1017 1018 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1019 "tso_tcp_flags_mask_first_segment", 1020 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1021 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU", 1022 "TSO TCP flags mask for first segment"); 1023 1024 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1025 "tso_tcp_flags_mask_middle_segment", 1026 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1027 sc, 1, em_sysctl_tso_tcp_flags_mask, "IU", 1028 "TSO TCP flags mask for middle segment"); 1029 1030 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1031 "tso_tcp_flags_mask_last_segment", 1032 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1033 sc, 2, em_sysctl_tso_tcp_flags_mask, "IU", 1034 "TSO TCP flags mask for last segment"); 1035 1036 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 1037 scctx->isc_nrxqsets_max = 1038 scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 1039 if (bootverbose) 1040 device_printf(dev, "attach_pre capping queues at %d\n", 1041 scctx->isc_ntxqsets_max); 1042 1043 if (hw->mac.type >= igb_mac_min) { 1044 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1045 sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 1046 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1047 sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 1048 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 1049 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 1050 scctx->isc_txrx = &igb_txrx; 1051 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1052 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1053 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1054 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 1055 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 1056 CSUM_IP6_TCP | CSUM_IP6_UDP; 1057 if (hw->mac.type != e1000_82575) 1058 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 1059 /* 1060 ** Some new devices, as with ixgbe, now may 1061 ** use a different BAR, so we need to keep 1062 ** track of which is used. 1063 */ 1064 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1065 } else if (hw->mac.type >= em_mac_min) { 1066 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1067 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1068 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1069 sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 1070 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1071 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 1072 scctx->isc_txrx = &em_txrx; 1073 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1074 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1075 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1076 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 1077 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1078 CSUM_IP6_TCP | CSUM_IP6_UDP; 1079 1080 /* Disable TSO on all em(4) until ring stalls are debugged */ 1081 scctx->isc_capenable &= ~IFCAP_TSO; 1082 1083 /* 1084 * Disable TSO on SPT due to errata that downclocks DMA 1085 * performance 1086 * i218-i219 Specification Update 1.5.4.5 1087 */ 1088 if (hw->mac.type == e1000_pch_spt) 1089 scctx->isc_capenable &= ~IFCAP_TSO; 1090 1091 /* 1092 * We support MSI-X with 82574 only, but indicate to iflib(4) 1093 * that it shall give MSI at least a try with other devices. 1094 */ 1095 if (hw->mac.type == e1000_82574) { 1096 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1097 } else { 1098 scctx->isc_msix_bar = -1; 1099 scctx->isc_disable_msix = 1; 1100 } 1101 } else { 1102 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * 1103 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1104 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * 1105 sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 1106 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1107 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 1108 scctx->isc_txrx = &lem_txrx; 1109 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1110 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1111 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1112 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 1113 if (em_unsupported_tso) 1114 scctx->isc_capabilities |= IFCAP_TSO6; 1115 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1116 CSUM_IP6_TCP | CSUM_IP6_UDP; 1117 1118 /* Disable TSO on all lem(4) until ring stalls debugged */ 1119 scctx->isc_capenable &= ~IFCAP_TSO; 1120 1121 /* 82541ER doesn't do HW tagging */ 1122 if (hw->device_id == E1000_DEV_ID_82541ER || 1123 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 1124 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 1125 scctx->isc_capenable = scctx->isc_capabilities; 1126 } 1127 /* This is the first e1000 chip and it does not do offloads */ 1128 if (hw->mac.type == e1000_82542) { 1129 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | 1130 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 | 1131 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER | 1132 IFCAP_TSO | IFCAP_VLAN_HWTSO); 1133 scctx->isc_capenable = scctx->isc_capabilities; 1134 } 1135 /* These can't do TSO for various reasons */ 1136 if (hw->mac.type < e1000_82544 || 1137 hw->mac.type == e1000_82547 || 1138 hw->mac.type == e1000_82547_rev_2) { 1139 scctx->isc_capabilities &= 1140 ~(IFCAP_TSO |IFCAP_VLAN_HWTSO); 1141 scctx->isc_capenable = scctx->isc_capabilities; 1142 } 1143 /* XXXKB: No IPv6 before this? */ 1144 if (hw->mac.type < e1000_82545){ 1145 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 1146 scctx->isc_capenable = scctx->isc_capabilities; 1147 } 1148 /* 1149 * "PCI/PCI-X SDM 4.0" page 33 (b): 1150 * FDX requirement on these chips 1151 */ 1152 if (hw->mac.type == e1000_82547 || 1153 hw->mac.type == e1000_82547_rev_2) 1154 scctx->isc_capenable &= ~(IFCAP_HWCSUM | 1155 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6); 1156 1157 /* INTx only */ 1158 scctx->isc_msix_bar = 0; 1159 } 1160 1161 /* Setup PCI resources */ 1162 if (em_allocate_pci_resources(ctx)) { 1163 device_printf(dev, "Allocation of PCI resources failed\n"); 1164 error = ENXIO; 1165 goto err_pci; 1166 } 1167 1168 /* 1169 ** For ICH8 and family we need to 1170 ** map the flash memory, and this 1171 ** must happen after the MAC is 1172 ** identified 1173 */ 1174 if ((hw->mac.type == e1000_ich8lan) || 1175 (hw->mac.type == e1000_ich9lan) || 1176 (hw->mac.type == e1000_ich10lan) || 1177 (hw->mac.type == e1000_pchlan) || 1178 (hw->mac.type == e1000_pch2lan) || 1179 (hw->mac.type == e1000_pch_lpt)) { 1180 int rid = EM_BAR_TYPE_FLASH; 1181 sc->flash = bus_alloc_resource_any(dev, 1182 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1183 if (sc->flash == NULL) { 1184 device_printf(dev, "Mapping of Flash failed\n"); 1185 error = ENXIO; 1186 goto err_pci; 1187 } 1188 /* This is used in the shared code */ 1189 hw->flash_address = (u8 *)sc->flash; 1190 sc->osdep.flash_bus_space_tag = 1191 rman_get_bustag(sc->flash); 1192 sc->osdep.flash_bus_space_handle = 1193 rman_get_bushandle(sc->flash); 1194 } 1195 /* 1196 ** In the new SPT device flash is not a 1197 ** separate BAR, rather it is also in BAR0, 1198 ** so use the same tag and an offset handle for the 1199 ** FLASH read/write macros in the shared code. 1200 */ 1201 else if (hw->mac.type >= e1000_pch_spt) { 1202 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1203 sc->osdep.flash_bus_space_handle = 1204 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; 1205 } 1206 1207 /* Do Shared Code initialization */ 1208 error = e1000_setup_init_funcs(hw, true); 1209 if (error) { 1210 device_printf(dev, "Setup of Shared code failed, error %d\n", 1211 error); 1212 error = ENXIO; 1213 goto err_pci; 1214 } 1215 1216 em_setup_msix(ctx); 1217 e1000_get_bus_info(hw); 1218 1219 /* Set up some sysctls for the tunable interrupt delays */ 1220 if (hw->mac.type < igb_mac_min) { 1221 em_add_int_delay_sysctl(sc, "rx_int_delay", 1222 "receive interrupt delay in usecs", &sc->rx_int_delay, 1223 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1224 em_add_int_delay_sysctl(sc, "tx_int_delay", 1225 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1226 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1227 } 1228 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1229 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1230 "receive interrupt delay limit in usecs", 1231 &sc->rx_abs_int_delay, 1232 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1233 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1234 "transmit interrupt delay limit in usecs", 1235 &sc->tx_abs_int_delay, 1236 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1237 } 1238 1239 hw->mac.autoneg = DO_AUTO_NEG; 1240 hw->phy.autoneg_wait_to_complete = false; 1241 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1242 1243 if (hw->mac.type < em_mac_min) { 1244 e1000_init_script_state_82541(hw, true); 1245 e1000_set_tbi_compatibility_82543(hw, true); 1246 } 1247 /* Copper options */ 1248 if (hw->phy.media_type == e1000_media_type_copper) { 1249 hw->phy.mdix = AUTO_ALL_MODES; 1250 hw->phy.disable_polarity_correction = false; 1251 hw->phy.ms_type = EM_MASTER_SLAVE; 1252 } 1253 1254 /* 1255 * Set the frame limits assuming 1256 * standard ethernet sized frames. 1257 */ 1258 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1259 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1260 1261 /* 1262 * This controls when hardware reports transmit completion 1263 * status. 1264 */ 1265 hw->mac.report_tx_early = 1; 1266 1267 /* Allocate multicast array memory. */ 1268 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1269 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1270 if (sc->mta == NULL) { 1271 device_printf(dev, 1272 "Can not allocate multicast setup array\n"); 1273 error = ENOMEM; 1274 goto err_late; 1275 } 1276 1277 /* Clear the IFCAP_TSO auto mask */ 1278 sc->tso_automasked = 0; 1279 1280 /* Check SOL/IDER usage */ 1281 if (e1000_check_reset_block(hw)) 1282 device_printf(dev, 1283 "PHY reset is blocked due to SOL/IDER session.\n"); 1284 1285 /* Sysctl for setting Energy Efficient Ethernet */ 1286 if (hw->mac.type < igb_mac_min) 1287 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1288 else 1289 hw->dev_spec._82575.eee_disable = eee_setting; 1290 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1291 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1292 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1293 1294 /* 1295 ** Start from a known state, this is 1296 ** important in reading the nvm and 1297 ** mac from that. 1298 */ 1299 e1000_reset_hw(hw); 1300 1301 /* Make sure we have a good EEPROM before we read from it */ 1302 if (e1000_validate_nvm_checksum(hw) < 0) { 1303 /* 1304 ** Some PCI-E parts fail the first check due to 1305 ** the link being in sleep state, call it again, 1306 ** if it fails a second time its a real issue. 1307 */ 1308 if (e1000_validate_nvm_checksum(hw) < 0) { 1309 device_printf(dev, 1310 "The EEPROM Checksum Is Not Valid\n"); 1311 error = EIO; 1312 goto err_late; 1313 } 1314 } 1315 1316 /* Copy the permanent MAC address out of the EEPROM */ 1317 if (e1000_read_mac_addr(hw) < 0) { 1318 device_printf(dev, 1319 "EEPROM read error while reading MAC address\n"); 1320 error = EIO; 1321 goto err_late; 1322 } 1323 1324 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1325 if (sc->vf_ifp) { 1326 ether_gen_addr(iflib_get_ifp(ctx), 1327 (struct ether_addr *)hw->mac.addr); 1328 } else { 1329 device_printf(dev, "Invalid MAC address\n"); 1330 error = EIO; 1331 goto err_late; 1332 } 1333 } 1334 1335 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1336 em_fw_version_locked(ctx); 1337 1338 em_print_fw_version(sc); 1339 1340 /* 1341 * Get Wake-on-Lan and Management info for later use 1342 */ 1343 em_get_wakeup(ctx); 1344 1345 /* Enable only WOL MAGIC by default */ 1346 scctx->isc_capenable &= ~IFCAP_WOL; 1347 if (sc->wol != 0) 1348 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1349 1350 iflib_set_mac(ctx, hw->mac.addr); 1351 1352 return (0); 1353 1354 err_late: 1355 em_release_hw_control(sc); 1356 err_pci: 1357 em_free_pci_resources(ctx); 1358 free(sc->mta, M_DEVBUF); 1359 1360 return (error); 1361 } 1362 1363 static int 1364 em_if_attach_post(if_ctx_t ctx) 1365 { 1366 struct e1000_softc *sc = iflib_get_softc(ctx); 1367 struct e1000_hw *hw = &sc->hw; 1368 int error = 0; 1369 1370 /* Setup OS specific network interface */ 1371 error = em_setup_interface(ctx); 1372 if (error != 0) { 1373 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1374 goto err_late; 1375 } 1376 1377 em_reset(ctx); 1378 1379 /* Initialize statistics */ 1380 em_update_stats_counters(sc); 1381 hw->mac.get_link_status = 1; 1382 em_if_update_admin_status(ctx); 1383 em_add_hw_stats(sc); 1384 1385 /* Non-AMT based hardware can now take control from firmware */ 1386 if (sc->has_manage && !sc->has_amt) 1387 em_get_hw_control(sc); 1388 1389 INIT_DEBUGOUT("em_if_attach_post: end"); 1390 1391 return (0); 1392 1393 err_late: 1394 /* 1395 * Upon em_if_attach_post() error, iflib calls em_if_detach() to 1396 * free resources 1397 */ 1398 return (error); 1399 } 1400 1401 /********************************************************************* 1402 * Device removal routine 1403 * 1404 * The detach entry point is called when the driver is being removed. 1405 * This routine stops the adapter and deallocates all the resources 1406 * that were allocated for driver operation. 1407 * 1408 * return 0 on success, positive on failure 1409 *********************************************************************/ 1410 static int 1411 em_if_detach(if_ctx_t ctx) 1412 { 1413 struct e1000_softc *sc = iflib_get_softc(ctx); 1414 1415 INIT_DEBUGOUT("em_if_detach: begin"); 1416 1417 e1000_phy_hw_reset(&sc->hw); 1418 1419 em_release_manageability(sc); 1420 em_release_hw_control(sc); 1421 em_free_pci_resources(ctx); 1422 free(sc->mta, M_DEVBUF); 1423 sc->mta = NULL; 1424 1425 return (0); 1426 } 1427 1428 /********************************************************************* 1429 * 1430 * Shutdown entry point 1431 * 1432 **********************************************************************/ 1433 1434 static int 1435 em_if_shutdown(if_ctx_t ctx) 1436 { 1437 return em_if_suspend(ctx); 1438 } 1439 1440 /* 1441 * Suspend/resume device methods. 1442 */ 1443 static int 1444 em_if_suspend(if_ctx_t ctx) 1445 { 1446 struct e1000_softc *sc = iflib_get_softc(ctx); 1447 1448 em_release_manageability(sc); 1449 em_release_hw_control(sc); 1450 em_enable_wakeup(ctx); 1451 return (0); 1452 } 1453 1454 static int 1455 em_if_resume(if_ctx_t ctx) 1456 { 1457 struct e1000_softc *sc = iflib_get_softc(ctx); 1458 1459 if (sc->hw.mac.type == e1000_pch2lan) 1460 e1000_resume_workarounds_pchlan(&sc->hw); 1461 em_if_init(ctx); 1462 em_init_manageability(sc); 1463 1464 return(0); 1465 } 1466 1467 static int 1468 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1469 { 1470 int max_frame_size; 1471 struct e1000_softc *sc = iflib_get_softc(ctx); 1472 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1473 1474 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1475 1476 switch (sc->hw.mac.type) { 1477 case e1000_82571: 1478 case e1000_82572: 1479 case e1000_ich9lan: 1480 case e1000_ich10lan: 1481 case e1000_pch2lan: 1482 case e1000_pch_lpt: 1483 case e1000_pch_spt: 1484 case e1000_pch_cnp: 1485 case e1000_pch_tgp: 1486 case e1000_pch_adp: 1487 case e1000_pch_mtp: 1488 case e1000_pch_ptp: 1489 case e1000_82574: 1490 case e1000_82583: 1491 case e1000_80003es2lan: 1492 /* 9K Jumbo Frame size */ 1493 max_frame_size = 9234; 1494 break; 1495 case e1000_pchlan: 1496 max_frame_size = 4096; 1497 break; 1498 case e1000_82542: 1499 case e1000_ich8lan: 1500 /* Adapters that do not support jumbo frames */ 1501 max_frame_size = ETHER_MAX_LEN; 1502 break; 1503 default: 1504 if (sc->hw.mac.type >= igb_mac_min) 1505 max_frame_size = 9234; 1506 else /* lem */ 1507 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1508 } 1509 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1510 return (EINVAL); 1511 } 1512 1513 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1514 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1515 return (0); 1516 } 1517 1518 /********************************************************************* 1519 * Init entry point 1520 * 1521 * This routine is used in two ways. It is used by the stack as 1522 * init entry point in network interface structure. It is also used 1523 * by the driver as a hw/sw initialization routine to get to a 1524 * consistent state. 1525 * 1526 **********************************************************************/ 1527 static void 1528 em_if_init(if_ctx_t ctx) 1529 { 1530 struct e1000_softc *sc = iflib_get_softc(ctx); 1531 if_softc_ctx_t scctx = sc->shared; 1532 if_t ifp = iflib_get_ifp(ctx); 1533 struct em_tx_queue *tx_que; 1534 int i; 1535 1536 INIT_DEBUGOUT("em_if_init: begin"); 1537 1538 /* Get the latest mac address, User can use a LAA */ 1539 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1540 1541 /* Put the address into the Receive Address Array */ 1542 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1543 1544 /* 1545 * With the 82571 adapter, RAR[0] may be overwritten 1546 * when the other port is reset, we make a duplicate 1547 * in RAR[14] for that eventuality, this assures 1548 * the interface continues to function. 1549 */ 1550 if (sc->hw.mac.type == e1000_82571) { 1551 e1000_set_laa_state_82571(&sc->hw, true); 1552 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1553 E1000_RAR_ENTRIES - 1); 1554 } 1555 1556 /* Initialize the hardware */ 1557 em_reset(ctx); 1558 em_if_update_admin_status(ctx); 1559 1560 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; 1561 i++, tx_que++) { 1562 struct tx_ring *txr = &tx_que->txr; 1563 1564 txr->tx_rs_cidx = txr->tx_rs_pidx; 1565 1566 /* Initialize the last processed descriptor to be the end of 1567 * the ring, rather than the start, so that we avoid an 1568 * off-by-one error when calculating how many descriptors are 1569 * done in the credits_update function. 1570 */ 1571 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1572 } 1573 1574 /* Setup VLAN support, basic and offload if available */ 1575 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1576 1577 /* Clear bad data from Rx FIFOs */ 1578 if (sc->hw.mac.type >= igb_mac_min) 1579 e1000_rx_fifo_flush_base(&sc->hw); 1580 1581 /* Configure for OS presence */ 1582 em_init_manageability(sc); 1583 1584 /* Prepare transmit descriptors and buffers */ 1585 em_initialize_transmit_unit(ctx); 1586 1587 /* Setup Multicast table */ 1588 em_if_multi_set(ctx); 1589 1590 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1591 em_initialize_receive_unit(ctx); 1592 1593 /* Set up VLAN support and filter */ 1594 em_setup_vlan_hw_support(ctx); 1595 1596 /* Don't lose promiscuous settings */ 1597 em_if_set_promisc(ctx, if_getflags(ifp)); 1598 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1599 1600 /* MSI-X configuration for 82574 */ 1601 if (sc->hw.mac.type == e1000_82574) { 1602 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1603 1604 tmp |= E1000_CTRL_EXT_PBA_CLR; 1605 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1606 /* Set the IVAR - interrupt vector routing. */ 1607 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1608 } else if (sc->intr_type == IFLIB_INTR_MSIX) { 1609 /* Set up queue routing */ 1610 igb_configure_queues(sc); 1611 } 1612 1613 /* this clears any pending interrupts */ 1614 E1000_READ_REG(&sc->hw, E1000_ICR); 1615 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1616 1617 /* AMT based hardware can now take control from firmware */ 1618 if (sc->has_manage && sc->has_amt) 1619 em_get_hw_control(sc); 1620 1621 /* Set Energy Efficient Ethernet */ 1622 if (sc->hw.mac.type >= igb_mac_min && 1623 sc->hw.phy.media_type == e1000_media_type_copper) { 1624 if (sc->hw.mac.type == e1000_i354) 1625 e1000_set_eee_i354(&sc->hw, true, true); 1626 else 1627 e1000_set_eee_i350(&sc->hw, true, true); 1628 } 1629 } 1630 1631 enum itr_latency_target { 1632 itr_latency_disabled = 0, 1633 itr_latency_lowest = 1, 1634 itr_latency_low = 2, 1635 itr_latency_bulk = 3 1636 }; 1637 /********************************************************************* 1638 * 1639 * Helper to calculate next (E)ITR value for AIM 1640 * 1641 *********************************************************************/ 1642 static void 1643 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, 1644 struct tx_ring *txr, struct rx_ring *rxr) 1645 { 1646 struct e1000_hw *hw = &sc->hw; 1647 unsigned long bytes, bytes_per_packet, packets; 1648 unsigned long rxbytes, rxpackets, txbytes, txpackets; 1649 u32 newitr; 1650 u8 nextlatency; 1651 1652 rxbytes = atomic_load_long(&rxr->rx_bytes); 1653 txbytes = atomic_load_long(&txr->tx_bytes); 1654 1655 /* Idle, do nothing */ 1656 if (txbytes == 0 && rxbytes == 0) 1657 return; 1658 1659 newitr = 0; 1660 1661 if (sc->enable_aim) { 1662 nextlatency = rxr->rx_nextlatency; 1663 1664 /* Use half default (4K) ITR if sub-gig */ 1665 if (sc->link_speed != 1000) { 1666 newitr = EM_INTS_4K; 1667 goto em_set_next_itr; 1668 } 1669 /* Want at least enough packet buffer for two frames to AIM */ 1670 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1671 newitr = em_max_interrupt_rate; 1672 sc->enable_aim = 0; 1673 goto em_set_next_itr; 1674 } 1675 1676 bytes = bytes_per_packet = 0; 1677 /* Get largest values from the associated tx and rx ring */ 1678 txpackets = atomic_load_long(&txr->tx_packets); 1679 if (txpackets != 0) { 1680 bytes = txbytes; 1681 bytes_per_packet = txbytes / txpackets; 1682 packets = txpackets; 1683 } 1684 rxpackets = atomic_load_long(&rxr->rx_packets); 1685 if (rxpackets != 0) { 1686 bytes = lmax(bytes, rxbytes); 1687 bytes_per_packet = 1688 lmax(bytes_per_packet, rxbytes / rxpackets); 1689 packets = lmax(packets, rxpackets); 1690 } 1691 1692 /* Latency state machine */ 1693 switch (nextlatency) { 1694 case itr_latency_disabled: /* Bootstrapping */ 1695 nextlatency = itr_latency_low; 1696 break; 1697 case itr_latency_lowest: /* 70k ints/s */ 1698 /* TSO and jumbo frames */ 1699 if (bytes_per_packet > 8000) 1700 nextlatency = itr_latency_bulk; 1701 else if ((packets < 5) && (bytes > 512)) 1702 nextlatency = itr_latency_low; 1703 break; 1704 case itr_latency_low: /* 20k ints/s */ 1705 if (bytes > 10000) { 1706 /* Handle TSO */ 1707 if (bytes_per_packet > 8000) 1708 nextlatency = itr_latency_bulk; 1709 else if ((packets < 10) || 1710 (bytes_per_packet > 1200)) 1711 nextlatency = itr_latency_bulk; 1712 else if (packets > 35) 1713 nextlatency = itr_latency_lowest; 1714 } else if (bytes_per_packet > 2000) { 1715 nextlatency = itr_latency_bulk; 1716 } else if (packets < 3 && bytes < 512) { 1717 nextlatency = itr_latency_lowest; 1718 } 1719 break; 1720 case itr_latency_bulk: /* 4k ints/s */ 1721 if (bytes > 25000) { 1722 if (packets > 35) 1723 nextlatency = itr_latency_low; 1724 } else if (bytes < 1500) 1725 nextlatency = itr_latency_low; 1726 break; 1727 default: 1728 nextlatency = itr_latency_low; 1729 device_printf(sc->dev, 1730 "Unexpected newitr transition %d\n", nextlatency); 1731 break; 1732 } 1733 1734 /* Trim itr_latency_lowest for default AIM setting */ 1735 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) 1736 nextlatency = itr_latency_low; 1737 1738 /* Request new latency */ 1739 rxr->rx_nextlatency = nextlatency; 1740 } else { 1741 /* We may have toggled to AIM disabled */ 1742 nextlatency = itr_latency_disabled; 1743 rxr->rx_nextlatency = nextlatency; 1744 } 1745 1746 /* ITR state machine */ 1747 switch(nextlatency) { 1748 case itr_latency_lowest: 1749 newitr = EM_INTS_70K; 1750 break; 1751 case itr_latency_low: 1752 newitr = EM_INTS_20K; 1753 break; 1754 case itr_latency_bulk: 1755 newitr = EM_INTS_4K; 1756 break; 1757 case itr_latency_disabled: 1758 default: 1759 newitr = em_max_interrupt_rate; 1760 break; 1761 } 1762 1763 em_set_next_itr: 1764 if (hw->mac.type >= igb_mac_min) { 1765 newitr = IGB_INTS_TO_EITR(newitr); 1766 1767 if (hw->mac.type == e1000_82575) 1768 newitr |= newitr << 16; 1769 else 1770 newitr |= E1000_EITR_CNT_IGNR; 1771 1772 if (newitr != que->itr_setting) { 1773 que->itr_setting = newitr; 1774 E1000_WRITE_REG(hw, E1000_EITR(que->msix), 1775 que->itr_setting); 1776 } 1777 } else { 1778 newitr = EM_INTS_TO_ITR(newitr); 1779 1780 if (newitr != que->itr_setting) { 1781 que->itr_setting = newitr; 1782 if (hw->mac.type == e1000_82574 && que->msix) { 1783 E1000_WRITE_REG(hw, 1784 E1000_EITR_82574(que->msix), 1785 que->itr_setting); 1786 } else { 1787 E1000_WRITE_REG(hw, E1000_ITR, 1788 que->itr_setting); 1789 } 1790 } 1791 } 1792 } 1793 1794 /********************************************************************* 1795 * 1796 * Fast Legacy/MSI Combined Interrupt Service routine 1797 * 1798 *********************************************************************/ 1799 int 1800 em_intr(void *arg) 1801 { 1802 struct e1000_softc *sc = arg; 1803 struct e1000_hw *hw = &sc->hw; 1804 struct em_rx_queue *que = &sc->rx_queues[0]; 1805 struct tx_ring *txr = &sc->tx_queues[0].txr; 1806 struct rx_ring *rxr = &que->rxr; 1807 if_ctx_t ctx = sc->ctx; 1808 u32 reg_icr; 1809 1810 reg_icr = E1000_READ_REG(hw, E1000_ICR); 1811 1812 /* Hot eject? */ 1813 if (reg_icr == 0xffffffff) 1814 return FILTER_STRAY; 1815 1816 /* Definitely not our interrupt. */ 1817 if (reg_icr == 0x0) 1818 return FILTER_STRAY; 1819 1820 /* 1821 * Starting with the 82571 chip, bit 31 should be used to 1822 * determine whether the interrupt belongs to us. 1823 */ 1824 if (hw->mac.type >= e1000_82571 && 1825 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1826 return FILTER_STRAY; 1827 1828 /* 1829 * Only MSI-X interrupts have one-shot behavior by taking advantage 1830 * of the EIAC register. Thus, explicitly disable interrupts. This 1831 * also works around the MSI message reordering errata on certain 1832 * systems. 1833 */ 1834 IFDI_INTR_DISABLE(ctx); 1835 1836 /* Link status change */ 1837 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1838 em_handle_link(ctx); 1839 1840 if (reg_icr & E1000_ICR_RXO) 1841 sc->rx_overruns++; 1842 1843 if (hw->mac.type >= e1000_82540) 1844 em_newitr(sc, que, txr, rxr); 1845 1846 /* Reset state */ 1847 txr->tx_bytes = 0; 1848 txr->tx_packets = 0; 1849 rxr->rx_bytes = 0; 1850 rxr->rx_packets = 0; 1851 1852 return (FILTER_SCHEDULE_THREAD); 1853 } 1854 1855 static int 1856 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1857 { 1858 struct e1000_softc *sc = iflib_get_softc(ctx); 1859 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1860 1861 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1862 return (0); 1863 } 1864 1865 static int 1866 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1867 { 1868 struct e1000_softc *sc = iflib_get_softc(ctx); 1869 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1870 1871 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1872 return (0); 1873 } 1874 1875 static int 1876 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1877 { 1878 struct e1000_softc *sc = iflib_get_softc(ctx); 1879 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1880 1881 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1882 return (0); 1883 } 1884 1885 static int 1886 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1887 { 1888 struct e1000_softc *sc = iflib_get_softc(ctx); 1889 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1890 1891 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1892 return (0); 1893 } 1894 1895 /********************************************************************* 1896 * 1897 * MSI-X RX Interrupt Service routine 1898 * 1899 **********************************************************************/ 1900 static int 1901 em_msix_que(void *arg) 1902 { 1903 struct em_rx_queue *que = arg; 1904 struct e1000_softc *sc = que->sc; 1905 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; 1906 struct rx_ring *rxr = &que->rxr; 1907 1908 ++que->irqs; 1909 1910 em_newitr(sc, que, txr, rxr); 1911 1912 /* Reset state */ 1913 txr->tx_bytes = 0; 1914 txr->tx_packets = 0; 1915 rxr->rx_bytes = 0; 1916 rxr->rx_packets = 0; 1917 1918 return (FILTER_SCHEDULE_THREAD); 1919 } 1920 1921 /********************************************************************* 1922 * 1923 * MSI-X Link Fast Interrupt Service routine 1924 * 1925 **********************************************************************/ 1926 static int 1927 em_msix_link(void *arg) 1928 { 1929 struct e1000_softc *sc = arg; 1930 u32 reg_icr; 1931 1932 ++sc->link_irq; 1933 MPASS(sc->hw.back != NULL); 1934 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1935 1936 if (reg_icr & E1000_ICR_RXO) 1937 sc->rx_overruns++; 1938 1939 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1940 em_handle_link(sc->ctx); 1941 1942 /* Re-arm unconditionally */ 1943 if (sc->hw.mac.type >= igb_mac_min) { 1944 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1945 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1946 } else if (sc->hw.mac.type == e1000_82574) { 1947 E1000_WRITE_REG(&sc->hw, E1000_IMS, 1948 E1000_IMS_LSC | E1000_IMS_OTHER); 1949 /* 1950 * Because we must read the ICR for this interrupt it may 1951 * clear other causes using autoclear, for this reason we 1952 * simply create a soft interrupt for all these vectors. 1953 */ 1954 if (reg_icr) 1955 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1956 } else 1957 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1958 1959 return (FILTER_HANDLED); 1960 } 1961 1962 static void 1963 em_handle_link(void *context) 1964 { 1965 if_ctx_t ctx = context; 1966 struct e1000_softc *sc = iflib_get_softc(ctx); 1967 1968 sc->hw.mac.get_link_status = 1; 1969 iflib_admin_intr_deferred(ctx); 1970 } 1971 1972 /********************************************************************* 1973 * 1974 * Media Ioctl callback 1975 * 1976 * This routine is called whenever the user queries the status of 1977 * the interface using ifconfig. 1978 * 1979 **********************************************************************/ 1980 static void 1981 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1982 { 1983 struct e1000_softc *sc = iflib_get_softc(ctx); 1984 u_char fiber_type = IFM_1000_SX; 1985 1986 INIT_DEBUGOUT("em_if_media_status: begin"); 1987 1988 iflib_admin_intr_deferred(ctx); 1989 1990 ifmr->ifm_status = IFM_AVALID; 1991 ifmr->ifm_active = IFM_ETHER; 1992 1993 if (!sc->link_active) { 1994 return; 1995 } 1996 1997 ifmr->ifm_status |= IFM_ACTIVE; 1998 1999 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 2000 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2001 if (sc->hw.mac.type == e1000_82545) 2002 fiber_type = IFM_1000_LX; 2003 switch (sc->link_speed) { 2004 case 10: 2005 ifmr->ifm_active |= IFM_10_FL; 2006 break; 2007 case 100: 2008 ifmr->ifm_active |= IFM_100_FX; 2009 break; 2010 case 1000: 2011 default: 2012 ifmr->ifm_active |= fiber_type | IFM_FDX; 2013 break; 2014 } 2015 } else { 2016 switch (sc->link_speed) { 2017 case 10: 2018 ifmr->ifm_active |= IFM_10_T; 2019 break; 2020 case 100: 2021 ifmr->ifm_active |= IFM_100_TX; 2022 break; 2023 case 1000: 2024 ifmr->ifm_active |= IFM_1000_T; 2025 break; 2026 } 2027 } 2028 2029 if (sc->link_duplex == FULL_DUPLEX) 2030 ifmr->ifm_active |= IFM_FDX; 2031 else 2032 ifmr->ifm_active |= IFM_HDX; 2033 } 2034 2035 /********************************************************************* 2036 * 2037 * Media Ioctl callback 2038 * 2039 * This routine is called when the user changes speed/duplex using 2040 * media/mediopt option with ifconfig. 2041 * 2042 **********************************************************************/ 2043 static int 2044 em_if_media_change(if_ctx_t ctx) 2045 { 2046 struct e1000_softc *sc = iflib_get_softc(ctx); 2047 struct ifmedia *ifm = iflib_get_media(ctx); 2048 2049 INIT_DEBUGOUT("em_if_media_change: begin"); 2050 2051 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2052 return (EINVAL); 2053 2054 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2055 case IFM_AUTO: 2056 sc->hw.mac.autoneg = DO_AUTO_NEG; 2057 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 2058 break; 2059 case IFM_1000_LX: 2060 case IFM_1000_SX: 2061 case IFM_1000_T: 2062 sc->hw.mac.autoneg = DO_AUTO_NEG; 2063 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 2064 break; 2065 case IFM_100_TX: 2066 sc->hw.mac.autoneg = DO_AUTO_NEG; 2067 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2068 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 2069 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2070 } else { 2071 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 2072 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2073 } 2074 break; 2075 case IFM_10_T: 2076 sc->hw.mac.autoneg = DO_AUTO_NEG; 2077 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2078 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 2079 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2080 } else { 2081 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 2082 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2083 } 2084 break; 2085 case IFM_100_FX: 2086 sc->hw.mac.autoneg = false; 2087 sc->hw.phy.autoneg_advertised = 0; 2088 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2089 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2090 else 2091 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2092 break; 2093 case IFM_10_FL: 2094 sc->hw.mac.autoneg = false; 2095 sc->hw.phy.autoneg_advertised = 0; 2096 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2097 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2098 else 2099 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2100 break; 2101 default: 2102 device_printf(sc->dev, "Unsupported media type\n"); 2103 } 2104 2105 em_if_init(ctx); 2106 2107 return (0); 2108 } 2109 2110 static int 2111 em_if_set_promisc(if_ctx_t ctx, int flags) 2112 { 2113 struct e1000_softc *sc = iflib_get_softc(ctx); 2114 if_t ifp = iflib_get_ifp(ctx); 2115 u32 reg_rctl; 2116 int mcnt = 0; 2117 2118 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2119 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 2120 if (flags & IFF_ALLMULTI) 2121 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2122 else 2123 mcnt = min(if_llmaddr_count(ifp), 2124 MAX_NUM_MULTICAST_ADDRESSES); 2125 2126 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2127 reg_rctl &= (~E1000_RCTL_MPE); 2128 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2129 2130 if (flags & IFF_PROMISC) { 2131 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2132 em_if_vlan_filter_disable(sc); 2133 /* Turn this on if you want to see bad packets */ 2134 if (em_debug_sbp) 2135 reg_rctl |= E1000_RCTL_SBP; 2136 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2137 } else { 2138 if (flags & IFF_ALLMULTI) { 2139 reg_rctl |= E1000_RCTL_MPE; 2140 reg_rctl &= ~E1000_RCTL_UPE; 2141 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2142 } 2143 if (em_if_vlan_filter_used(ctx)) 2144 em_if_vlan_filter_enable(sc); 2145 } 2146 return (0); 2147 } 2148 2149 static u_int 2150 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 2151 { 2152 u8 *mta = arg; 2153 2154 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 2155 return (0); 2156 2157 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2158 2159 return (1); 2160 } 2161 2162 /********************************************************************* 2163 * Multicast Update 2164 * 2165 * This routine is called whenever multicast address list is updated. 2166 * 2167 **********************************************************************/ 2168 static void 2169 em_if_multi_set(if_ctx_t ctx) 2170 { 2171 struct e1000_softc *sc = iflib_get_softc(ctx); 2172 if_t ifp = iflib_get_ifp(ctx); 2173 u8 *mta; /* Multicast array memory */ 2174 u32 reg_rctl = 0; 2175 int mcnt = 0; 2176 2177 IOCTL_DEBUGOUT("em_set_multi: begin"); 2178 2179 mta = sc->mta; 2180 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2181 2182 if (sc->hw.mac.type == e1000_82542 && 2183 sc->hw.revision_id == E1000_REVISION_2) { 2184 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2185 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2186 e1000_pci_clear_mwi(&sc->hw); 2187 reg_rctl |= E1000_RCTL_RST; 2188 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2189 msec_delay(5); 2190 } 2191 2192 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 2193 2194 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2195 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 2196 2197 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2198 2199 if (if_getflags(ifp) & IFF_PROMISC) 2200 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2201 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 2202 if_getflags(ifp) & IFF_ALLMULTI) { 2203 reg_rctl |= E1000_RCTL_MPE; 2204 reg_rctl &= ~E1000_RCTL_UPE; 2205 } else 2206 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2207 2208 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2209 2210 if (sc->hw.mac.type == e1000_82542 && 2211 sc->hw.revision_id == E1000_REVISION_2) { 2212 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2213 reg_rctl &= ~E1000_RCTL_RST; 2214 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2215 msec_delay(5); 2216 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2217 e1000_pci_set_mwi(&sc->hw); 2218 } 2219 } 2220 2221 /********************************************************************* 2222 * Timer routine 2223 * 2224 * This routine schedules em_if_update_admin_status() to check for 2225 * link status and to gather statistics as well as to perform some 2226 * controller-specific hardware patting. 2227 * 2228 **********************************************************************/ 2229 static void 2230 em_if_timer(if_ctx_t ctx, uint16_t qid) 2231 { 2232 if (qid != 0) 2233 return; 2234 2235 iflib_admin_intr_deferred(ctx); 2236 } 2237 2238 static void 2239 em_if_update_admin_status(if_ctx_t ctx) 2240 { 2241 struct e1000_softc *sc = iflib_get_softc(ctx); 2242 struct e1000_hw *hw = &sc->hw; 2243 device_t dev = iflib_get_dev(ctx); 2244 u32 link_check, thstat, ctrl; 2245 bool automasked = false; 2246 2247 link_check = thstat = ctrl = 0; 2248 /* Get the cached link value or read phy for real */ 2249 switch (hw->phy.media_type) { 2250 case e1000_media_type_copper: 2251 if (hw->mac.get_link_status) { 2252 if (hw->mac.type == e1000_pch_spt) 2253 msec_delay(50); 2254 /* Do the work to read phy */ 2255 e1000_check_for_link(hw); 2256 link_check = !hw->mac.get_link_status; 2257 if (link_check) /* ESB2 fix */ 2258 e1000_cfg_on_link_up(hw); 2259 } else { 2260 link_check = true; 2261 } 2262 break; 2263 case e1000_media_type_fiber: 2264 e1000_check_for_link(hw); 2265 link_check = 2266 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2267 break; 2268 case e1000_media_type_internal_serdes: 2269 e1000_check_for_link(hw); 2270 link_check = hw->mac.serdes_has_link; 2271 break; 2272 /* VF device is type_unknown */ 2273 case e1000_media_type_unknown: 2274 e1000_check_for_link(hw); 2275 link_check = !hw->mac.get_link_status; 2276 /* FALLTHROUGH */ 2277 default: 2278 break; 2279 } 2280 2281 /* Check for thermal downshift or shutdown */ 2282 if (hw->mac.type == e1000_i350) { 2283 thstat = E1000_READ_REG(hw, E1000_THSTAT); 2284 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 2285 } 2286 2287 /* Now check for a transition */ 2288 if (link_check && (sc->link_active == 0)) { 2289 e1000_get_speed_and_duplex(hw, &sc->link_speed, 2290 &sc->link_duplex); 2291 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2292 if ((sc->link_speed != SPEED_1000) && 2293 ((hw->mac.type == e1000_82571) || 2294 (hw->mac.type == e1000_82572))) { 2295 int tarc0; 2296 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2297 tarc0 &= ~TARC_SPEED_MODE_BIT; 2298 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2299 } 2300 if (bootverbose) 2301 device_printf(dev, "Link is up %d Mbps %s\n", 2302 sc->link_speed, 2303 ((sc->link_duplex == FULL_DUPLEX) ? 2304 "Full Duplex" : "Half Duplex")); 2305 sc->link_active = 1; 2306 sc->smartspeed = 0; 2307 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 2308 E1000_CTRL_EXT_LINK_MODE_GMII && 2309 (thstat & E1000_THSTAT_LINK_THROTTLE)) 2310 device_printf(dev, "Link: thermal downshift\n"); 2311 /* Delay Link Up for Phy update */ 2312 if (((hw->mac.type == e1000_i210) || 2313 (hw->mac.type == e1000_i211)) && 2314 (hw->phy.id == I210_I_PHY_ID)) 2315 msec_delay(I210_LINK_DELAY); 2316 /* Reset if the media type changed. */ 2317 if (hw->dev_spec._82575.media_changed && 2318 hw->mac.type >= igb_mac_min) { 2319 hw->dev_spec._82575.media_changed = false; 2320 sc->flags |= IGB_MEDIA_RESET; 2321 em_reset(ctx); 2322 } 2323 /* Only do TSO on gigabit for older chips due to errata */ 2324 if (hw->mac.type < igb_mac_min) 2325 automasked = em_automask_tso(ctx); 2326 2327 /* Automasking resets the interface so don't mark it up yet */ 2328 if (!automasked) 2329 iflib_link_state_change(ctx, LINK_STATE_UP, 2330 IF_Mbps(sc->link_speed)); 2331 } else if (!link_check && (sc->link_active == 1)) { 2332 sc->link_speed = 0; 2333 sc->link_duplex = 0; 2334 sc->link_active = 0; 2335 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2336 } 2337 em_update_stats_counters(sc); 2338 2339 /* Reset LAA into RAR[0] on 82571 */ 2340 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 2341 e1000_rar_set(hw, hw->mac.addr, 0); 2342 2343 if (hw->mac.type < em_mac_min) 2344 lem_smartspeed(sc); 2345 } 2346 2347 static void 2348 em_if_watchdog_reset(if_ctx_t ctx) 2349 { 2350 struct e1000_softc *sc = iflib_get_softc(ctx); 2351 2352 /* 2353 * Just count the event; iflib(4) will already trigger a 2354 * sufficient reset of the controller. 2355 */ 2356 sc->watchdog_events++; 2357 } 2358 2359 /********************************************************************* 2360 * 2361 * This routine disables all traffic on the adapter by issuing a 2362 * global reset on the MAC. 2363 * 2364 **********************************************************************/ 2365 static void 2366 em_if_stop(if_ctx_t ctx) 2367 { 2368 struct e1000_softc *sc = iflib_get_softc(ctx); 2369 2370 INIT_DEBUGOUT("em_if_stop: begin"); 2371 2372 /* I219 needs special flushing to avoid hangs */ 2373 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2374 em_flush_desc_rings(sc); 2375 2376 e1000_reset_hw(&sc->hw); 2377 if (sc->hw.mac.type >= e1000_82544) 2378 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 2379 2380 e1000_led_off(&sc->hw); 2381 e1000_cleanup_led(&sc->hw); 2382 } 2383 2384 /********************************************************************* 2385 * 2386 * Determine hardware revision. 2387 * 2388 **********************************************************************/ 2389 static void 2390 em_identify_hardware(if_ctx_t ctx) 2391 { 2392 device_t dev = iflib_get_dev(ctx); 2393 struct e1000_softc *sc = iflib_get_softc(ctx); 2394 2395 /* Make sure our PCI config space has the necessary stuff set */ 2396 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2397 2398 /* Save off the information about this board */ 2399 sc->hw.vendor_id = pci_get_vendor(dev); 2400 sc->hw.device_id = pci_get_device(dev); 2401 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2402 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2403 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2404 2405 /* Do Shared Code Init and Setup */ 2406 if (e1000_set_mac_type(&sc->hw)) { 2407 device_printf(dev, "Setup init failure\n"); 2408 return; 2409 } 2410 2411 /* Are we a VF device? */ 2412 if ((sc->hw.mac.type == e1000_vfadapt) || 2413 (sc->hw.mac.type == e1000_vfadapt_i350)) 2414 sc->vf_ifp = 1; 2415 else 2416 sc->vf_ifp = 0; 2417 } 2418 2419 static int 2420 em_allocate_pci_resources(if_ctx_t ctx) 2421 { 2422 struct e1000_softc *sc = iflib_get_softc(ctx); 2423 device_t dev = iflib_get_dev(ctx); 2424 int rid, val; 2425 2426 rid = PCIR_BAR(0); 2427 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2428 RF_ACTIVE); 2429 if (sc->memory == NULL) { 2430 device_printf(dev, 2431 "Unable to allocate bus resource: memory\n"); 2432 return (ENXIO); 2433 } 2434 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2435 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 2436 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2437 2438 /* Only older adapters use IO mapping */ 2439 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2440 /* Figure our where our IO BAR is ? */ 2441 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2442 val = pci_read_config(dev, rid, 4); 2443 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2444 break; 2445 } 2446 rid += 4; 2447 /* check for 64bit BAR */ 2448 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2449 rid += 4; 2450 } 2451 if (rid >= PCIR_CIS) { 2452 device_printf(dev, "Unable to locate IO BAR\n"); 2453 return (ENXIO); 2454 } 2455 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2456 &rid, RF_ACTIVE); 2457 if (sc->ioport == NULL) { 2458 device_printf(dev, 2459 "Unable to allocate bus resource: ioport\n"); 2460 return (ENXIO); 2461 } 2462 sc->hw.io_base = 0; 2463 sc->osdep.io_bus_space_tag = 2464 rman_get_bustag(sc->ioport); 2465 sc->osdep.io_bus_space_handle = 2466 rman_get_bushandle(sc->ioport); 2467 } 2468 2469 sc->hw.back = &sc->osdep; 2470 2471 return (0); 2472 } 2473 2474 /********************************************************************* 2475 * 2476 * Set up the MSI-X Interrupt handlers 2477 * 2478 **********************************************************************/ 2479 static int 2480 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2481 { 2482 struct e1000_softc *sc = iflib_get_softc(ctx); 2483 struct em_rx_queue *rx_que = sc->rx_queues; 2484 struct em_tx_queue *tx_que = sc->tx_queues; 2485 int error, rid, i, vector = 0, rx_vectors; 2486 char buf[16]; 2487 2488 /* First set up ring resources */ 2489 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2490 rid = vector + 1; 2491 snprintf(buf, sizeof(buf), "rxq%d", i); 2492 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2493 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2494 if (error) { 2495 device_printf(iflib_get_dev(ctx), 2496 "Failed to allocate que int %d err: %d", 2497 i, error); 2498 sc->rx_num_queues = i + 1; 2499 goto fail; 2500 } 2501 2502 rx_que->msix = vector; 2503 2504 /* 2505 * Set the bit to enable interrupt 2506 * in E1000_IMS -- bits 20 and 21 2507 * are for RX0 and RX1, note this has 2508 * NOTHING to do with the MSI-X vector 2509 */ 2510 if (sc->hw.mac.type == e1000_82574) { 2511 rx_que->eims = 1 << (20 + i); 2512 sc->ims |= rx_que->eims; 2513 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2514 } else if (sc->hw.mac.type == e1000_82575) 2515 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2516 else 2517 rx_que->eims = 1 << vector; 2518 } 2519 rx_vectors = vector; 2520 2521 vector = 0; 2522 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2523 snprintf(buf, sizeof(buf), "txq%d", i); 2524 tx_que = &sc->tx_queues[i]; 2525 iflib_softirq_alloc_generic(ctx, 2526 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2527 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2528 2529 tx_que->msix = (vector % sc->rx_num_queues); 2530 2531 /* 2532 * Set the bit to enable interrupt 2533 * in E1000_IMS -- bits 22 and 23 2534 * are for TX0 and TX1, note this has 2535 * NOTHING to do with the MSI-X vector 2536 */ 2537 if (sc->hw.mac.type == e1000_82574) { 2538 tx_que->eims = 1 << (22 + i); 2539 sc->ims |= tx_que->eims; 2540 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2541 } else if (sc->hw.mac.type == e1000_82575) { 2542 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2543 } else { 2544 tx_que->eims = 1 << i; 2545 } 2546 } 2547 2548 /* Link interrupt */ 2549 rid = rx_vectors + 1; 2550 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, 2551 em_msix_link, sc, 0, "aq"); 2552 2553 if (error) { 2554 device_printf(iflib_get_dev(ctx), 2555 "Failed to register admin handler"); 2556 goto fail; 2557 } 2558 sc->linkvec = rx_vectors; 2559 if (sc->hw.mac.type < igb_mac_min) { 2560 sc->ivars |= (8 | rx_vectors) << 16; 2561 sc->ivars |= 0x80000000; 2562 /* Enable the "Other" interrupt type for link status change */ 2563 sc->ims |= E1000_IMS_OTHER; 2564 } 2565 2566 return (0); 2567 fail: 2568 iflib_irq_free(ctx, &sc->irq); 2569 rx_que = sc->rx_queues; 2570 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2571 iflib_irq_free(ctx, &rx_que->que_irq); 2572 return (error); 2573 } 2574 2575 static void 2576 igb_configure_queues(struct e1000_softc *sc) 2577 { 2578 struct e1000_hw *hw = &sc->hw; 2579 struct em_rx_queue *rx_que; 2580 struct em_tx_queue *tx_que; 2581 u32 tmp, ivar = 0, newitr = 0; 2582 2583 /* First turn on RSS capability */ 2584 if (hw->mac.type != e1000_82575) 2585 E1000_WRITE_REG(hw, E1000_GPIE, 2586 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2587 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2588 2589 /* Turn on MSI-X */ 2590 switch (hw->mac.type) { 2591 case e1000_82580: 2592 case e1000_i350: 2593 case e1000_i354: 2594 case e1000_i210: 2595 case e1000_i211: 2596 case e1000_vfadapt: 2597 case e1000_vfadapt_i350: 2598 /* RX entries */ 2599 for (int i = 0; i < sc->rx_num_queues; i++) { 2600 u32 index = i >> 1; 2601 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2602 rx_que = &sc->rx_queues[i]; 2603 if (i & 1) { 2604 ivar &= 0xFF00FFFF; 2605 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2606 16; 2607 } else { 2608 ivar &= 0xFFFFFF00; 2609 ivar |= rx_que->msix | E1000_IVAR_VALID; 2610 } 2611 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2612 } 2613 /* TX entries */ 2614 for (int i = 0; i < sc->tx_num_queues; i++) { 2615 u32 index = i >> 1; 2616 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2617 tx_que = &sc->tx_queues[i]; 2618 if (i & 1) { 2619 ivar &= 0x00FFFFFF; 2620 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2621 24; 2622 } else { 2623 ivar &= 0xFFFF00FF; 2624 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2625 8; 2626 } 2627 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2628 sc->que_mask |= tx_que->eims; 2629 } 2630 2631 /* And for the link interrupt */ 2632 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2633 sc->link_mask = 1 << sc->linkvec; 2634 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2635 break; 2636 case e1000_82576: 2637 /* RX entries */ 2638 for (int i = 0; i < sc->rx_num_queues; i++) { 2639 u32 index = i & 0x7; /* Each IVAR has two entries */ 2640 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2641 rx_que = &sc->rx_queues[i]; 2642 if (i < 8) { 2643 ivar &= 0xFFFFFF00; 2644 ivar |= rx_que->msix | E1000_IVAR_VALID; 2645 } else { 2646 ivar &= 0xFF00FFFF; 2647 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2648 16; 2649 } 2650 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2651 sc->que_mask |= rx_que->eims; 2652 } 2653 /* TX entries */ 2654 for (int i = 0; i < sc->tx_num_queues; i++) { 2655 u32 index = i & 0x7; /* Each IVAR has two entries */ 2656 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2657 tx_que = &sc->tx_queues[i]; 2658 if (i < 8) { 2659 ivar &= 0xFFFF00FF; 2660 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2661 8; 2662 } else { 2663 ivar &= 0x00FFFFFF; 2664 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2665 24; 2666 } 2667 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2668 sc->que_mask |= tx_que->eims; 2669 } 2670 2671 /* And for the link interrupt */ 2672 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2673 sc->link_mask = 1 << sc->linkvec; 2674 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2675 break; 2676 2677 case e1000_82575: 2678 /* enable MSI-X support*/ 2679 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2680 tmp |= E1000_CTRL_EXT_PBA_CLR; 2681 /* Auto-Mask interrupts upon ICR read. */ 2682 tmp |= E1000_CTRL_EXT_EIAME; 2683 tmp |= E1000_CTRL_EXT_IRCA; 2684 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2685 2686 /* Queues */ 2687 for (int i = 0; i < sc->rx_num_queues; i++) { 2688 rx_que = &sc->rx_queues[i]; 2689 tmp = E1000_EICR_RX_QUEUE0 << i; 2690 tmp |= E1000_EICR_TX_QUEUE0 << i; 2691 rx_que->eims = tmp; 2692 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i, 2693 rx_que->eims); 2694 sc->que_mask |= rx_que->eims; 2695 } 2696 2697 /* Link */ 2698 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2699 E1000_EIMS_OTHER); 2700 sc->link_mask |= E1000_EIMS_OTHER; 2701 default: 2702 break; 2703 } 2704 2705 /* Set the igb starting interrupt rate */ 2706 if (em_max_interrupt_rate > 0) { 2707 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2708 2709 if (hw->mac.type == e1000_82575) 2710 newitr |= newitr << 16; 2711 else 2712 newitr |= E1000_EITR_CNT_IGNR; 2713 2714 for (int i = 0; i < sc->rx_num_queues; i++) { 2715 rx_que = &sc->rx_queues[i]; 2716 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2717 } 2718 } 2719 2720 return; 2721 } 2722 2723 static void 2724 em_free_pci_resources(if_ctx_t ctx) 2725 { 2726 struct e1000_softc *sc = iflib_get_softc(ctx); 2727 struct em_rx_queue *que = sc->rx_queues; 2728 device_t dev = iflib_get_dev(ctx); 2729 2730 /* Release all MSI-X queue resources */ 2731 if (sc->intr_type == IFLIB_INTR_MSIX) 2732 iflib_irq_free(ctx, &sc->irq); 2733 2734 if (que != NULL) { 2735 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2736 iflib_irq_free(ctx, &que->que_irq); 2737 } 2738 } 2739 2740 if (sc->memory != NULL) { 2741 bus_release_resource(dev, SYS_RES_MEMORY, 2742 rman_get_rid(sc->memory), sc->memory); 2743 sc->memory = NULL; 2744 } 2745 2746 if (sc->flash != NULL) { 2747 bus_release_resource(dev, SYS_RES_MEMORY, 2748 rman_get_rid(sc->flash), sc->flash); 2749 sc->flash = NULL; 2750 } 2751 2752 if (sc->ioport != NULL) { 2753 bus_release_resource(dev, SYS_RES_IOPORT, 2754 rman_get_rid(sc->ioport), sc->ioport); 2755 sc->ioport = NULL; 2756 } 2757 } 2758 2759 /* Set up MSI or MSI-X */ 2760 static int 2761 em_setup_msix(if_ctx_t ctx) 2762 { 2763 struct e1000_softc *sc = iflib_get_softc(ctx); 2764 2765 if (sc->hw.mac.type == e1000_82574) { 2766 em_enable_vectors_82574(ctx); 2767 } 2768 return (0); 2769 } 2770 2771 /********************************************************************* 2772 * 2773 * Workaround for SmartSpeed on 82541 and 82547 controllers 2774 * 2775 **********************************************************************/ 2776 static void 2777 lem_smartspeed(struct e1000_softc *sc) 2778 { 2779 u16 phy_tmp; 2780 2781 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2782 sc->hw.mac.autoneg == 0 || 2783 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2784 return; 2785 2786 if (sc->smartspeed == 0) { 2787 /* If Master/Slave config fault is asserted twice, 2788 * we assume back-to-back */ 2789 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2790 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2791 return; 2792 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2793 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2794 e1000_read_phy_reg(&sc->hw, 2795 PHY_1000T_CTRL, &phy_tmp); 2796 if(phy_tmp & CR_1000T_MS_ENABLE) { 2797 phy_tmp &= ~CR_1000T_MS_ENABLE; 2798 e1000_write_phy_reg(&sc->hw, 2799 PHY_1000T_CTRL, phy_tmp); 2800 sc->smartspeed++; 2801 if(sc->hw.mac.autoneg && 2802 !e1000_copper_link_autoneg(&sc->hw) && 2803 !e1000_read_phy_reg(&sc->hw, 2804 PHY_CONTROL, &phy_tmp)) { 2805 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2806 MII_CR_RESTART_AUTO_NEG); 2807 e1000_write_phy_reg(&sc->hw, 2808 PHY_CONTROL, phy_tmp); 2809 } 2810 } 2811 } 2812 return; 2813 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2814 /* If still no link, perhaps using 2/3 pair cable */ 2815 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2816 phy_tmp |= CR_1000T_MS_ENABLE; 2817 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2818 if(sc->hw.mac.autoneg && 2819 !e1000_copper_link_autoneg(&sc->hw) && 2820 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2821 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2822 MII_CR_RESTART_AUTO_NEG); 2823 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2824 } 2825 } 2826 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2827 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2828 sc->smartspeed = 0; 2829 } 2830 2831 /********************************************************************* 2832 * 2833 * Initialize the DMA Coalescing feature 2834 * 2835 **********************************************************************/ 2836 static void 2837 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2838 { 2839 device_t dev = sc->dev; 2840 struct e1000_hw *hw = &sc->hw; 2841 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2842 u16 hwm; 2843 u16 max_frame_size; 2844 2845 if (hw->mac.type == e1000_i211) 2846 return; 2847 2848 max_frame_size = sc->shared->isc_max_frame_size; 2849 if (hw->mac.type > e1000_82580) { 2850 2851 if (sc->dmac == 0) { /* Disabling it */ 2852 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2853 return; 2854 } else 2855 device_printf(dev, "DMA Coalescing enabled\n"); 2856 2857 /* Set starting threshold */ 2858 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2859 2860 hwm = 64 * pba - max_frame_size / 16; 2861 if (hwm < 64 * (pba - 6)) 2862 hwm = 64 * (pba - 6); 2863 reg = E1000_READ_REG(hw, E1000_FCRTC); 2864 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2865 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2866 & E1000_FCRTC_RTH_COAL_MASK); 2867 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2868 2869 2870 dmac = pba - max_frame_size / 512; 2871 if (dmac < pba - 10) 2872 dmac = pba - 10; 2873 reg = E1000_READ_REG(hw, E1000_DMACR); 2874 reg &= ~E1000_DMACR_DMACTHR_MASK; 2875 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2876 & E1000_DMACR_DMACTHR_MASK); 2877 2878 /* transition to L0x or L1 if available..*/ 2879 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2880 2881 /* Check if status is 2.5Gb backplane connection 2882 * before configuration of watchdog timer, which is 2883 * in msec values in 12.8usec intervals 2884 * watchdog timer= msec values in 32usec intervals 2885 * for non 2.5Gb connection 2886 */ 2887 if (hw->mac.type == e1000_i354) { 2888 int status = E1000_READ_REG(hw, E1000_STATUS); 2889 if ((status & E1000_STATUS_2P5_SKU) && 2890 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2891 reg |= ((sc->dmac * 5) >> 6); 2892 else 2893 reg |= (sc->dmac >> 5); 2894 } else { 2895 reg |= (sc->dmac >> 5); 2896 } 2897 2898 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2899 2900 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2901 2902 /* Set the interval before transition */ 2903 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2904 if (hw->mac.type == e1000_i350) 2905 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2906 /* 2907 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2908 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2909 */ 2910 if (hw->mac.type == e1000_i354) { 2911 int status = E1000_READ_REG(hw, E1000_STATUS); 2912 if ((status & E1000_STATUS_2P5_SKU) && 2913 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2914 reg |= 0xA; 2915 else 2916 reg |= 0x4; 2917 } else { 2918 reg |= 0x4; 2919 } 2920 2921 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2922 2923 /* free space in tx packet buffer to wake from DMA coal */ 2924 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2925 (2 * max_frame_size)) >> 6); 2926 2927 /* make low power state decision controlled by DMA coal */ 2928 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2929 reg &= ~E1000_PCIEMISC_LX_DECISION; 2930 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2931 2932 } else if (hw->mac.type == e1000_82580) { 2933 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2934 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2935 reg & ~E1000_PCIEMISC_LX_DECISION); 2936 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2937 } 2938 } 2939 /********************************************************************* 2940 * The 3 following flush routines are used as a workaround in the 2941 * I219 client parts and only for them. 2942 * 2943 * em_flush_tx_ring - remove all descriptors from the tx_ring 2944 * 2945 * We want to clear all pending descriptors from the TX ring. 2946 * zeroing happens when the HW reads the regs. We assign the ring itself as 2947 * the data of the next descriptor. We don't care about the data we are about 2948 * to reset the HW. 2949 **********************************************************************/ 2950 static void 2951 em_flush_tx_ring(struct e1000_softc *sc) 2952 { 2953 struct e1000_hw *hw = &sc->hw; 2954 struct tx_ring *txr = &sc->tx_queues->txr; 2955 struct e1000_tx_desc *txd; 2956 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2957 u16 size = 512; 2958 2959 tctl = E1000_READ_REG(hw, E1000_TCTL); 2960 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2961 2962 txd = &txr->tx_base[txr->tx_cidx_processed]; 2963 2964 /* Just use the ring as a dummy buffer addr */ 2965 txd->buffer_addr = txr->tx_paddr; 2966 txd->lower.data = htole32(txd_lower | size); 2967 txd->upper.data = 0; 2968 2969 /* flush descriptors to memory before notifying the HW */ 2970 wmb(); 2971 2972 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2973 mb(); 2974 usec_delay(250); 2975 } 2976 2977 /********************************************************************* 2978 * em_flush_rx_ring - remove all descriptors from the rx_ring 2979 * 2980 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2981 **********************************************************************/ 2982 static void 2983 em_flush_rx_ring(struct e1000_softc *sc) 2984 { 2985 struct e1000_hw *hw = &sc->hw; 2986 u32 rctl, rxdctl; 2987 2988 rctl = E1000_READ_REG(hw, E1000_RCTL); 2989 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2990 E1000_WRITE_FLUSH(hw); 2991 usec_delay(150); 2992 2993 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2994 /* zero the lower 14 bits (prefetch and host thresholds) */ 2995 rxdctl &= 0xffffc000; 2996 /* 2997 * update thresholds: prefetch threshold to 31, host threshold to 1 2998 * and make sure the granularity is "descriptors" and not 2999 * "cache lines" 3000 */ 3001 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 3002 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 3003 3004 /* momentarily enable the RX ring for the changes to take effect */ 3005 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3006 E1000_WRITE_FLUSH(hw); 3007 usec_delay(150); 3008 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3009 } 3010 3011 /********************************************************************* 3012 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3013 * 3014 * In I219, the descriptor rings must be emptied before resetting the HW 3015 * or before changing the device state to D3 during runtime (runtime PM). 3016 * 3017 * Failure to do this will cause the HW to enter a unit hang state which can 3018 * only be released by PCI reset on the device 3019 * 3020 **********************************************************************/ 3021 static void 3022 em_flush_desc_rings(struct e1000_softc *sc) 3023 { 3024 struct e1000_hw *hw = &sc->hw; 3025 device_t dev = sc->dev; 3026 u16 hang_state; 3027 u32 fext_nvm11, tdlen; 3028 3029 /* First, disable MULR fix in FEXTNVM11 */ 3030 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 3031 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3032 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 3033 3034 /* do nothing if we're not in faulty state, or the queue is empty */ 3035 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 3036 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3037 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3038 return; 3039 em_flush_tx_ring(sc); 3040 3041 /* recheck, maybe the fault is caused by the rx ring */ 3042 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3043 if (hang_state & FLUSH_DESC_REQUIRED) 3044 em_flush_rx_ring(sc); 3045 } 3046 3047 3048 /********************************************************************* 3049 * 3050 * Initialize the hardware to a configuration as specified by the 3051 * sc structure. 3052 * 3053 **********************************************************************/ 3054 static void 3055 em_reset(if_ctx_t ctx) 3056 { 3057 device_t dev = iflib_get_dev(ctx); 3058 struct e1000_softc *sc = iflib_get_softc(ctx); 3059 if_t ifp = iflib_get_ifp(ctx); 3060 struct e1000_hw *hw = &sc->hw; 3061 u32 rx_buffer_size; 3062 u32 pba; 3063 3064 INIT_DEBUGOUT("em_reset: begin"); 3065 /* Let the firmware know the OS is in control */ 3066 em_get_hw_control(sc); 3067 3068 /* Set up smart power down as default off on newer adapters. */ 3069 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 3070 hw->mac.type == e1000_82572)) { 3071 u16 phy_tmp = 0; 3072 3073 /* Speed up time to link by disabling smart power down. */ 3074 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 3075 phy_tmp &= ~IGP02E1000_PM_SPD; 3076 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 3077 } 3078 3079 /* 3080 * Packet Buffer Allocation (PBA) 3081 * Writing PBA sets the receive portion of the buffer 3082 * the remainder is used for the transmit buffer. 3083 */ 3084 switch (hw->mac.type) { 3085 /* 82547: Total Packet Buffer is 40K */ 3086 case e1000_82547: 3087 case e1000_82547_rev_2: 3088 if (hw->mac.max_frame_size > 8192) 3089 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 3090 else 3091 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 3092 break; 3093 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 3094 case e1000_82571: 3095 case e1000_82572: 3096 case e1000_80003es2lan: 3097 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 3098 break; 3099 /* 82573: Total Packet Buffer is 32K */ 3100 case e1000_82573: 3101 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 3102 break; 3103 case e1000_82574: 3104 case e1000_82583: 3105 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 3106 break; 3107 case e1000_ich8lan: 3108 pba = E1000_PBA_8K; 3109 break; 3110 case e1000_ich9lan: 3111 case e1000_ich10lan: 3112 /* Boost Receive side for jumbo frames */ 3113 if (hw->mac.max_frame_size > 4096) 3114 pba = E1000_PBA_14K; 3115 else 3116 pba = E1000_PBA_10K; 3117 break; 3118 case e1000_pchlan: 3119 case e1000_pch2lan: 3120 case e1000_pch_lpt: 3121 case e1000_pch_spt: 3122 case e1000_pch_cnp: 3123 case e1000_pch_tgp: 3124 case e1000_pch_adp: 3125 case e1000_pch_mtp: 3126 case e1000_pch_ptp: 3127 pba = E1000_PBA_26K; 3128 break; 3129 case e1000_82575: 3130 pba = E1000_PBA_32K; 3131 break; 3132 case e1000_82576: 3133 case e1000_vfadapt: 3134 pba = E1000_READ_REG(hw, E1000_RXPBS); 3135 pba &= E1000_RXPBS_SIZE_MASK_82576; 3136 break; 3137 case e1000_82580: 3138 case e1000_i350: 3139 case e1000_i354: 3140 case e1000_vfadapt_i350: 3141 pba = E1000_READ_REG(hw, E1000_RXPBS); 3142 pba = e1000_rxpbs_adjust_82580(pba); 3143 break; 3144 case e1000_i210: 3145 case e1000_i211: 3146 pba = E1000_PBA_34K; 3147 break; 3148 default: 3149 /* Remaining devices assumed to have Packet Buffer of 64K. */ 3150 if (hw->mac.max_frame_size > 8192) 3151 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 3152 else 3153 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 3154 } 3155 3156 /* Special needs in case of Jumbo frames */ 3157 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 3158 u32 tx_space, min_tx, min_rx; 3159 pba = E1000_READ_REG(hw, E1000_PBA); 3160 tx_space = pba >> 16; 3161 pba &= 0xffff; 3162 min_tx = (hw->mac.max_frame_size + 3163 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 3164 min_tx = roundup2(min_tx, 1024); 3165 min_tx >>= 10; 3166 min_rx = hw->mac.max_frame_size; 3167 min_rx = roundup2(min_rx, 1024); 3168 min_rx >>= 10; 3169 if (tx_space < min_tx && 3170 ((min_tx - tx_space) < pba)) { 3171 pba = pba - (min_tx - tx_space); 3172 /* 3173 * if short on rx space, rx wins 3174 * and must trump tx adjustment 3175 */ 3176 if (pba < min_rx) 3177 pba = min_rx; 3178 } 3179 E1000_WRITE_REG(hw, E1000_PBA, pba); 3180 } 3181 3182 if (hw->mac.type < igb_mac_min) 3183 E1000_WRITE_REG(hw, E1000_PBA, pba); 3184 3185 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 3186 3187 /* 3188 * These parameters control the automatic generation (Tx) and 3189 * response (Rx) to Ethernet PAUSE frames. 3190 * - High water mark should allow for at least two frames to be 3191 * received after sending an XOFF. 3192 * - Low water mark works best when it is very near the high water 3193 mark. 3194 * This allows the receiver to restart by sending XON when it has 3195 * drained a bit. Here we use an arbitrary value of 1500 which will 3196 * restart after one full frame is pulled from the buffer. There 3197 * could be several smaller frames in the buffer and if so they will 3198 * not trigger the XON until their total number reduces the buffer 3199 * by 1500. 3200 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 3201 */ 3202 rx_buffer_size = (pba & 0xffff) << 10; 3203 hw->fc.high_water = rx_buffer_size - 3204 roundup2(hw->mac.max_frame_size, 1024); 3205 hw->fc.low_water = hw->fc.high_water - 1500; 3206 3207 if (sc->fc) /* locally set flow control value? */ 3208 hw->fc.requested_mode = sc->fc; 3209 else 3210 hw->fc.requested_mode = e1000_fc_full; 3211 3212 if (hw->mac.type == e1000_80003es2lan) 3213 hw->fc.pause_time = 0xFFFF; 3214 else 3215 hw->fc.pause_time = EM_FC_PAUSE_TIME; 3216 3217 hw->fc.send_xon = true; 3218 3219 /* Device specific overrides/settings */ 3220 switch (hw->mac.type) { 3221 case e1000_pchlan: 3222 /* Workaround: no TX flow ctrl for PCH */ 3223 hw->fc.requested_mode = e1000_fc_rx_pause; 3224 hw->fc.pause_time = 0xFFFF; /* override */ 3225 if (if_getmtu(ifp) > ETHERMTU) { 3226 hw->fc.high_water = 0x3500; 3227 hw->fc.low_water = 0x1500; 3228 } else { 3229 hw->fc.high_water = 0x5000; 3230 hw->fc.low_water = 0x3000; 3231 } 3232 hw->fc.refresh_time = 0x1000; 3233 break; 3234 case e1000_pch2lan: 3235 case e1000_pch_lpt: 3236 case e1000_pch_spt: 3237 case e1000_pch_cnp: 3238 case e1000_pch_tgp: 3239 case e1000_pch_adp: 3240 case e1000_pch_mtp: 3241 case e1000_pch_ptp: 3242 hw->fc.high_water = 0x5C20; 3243 hw->fc.low_water = 0x5048; 3244 hw->fc.pause_time = 0x0650; 3245 hw->fc.refresh_time = 0x0400; 3246 /* Jumbos need adjusted PBA */ 3247 if (if_getmtu(ifp) > ETHERMTU) 3248 E1000_WRITE_REG(hw, E1000_PBA, 12); 3249 else 3250 E1000_WRITE_REG(hw, E1000_PBA, 26); 3251 break; 3252 case e1000_82575: 3253 case e1000_82576: 3254 /* 8-byte granularity */ 3255 hw->fc.low_water = hw->fc.high_water - 8; 3256 break; 3257 case e1000_82580: 3258 case e1000_i350: 3259 case e1000_i354: 3260 case e1000_i210: 3261 case e1000_i211: 3262 case e1000_vfadapt: 3263 case e1000_vfadapt_i350: 3264 /* 16-byte granularity */ 3265 hw->fc.low_water = hw->fc.high_water - 16; 3266 break; 3267 case e1000_ich9lan: 3268 case e1000_ich10lan: 3269 if (if_getmtu(ifp) > ETHERMTU) { 3270 hw->fc.high_water = 0x2800; 3271 hw->fc.low_water = hw->fc.high_water - 8; 3272 break; 3273 } 3274 /* FALLTHROUGH */ 3275 default: 3276 if (hw->mac.type == e1000_80003es2lan) 3277 hw->fc.pause_time = 0xFFFF; 3278 break; 3279 } 3280 3281 /* I219 needs some special flushing to avoid hangs */ 3282 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 3283 em_flush_desc_rings(sc); 3284 3285 /* Issue a global reset */ 3286 e1000_reset_hw(hw); 3287 if (hw->mac.type >= igb_mac_min) { 3288 E1000_WRITE_REG(hw, E1000_WUC, 0); 3289 } else { 3290 E1000_WRITE_REG(hw, E1000_WUFC, 0); 3291 em_disable_aspm(sc); 3292 } 3293 if (sc->flags & IGB_MEDIA_RESET) { 3294 e1000_setup_init_funcs(hw, true); 3295 e1000_get_bus_info(hw); 3296 sc->flags &= ~IGB_MEDIA_RESET; 3297 } 3298 /* and a re-init */ 3299 if (e1000_init_hw(hw) < 0) { 3300 device_printf(dev, "Hardware Initialization Failed\n"); 3301 return; 3302 } 3303 if (hw->mac.type >= igb_mac_min) 3304 igb_init_dmac(sc, pba); 3305 3306 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 3307 sc->pba = pba; 3308 3309 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 3310 e1000_get_phy_info(hw); 3311 e1000_check_for_link(hw); 3312 } 3313 3314 /* 3315 * Initialise the RSS mapping for NICs that support multiple transmit/ 3316 * receive rings. 3317 */ 3318 3319 #define RSSKEYLEN 10 3320 static void 3321 em_initialize_rss_mapping(struct e1000_softc *sc) 3322 { 3323 uint8_t rss_key[4 * RSSKEYLEN]; 3324 uint32_t reta = 0; 3325 struct e1000_hw *hw = &sc->hw; 3326 int i; 3327 3328 /* 3329 * Configure RSS key 3330 */ 3331 arc4rand(rss_key, sizeof(rss_key), 0); 3332 for (i = 0; i < RSSKEYLEN; ++i) { 3333 uint32_t rssrk = 0; 3334 3335 rssrk = EM_RSSRK_VAL(rss_key, i); 3336 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 3337 } 3338 3339 /* 3340 * Configure RSS redirect table in following fashion: 3341 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3342 */ 3343 for (i = 0; i < sizeof(reta); ++i) { 3344 uint32_t q; 3345 3346 q = (i % sc->rx_num_queues) << 7; 3347 reta |= q << (8 * i); 3348 } 3349 3350 for (i = 0; i < 32; ++i) 3351 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 3352 3353 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 3354 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3355 E1000_MRQC_RSS_FIELD_IPV4 | 3356 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 3357 E1000_MRQC_RSS_FIELD_IPV6_EX | 3358 E1000_MRQC_RSS_FIELD_IPV6); 3359 } 3360 3361 static void 3362 igb_initialize_rss_mapping(struct e1000_softc *sc) 3363 { 3364 struct e1000_hw *hw = &sc->hw; 3365 int i; 3366 int queue_id; 3367 u32 reta; 3368 u32 rss_key[10], mrqc, shift = 0; 3369 3370 /* XXX? */ 3371 if (hw->mac.type == e1000_82575) 3372 shift = 6; 3373 3374 /* 3375 * The redirection table controls which destination 3376 * queue each bucket redirects traffic to. 3377 * Each DWORD represents four queues, with the LSB 3378 * being the first queue in the DWORD. 3379 * 3380 * This just allocates buckets to queues using round-robin 3381 * allocation. 3382 * 3383 * NOTE: It Just Happens to line up with the default 3384 * RSS allocation method. 3385 */ 3386 3387 /* Warning FM follows */ 3388 reta = 0; 3389 for (i = 0; i < 128; i++) { 3390 #ifdef RSS 3391 queue_id = rss_get_indirection_to_bucket(i); 3392 /* 3393 * If we have more queues than buckets, we'll 3394 * end up mapping buckets to a subset of the 3395 * queues. 3396 * 3397 * If we have more buckets than queues, we'll 3398 * end up instead assigning multiple buckets 3399 * to queues. 3400 * 3401 * Both are suboptimal, but we need to handle 3402 * the case so we don't go out of bounds 3403 * indexing arrays and such. 3404 */ 3405 queue_id = queue_id % sc->rx_num_queues; 3406 #else 3407 queue_id = (i % sc->rx_num_queues); 3408 #endif 3409 /* Adjust if required */ 3410 queue_id = queue_id << shift; 3411 3412 /* 3413 * The low 8 bits are for hash value (n+0); 3414 * The next 8 bits are for hash value (n+1), etc. 3415 */ 3416 reta = reta >> 8; 3417 reta = reta | ( ((uint32_t) queue_id) << 24); 3418 if ((i & 3) == 3) { 3419 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3420 reta = 0; 3421 } 3422 } 3423 3424 /* Now fill in hash table */ 3425 3426 /* 3427 * MRQC: Multiple Receive Queues Command 3428 * Set queuing to RSS control, number depends on the device. 3429 */ 3430 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3431 3432 #ifdef RSS 3433 /* XXX ew typecasting */ 3434 rss_getkey((uint8_t *) &rss_key); 3435 #else 3436 arc4rand(&rss_key, sizeof(rss_key), 0); 3437 #endif 3438 for (i = 0; i < 10; i++) 3439 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3440 3441 /* 3442 * Configure the RSS fields to hash upon. 3443 */ 3444 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3445 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3446 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3447 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3448 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3449 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3450 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3451 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3452 3453 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3454 } 3455 3456 /********************************************************************* 3457 * 3458 * Setup networking device structure and register interface media. 3459 * 3460 **********************************************************************/ 3461 static int 3462 em_setup_interface(if_ctx_t ctx) 3463 { 3464 if_t ifp = iflib_get_ifp(ctx); 3465 struct e1000_softc *sc = iflib_get_softc(ctx); 3466 if_softc_ctx_t scctx = sc->shared; 3467 3468 INIT_DEBUGOUT("em_setup_interface: begin"); 3469 3470 /* Single Queue */ 3471 if (sc->tx_num_queues == 1) { 3472 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3473 if_setsendqready(ifp); 3474 } 3475 3476 /* 3477 * Specify the media types supported by this adapter and register 3478 * callbacks to update media and link information 3479 */ 3480 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3481 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3482 u_char fiber_type = IFM_1000_SX; /* default type */ 3483 3484 if (sc->hw.mac.type == e1000_82545) 3485 fiber_type = IFM_1000_LX; 3486 ifmedia_add(sc->media, 3487 IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3488 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3489 } else { 3490 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3491 ifmedia_add(sc->media, 3492 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3493 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3494 ifmedia_add(sc->media, 3495 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3496 if (sc->hw.phy.type != e1000_phy_ife) { 3497 ifmedia_add(sc->media, 3498 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3499 ifmedia_add(sc->media, 3500 IFM_ETHER | IFM_1000_T, 0, NULL); 3501 } 3502 } 3503 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3504 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3505 return (0); 3506 } 3507 3508 static int 3509 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3510 int ntxqs, int ntxqsets) 3511 { 3512 struct e1000_softc *sc = iflib_get_softc(ctx); 3513 if_softc_ctx_t scctx = sc->shared; 3514 int error = E1000_SUCCESS; 3515 struct em_tx_queue *que; 3516 int i, j; 3517 3518 MPASS(sc->tx_num_queues > 0); 3519 MPASS(sc->tx_num_queues == ntxqsets); 3520 3521 /* First allocate the top level queue structs */ 3522 if (!(sc->tx_queues = 3523 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3524 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3525 device_printf(iflib_get_dev(ctx), 3526 "Unable to allocate queue memory\n"); 3527 return(ENOMEM); 3528 } 3529 3530 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3531 /* Set up some basics */ 3532 3533 struct tx_ring *txr = &que->txr; 3534 txr->sc = que->sc = sc; 3535 que->me = txr->me = i; 3536 3537 /* Allocate report status array */ 3538 if (!(txr->tx_rsq = 3539 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], 3540 M_DEVBUF, M_NOWAIT | M_ZERO))) { 3541 device_printf(iflib_get_dev(ctx), 3542 "failed to allocate rs_idxs memory\n"); 3543 error = ENOMEM; 3544 goto fail; 3545 } 3546 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3547 txr->tx_rsq[j] = QIDX_INVALID; 3548 /* get the virtual and physical address of hardware queues */ 3549 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3550 txr->tx_paddr = paddrs[i*ntxqs]; 3551 } 3552 3553 if (bootverbose) 3554 device_printf(iflib_get_dev(ctx), 3555 "allocated for %d tx_queues\n", sc->tx_num_queues); 3556 return (0); 3557 fail: 3558 em_if_queues_free(ctx); 3559 return (error); 3560 } 3561 3562 static int 3563 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3564 int nrxqs, int nrxqsets) 3565 { 3566 struct e1000_softc *sc = iflib_get_softc(ctx); 3567 int error = E1000_SUCCESS; 3568 struct em_rx_queue *que; 3569 int i; 3570 3571 MPASS(sc->rx_num_queues > 0); 3572 MPASS(sc->rx_num_queues == nrxqsets); 3573 3574 /* First allocate the top level queue structs */ 3575 if (!(sc->rx_queues = 3576 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3577 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3578 device_printf(iflib_get_dev(ctx), 3579 "Unable to allocate queue memory\n"); 3580 error = ENOMEM; 3581 goto fail; 3582 } 3583 3584 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3585 /* Set up some basics */ 3586 struct rx_ring *rxr = &que->rxr; 3587 rxr->sc = que->sc = sc; 3588 rxr->que = que; 3589 que->me = rxr->me = i; 3590 3591 /* get the virtual and physical address of hardware queues */ 3592 rxr->rx_base = 3593 (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3594 rxr->rx_paddr = paddrs[i*nrxqs]; 3595 } 3596 3597 if (bootverbose) 3598 device_printf(iflib_get_dev(ctx), 3599 "allocated for %d rx_queues\n", sc->rx_num_queues); 3600 3601 return (0); 3602 fail: 3603 em_if_queues_free(ctx); 3604 return (error); 3605 } 3606 3607 static void 3608 em_if_queues_free(if_ctx_t ctx) 3609 { 3610 struct e1000_softc *sc = iflib_get_softc(ctx); 3611 struct em_tx_queue *tx_que = sc->tx_queues; 3612 struct em_rx_queue *rx_que = sc->rx_queues; 3613 3614 if (tx_que != NULL) { 3615 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3616 struct tx_ring *txr = &tx_que->txr; 3617 if (txr->tx_rsq == NULL) 3618 break; 3619 3620 free(txr->tx_rsq, M_DEVBUF); 3621 txr->tx_rsq = NULL; 3622 } 3623 free(sc->tx_queues, M_DEVBUF); 3624 sc->tx_queues = NULL; 3625 } 3626 3627 if (rx_que != NULL) { 3628 free(sc->rx_queues, M_DEVBUF); 3629 sc->rx_queues = NULL; 3630 } 3631 } 3632 3633 /********************************************************************* 3634 * 3635 * Enable transmit unit. 3636 * 3637 **********************************************************************/ 3638 static void 3639 em_initialize_transmit_unit(if_ctx_t ctx) 3640 { 3641 struct e1000_softc *sc = iflib_get_softc(ctx); 3642 if_softc_ctx_t scctx = sc->shared; 3643 struct em_tx_queue *que; 3644 struct tx_ring *txr; 3645 struct e1000_hw *hw = &sc->hw; 3646 u32 tctl, txdctl = 0, tarc, tipg = 0; 3647 3648 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3649 3650 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3651 u64 bus_addr; 3652 caddr_t offp, endp; 3653 3654 que = &sc->tx_queues[i]; 3655 txr = &que->txr; 3656 bus_addr = txr->tx_paddr; 3657 3658 /* Clear checksum offload context. */ 3659 offp = (caddr_t)&txr->csum_flags; 3660 endp = (caddr_t)(txr + 1); 3661 bzero(offp, endp - offp); 3662 3663 /* Base and Len of TX Ring */ 3664 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3665 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3666 E1000_WRITE_REG(hw, E1000_TDBAH(i), (u32)(bus_addr >> 32)); 3667 E1000_WRITE_REG(hw, E1000_TDBAL(i), (u32)bus_addr); 3668 /* Init the HEAD/TAIL indices */ 3669 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3670 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3671 3672 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3673 E1000_READ_REG(hw, E1000_TDBAL(i)), 3674 E1000_READ_REG(hw, E1000_TDLEN(i))); 3675 3676 txdctl = 0; /* clear txdctl */ 3677 txdctl |= 0x1f; /* PTHRESH */ 3678 txdctl |= 1 << 8; /* HTHRESH */ 3679 txdctl |= 1 << 16;/* WTHRESH */ 3680 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3681 txdctl |= E1000_TXDCTL_GRAN; 3682 txdctl |= 1 << 25; /* LWTHRESH */ 3683 3684 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3685 } 3686 3687 /* Set the default values for the Tx Inter Packet Gap timer */ 3688 switch (hw->mac.type) { 3689 case e1000_80003es2lan: 3690 tipg = DEFAULT_82543_TIPG_IPGR1; 3691 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3692 E1000_TIPG_IPGR2_SHIFT; 3693 break; 3694 case e1000_82542: 3695 tipg = DEFAULT_82542_TIPG_IPGT; 3696 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3697 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3698 break; 3699 default: 3700 if (hw->phy.media_type == e1000_media_type_fiber || 3701 hw->phy.media_type == e1000_media_type_internal_serdes) 3702 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3703 else 3704 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3705 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3706 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3707 } 3708 3709 if (hw->mac.type < igb_mac_min) { 3710 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3711 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3712 3713 if (sc->tx_int_delay.value > 0) 3714 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3715 } 3716 3717 if (hw->mac.type >= e1000_82540) 3718 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3719 3720 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3721 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3722 tarc |= TARC_SPEED_MODE_BIT; 3723 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3724 } else if (hw->mac.type == e1000_80003es2lan) { 3725 /* errata: program both queues to unweighted RR */ 3726 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3727 tarc |= 1; 3728 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3729 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3730 tarc |= 1; 3731 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3732 } else if (hw->mac.type == e1000_82574) { 3733 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3734 tarc |= TARC_ERRATA_BIT; 3735 if ( sc->tx_num_queues > 1) { 3736 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3737 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3738 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3739 } else 3740 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3741 } 3742 3743 /* Program the Transmit Control Register */ 3744 tctl = E1000_READ_REG(hw, E1000_TCTL); 3745 tctl &= ~E1000_TCTL_CT; 3746 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3747 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3748 3749 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3750 tctl |= E1000_TCTL_MULR; 3751 3752 /* This write will effectively turn on the transmit unit. */ 3753 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3754 3755 /* SPT and KBL errata workarounds */ 3756 if (hw->mac.type == e1000_pch_spt) { 3757 u32 reg; 3758 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3759 reg |= E1000_RCTL_RDMTS_HEX; 3760 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3761 /* i218-i219 Specification Update 1.5.4.5 */ 3762 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3763 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3764 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3765 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3766 } 3767 } 3768 3769 /********************************************************************* 3770 * 3771 * Enable receive unit. 3772 * 3773 **********************************************************************/ 3774 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3775 3776 static void 3777 em_initialize_receive_unit(if_ctx_t ctx) 3778 { 3779 struct e1000_softc *sc = iflib_get_softc(ctx); 3780 if_softc_ctx_t scctx = sc->shared; 3781 if_t ifp = iflib_get_ifp(ctx); 3782 struct e1000_hw *hw = &sc->hw; 3783 struct em_rx_queue *que; 3784 int i; 3785 uint32_t rctl, rxcsum; 3786 3787 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3788 3789 /* 3790 * Make sure receives are disabled while setting 3791 * up the descriptor ring 3792 */ 3793 rctl = E1000_READ_REG(hw, E1000_RCTL); 3794 /* Do not disable if ever enabled on this hardware */ 3795 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3796 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3797 3798 /* Setup the Receive Control Register */ 3799 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3800 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3801 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3802 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3803 3804 /* Do not store bad packets */ 3805 rctl &= ~E1000_RCTL_SBP; 3806 3807 /* Enable Long Packet receive */ 3808 if (if_getmtu(ifp) > ETHERMTU) 3809 rctl |= E1000_RCTL_LPE; 3810 else 3811 rctl &= ~E1000_RCTL_LPE; 3812 3813 /* Strip the CRC */ 3814 if (!em_disable_crc_stripping) 3815 rctl |= E1000_RCTL_SECRC; 3816 3817 /* lem/em default interrupt moderation */ 3818 if (hw->mac.type < igb_mac_min) { 3819 if (hw->mac.type >= e1000_82540) { 3820 E1000_WRITE_REG(hw, E1000_RADV, 3821 sc->rx_abs_int_delay.value); 3822 3823 /* Set the default interrupt throttling rate */ 3824 E1000_WRITE_REG(hw, E1000_ITR, 3825 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3826 } 3827 3828 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3829 * long latencies are observed, like Lenovo X60. This 3830 * change eliminates the problem, but since having positive 3831 * values in RDTR is a known source of problems on other 3832 * platforms another solution is being sought. 3833 */ 3834 if (hw->mac.type == e1000_82573) 3835 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3836 else 3837 E1000_WRITE_REG(hw, E1000_RDTR, 3838 sc->rx_int_delay.value); 3839 } 3840 3841 if (hw->mac.type >= em_mac_min) { 3842 uint32_t rfctl; 3843 /* Use extended rx descriptor formats */ 3844 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3845 rfctl |= E1000_RFCTL_EXTEN; 3846 3847 /* 3848 * When using MSI-X interrupts we need to throttle 3849 * using the EITR register (82574 only) 3850 */ 3851 if (hw->mac.type == e1000_82574) { 3852 for (int i = 0; i < 4; i++) 3853 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3854 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3855 /* Disable accelerated acknowledge */ 3856 rfctl |= E1000_RFCTL_ACK_DIS; 3857 } 3858 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3859 } 3860 3861 /* Set up L3 and L4 csum Rx descriptor offloads */ 3862 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3863 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3864 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3865 if (hw->mac.type > e1000_82575) 3866 rxcsum |= E1000_RXCSUM_CRCOFL; 3867 else if (hw->mac.type < em_mac_min && 3868 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3869 rxcsum |= E1000_RXCSUM_IPV6OFL; 3870 } else { 3871 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3872 if (hw->mac.type > e1000_82575) 3873 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3874 else if (hw->mac.type < em_mac_min) 3875 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3876 } 3877 3878 if (sc->rx_num_queues > 1) { 3879 /* RSS hash needed in the Rx descriptor */ 3880 rxcsum |= E1000_RXCSUM_PCSD; 3881 3882 if (hw->mac.type >= igb_mac_min) 3883 igb_initialize_rss_mapping(sc); 3884 else 3885 em_initialize_rss_mapping(sc); 3886 } 3887 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3888 3889 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3890 struct rx_ring *rxr = &que->rxr; 3891 /* Setup the Base and Length of the Rx Descriptor Ring */ 3892 u64 bus_addr = rxr->rx_paddr; 3893 #if 0 3894 u32 rdt = sc->rx_num_queues -1; /* default */ 3895 #endif 3896 3897 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3898 scctx->isc_nrxd[0] * 3899 sizeof(union e1000_rx_desc_extended)); 3900 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3901 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3902 /* Setup the Head and Tail Descriptor Pointers */ 3903 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3904 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3905 } 3906 3907 /* 3908 * Set PTHRESH for improved jumbo performance 3909 * According to 10.2.5.11 of Intel 82574 Datasheet, 3910 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3911 * Only write to RXDCTL(1) if there is a need for different 3912 * settings. 3913 */ 3914 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3915 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3916 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3917 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3918 } else if (hw->mac.type == e1000_82574) { 3919 for (int i = 0; i < sc->rx_num_queues; i++) { 3920 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3921 rxdctl |= 0x20; /* PTHRESH */ 3922 rxdctl |= 4 << 8; /* HTHRESH */ 3923 rxdctl |= 4 << 16;/* WTHRESH */ 3924 rxdctl |= 1 << 24; /* Switch to granularity */ 3925 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3926 } 3927 } else if (hw->mac.type >= igb_mac_min) { 3928 u32 psize, srrctl = 0; 3929 3930 if (if_getmtu(ifp) > ETHERMTU) { 3931 psize = scctx->isc_max_frame_size; 3932 /* are we on a vlan? */ 3933 if (if_vlantrunkinuse(ifp)) 3934 psize += VLAN_TAG_SIZE; 3935 3936 if (sc->vf_ifp) 3937 e1000_rlpml_set_vf(hw, psize); 3938 else 3939 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3940 } 3941 3942 /* Set maximum packet buffer len */ 3943 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3944 E1000_SRRCTL_BSIZEPKT_SHIFT; 3945 3946 /* 3947 * If TX flow control is disabled and there's >1 queue 3948 * defined, enable DROP. 3949 * 3950 * This drops frames rather than hanging the RX MAC for all 3951 * queues. 3952 */ 3953 if ((sc->rx_num_queues > 1) && 3954 (sc->fc == e1000_fc_none || 3955 sc->fc == e1000_fc_rx_pause)) { 3956 srrctl |= E1000_SRRCTL_DROP_EN; 3957 } 3958 /* Setup the Base and Length of the Rx Descriptor Rings */ 3959 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; 3960 i++, que++) { 3961 struct rx_ring *rxr = &que->rxr; 3962 u64 bus_addr = rxr->rx_paddr; 3963 u32 rxdctl; 3964 3965 #ifdef notyet 3966 /* Configure for header split? -- ignore for now */ 3967 rxr->hdr_split = igb_header_split; 3968 #else 3969 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3970 #endif 3971 3972 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3973 scctx->isc_nrxd[0] * 3974 sizeof(struct e1000_rx_desc)); 3975 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3976 (uint32_t)(bus_addr >> 32)); 3977 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3978 (uint32_t)bus_addr); 3979 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3980 /* Enable this Queue */ 3981 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3982 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3983 rxdctl &= 0xFFF00000; 3984 rxdctl |= IGB_RX_PTHRESH; 3985 rxdctl |= IGB_RX_HTHRESH << 8; 3986 rxdctl |= IGB_RX_WTHRESH << 16; 3987 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3988 } 3989 } else if (hw->mac.type >= e1000_pch2lan) { 3990 if (if_getmtu(ifp) > ETHERMTU) 3991 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3992 else 3993 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3994 } 3995 3996 /* Make sure VLAN Filters are off */ 3997 rctl &= ~E1000_RCTL_VFE; 3998 3999 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 4000 if (hw->mac.type < igb_mac_min) { 4001 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 4002 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 4003 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 4004 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 4005 else if (sc->rx_mbuf_sz > 8192) 4006 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 4007 else { 4008 rctl |= E1000_RCTL_SZ_2048; 4009 rctl &= ~E1000_RCTL_BSEX; 4010 } 4011 } else 4012 rctl |= E1000_RCTL_SZ_2048; 4013 4014 /* 4015 * rctl bits 11:10 are as follows 4016 * lem: reserved 4017 * em: DTYPE 4018 * igb: reserved 4019 * and should be 00 on all of the above 4020 */ 4021 rctl &= ~0x00000C00; 4022 4023 /* Write out the settings */ 4024 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4025 4026 return; 4027 } 4028 4029 static void 4030 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 4031 { 4032 struct e1000_softc *sc = iflib_get_softc(ctx); 4033 u32 index, bit; 4034 4035 index = (vtag >> 5) & 0x7F; 4036 bit = vtag & 0x1F; 4037 sc->shadow_vfta[index] |= (1 << bit); 4038 ++sc->num_vlans; 4039 em_if_vlan_filter_write(sc); 4040 } 4041 4042 static void 4043 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 4044 { 4045 struct e1000_softc *sc = iflib_get_softc(ctx); 4046 u32 index, bit; 4047 4048 index = (vtag >> 5) & 0x7F; 4049 bit = vtag & 0x1F; 4050 sc->shadow_vfta[index] &= ~(1 << bit); 4051 --sc->num_vlans; 4052 em_if_vlan_filter_write(sc); 4053 } 4054 4055 static bool 4056 em_if_vlan_filter_capable(if_ctx_t ctx) 4057 { 4058 if_t ifp = iflib_get_ifp(ctx); 4059 4060 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 4061 !em_disable_crc_stripping) 4062 return (true); 4063 4064 return (false); 4065 } 4066 4067 static bool 4068 em_if_vlan_filter_used(if_ctx_t ctx) 4069 { 4070 struct e1000_softc *sc = iflib_get_softc(ctx); 4071 4072 if (!em_if_vlan_filter_capable(ctx)) 4073 return (false); 4074 4075 for (int i = 0; i < EM_VFTA_SIZE; i++) 4076 if (sc->shadow_vfta[i] != 0) 4077 return (true); 4078 4079 return (false); 4080 } 4081 4082 static void 4083 em_if_vlan_filter_enable(struct e1000_softc *sc) 4084 { 4085 struct e1000_hw *hw = &sc->hw; 4086 u32 reg; 4087 4088 reg = E1000_READ_REG(hw, E1000_RCTL); 4089 reg &= ~E1000_RCTL_CFIEN; 4090 reg |= E1000_RCTL_VFE; 4091 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4092 } 4093 4094 static void 4095 em_if_vlan_filter_disable(struct e1000_softc *sc) 4096 { 4097 struct e1000_hw *hw = &sc->hw; 4098 u32 reg; 4099 4100 reg = E1000_READ_REG(hw, E1000_RCTL); 4101 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 4102 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4103 } 4104 4105 static void 4106 em_if_vlan_filter_write(struct e1000_softc *sc) 4107 { 4108 struct e1000_hw *hw = &sc->hw; 4109 4110 if (sc->vf_ifp) 4111 return; 4112 4113 /* Disable interrupts for lem(4) devices during the filter change */ 4114 if (hw->mac.type < em_mac_min) 4115 em_if_intr_disable(sc->ctx); 4116 4117 for (int i = 0; i < EM_VFTA_SIZE; i++) 4118 if (sc->shadow_vfta[i] != 0) { 4119 /* XXXKB: incomplete VF support, we returned above */ 4120 if (sc->vf_ifp) 4121 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], 4122 true); 4123 else 4124 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 4125 } 4126 4127 /* Re-enable interrupts for lem-class devices */ 4128 if (hw->mac.type < em_mac_min) 4129 em_if_intr_enable(sc->ctx); 4130 } 4131 4132 static void 4133 em_setup_vlan_hw_support(if_ctx_t ctx) 4134 { 4135 struct e1000_softc *sc = iflib_get_softc(ctx); 4136 struct e1000_hw *hw = &sc->hw; 4137 if_t ifp = iflib_get_ifp(ctx); 4138 u32 reg; 4139 4140 /* XXXKB: Return early if we are a VF until VF decap and filter 4141 * management is ready and tested. 4142 */ 4143 if (sc->vf_ifp) 4144 return; 4145 4146 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4147 !em_disable_crc_stripping) { 4148 reg = E1000_READ_REG(hw, E1000_CTRL); 4149 reg |= E1000_CTRL_VME; 4150 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4151 } else { 4152 reg = E1000_READ_REG(hw, E1000_CTRL); 4153 reg &= ~E1000_CTRL_VME; 4154 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4155 } 4156 4157 /* If we aren't doing HW filtering, we're done */ 4158 if (!em_if_vlan_filter_capable(ctx)) { 4159 em_if_vlan_filter_disable(sc); 4160 return; 4161 } 4162 4163 /* 4164 * A soft reset zero's out the VFTA, so 4165 * we need to repopulate it now. 4166 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 4167 * traffic through. This will write the entire table. 4168 */ 4169 em_if_vlan_register(ctx, 0); 4170 4171 /* Enable the Filter Table */ 4172 em_if_vlan_filter_enable(sc); 4173 } 4174 4175 static void 4176 em_if_intr_enable(if_ctx_t ctx) 4177 { 4178 struct e1000_softc *sc = iflib_get_softc(ctx); 4179 struct e1000_hw *hw = &sc->hw; 4180 u32 ims_mask = IMS_ENABLE_MASK; 4181 4182 if (sc->intr_type == IFLIB_INTR_MSIX) { 4183 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 4184 ims_mask |= sc->ims; 4185 } 4186 4187 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 4188 E1000_WRITE_FLUSH(hw); 4189 } 4190 4191 static void 4192 em_if_intr_disable(if_ctx_t ctx) 4193 { 4194 struct e1000_softc *sc = iflib_get_softc(ctx); 4195 struct e1000_hw *hw = &sc->hw; 4196 4197 if (sc->intr_type == IFLIB_INTR_MSIX) 4198 E1000_WRITE_REG(hw, EM_EIAC, 0); 4199 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4200 E1000_WRITE_FLUSH(hw); 4201 } 4202 4203 static void 4204 igb_if_intr_enable(if_ctx_t ctx) 4205 { 4206 struct e1000_softc *sc = iflib_get_softc(ctx); 4207 struct e1000_hw *hw = &sc->hw; 4208 u32 mask; 4209 4210 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4211 mask = (sc->que_mask | sc->link_mask); 4212 E1000_WRITE_REG(hw, E1000_EIAC, mask); 4213 E1000_WRITE_REG(hw, E1000_EIAM, mask); 4214 E1000_WRITE_REG(hw, E1000_EIMS, mask); 4215 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 4216 } else 4217 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 4218 E1000_WRITE_FLUSH(hw); 4219 } 4220 4221 static void 4222 igb_if_intr_disable(if_ctx_t ctx) 4223 { 4224 struct e1000_softc *sc = iflib_get_softc(ctx); 4225 struct e1000_hw *hw = &sc->hw; 4226 4227 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4228 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 4229 E1000_WRITE_REG(hw, E1000_EIAC, 0); 4230 } 4231 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4232 E1000_WRITE_FLUSH(hw); 4233 } 4234 4235 /* 4236 * Bit of a misnomer, what this really means is 4237 * to enable OS management of the system... aka 4238 * to disable special hardware management features 4239 */ 4240 static void 4241 em_init_manageability(struct e1000_softc *sc) 4242 { 4243 /* A shared code workaround */ 4244 #define E1000_82542_MANC2H E1000_MANC2H 4245 if (sc->has_manage) { 4246 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 4247 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4248 4249 /* disable hardware interception of ARP */ 4250 manc &= ~(E1000_MANC_ARP_EN); 4251 4252 /* enable receiving management packets to the host */ 4253 manc |= E1000_MANC_EN_MNG2HOST; 4254 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4255 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4256 manc2h |= E1000_MNG2HOST_PORT_623; 4257 manc2h |= E1000_MNG2HOST_PORT_664; 4258 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 4259 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4260 } 4261 } 4262 4263 /* 4264 * Give control back to hardware management 4265 * controller if there is one. 4266 */ 4267 static void 4268 em_release_manageability(struct e1000_softc *sc) 4269 { 4270 if (sc->has_manage) { 4271 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4272 4273 /* re-enable hardware interception of ARP */ 4274 manc |= E1000_MANC_ARP_EN; 4275 manc &= ~E1000_MANC_EN_MNG2HOST; 4276 4277 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4278 } 4279 } 4280 4281 /* 4282 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 4283 * For ASF and Pass Through versions of f/w this means 4284 * that the driver is loaded. For AMT version type f/w 4285 * this means that the network i/f is open. 4286 */ 4287 static void 4288 em_get_hw_control(struct e1000_softc *sc) 4289 { 4290 u32 ctrl_ext, swsm; 4291 4292 if (sc->vf_ifp) 4293 return; 4294 4295 if (sc->hw.mac.type == e1000_82573) { 4296 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4297 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4298 swsm | E1000_SWSM_DRV_LOAD); 4299 return; 4300 } 4301 /* else */ 4302 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4303 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4304 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4305 } 4306 4307 /* 4308 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4309 * For ASF and Pass Through versions of f/w this means that 4310 * the driver is no longer loaded. For AMT versions of the 4311 * f/w this means that the network i/f is closed. 4312 */ 4313 static void 4314 em_release_hw_control(struct e1000_softc *sc) 4315 { 4316 u32 ctrl_ext, swsm; 4317 4318 if (!sc->has_manage) 4319 return; 4320 4321 if (sc->hw.mac.type == e1000_82573) { 4322 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4323 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4324 swsm & ~E1000_SWSM_DRV_LOAD); 4325 return; 4326 } 4327 /* else */ 4328 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4329 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4330 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4331 return; 4332 } 4333 4334 static int 4335 em_is_valid_ether_addr(u8 *addr) 4336 { 4337 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4338 4339 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4340 return (false); 4341 } 4342 4343 return (true); 4344 } 4345 4346 static bool 4347 em_automask_tso(if_ctx_t ctx) 4348 { 4349 struct e1000_softc *sc = iflib_get_softc(ctx); 4350 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 4351 if_t ifp = iflib_get_ifp(ctx); 4352 4353 if (!em_unsupported_tso && sc->link_speed && 4354 sc->link_speed != SPEED_1000 && 4355 scctx->isc_capenable & IFCAP_TSO) { 4356 device_printf(sc->dev, 4357 "Disabling TSO for 10/100 Ethernet.\n"); 4358 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 4359 scctx->isc_capenable &= ~IFCAP_TSO; 4360 if_setcapenablebit(ifp, 0, IFCAP_TSO); 4361 /* iflib_init_locked handles ifnet hwassistbits */ 4362 iflib_request_reset(ctx); 4363 return true; 4364 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 4365 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 4366 scctx->isc_capenable |= sc->tso_automasked; 4367 if_setcapenablebit(ifp, sc->tso_automasked, 0); 4368 sc->tso_automasked = 0; 4369 /* iflib_init_locked handles ifnet hwassistbits */ 4370 iflib_request_reset(ctx); 4371 return true; 4372 } 4373 4374 return false; 4375 } 4376 4377 /* 4378 ** Parse the interface capabilities with regard 4379 ** to both system management and wake-on-lan for 4380 ** later use. 4381 */ 4382 static void 4383 em_get_wakeup(if_ctx_t ctx) 4384 { 4385 struct e1000_softc *sc = iflib_get_softc(ctx); 4386 device_t dev = iflib_get_dev(ctx); 4387 u16 eeprom_data = 0, device_id, apme_mask; 4388 4389 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 4390 apme_mask = EM_EEPROM_APME; 4391 4392 switch (sc->hw.mac.type) { 4393 case e1000_82542: 4394 case e1000_82543: 4395 break; 4396 case e1000_82544: 4397 e1000_read_nvm(&sc->hw, 4398 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 4399 apme_mask = EM_82544_APME; 4400 break; 4401 case e1000_82546: 4402 case e1000_82546_rev_3: 4403 if (sc->hw.bus.func == 1) { 4404 e1000_read_nvm(&sc->hw, 4405 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4406 break; 4407 } else 4408 e1000_read_nvm(&sc->hw, 4409 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4410 break; 4411 case e1000_82573: 4412 case e1000_82583: 4413 sc->has_amt = true; 4414 /* FALLTHROUGH */ 4415 case e1000_82571: 4416 case e1000_82572: 4417 case e1000_80003es2lan: 4418 if (sc->hw.bus.func == 1) { 4419 e1000_read_nvm(&sc->hw, 4420 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4421 break; 4422 } else 4423 e1000_read_nvm(&sc->hw, 4424 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4425 break; 4426 case e1000_ich8lan: 4427 case e1000_ich9lan: 4428 case e1000_ich10lan: 4429 case e1000_pchlan: 4430 case e1000_pch2lan: 4431 case e1000_pch_lpt: 4432 case e1000_pch_spt: 4433 case e1000_82575: /* listing all igb devices */ 4434 case e1000_82576: 4435 case e1000_82580: 4436 case e1000_i350: 4437 case e1000_i354: 4438 case e1000_i210: 4439 case e1000_i211: 4440 case e1000_vfadapt: 4441 case e1000_vfadapt_i350: 4442 apme_mask = E1000_WUC_APME; 4443 sc->has_amt = true; 4444 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4445 break; 4446 default: 4447 e1000_read_nvm(&sc->hw, 4448 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4449 break; 4450 } 4451 if (eeprom_data & apme_mask) 4452 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4453 /* 4454 * We have the eeprom settings, now apply the special cases 4455 * where the eeprom may be wrong or the board won't support 4456 * wake on lan on a particular port 4457 */ 4458 device_id = pci_get_device(dev); 4459 switch (device_id) { 4460 case E1000_DEV_ID_82546GB_PCIE: 4461 sc->wol = 0; 4462 break; 4463 case E1000_DEV_ID_82546EB_FIBER: 4464 case E1000_DEV_ID_82546GB_FIBER: 4465 /* Wake events only supported on port A for dual fiber 4466 * regardless of eeprom setting */ 4467 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4468 E1000_STATUS_FUNC_1) 4469 sc->wol = 0; 4470 break; 4471 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4472 /* if quad port adapter, disable WoL on all but port A */ 4473 if (global_quad_port_a != 0) 4474 sc->wol = 0; 4475 /* Reset for multiple quad port adapters */ 4476 if (++global_quad_port_a == 4) 4477 global_quad_port_a = 0; 4478 break; 4479 case E1000_DEV_ID_82571EB_FIBER: 4480 /* Wake events only supported on port A for dual fiber 4481 * regardless of eeprom setting */ 4482 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4483 E1000_STATUS_FUNC_1) 4484 sc->wol = 0; 4485 break; 4486 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4487 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4488 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4489 /* if quad port adapter, disable WoL on all but port A */ 4490 if (global_quad_port_a != 0) 4491 sc->wol = 0; 4492 /* Reset for multiple quad port adapters */ 4493 if (++global_quad_port_a == 4) 4494 global_quad_port_a = 0; 4495 break; 4496 } 4497 return; 4498 } 4499 4500 4501 /* 4502 * Enable PCI Wake On Lan capability 4503 */ 4504 static void 4505 em_enable_wakeup(if_ctx_t ctx) 4506 { 4507 struct e1000_softc *sc = iflib_get_softc(ctx); 4508 device_t dev = iflib_get_dev(ctx); 4509 if_t ifp = iflib_get_ifp(ctx); 4510 int error = 0; 4511 u32 ctrl, ctrl_ext, rctl; 4512 4513 if (!pci_has_pm(dev)) 4514 return; 4515 4516 /* 4517 * Determine type of Wakeup: note that wol 4518 * is set with all bits on by default. 4519 */ 4520 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4521 sc->wol &= ~E1000_WUFC_MAG; 4522 4523 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4524 sc->wol &= ~E1000_WUFC_EX; 4525 4526 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4527 sc->wol &= ~E1000_WUFC_MC; 4528 else { 4529 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4530 rctl |= E1000_RCTL_MPE; 4531 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4532 } 4533 4534 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4535 goto pme; 4536 4537 /* Advertise the wakeup capability */ 4538 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4539 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4540 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4541 4542 /* Keep the laser running on Fiber adapters */ 4543 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4544 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4545 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4546 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4547 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4548 } 4549 4550 if ((sc->hw.mac.type == e1000_ich8lan) || 4551 (sc->hw.mac.type == e1000_pchlan) || 4552 (sc->hw.mac.type == e1000_ich9lan) || 4553 (sc->hw.mac.type == e1000_ich10lan)) 4554 e1000_suspend_workarounds_ich8lan(&sc->hw); 4555 4556 if ( sc->hw.mac.type >= e1000_pchlan) { 4557 error = em_enable_phy_wakeup(sc); 4558 if (error) 4559 goto pme; 4560 } else { 4561 /* Enable wakeup by the MAC */ 4562 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4563 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4564 } 4565 4566 if (sc->hw.phy.type == e1000_phy_igp_3) 4567 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4568 4569 pme: 4570 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4571 pci_enable_pme(dev); 4572 4573 return; 4574 } 4575 4576 /* 4577 * WOL in the newer chipset interfaces (pchlan) 4578 * require thing to be copied into the phy 4579 */ 4580 static int 4581 em_enable_phy_wakeup(struct e1000_softc *sc) 4582 { 4583 struct e1000_hw *hw = &sc->hw; 4584 u32 mreg, ret = 0; 4585 u16 preg; 4586 4587 /* copy MAC RARs to PHY RARs */ 4588 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4589 4590 /* copy MAC MTA to PHY MTA */ 4591 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4592 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4593 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4594 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4595 (u16)((mreg >> 16) & 0xFFFF)); 4596 } 4597 4598 /* configure PHY Rx Control register */ 4599 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4600 mreg = E1000_READ_REG(hw, E1000_RCTL); 4601 if (mreg & E1000_RCTL_UPE) 4602 preg |= BM_RCTL_UPE; 4603 if (mreg & E1000_RCTL_MPE) 4604 preg |= BM_RCTL_MPE; 4605 preg &= ~(BM_RCTL_MO_MASK); 4606 if (mreg & E1000_RCTL_MO_3) 4607 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4608 << BM_RCTL_MO_SHIFT); 4609 if (mreg & E1000_RCTL_BAM) 4610 preg |= BM_RCTL_BAM; 4611 if (mreg & E1000_RCTL_PMCF) 4612 preg |= BM_RCTL_PMCF; 4613 mreg = E1000_READ_REG(hw, E1000_CTRL); 4614 if (mreg & E1000_CTRL_RFCE) 4615 preg |= BM_RCTL_RFCE; 4616 e1000_write_phy_reg(hw, BM_RCTL, preg); 4617 4618 /* enable PHY wakeup in MAC register */ 4619 E1000_WRITE_REG(hw, E1000_WUC, 4620 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4621 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4622 4623 /* configure and enable PHY wakeup in PHY registers */ 4624 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4625 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4626 4627 /* activate PHY wakeup */ 4628 ret = hw->phy.ops.acquire(hw); 4629 if (ret) { 4630 printf("Could not acquire PHY\n"); 4631 return ret; 4632 } 4633 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4634 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4635 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4636 if (ret) { 4637 printf("Could not read PHY page 769\n"); 4638 goto out; 4639 } 4640 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4641 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4642 if (ret) 4643 printf("Could not set PHY Host Wakeup bit\n"); 4644 out: 4645 hw->phy.ops.release(hw); 4646 4647 return ret; 4648 } 4649 4650 static void 4651 em_if_led_func(if_ctx_t ctx, int onoff) 4652 { 4653 struct e1000_softc *sc = iflib_get_softc(ctx); 4654 4655 if (onoff) { 4656 e1000_setup_led(&sc->hw); 4657 e1000_led_on(&sc->hw); 4658 } else { 4659 e1000_led_off(&sc->hw); 4660 e1000_cleanup_led(&sc->hw); 4661 } 4662 } 4663 4664 /* 4665 * Disable the L0S and L1 LINK states 4666 */ 4667 static void 4668 em_disable_aspm(struct e1000_softc *sc) 4669 { 4670 int base, reg; 4671 u16 link_cap,link_ctrl; 4672 device_t dev = sc->dev; 4673 4674 switch (sc->hw.mac.type) { 4675 case e1000_82573: 4676 case e1000_82574: 4677 case e1000_82583: 4678 break; 4679 default: 4680 return; 4681 } 4682 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4683 return; 4684 reg = base + PCIER_LINK_CAP; 4685 link_cap = pci_read_config(dev, reg, 2); 4686 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4687 return; 4688 reg = base + PCIER_LINK_CTL; 4689 link_ctrl = pci_read_config(dev, reg, 2); 4690 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4691 pci_write_config(dev, reg, link_ctrl, 2); 4692 return; 4693 } 4694 4695 /********************************************************************** 4696 * 4697 * Update the board statistics counters. 4698 * 4699 **********************************************************************/ 4700 static void 4701 em_update_stats_counters(struct e1000_softc *sc) 4702 { 4703 u64 prev_xoffrxc = sc->stats.xoffrxc; 4704 4705 if(sc->hw.phy.media_type == e1000_media_type_copper || 4706 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4707 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4708 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4709 } 4710 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4711 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4712 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4713 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4714 4715 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4716 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4717 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4718 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4719 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4720 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4721 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4722 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4723 /* 4724 ** For watchdog management we need to know if we have been 4725 ** paused during the last interval, so capture that here. 4726 */ 4727 if (sc->stats.xoffrxc != prev_xoffrxc) 4728 sc->shared->isc_pause_frames = 1; 4729 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4730 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4731 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4732 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4733 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4734 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4735 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4736 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4737 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4738 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4739 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4740 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4741 4742 /* For the 64-bit byte counters the low dword must be read first. */ 4743 /* Both registers clear on the read of the high dword */ 4744 4745 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4746 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4747 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4748 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4749 4750 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4751 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4752 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4753 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4754 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4755 4756 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4757 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4758 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4759 4760 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4761 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4762 4763 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4764 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4765 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4766 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4767 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4768 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4769 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4770 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4771 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4772 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4773 4774 /* Interrupt Counts */ 4775 4776 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4777 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4778 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4779 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4780 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4781 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4782 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4783 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4784 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4785 4786 if (sc->hw.mac.type >= e1000_82543) { 4787 sc->stats.algnerrc += 4788 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4789 sc->stats.rxerrc += 4790 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4791 sc->stats.tncrs += 4792 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4793 sc->stats.cexterr += 4794 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4795 sc->stats.tsctc += 4796 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4797 sc->stats.tsctfc += 4798 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4799 } 4800 } 4801 4802 static uint64_t 4803 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4804 { 4805 struct e1000_softc *sc = iflib_get_softc(ctx); 4806 if_t ifp = iflib_get_ifp(ctx); 4807 4808 switch (cnt) { 4809 case IFCOUNTER_COLLISIONS: 4810 return (sc->stats.colc); 4811 case IFCOUNTER_IERRORS: 4812 return (sc->dropped_pkts + sc->stats.rxerrc + 4813 sc->stats.crcerrs + sc->stats.algnerrc + 4814 sc->stats.ruc + sc->stats.roc + 4815 sc->stats.mpc + sc->stats.cexterr); 4816 case IFCOUNTER_OERRORS: 4817 return (sc->stats.ecol + sc->stats.latecol + 4818 sc->watchdog_events); 4819 default: 4820 return (if_get_counter_default(ifp, cnt)); 4821 } 4822 } 4823 4824 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4825 * @ctx: iflib context 4826 * @event: event code to check 4827 * 4828 * Defaults to returning false for unknown events. 4829 * 4830 * @returns true if iflib needs to reinit the interface 4831 */ 4832 static bool 4833 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4834 { 4835 switch (event) { 4836 case IFLIB_RESTART_VLAN_CONFIG: 4837 default: 4838 return (false); 4839 } 4840 } 4841 4842 /* Export a single 32-bit register via a read-only sysctl. */ 4843 static int 4844 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4845 { 4846 struct e1000_softc *sc; 4847 u_int val; 4848 4849 sc = oidp->oid_arg1; 4850 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4851 return (sysctl_handle_int(oidp, &val, 0, req)); 4852 } 4853 4854 /* Per queue holdoff interrupt rate handler */ 4855 static int 4856 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 4857 { 4858 struct em_rx_queue *rque; 4859 struct em_tx_queue *tque; 4860 struct e1000_hw *hw; 4861 int error; 4862 u32 reg, usec, rate; 4863 4864 bool tx = oidp->oid_arg2; 4865 4866 if (tx) { 4867 tque = oidp->oid_arg1; 4868 hw = &tque->sc->hw; 4869 if (hw->mac.type >= igb_mac_min) 4870 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); 4871 else if (hw->mac.type == e1000_82574 && tque->msix) 4872 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); 4873 else 4874 reg = E1000_READ_REG(hw, E1000_ITR); 4875 } else { 4876 rque = oidp->oid_arg1; 4877 hw = &rque->sc->hw; 4878 if (hw->mac.type >= igb_mac_min) 4879 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); 4880 else if (hw->mac.type == e1000_82574 && rque->msix) 4881 reg = E1000_READ_REG(hw, 4882 E1000_EITR_82574(rque->msix)); 4883 else 4884 reg = E1000_READ_REG(hw, E1000_ITR); 4885 } 4886 4887 if (hw->mac.type < igb_mac_min) { 4888 if (reg > 0) 4889 rate = EM_INTS_TO_ITR(reg); 4890 else 4891 rate = 0; 4892 } else { 4893 usec = (reg & IGB_QVECTOR_MASK); 4894 if (usec > 0) 4895 rate = IGB_INTS_TO_EITR(usec); 4896 else 4897 rate = 0; 4898 } 4899 4900 error = sysctl_handle_int(oidp, &rate, 0, req); 4901 if (error || !req->newptr) 4902 return error; 4903 return 0; 4904 } 4905 4906 /* 4907 * Add sysctl variables, one per statistic, to the system. 4908 */ 4909 static void 4910 em_add_hw_stats(struct e1000_softc *sc) 4911 { 4912 device_t dev = iflib_get_dev(sc->ctx); 4913 struct em_tx_queue *tx_que = sc->tx_queues; 4914 struct em_rx_queue *rx_que = sc->rx_queues; 4915 4916 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4917 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4918 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4919 struct e1000_hw_stats *stats = &sc->stats; 4920 4921 struct sysctl_oid *stat_node, *queue_node, *int_node; 4922 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4923 4924 #define QUEUE_NAME_LEN 32 4925 char namebuf[QUEUE_NAME_LEN]; 4926 4927 /* Driver Statistics */ 4928 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4929 CTLFLAG_RD, &sc->dropped_pkts, 4930 "Driver dropped packets"); 4931 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4932 CTLFLAG_RD, &sc->link_irq, 4933 "Link MSI-X IRQ Handled"); 4934 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4935 CTLFLAG_RD, &sc->rx_overruns, 4936 "RX overruns"); 4937 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4938 CTLFLAG_RD, &sc->watchdog_events, 4939 "Watchdog timeouts"); 4940 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4941 CTLTYPE_UINT | CTLFLAG_RD, 4942 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4943 "Device Control Register"); 4944 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4945 CTLTYPE_UINT | CTLFLAG_RD, 4946 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4947 "Receiver Control Register"); 4948 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4949 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4950 "Flow Control High Watermark"); 4951 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4952 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4953 "Flow Control Low Watermark"); 4954 4955 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4956 struct tx_ring *txr = &tx_que->txr; 4957 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4958 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4959 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4960 queue_list = SYSCTL_CHILDREN(queue_node); 4961 4962 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4963 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 4964 true, em_sysctl_interrupt_rate_handler, 4965 "IU", "Interrupt Rate"); 4966 4967 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4968 CTLTYPE_UINT | CTLFLAG_RD, sc, 4969 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4970 "Transmit Descriptor Head"); 4971 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4972 CTLTYPE_UINT | CTLFLAG_RD, sc, 4973 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4974 "Transmit Descriptor Tail"); 4975 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4976 CTLFLAG_RD, &txr->tx_irq, 4977 "Queue MSI-X Transmit Interrupts"); 4978 } 4979 4980 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4981 struct rx_ring *rxr = &rx_que->rxr; 4982 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4983 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4984 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4985 queue_list = SYSCTL_CHILDREN(queue_node); 4986 4987 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4988 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 4989 false, em_sysctl_interrupt_rate_handler, 4990 "IU", "Interrupt Rate"); 4991 4992 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4993 CTLTYPE_UINT | CTLFLAG_RD, sc, 4994 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4995 "Receive Descriptor Head"); 4996 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4997 CTLTYPE_UINT | CTLFLAG_RD, sc, 4998 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4999 "Receive Descriptor Tail"); 5000 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 5001 CTLFLAG_RD, &rxr->rx_irq, 5002 "Queue MSI-X Receive Interrupts"); 5003 } 5004 5005 /* MAC stats get their own sub node */ 5006 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 5007 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 5008 stat_list = SYSCTL_CHILDREN(stat_node); 5009 5010 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 5011 CTLFLAG_RD, &stats->ecol, 5012 "Excessive collisions"); 5013 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 5014 CTLFLAG_RD, &stats->scc, 5015 "Single collisions"); 5016 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 5017 CTLFLAG_RD, &stats->mcc, 5018 "Multiple collisions"); 5019 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 5020 CTLFLAG_RD, &stats->latecol, 5021 "Late collisions"); 5022 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 5023 CTLFLAG_RD, &stats->colc, 5024 "Collision Count"); 5025 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 5026 CTLFLAG_RD, &sc->stats.symerrs, 5027 "Symbol Errors"); 5028 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 5029 CTLFLAG_RD, &sc->stats.sec, 5030 "Sequence Errors"); 5031 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 5032 CTLFLAG_RD, &sc->stats.dc, 5033 "Defer Count"); 5034 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 5035 CTLFLAG_RD, &sc->stats.mpc, 5036 "Missed Packets"); 5037 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 5038 CTLFLAG_RD, &sc->stats.rlec, 5039 "Receive Length Errors"); 5040 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 5041 CTLFLAG_RD, &sc->stats.rnbc, 5042 "Receive No Buffers"); 5043 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 5044 CTLFLAG_RD, &sc->stats.ruc, 5045 "Receive Undersize"); 5046 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 5047 CTLFLAG_RD, &sc->stats.rfc, 5048 "Fragmented Packets Received "); 5049 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 5050 CTLFLAG_RD, &sc->stats.roc, 5051 "Oversized Packets Received"); 5052 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 5053 CTLFLAG_RD, &sc->stats.rjc, 5054 "Recevied Jabber"); 5055 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 5056 CTLFLAG_RD, &sc->stats.rxerrc, 5057 "Receive Errors"); 5058 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 5059 CTLFLAG_RD, &sc->stats.crcerrs, 5060 "CRC errors"); 5061 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 5062 CTLFLAG_RD, &sc->stats.algnerrc, 5063 "Alignment Errors"); 5064 /* On 82575 these are collision counts */ 5065 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 5066 CTLFLAG_RD, &sc->stats.cexterr, 5067 "Collision/Carrier extension errors"); 5068 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 5069 CTLFLAG_RD, &sc->stats.xonrxc, 5070 "XON Received"); 5071 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 5072 CTLFLAG_RD, &sc->stats.xontxc, 5073 "XON Transmitted"); 5074 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 5075 CTLFLAG_RD, &sc->stats.xoffrxc, 5076 "XOFF Received"); 5077 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 5078 CTLFLAG_RD, &sc->stats.xofftxc, 5079 "XOFF Transmitted"); 5080 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 5081 CTLFLAG_RD, &sc->stats.fcruc, 5082 "Unsupported Flow Control Received"); 5083 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 5084 CTLFLAG_RD, &sc->stats.mgprc, 5085 "Management Packets Received"); 5086 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 5087 CTLFLAG_RD, &sc->stats.mgpdc, 5088 "Management Packets Dropped"); 5089 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 5090 CTLFLAG_RD, &sc->stats.mgptc, 5091 "Management Packets Transmitted"); 5092 5093 /* Packet Reception Stats */ 5094 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 5095 CTLFLAG_RD, &sc->stats.tpr, 5096 "Total Packets Received "); 5097 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5098 CTLFLAG_RD, &sc->stats.gprc, 5099 "Good Packets Received"); 5100 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 5101 CTLFLAG_RD, &sc->stats.bprc, 5102 "Broadcast Packets Received"); 5103 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5104 CTLFLAG_RD, &sc->stats.mprc, 5105 "Multicast Packets Received"); 5106 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 5107 CTLFLAG_RD, &sc->stats.prc64, 5108 "64 byte frames received "); 5109 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 5110 CTLFLAG_RD, &sc->stats.prc127, 5111 "65-127 byte frames received"); 5112 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 5113 CTLFLAG_RD, &sc->stats.prc255, 5114 "128-255 byte frames received"); 5115 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 5116 CTLFLAG_RD, &sc->stats.prc511, 5117 "256-511 byte frames received"); 5118 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 5119 CTLFLAG_RD, &sc->stats.prc1023, 5120 "512-1023 byte frames received"); 5121 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 5122 CTLFLAG_RD, &sc->stats.prc1522, 5123 "1023-1522 byte frames received"); 5124 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5125 CTLFLAG_RD, &sc->stats.gorc, 5126 "Good Octets Received"); 5127 5128 /* Packet Transmission Stats */ 5129 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5130 CTLFLAG_RD, &sc->stats.gotc, 5131 "Good Octets Transmitted"); 5132 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 5133 CTLFLAG_RD, &sc->stats.tpt, 5134 "Total Packets Transmitted"); 5135 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5136 CTLFLAG_RD, &sc->stats.gptc, 5137 "Good Packets Transmitted"); 5138 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 5139 CTLFLAG_RD, &sc->stats.bptc, 5140 "Broadcast Packets Transmitted"); 5141 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 5142 CTLFLAG_RD, &sc->stats.mptc, 5143 "Multicast Packets Transmitted"); 5144 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 5145 CTLFLAG_RD, &sc->stats.ptc64, 5146 "64 byte frames transmitted "); 5147 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 5148 CTLFLAG_RD, &sc->stats.ptc127, 5149 "65-127 byte frames transmitted"); 5150 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 5151 CTLFLAG_RD, &sc->stats.ptc255, 5152 "128-255 byte frames transmitted"); 5153 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 5154 CTLFLAG_RD, &sc->stats.ptc511, 5155 "256-511 byte frames transmitted"); 5156 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 5157 CTLFLAG_RD, &sc->stats.ptc1023, 5158 "512-1023 byte frames transmitted"); 5159 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 5160 CTLFLAG_RD, &sc->stats.ptc1522, 5161 "1024-1522 byte frames transmitted"); 5162 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 5163 CTLFLAG_RD, &sc->stats.tsctc, 5164 "TSO Contexts Transmitted"); 5165 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 5166 CTLFLAG_RD, &sc->stats.tsctfc, 5167 "TSO Contexts Failed"); 5168 5169 /* Interrupt Stats */ 5170 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 5171 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 5172 int_list = SYSCTL_CHILDREN(int_node); 5173 5174 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 5175 CTLFLAG_RD, &sc->stats.iac, 5176 "Interrupt Assertion Count"); 5177 5178 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 5179 CTLFLAG_RD, &sc->stats.icrxptc, 5180 "Interrupt Cause Rx Pkt Timer Expire Count"); 5181 5182 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 5183 CTLFLAG_RD, &sc->stats.icrxatc, 5184 "Interrupt Cause Rx Abs Timer Expire Count"); 5185 5186 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 5187 CTLFLAG_RD, &sc->stats.ictxptc, 5188 "Interrupt Cause Tx Pkt Timer Expire Count"); 5189 5190 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 5191 CTLFLAG_RD, &sc->stats.ictxatc, 5192 "Interrupt Cause Tx Abs Timer Expire Count"); 5193 5194 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 5195 CTLFLAG_RD, &sc->stats.ictxqec, 5196 "Interrupt Cause Tx Queue Empty Count"); 5197 5198 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 5199 CTLFLAG_RD, &sc->stats.ictxqmtc, 5200 "Interrupt Cause Tx Queue Min Thresh Count"); 5201 5202 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 5203 CTLFLAG_RD, &sc->stats.icrxdmtc, 5204 "Interrupt Cause Rx Desc Min Thresh Count"); 5205 5206 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 5207 CTLFLAG_RD, &sc->stats.icrxoc, 5208 "Interrupt Cause Receiver Overrun Count"); 5209 } 5210 5211 static void 5212 em_fw_version_locked(if_ctx_t ctx) 5213 { 5214 struct e1000_softc *sc = iflib_get_softc(ctx); 5215 struct e1000_hw *hw = &sc->hw; 5216 struct e1000_fw_version *fw_ver = &sc->fw_ver; 5217 uint16_t eep = 0; 5218 5219 /* 5220 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet 5221 * the NVM locking model, so we do it in em_if_attach_pre() and store 5222 * the info in the softc 5223 */ 5224 ASSERT_CTX_LOCK_HELD(hw); 5225 5226 *fw_ver = (struct e1000_fw_version){0}; 5227 5228 if (hw->mac.type >= igb_mac_min) { 5229 /* 5230 * Use the Shared Code for igb(4) 5231 */ 5232 e1000_get_fw_version(hw, fw_ver); 5233 } else { 5234 /* 5235 * Otherwise, EEPROM version should be present on (almost?) 5236 * all devices here 5237 */ 5238 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 5239 INIT_DEBUGOUT("can't get EEPROM version"); 5240 return; 5241 } 5242 5243 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 5244 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 5245 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 5246 } 5247 } 5248 5249 static void 5250 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 5251 { 5252 const char *space = ""; 5253 5254 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 5255 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 5256 fw_ver->eep_minor, fw_ver->eep_build); 5257 space = " "; 5258 } 5259 5260 if (fw_ver->invm_major || fw_ver->invm_minor || 5261 fw_ver->invm_img_type) { 5262 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 5263 space, fw_ver->invm_major, fw_ver->invm_minor, 5264 fw_ver->invm_img_type); 5265 space = " "; 5266 } 5267 5268 if (fw_ver->or_valid) { 5269 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 5270 space, fw_ver->or_major, fw_ver->or_build, 5271 fw_ver->or_patch); 5272 space = " "; 5273 } 5274 5275 if (fw_ver->etrack_id) 5276 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 5277 } 5278 5279 static void 5280 em_print_fw_version(struct e1000_softc *sc ) 5281 { 5282 device_t dev = sc->dev; 5283 struct sbuf *buf; 5284 int error = 0; 5285 5286 buf = sbuf_new_auto(); 5287 if (!buf) { 5288 device_printf(dev, "Could not allocate sbuf for output.\n"); 5289 return; 5290 } 5291 5292 em_sbuf_fw_version(&sc->fw_ver, buf); 5293 5294 error = sbuf_finish(buf); 5295 if (error) 5296 device_printf(dev, "Error finishing sbuf: %d\n", error); 5297 else if (sbuf_len(buf)) 5298 device_printf(dev, "%s\n", sbuf_data(buf)); 5299 5300 sbuf_delete(buf); 5301 } 5302 5303 static int 5304 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 5305 { 5306 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5307 device_t dev = sc->dev; 5308 struct sbuf *buf; 5309 int error = 0; 5310 5311 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5312 if (!buf) { 5313 device_printf(dev, "Could not allocate sbuf for output.\n"); 5314 return (ENOMEM); 5315 } 5316 5317 em_sbuf_fw_version(&sc->fw_ver, buf); 5318 5319 error = sbuf_finish(buf); 5320 if (error) 5321 device_printf(dev, "Error finishing sbuf: %d\n", error); 5322 5323 sbuf_delete(buf); 5324 5325 return (0); 5326 } 5327 5328 /********************************************************************** 5329 * 5330 * This routine provides a way to dump out the adapter eeprom, 5331 * often a useful debug/service tool. This only dumps the first 5332 * 32 words, stuff that matters is in that extent. 5333 * 5334 **********************************************************************/ 5335 static int 5336 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 5337 { 5338 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5339 int error; 5340 int result; 5341 5342 result = -1; 5343 error = sysctl_handle_int(oidp, &result, 0, req); 5344 5345 if (error || !req->newptr) 5346 return (error); 5347 5348 /* 5349 * This value will cause a hex dump of the 5350 * first 32 16-bit words of the EEPROM to 5351 * the screen. 5352 */ 5353 if (result == 1) 5354 em_print_nvm_info(sc); 5355 5356 return (error); 5357 } 5358 5359 static void 5360 em_print_nvm_info(struct e1000_softc *sc) 5361 { 5362 struct e1000_hw *hw = &sc->hw; 5363 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 5364 u16 eeprom_data; 5365 int i, j, row = 0; 5366 5367 /* Its a bit crude, but it gets the job done */ 5368 printf("\nInterface EEPROM Dump:\n"); 5369 printf("Offset\n0x0000 "); 5370 5371 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 5372 sx_xlock(iflib_ctx_lock); 5373 ASSERT_CTX_LOCK_HELD(hw); 5374 for (i = 0, j = 0; i < 32; i++, j++) { 5375 if (j == 8) { /* Make the offset block */ 5376 j = 0; ++row; 5377 printf("\n0x00%x0 ",row); 5378 } 5379 e1000_read_nvm(hw, i, 1, &eeprom_data); 5380 printf("%04x ", eeprom_data); 5381 } 5382 sx_xunlock(iflib_ctx_lock); 5383 printf("\n"); 5384 } 5385 5386 static int 5387 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5388 { 5389 struct em_int_delay_info *info; 5390 struct e1000_softc *sc; 5391 u32 regval; 5392 int error, usecs, ticks; 5393 5394 info = (struct em_int_delay_info *) arg1; 5395 usecs = info->value; 5396 error = sysctl_handle_int(oidp, &usecs, 0, req); 5397 if (error != 0 || req->newptr == NULL) 5398 return (error); 5399 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5400 return (EINVAL); 5401 info->value = usecs; 5402 ticks = EM_USECS_TO_TICKS(usecs); 5403 5404 sc = info->sc; 5405 5406 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 5407 regval = (regval & ~0xffff) | (ticks & 0xffff); 5408 /* Handle a few special cases. */ 5409 switch (info->offset) { 5410 case E1000_RDTR: 5411 break; 5412 case E1000_TIDV: 5413 if (ticks == 0) { 5414 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 5415 /* Don't write 0 into the TIDV register. */ 5416 regval++; 5417 } else 5418 sc->txd_cmd |= E1000_TXD_CMD_IDE; 5419 break; 5420 } 5421 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 5422 return (0); 5423 } 5424 5425 static int 5426 em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 5427 { 5428 struct e1000_softc *sc; 5429 u32 reg, val, shift; 5430 int error, mask; 5431 5432 sc = oidp->oid_arg1; 5433 switch (oidp->oid_arg2) { 5434 case 0: 5435 reg = E1000_DTXTCPFLGL; 5436 shift = 0; 5437 break; 5438 case 1: 5439 reg = E1000_DTXTCPFLGL; 5440 shift = 16; 5441 break; 5442 case 2: 5443 reg = E1000_DTXTCPFLGH; 5444 shift = 0; 5445 break; 5446 default: 5447 return (EINVAL); 5448 break; 5449 } 5450 val = E1000_READ_REG(&sc->hw, reg); 5451 mask = (val >> shift) & 0xfff; 5452 error = sysctl_handle_int(oidp, &mask, 0, req); 5453 if (error != 0 || req->newptr == NULL) 5454 return (error); 5455 if (mask < 0 || mask > 0xfff) 5456 return (EINVAL); 5457 val = (val & ~(0xfff << shift)) | (mask << shift); 5458 E1000_WRITE_REG(&sc->hw, reg, val); 5459 return (0); 5460 } 5461 5462 static void 5463 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 5464 const char *description, struct em_int_delay_info *info, int offset, 5465 int value) 5466 { 5467 info->sc = sc; 5468 info->offset = offset; 5469 info->value = value; 5470 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5471 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 5472 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 5473 info, 0, em_sysctl_int_delay, "I", description); 5474 } 5475 5476 /* 5477 * Set flow control using sysctl: 5478 * Flow control values: 5479 * 0 - off 5480 * 1 - rx pause 5481 * 2 - tx pause 5482 * 3 - full 5483 */ 5484 static int 5485 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 5486 { 5487 int error; 5488 static int input = 3; /* default is full */ 5489 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5490 5491 error = sysctl_handle_int(oidp, &input, 0, req); 5492 5493 if ((error) || (req->newptr == NULL)) 5494 return (error); 5495 5496 if (input == sc->fc) /* no change? */ 5497 return (error); 5498 5499 switch (input) { 5500 case e1000_fc_rx_pause: 5501 case e1000_fc_tx_pause: 5502 case e1000_fc_full: 5503 case e1000_fc_none: 5504 sc->hw.fc.requested_mode = input; 5505 sc->fc = input; 5506 break; 5507 default: 5508 /* Do nothing */ 5509 return (error); 5510 } 5511 5512 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 5513 e1000_force_mac_fc(&sc->hw); 5514 return (error); 5515 } 5516 5517 /* 5518 * Manage DMA Coalesce: 5519 * Control values: 5520 * 0/1 - off/on 5521 * Legal timer values are: 5522 * 250,500,1000-10000 in thousands 5523 */ 5524 static int 5525 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5526 { 5527 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5528 int error; 5529 5530 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 5531 5532 if ((error) || (req->newptr == NULL)) 5533 return (error); 5534 5535 switch (sc->dmac) { 5536 case 0: 5537 /* Disabling */ 5538 break; 5539 case 1: /* Just enable and use default */ 5540 sc->dmac = 1000; 5541 break; 5542 case 250: 5543 case 500: 5544 case 1000: 5545 case 2000: 5546 case 3000: 5547 case 4000: 5548 case 5000: 5549 case 6000: 5550 case 7000: 5551 case 8000: 5552 case 9000: 5553 case 10000: 5554 /* Legal values - allow */ 5555 break; 5556 default: 5557 /* Do nothing, illegal value */ 5558 sc->dmac = 0; 5559 return (EINVAL); 5560 } 5561 /* Reinit the interface */ 5562 em_if_init(sc->ctx); 5563 return (error); 5564 } 5565 5566 /* 5567 * Manage Energy Efficient Ethernet: 5568 * Control values: 5569 * 0/1 - enabled/disabled 5570 */ 5571 static int 5572 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5573 { 5574 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5575 int error, value; 5576 5577 if (sc->hw.mac.type < igb_mac_min) 5578 value = sc->hw.dev_spec.ich8lan.eee_disable; 5579 else 5580 value = sc->hw.dev_spec._82575.eee_disable; 5581 error = sysctl_handle_int(oidp, &value, 0, req); 5582 if (error || req->newptr == NULL) 5583 return (error); 5584 if (sc->hw.mac.type < igb_mac_min) 5585 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5586 else 5587 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5588 em_if_init(sc->ctx); 5589 5590 return (0); 5591 } 5592 5593 static int 5594 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5595 { 5596 struct e1000_softc *sc; 5597 int error; 5598 int result; 5599 5600 result = -1; 5601 error = sysctl_handle_int(oidp, &result, 0, req); 5602 5603 if (error || !req->newptr) 5604 return (error); 5605 5606 if (result == 1) { 5607 sc = (struct e1000_softc *) arg1; 5608 em_print_debug_info(sc); 5609 } 5610 5611 return (error); 5612 } 5613 5614 static int 5615 em_get_rs(SYSCTL_HANDLER_ARGS) 5616 { 5617 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5618 int error; 5619 int result; 5620 5621 result = 0; 5622 error = sysctl_handle_int(oidp, &result, 0, req); 5623 5624 if (error || !req->newptr || result != 1) 5625 return (error); 5626 em_dump_rs(sc); 5627 5628 return (error); 5629 } 5630 5631 static void 5632 em_if_debug(if_ctx_t ctx) 5633 { 5634 em_dump_rs(iflib_get_softc(ctx)); 5635 } 5636 5637 /* 5638 * This routine is meant to be fluid, add whatever is 5639 * needed for debugging a problem. -jfv 5640 */ 5641 static void 5642 em_print_debug_info(struct e1000_softc *sc) 5643 { 5644 device_t dev = iflib_get_dev(sc->ctx); 5645 if_t ifp = iflib_get_ifp(sc->ctx); 5646 struct tx_ring *txr = &sc->tx_queues->txr; 5647 struct rx_ring *rxr = &sc->rx_queues->rxr; 5648 5649 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5650 printf("Interface is RUNNING "); 5651 else 5652 printf("Interface is NOT RUNNING\n"); 5653 5654 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5655 printf("and INACTIVE\n"); 5656 else 5657 printf("and ACTIVE\n"); 5658 5659 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5660 device_printf(dev, "TX Queue %d ------\n", i); 5661 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5662 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5663 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5664 5665 } 5666 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5667 device_printf(dev, "RX Queue %d ------\n", j); 5668 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5669 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5670 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5671 } 5672 } 5673 5674 /* 5675 * 82574 only: 5676 * Write a new value to the EEPROM increasing the number of MSI-X 5677 * vectors from 3 to 5, for proper multiqueue support. 5678 */ 5679 static void 5680 em_enable_vectors_82574(if_ctx_t ctx) 5681 { 5682 struct e1000_softc *sc = iflib_get_softc(ctx); 5683 struct e1000_hw *hw = &sc->hw; 5684 device_t dev = iflib_get_dev(ctx); 5685 u16 edata; 5686 5687 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5688 if (bootverbose) 5689 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5690 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5691 device_printf(dev, "Writing to eeprom: increasing " 5692 "reported MSI-X vectors from 3 to 5...\n"); 5693 edata &= ~(EM_NVM_MSIX_N_MASK); 5694 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5695 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5696 e1000_update_nvm_checksum(hw); 5697 device_printf(dev, "Writing to eeprom: done\n"); 5698 } 5699 } 5700