1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static const pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, 57 "Intel(R) Legacy PRO/1000 MT 82540EM"), 58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, 59 "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP, 61 "Intel(R) Legacy PRO/1000 MT 82540EP"), 62 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, 63 "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 64 PVID(0x8086, E1000_DEV_ID_82540EP_LP, 65 "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 66 67 PVID(0x8086, E1000_DEV_ID_82541EI, 68 "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 69 PVID(0x8086, E1000_DEV_ID_82541ER, 70 "Intel(R) Legacy PRO/1000 82541ER"), 71 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, 72 "Intel(R) Legacy PRO/1000 MT 82541ER"), 73 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, 74 "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 75 PVID(0x8086, E1000_DEV_ID_82541GI, 76 "Intel(R) Legacy PRO/1000 MT 82541GI"), 77 PVID(0x8086, E1000_DEV_ID_82541GI_LF, 78 "Intel(R) Legacy PRO/1000 GT 82541PI"), 79 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, 80 "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 81 82 PVID(0x8086, E1000_DEV_ID_82542, 83 "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 84 85 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, 86 "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, 88 "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 89 90 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, 91 "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 92 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, 93 "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 94 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, 95 "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 96 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, 97 "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 98 99 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, 100 "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, 102 "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, 104 "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 105 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, 106 "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 107 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, 108 "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 109 110 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, 111 "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, 113 "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 114 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, 115 "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 116 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, 117 "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, 119 "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 120 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, 121 "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, 123 "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 124 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, 125 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 126 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 127 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 128 129 PVID(0x8086, E1000_DEV_ID_82547EI, 130 "Intel(R) Legacy PRO/1000 CT 82547EI"), 131 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, 132 "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 133 PVID(0x8086, E1000_DEV_ID_82547GI, 134 "Intel(R) Legacy PRO/1000 CT 82547GI"), 135 136 /* Intel(R) - em-class devices */ 137 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, 138 "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 139 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, 140 "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 141 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, 142 "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 143 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, 144 "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 145 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, 146 "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 147 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 148 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 149 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 150 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 151 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 152 "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 153 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 154 "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 155 PVID(0x8086, E1000_DEV_ID_82572EI, 156 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 157 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, 158 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 159 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, 160 "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 161 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, 162 "Intel(R) PRO/1000 82572EI (SERDES)"), 163 PVID(0x8086, E1000_DEV_ID_82573E, 164 "Intel(R) PRO/1000 82573E (Copper)"), 165 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, 166 "Intel(R) PRO/1000 82573E AMT (Copper)"), 167 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 168 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 169 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 170 "Intel(R) 80003ES2LAN (Copper)"), 171 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 172 "Intel(R) 80003ES2LAN (SERDES)"), 173 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 174 "Intel(R) 80003ES2LAN (Dual Copper)"), 175 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 176 "Intel(R) 80003ES2LAN (Dual SERDES)"), 177 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, 178 "Intel(R) 82566MM ICH8 AMT (Mobile)"), 179 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 180 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 181 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 182 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 183 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 184 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 186 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, 187 "Intel(R) 82567LM ICH9 AMT"), 188 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, 189 "Intel(R) 82566DM-2 ICH9 AMT"), 190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 192 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 197 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 205 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 206 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 207 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 208 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 209 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 210 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 213 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, 214 "Intel(R) I218-LM LPTLP"), 215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 222 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, 223 "Intel(R) I219-LM SPT-H(2)"), 224 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, 225 "Intel(R) I219-V SPT-H(2)"), 226 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, 227 "Intel(R) I219-LM LBG(3)"), 228 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, 229 "Intel(R) I219-LM SPT(4)"), 230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 231 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, 232 "Intel(R) I219-LM SPT(5)"), 233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 234 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, 235 "Intel(R) I219-LM CNP(6)"), 236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 237 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, 238 "Intel(R) I219-LM CNP(7)"), 239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 240 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, 241 "Intel(R) I219-LM ICP(8)"), 242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 243 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, 244 "Intel(R) I219-LM ICP(9)"), 245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 246 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, 247 "Intel(R) I219-LM CMP(10)"), 248 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, 249 "Intel(R) I219-V CMP(10)"), 250 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, 251 "Intel(R) I219-LM CMP(11)"), 252 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, 253 "Intel(R) I219-V CMP(11)"), 254 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, 255 "Intel(R) I219-LM CMP(12)"), 256 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, 257 "Intel(R) I219-V CMP(12)"), 258 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, 259 "Intel(R) I219-LM TGP(13)"), 260 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, 261 "Intel(R) I219-V TGP(13)"), 262 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, 263 "Intel(R) I219-LM TGP(14)"), 264 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, 265 "Intel(R) I219-V GTP(14)"), 266 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, 267 "Intel(R) I219-LM TGP(15)"), 268 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, 269 "Intel(R) I219-V TGP(15)"), 270 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, 271 "Intel(R) I219-LM ADL(16)"), 272 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, 273 "Intel(R) I219-V ADL(16)"), 274 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, 275 "Intel(R) I219-LM ADL(17)"), 276 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, 277 "Intel(R) I219-V ADL(17)"), 278 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, 279 "Intel(R) I219-LM MTP(18)"), 280 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, 281 "Intel(R) I219-V MTP(18)"), 282 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19, 283 "Intel(R) I219-LM ADL(19)"), 284 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19, 285 "Intel(R) I219-V ADL(19)"), 286 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, 287 "Intel(R) I219-LM LNL(20)"), 288 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, 289 "Intel(R) I219-V LNL(20)"), 290 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, 291 "Intel(R) I219-LM LNL(21)"), 292 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, 293 "Intel(R) I219-V LNL(21)"), 294 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, 295 "Intel(R) I219-LM RPL(22)"), 296 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, 297 "Intel(R) I219-V RPL(22)"), 298 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, 299 "Intel(R) I219-LM RPL(23)"), 300 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, 301 "Intel(R) I219-V RPL(23)"), 302 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, 303 "Intel(R) I219-LM ARL(24)"), 304 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, 305 "Intel(R) I219-V ARL(24)"), 306 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, 307 "Intel(R) I219-LM PTP(25)"), 308 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, 309 "Intel(R) I219-V PTP(25)"), 310 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, 311 "Intel(R) I219-LM PTP(26)"), 312 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, 313 "Intel(R) I219-V PTP(26)"), 314 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, 315 "Intel(R) I219-LM PTP(27)"), 316 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, 317 "Intel(R) I219-V PTP(27)"), 318 /* required last entry */ 319 PVID_END 320 }; 321 322 static const pci_vendor_info_t igb_vendor_info_array[] = 323 { 324 /* Intel(R) - igb-class devices */ 325 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, 326 "Intel(R) PRO/1000 82575EB (Copper)"), 327 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 328 "Intel(R) PRO/1000 82575EB (SERDES)"), 329 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 330 "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 331 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 332 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 333 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, 334 "Intel(R) PRO/1000 82576NS (SERDES)"), 335 PVID(0x8086, E1000_DEV_ID_82576_FIBER, 336 "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 337 PVID(0x8086, E1000_DEV_ID_82576_SERDES, 338 "Intel(R) PRO/1000 82576 (Dual SERDES)"), 339 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, 340 "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 341 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, 342 "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 343 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, 344 "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 345 PVID(0x8086, E1000_DEV_ID_82576_VF, 346 "Intel(R) PRO/1000 82576 Virtual Function"), 347 PVID(0x8086, E1000_DEV_ID_82580_COPPER, 348 "Intel(R) I340 82580 (Copper)"), 349 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 350 PVID(0x8086, E1000_DEV_ID_82580_SERDES, 351 "Intel(R) I340 82580 (SERDES)"), 352 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 353 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, 354 "Intel(R) I340-T2 82580 (Dual Copper)"), 355 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, 356 "Intel(R) I340-F4 82580 (Quad Fiber)"), 357 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, 358 "Intel(R) DH89XXCC (SERDES)"), 359 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, 360 "Intel(R) I347-AT4 DH89XXCC"), 361 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 362 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, 363 "Intel(R) DH89XXCC (Backplane)"), 364 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 365 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 366 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 367 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 368 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 369 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 370 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, 371 "Intel(R) I210 IT (Copper)"), 372 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 373 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, 374 "Intel(R) I210 Flashless (Copper)"), 375 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, 376 "Intel(R) I210 Flashless (SERDES)"), 377 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, 378 "Intel(R) I210 Flashless (SGMII)"), 379 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 380 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 381 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 382 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 383 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, 384 "Intel(R) I354 (1.0 GbE Backplane)"), 385 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, 386 "Intel(R) I354 (2.5 GbE Backplane)"), 387 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 388 /* required last entry */ 389 PVID_END 390 }; 391 392 /********************************************************************* 393 * Function prototypes 394 *********************************************************************/ 395 static void *em_register(device_t); 396 static void *igb_register(device_t); 397 static int em_if_attach_pre(if_ctx_t); 398 static int em_if_attach_post(if_ctx_t); 399 static int em_if_detach(if_ctx_t); 400 static int em_if_shutdown(if_ctx_t); 401 static int em_if_suspend(if_ctx_t); 402 static int em_if_resume(if_ctx_t); 403 404 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 405 int); 406 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 407 int); 408 static void em_if_queues_free(if_ctx_t); 409 410 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 411 static void em_if_init(if_ctx_t); 412 static void em_if_stop(if_ctx_t); 413 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 414 static int em_if_media_change(if_ctx_t); 415 static int em_if_mtu_set(if_ctx_t, uint32_t); 416 static void em_if_timer(if_ctx_t, uint16_t); 417 static void em_if_vlan_register(if_ctx_t, u16); 418 static void em_if_vlan_unregister(if_ctx_t, u16); 419 static void em_if_watchdog_reset(if_ctx_t); 420 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 421 422 static void em_identify_hardware(if_ctx_t); 423 static int em_allocate_pci_resources(if_ctx_t); 424 static void em_free_pci_resources(if_ctx_t); 425 static void em_reset(if_ctx_t); 426 static int em_setup_interface(if_ctx_t); 427 static int em_setup_msix(if_ctx_t); 428 429 static void em_initialize_transmit_unit(if_ctx_t); 430 static void em_initialize_receive_unit(if_ctx_t); 431 432 static void em_if_intr_enable(if_ctx_t); 433 static void em_if_intr_disable(if_ctx_t); 434 static void igb_if_intr_enable(if_ctx_t); 435 static void igb_if_intr_disable(if_ctx_t); 436 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 437 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 438 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 439 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 440 static void em_if_multi_set(if_ctx_t); 441 static void em_if_update_admin_status(if_ctx_t); 442 static void em_if_debug(if_ctx_t); 443 static void em_update_stats_counters(struct e1000_softc *); 444 static void em_add_hw_stats(struct e1000_softc *); 445 static int em_if_set_promisc(if_ctx_t, int); 446 static bool em_if_vlan_filter_capable(if_ctx_t); 447 static bool em_if_vlan_filter_used(if_ctx_t); 448 static void em_if_vlan_filter_enable(struct e1000_softc *); 449 static void em_if_vlan_filter_disable(struct e1000_softc *); 450 static void em_if_vlan_filter_write(struct e1000_softc *); 451 static void em_setup_vlan_hw_support(if_ctx_t ctx); 452 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 453 static void em_print_nvm_info(struct e1000_softc *); 454 static void em_fw_version_locked(if_ctx_t); 455 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 456 static void em_print_fw_version(struct e1000_softc *); 457 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 458 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 459 static int em_get_rs(SYSCTL_HANDLER_ARGS); 460 static void em_print_debug_info(struct e1000_softc *); 461 static int em_is_valid_ether_addr(u8 *); 462 static void em_newitr(struct e1000_softc *, struct em_rx_queue *, 463 struct tx_ring *, struct rx_ring *); 464 static bool em_automask_tso(if_ctx_t); 465 static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 466 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 467 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 468 const char *, struct em_int_delay_info *, int, int); 469 /* Management and WOL Support */ 470 static void em_init_manageability(struct e1000_softc *); 471 static void em_release_manageability(struct e1000_softc *); 472 static void em_get_hw_control(struct e1000_softc *); 473 static void em_release_hw_control(struct e1000_softc *); 474 static void em_get_wakeup(if_ctx_t); 475 static void em_enable_wakeup(if_ctx_t); 476 static int em_enable_phy_wakeup(struct e1000_softc *); 477 static void em_disable_aspm(struct e1000_softc *); 478 479 int em_intr(void *); 480 481 /* MSI-X handlers */ 482 static int em_if_msix_intr_assign(if_ctx_t, int); 483 static int em_msix_link(void *); 484 static void em_handle_link(void *); 485 486 static void em_enable_vectors_82574(if_ctx_t); 487 488 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 489 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 490 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 491 static void em_if_led_func(if_ctx_t, int); 492 493 static int em_get_regs(SYSCTL_HANDLER_ARGS); 494 495 static void lem_smartspeed(struct e1000_softc *); 496 static void igb_configure_queues(struct e1000_softc *); 497 static void em_flush_desc_rings(struct e1000_softc *); 498 499 500 /********************************************************************* 501 * FreeBSD Device Interface Entry Points 502 *********************************************************************/ 503 static device_method_t em_methods[] = { 504 /* Device interface */ 505 DEVMETHOD(device_register, em_register), 506 DEVMETHOD(device_probe, iflib_device_probe), 507 DEVMETHOD(device_attach, iflib_device_attach), 508 DEVMETHOD(device_detach, iflib_device_detach), 509 DEVMETHOD(device_shutdown, iflib_device_shutdown), 510 DEVMETHOD(device_suspend, iflib_device_suspend), 511 DEVMETHOD(device_resume, iflib_device_resume), 512 DEVMETHOD_END 513 }; 514 515 static device_method_t igb_methods[] = { 516 /* Device interface */ 517 DEVMETHOD(device_register, igb_register), 518 DEVMETHOD(device_probe, iflib_device_probe), 519 DEVMETHOD(device_attach, iflib_device_attach), 520 DEVMETHOD(device_detach, iflib_device_detach), 521 DEVMETHOD(device_shutdown, iflib_device_shutdown), 522 DEVMETHOD(device_suspend, iflib_device_suspend), 523 DEVMETHOD(device_resume, iflib_device_resume), 524 DEVMETHOD_END 525 }; 526 527 528 static driver_t em_driver = { 529 "em", em_methods, sizeof(struct e1000_softc), 530 }; 531 532 DRIVER_MODULE(em, pci, em_driver, 0, 0); 533 534 MODULE_DEPEND(em, pci, 1, 1, 1); 535 MODULE_DEPEND(em, ether, 1, 1, 1); 536 MODULE_DEPEND(em, iflib, 1, 1, 1); 537 538 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 539 540 static driver_t igb_driver = { 541 "igb", igb_methods, sizeof(struct e1000_softc), 542 }; 543 544 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 545 546 MODULE_DEPEND(igb, pci, 1, 1, 1); 547 MODULE_DEPEND(igb, ether, 1, 1, 1); 548 MODULE_DEPEND(igb, iflib, 1, 1, 1); 549 550 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 551 552 static device_method_t em_if_methods[] = { 553 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 554 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 555 DEVMETHOD(ifdi_detach, em_if_detach), 556 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 557 DEVMETHOD(ifdi_suspend, em_if_suspend), 558 DEVMETHOD(ifdi_resume, em_if_resume), 559 DEVMETHOD(ifdi_init, em_if_init), 560 DEVMETHOD(ifdi_stop, em_if_stop), 561 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 562 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 563 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 564 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 565 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 566 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 567 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 568 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 569 DEVMETHOD(ifdi_media_status, em_if_media_status), 570 DEVMETHOD(ifdi_media_change, em_if_media_change), 571 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 572 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 573 DEVMETHOD(ifdi_timer, em_if_timer), 574 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 575 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 576 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 577 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 578 DEVMETHOD(ifdi_led_func, em_if_led_func), 579 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 580 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 581 DEVMETHOD(ifdi_debug, em_if_debug), 582 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 583 DEVMETHOD_END 584 }; 585 586 static driver_t em_if_driver = { 587 "em_if", em_if_methods, sizeof(struct e1000_softc) 588 }; 589 590 static device_method_t igb_if_methods[] = { 591 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 592 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 593 DEVMETHOD(ifdi_detach, em_if_detach), 594 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 595 DEVMETHOD(ifdi_suspend, em_if_suspend), 596 DEVMETHOD(ifdi_resume, em_if_resume), 597 DEVMETHOD(ifdi_init, em_if_init), 598 DEVMETHOD(ifdi_stop, em_if_stop), 599 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 600 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 601 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 602 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 603 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 604 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 605 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 606 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 607 DEVMETHOD(ifdi_media_status, em_if_media_status), 608 DEVMETHOD(ifdi_media_change, em_if_media_change), 609 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 610 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 611 DEVMETHOD(ifdi_timer, em_if_timer), 612 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 613 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 614 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 615 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 616 DEVMETHOD(ifdi_led_func, em_if_led_func), 617 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 618 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 619 DEVMETHOD(ifdi_debug, em_if_debug), 620 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 621 DEVMETHOD_END 622 }; 623 624 static driver_t igb_if_driver = { 625 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 626 }; 627 628 /********************************************************************* 629 * Tunable default values. 630 *********************************************************************/ 631 632 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 633 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 634 635 /* Allow common code without TSO */ 636 #ifndef CSUM_TSO 637 #define CSUM_TSO 0 638 #endif 639 640 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 641 "EM driver parameters"); 642 643 static int em_disable_crc_stripping = 0; 644 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 645 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 646 647 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 648 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 649 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, 650 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs"); 651 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, 652 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs"); 653 654 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 655 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 656 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 657 &em_tx_abs_int_delay_dflt, 0, 658 "Default transmit interrupt delay limit in usecs"); 659 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 660 &em_rx_abs_int_delay_dflt, 0, 661 "Default receive interrupt delay limit in usecs"); 662 663 static int em_smart_pwr_down = false; 664 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, 665 &em_smart_pwr_down, 666 0, "Set to true to leave smart power down enabled on newer adapters"); 667 668 static bool em_unsupported_tso = false; 669 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 670 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 671 672 /* Controls whether promiscuous also shows bad packets */ 673 static int em_debug_sbp = false; 674 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 675 "Show bad packets in promiscuous mode"); 676 677 /* Energy efficient ethernet - default to OFF */ 678 static int eee_setting = 1; 679 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 680 "Enable Energy Efficient Ethernet"); 681 682 /* 683 * AIM: Adaptive Interrupt Moderation 684 * which means that the interrupt rate is varied over time based on the 685 * traffic for that interrupt vector 686 */ 687 static int em_enable_aim = 1; 688 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim, 689 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 690 691 /* 692 ** Tuneable Interrupt rate 693 */ 694 static int em_max_interrupt_rate = EM_INTS_DEFAULT; 695 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 696 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 697 698 /* Global used in WOL setup with multiport cards */ 699 static int global_quad_port_a = 0; 700 701 extern struct if_txrx igb_txrx; 702 extern struct if_txrx em_txrx; 703 extern struct if_txrx lem_txrx; 704 705 static struct if_shared_ctx em_sctx_init = { 706 .isc_magic = IFLIB_MAGIC, 707 .isc_q_align = PAGE_SIZE, 708 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 709 .isc_tx_maxsegsize = PAGE_SIZE, 710 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 711 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 712 .isc_rx_maxsize = MJUM9BYTES, 713 .isc_rx_nsegments = 1, 714 .isc_rx_maxsegsize = MJUM9BYTES, 715 .isc_nfl = 1, 716 .isc_nrxqs = 1, 717 .isc_ntxqs = 1, 718 .isc_admin_intrcnt = 1, 719 .isc_vendor_info = em_vendor_info_array, 720 .isc_driver_version = em_driver_version, 721 .isc_driver = &em_if_driver, 722 .isc_flags = 723 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 724 725 .isc_nrxd_min = {EM_MIN_RXD}, 726 .isc_ntxd_min = {EM_MIN_TXD}, 727 .isc_nrxd_max = {EM_MAX_RXD}, 728 .isc_ntxd_max = {EM_MAX_TXD}, 729 .isc_nrxd_default = {EM_DEFAULT_RXD}, 730 .isc_ntxd_default = {EM_DEFAULT_TXD}, 731 }; 732 733 static struct if_shared_ctx igb_sctx_init = { 734 .isc_magic = IFLIB_MAGIC, 735 .isc_q_align = PAGE_SIZE, 736 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 737 .isc_tx_maxsegsize = PAGE_SIZE, 738 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 739 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 740 .isc_rx_maxsize = MJUM9BYTES, 741 .isc_rx_nsegments = 1, 742 .isc_rx_maxsegsize = MJUM9BYTES, 743 .isc_nfl = 1, 744 .isc_nrxqs = 1, 745 .isc_ntxqs = 1, 746 .isc_admin_intrcnt = 1, 747 .isc_vendor_info = igb_vendor_info_array, 748 .isc_driver_version = igb_driver_version, 749 .isc_driver = &igb_if_driver, 750 .isc_flags = 751 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 752 753 .isc_nrxd_min = {EM_MIN_RXD}, 754 .isc_ntxd_min = {EM_MIN_TXD}, 755 .isc_nrxd_max = {IGB_MAX_RXD}, 756 .isc_ntxd_max = {IGB_MAX_TXD}, 757 .isc_nrxd_default = {EM_DEFAULT_RXD}, 758 .isc_ntxd_default = {EM_DEFAULT_TXD}, 759 }; 760 761 /***************************************************************** 762 * 763 * Dump Registers 764 * 765 ****************************************************************/ 766 #define IGB_REGS_LEN 739 767 768 static int em_get_regs(SYSCTL_HANDLER_ARGS) 769 { 770 struct e1000_softc *sc = (struct e1000_softc *)arg1; 771 struct e1000_hw *hw = &sc->hw; 772 struct sbuf *sb; 773 u32 *regs_buff; 774 int rc; 775 776 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 777 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 778 779 rc = sysctl_wire_old_buffer(req, 0); 780 MPASS(rc == 0); 781 if (rc != 0) { 782 free(regs_buff, M_DEVBUF); 783 return (rc); 784 } 785 786 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 787 MPASS(sb != NULL); 788 if (sb == NULL) { 789 free(regs_buff, M_DEVBUF); 790 return (ENOMEM); 791 } 792 793 /* General Registers */ 794 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 795 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 796 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 797 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 798 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 799 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 800 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 801 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 802 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 803 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 804 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 805 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 806 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 807 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 808 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 809 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 810 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 811 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 812 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 813 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 814 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 815 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 816 817 sbuf_printf(sb, "General Registers\n"); 818 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 819 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 820 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 821 822 sbuf_printf(sb, "Interrupt Registers\n"); 823 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 824 825 sbuf_printf(sb, "RX Registers\n"); 826 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 827 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 828 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 829 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 830 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 831 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 832 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 833 834 sbuf_printf(sb, "TX Registers\n"); 835 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 836 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 837 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 838 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 839 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 840 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 841 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 842 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 843 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 844 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 845 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 846 847 free(regs_buff, M_DEVBUF); 848 849 #ifdef DUMP_DESCS 850 { 851 if_softc_ctx_t scctx = sc->shared; 852 struct rx_ring *rxr = &rx_que->rxr; 853 struct tx_ring *txr = &tx_que->txr; 854 int ntxd = scctx->isc_ntxd[0]; 855 int nrxd = scctx->isc_nrxd[0]; 856 int j; 857 858 for (j = 0; j < nrxd; j++) { 859 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 860 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 861 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" 862 PRIx64 " Error:%d Length:%d\n", 863 j, rxr->rx_base[j].read.buffer_addr, staterr, length); 864 } 865 866 for (j = 0; j < min(ntxd, 256); j++) { 867 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 868 869 sbuf_printf(sb, 870 "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x" 871 " eop: %d DD=%d\n", 872 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 873 buf->eop != -1 ? 874 txr->tx_base[buf->eop].upper.fields.status & 875 E1000_TXD_STAT_DD : 0); 876 877 } 878 } 879 #endif 880 881 rc = sbuf_finish(sb); 882 sbuf_delete(sb); 883 return(rc); 884 } 885 886 static void * 887 em_register(device_t dev) 888 { 889 return (&em_sctx_init); 890 } 891 892 static void * 893 igb_register(device_t dev) 894 { 895 return (&igb_sctx_init); 896 } 897 898 static int 899 em_set_num_queues(if_ctx_t ctx) 900 { 901 struct e1000_softc *sc = iflib_get_softc(ctx); 902 int maxqueues; 903 904 /* Sanity check based on HW */ 905 switch (sc->hw.mac.type) { 906 case e1000_82576: 907 case e1000_82580: 908 case e1000_i350: 909 case e1000_i354: 910 maxqueues = 8; 911 break; 912 case e1000_i210: 913 case e1000_82575: 914 maxqueues = 4; 915 break; 916 case e1000_i211: 917 case e1000_82574: 918 maxqueues = 2; 919 break; 920 default: 921 maxqueues = 1; 922 break; 923 } 924 925 return (maxqueues); 926 } 927 928 #define LEM_CAPS \ 929 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 930 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 931 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 932 933 #define EM_CAPS \ 934 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 935 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 936 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 937 IFCAP_TSO6 938 939 #define IGB_CAPS \ 940 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 941 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 942 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 943 IFCAP_TSO6 944 945 /********************************************************************* 946 * Device initialization routine 947 * 948 * The attach entry point is called when the driver is being loaded. 949 * This routine identifies the type of hardware, allocates all resources 950 * and initializes the hardware. 951 * 952 * return 0 on success, positive on failure 953 *********************************************************************/ 954 static int 955 em_if_attach_pre(if_ctx_t ctx) 956 { 957 struct e1000_softc *sc; 958 if_softc_ctx_t scctx; 959 device_t dev; 960 struct e1000_hw *hw; 961 struct sysctl_oid_list *child; 962 struct sysctl_ctx_list *ctx_list; 963 int error = 0; 964 965 INIT_DEBUGOUT("em_if_attach_pre: begin"); 966 dev = iflib_get_dev(ctx); 967 sc = iflib_get_softc(ctx); 968 969 sc->ctx = sc->osdep.ctx = ctx; 970 sc->dev = sc->osdep.dev = dev; 971 scctx = sc->shared = iflib_get_softc_ctx(ctx); 972 sc->media = iflib_get_media(ctx); 973 hw = &sc->hw; 974 975 /* Determine hardware and mac info */ 976 em_identify_hardware(ctx); 977 978 /* SYSCTL stuff */ 979 ctx_list = device_get_sysctl_ctx(dev); 980 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 981 982 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 983 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 984 em_sysctl_nvm_info, "I", "NVM Information"); 985 986 sc->enable_aim = em_enable_aim; 987 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", 988 CTLFLAG_RW, &sc->enable_aim, 0, 989 "Interrupt Moderation (1=normal, 2=lowlatency)"); 990 991 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 992 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 993 em_sysctl_print_fw_version, "A", 994 "Prints FW/NVM Versions"); 995 996 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 997 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 998 em_sysctl_debug_info, "I", "Debug Information"); 999 1000 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 1001 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1002 em_set_flowcntl, "I", "Flow Control"); 1003 1004 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 1005 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 1006 em_get_regs, "A", "Dump Registers"); 1007 1008 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 1009 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1010 em_get_rs, "I", "Dump RS indexes"); 1011 1012 if (hw->mac.type >= e1000_i350) { 1013 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 1014 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1015 igb_sysctl_dmac, "I", "DMA Coalesce"); 1016 } 1017 1018 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1019 "tso_tcp_flags_mask_first_segment", 1020 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1021 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU", 1022 "TSO TCP flags mask for first segment"); 1023 1024 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1025 "tso_tcp_flags_mask_middle_segment", 1026 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1027 sc, 1, em_sysctl_tso_tcp_flags_mask, "IU", 1028 "TSO TCP flags mask for middle segment"); 1029 1030 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1031 "tso_tcp_flags_mask_last_segment", 1032 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1033 sc, 2, em_sysctl_tso_tcp_flags_mask, "IU", 1034 "TSO TCP flags mask for last segment"); 1035 1036 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 1037 scctx->isc_nrxqsets_max = 1038 scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 1039 if (bootverbose) 1040 device_printf(dev, "attach_pre capping queues at %d\n", 1041 scctx->isc_ntxqsets_max); 1042 1043 if (hw->mac.type >= igb_mac_min) { 1044 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1045 sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 1046 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1047 sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 1048 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 1049 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 1050 scctx->isc_txrx = &igb_txrx; 1051 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1052 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1053 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1054 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 1055 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 1056 CSUM_IP6_TCP | CSUM_IP6_UDP; 1057 if (hw->mac.type != e1000_82575) 1058 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 1059 /* 1060 ** Some new devices, as with ixgbe, now may 1061 ** use a different BAR, so we need to keep 1062 ** track of which is used. 1063 */ 1064 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1065 } else if (hw->mac.type >= em_mac_min) { 1066 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1067 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1068 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1069 sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 1070 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1071 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 1072 scctx->isc_txrx = &em_txrx; 1073 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1074 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1075 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1076 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 1077 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1078 CSUM_IP6_TCP | CSUM_IP6_UDP; 1079 1080 /* Disable TSO on all em(4) until ring stalls are debugged */ 1081 scctx->isc_capenable &= ~IFCAP_TSO; 1082 1083 /* 1084 * Disable TSO on SPT due to errata that downclocks DMA 1085 * performance 1086 * i218-i219 Specification Update 1.5.4.5 1087 */ 1088 if (hw->mac.type == e1000_pch_spt) 1089 scctx->isc_capenable &= ~IFCAP_TSO; 1090 1091 /* 1092 * We support MSI-X with 82574 only, but indicate to iflib(4) 1093 * that it shall give MSI at least a try with other devices. 1094 */ 1095 if (hw->mac.type == e1000_82574) { 1096 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1097 } else { 1098 scctx->isc_msix_bar = -1; 1099 scctx->isc_disable_msix = 1; 1100 } 1101 } else { 1102 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * 1103 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1104 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * 1105 sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 1106 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1107 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 1108 scctx->isc_txrx = &lem_txrx; 1109 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1110 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1111 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1112 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 1113 if (em_unsupported_tso) 1114 scctx->isc_capabilities |= IFCAP_TSO6; 1115 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1116 CSUM_IP6_TCP | CSUM_IP6_UDP; 1117 1118 /* Disable TSO on all lem(4) until ring stalls debugged */ 1119 scctx->isc_capenable &= ~IFCAP_TSO; 1120 1121 /* 82541ER doesn't do HW tagging */ 1122 if (hw->device_id == E1000_DEV_ID_82541ER || 1123 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 1124 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 1125 scctx->isc_capenable = scctx->isc_capabilities; 1126 } 1127 /* This is the first e1000 chip and it does not do offloads */ 1128 if (hw->mac.type == e1000_82542) { 1129 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | 1130 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 | 1131 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER | 1132 IFCAP_TSO | IFCAP_VLAN_HWTSO); 1133 scctx->isc_capenable = scctx->isc_capabilities; 1134 } 1135 /* These can't do TSO for various reasons */ 1136 if (hw->mac.type < e1000_82544 || 1137 hw->mac.type == e1000_82547 || 1138 hw->mac.type == e1000_82547_rev_2) { 1139 scctx->isc_capabilities &= 1140 ~(IFCAP_TSO |IFCAP_VLAN_HWTSO); 1141 scctx->isc_capenable = scctx->isc_capabilities; 1142 } 1143 /* XXXKB: No IPv6 before this? */ 1144 if (hw->mac.type < e1000_82545){ 1145 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 1146 scctx->isc_capenable = scctx->isc_capabilities; 1147 } 1148 /* 1149 * "PCI/PCI-X SDM 4.0" page 33 (b): 1150 * FDX requirement on these chips 1151 */ 1152 if (hw->mac.type == e1000_82547 || 1153 hw->mac.type == e1000_82547_rev_2) 1154 scctx->isc_capenable &= ~(IFCAP_HWCSUM | 1155 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6); 1156 1157 /* INTx only */ 1158 scctx->isc_msix_bar = 0; 1159 } 1160 1161 /* Setup PCI resources */ 1162 if (em_allocate_pci_resources(ctx)) { 1163 device_printf(dev, "Allocation of PCI resources failed\n"); 1164 error = ENXIO; 1165 goto err_pci; 1166 } 1167 1168 /* 1169 ** For ICH8 and family we need to 1170 ** map the flash memory, and this 1171 ** must happen after the MAC is 1172 ** identified 1173 */ 1174 if ((hw->mac.type == e1000_ich8lan) || 1175 (hw->mac.type == e1000_ich9lan) || 1176 (hw->mac.type == e1000_ich10lan) || 1177 (hw->mac.type == e1000_pchlan) || 1178 (hw->mac.type == e1000_pch2lan) || 1179 (hw->mac.type == e1000_pch_lpt)) { 1180 int rid = EM_BAR_TYPE_FLASH; 1181 sc->flash = bus_alloc_resource_any(dev, 1182 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1183 if (sc->flash == NULL) { 1184 device_printf(dev, "Mapping of Flash failed\n"); 1185 error = ENXIO; 1186 goto err_pci; 1187 } 1188 /* This is used in the shared code */ 1189 hw->flash_address = (u8 *)sc->flash; 1190 sc->osdep.flash_bus_space_tag = 1191 rman_get_bustag(sc->flash); 1192 sc->osdep.flash_bus_space_handle = 1193 rman_get_bushandle(sc->flash); 1194 } 1195 /* 1196 ** In the new SPT device flash is not a 1197 ** separate BAR, rather it is also in BAR0, 1198 ** so use the same tag and an offset handle for the 1199 ** FLASH read/write macros in the shared code. 1200 */ 1201 else if (hw->mac.type >= e1000_pch_spt) { 1202 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1203 sc->osdep.flash_bus_space_handle = 1204 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; 1205 } 1206 1207 /* Do Shared Code initialization */ 1208 error = e1000_setup_init_funcs(hw, true); 1209 if (error) { 1210 device_printf(dev, "Setup of Shared code failed, error %d\n", 1211 error); 1212 error = ENXIO; 1213 goto err_pci; 1214 } 1215 1216 em_setup_msix(ctx); 1217 e1000_get_bus_info(hw); 1218 1219 /* Set up some sysctls for the tunable interrupt delays */ 1220 if (hw->mac.type < igb_mac_min) { 1221 em_add_int_delay_sysctl(sc, "rx_int_delay", 1222 "receive interrupt delay in usecs", &sc->rx_int_delay, 1223 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1224 em_add_int_delay_sysctl(sc, "tx_int_delay", 1225 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1226 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1227 } 1228 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1229 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1230 "receive interrupt delay limit in usecs", 1231 &sc->rx_abs_int_delay, 1232 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1233 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1234 "transmit interrupt delay limit in usecs", 1235 &sc->tx_abs_int_delay, 1236 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1237 } 1238 1239 hw->mac.autoneg = DO_AUTO_NEG; 1240 hw->phy.autoneg_wait_to_complete = false; 1241 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1242 1243 if (hw->mac.type < em_mac_min) { 1244 e1000_init_script_state_82541(hw, true); 1245 e1000_set_tbi_compatibility_82543(hw, true); 1246 } 1247 /* Copper options */ 1248 if (hw->phy.media_type == e1000_media_type_copper) { 1249 hw->phy.mdix = AUTO_ALL_MODES; 1250 hw->phy.disable_polarity_correction = false; 1251 hw->phy.ms_type = EM_MASTER_SLAVE; 1252 } 1253 1254 /* 1255 * Set the frame limits assuming 1256 * standard ethernet sized frames. 1257 */ 1258 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1259 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1260 1261 /* 1262 * This controls when hardware reports transmit completion 1263 * status. 1264 */ 1265 hw->mac.report_tx_early = 1; 1266 1267 /* Allocate multicast array memory. */ 1268 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1269 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1270 if (sc->mta == NULL) { 1271 device_printf(dev, 1272 "Can not allocate multicast setup array\n"); 1273 error = ENOMEM; 1274 goto err_late; 1275 } 1276 1277 /* Clear the IFCAP_TSO auto mask */ 1278 sc->tso_automasked = 0; 1279 1280 /* Check SOL/IDER usage */ 1281 if (e1000_check_reset_block(hw)) 1282 device_printf(dev, 1283 "PHY reset is blocked due to SOL/IDER session.\n"); 1284 1285 /* Sysctl for setting Energy Efficient Ethernet */ 1286 if (hw->mac.type < igb_mac_min) 1287 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1288 else 1289 hw->dev_spec._82575.eee_disable = eee_setting; 1290 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1291 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1292 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1293 1294 /* 1295 ** Start from a known state, this is 1296 ** important in reading the nvm and 1297 ** mac from that. 1298 */ 1299 e1000_reset_hw(hw); 1300 1301 /* Make sure we have a good EEPROM before we read from it */ 1302 if (e1000_validate_nvm_checksum(hw) < 0) { 1303 /* 1304 ** Some PCI-E parts fail the first check due to 1305 ** the link being in sleep state, call it again, 1306 ** if it fails a second time its a real issue. 1307 */ 1308 if (e1000_validate_nvm_checksum(hw) < 0) { 1309 device_printf(dev, 1310 "The EEPROM Checksum Is Not Valid\n"); 1311 error = EIO; 1312 goto err_late; 1313 } 1314 } 1315 1316 /* Copy the permanent MAC address out of the EEPROM */ 1317 if (e1000_read_mac_addr(hw) < 0) { 1318 device_printf(dev, 1319 "EEPROM read error while reading MAC address\n"); 1320 error = EIO; 1321 goto err_late; 1322 } 1323 1324 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1325 if (sc->vf_ifp) { 1326 ether_gen_addr(iflib_get_ifp(ctx), 1327 (struct ether_addr *)hw->mac.addr); 1328 } else { 1329 device_printf(dev, "Invalid MAC address\n"); 1330 error = EIO; 1331 goto err_late; 1332 } 1333 } 1334 1335 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1336 em_fw_version_locked(ctx); 1337 1338 em_print_fw_version(sc); 1339 1340 /* 1341 * Get Wake-on-Lan and Management info for later use 1342 */ 1343 em_get_wakeup(ctx); 1344 1345 /* Enable only WOL MAGIC by default */ 1346 scctx->isc_capenable &= ~IFCAP_WOL; 1347 if (sc->wol != 0) 1348 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1349 1350 iflib_set_mac(ctx, hw->mac.addr); 1351 1352 return (0); 1353 1354 err_late: 1355 em_release_hw_control(sc); 1356 err_pci: 1357 em_free_pci_resources(ctx); 1358 free(sc->mta, M_DEVBUF); 1359 1360 return (error); 1361 } 1362 1363 static int 1364 em_if_attach_post(if_ctx_t ctx) 1365 { 1366 struct e1000_softc *sc = iflib_get_softc(ctx); 1367 struct e1000_hw *hw = &sc->hw; 1368 int error = 0; 1369 1370 /* Setup OS specific network interface */ 1371 error = em_setup_interface(ctx); 1372 if (error != 0) { 1373 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1374 goto err_late; 1375 } 1376 1377 em_reset(ctx); 1378 1379 /* Initialize statistics */ 1380 em_update_stats_counters(sc); 1381 hw->mac.get_link_status = 1; 1382 em_if_update_admin_status(ctx); 1383 em_add_hw_stats(sc); 1384 1385 /* Non-AMT based hardware can now take control from firmware */ 1386 if (sc->has_manage && !sc->has_amt) 1387 em_get_hw_control(sc); 1388 1389 INIT_DEBUGOUT("em_if_attach_post: end"); 1390 1391 return (0); 1392 1393 err_late: 1394 /* 1395 * Upon em_if_attach_post() error, iflib calls em_if_detach() to 1396 * free resources 1397 */ 1398 return (error); 1399 } 1400 1401 /********************************************************************* 1402 * Device removal routine 1403 * 1404 * The detach entry point is called when the driver is being removed. 1405 * This routine stops the adapter and deallocates all the resources 1406 * that were allocated for driver operation. 1407 * 1408 * return 0 on success, positive on failure 1409 *********************************************************************/ 1410 static int 1411 em_if_detach(if_ctx_t ctx) 1412 { 1413 struct e1000_softc *sc = iflib_get_softc(ctx); 1414 1415 INIT_DEBUGOUT("em_if_detach: begin"); 1416 1417 e1000_phy_hw_reset(&sc->hw); 1418 1419 em_release_manageability(sc); 1420 em_release_hw_control(sc); 1421 em_free_pci_resources(ctx); 1422 free(sc->mta, M_DEVBUF); 1423 sc->mta = NULL; 1424 1425 return (0); 1426 } 1427 1428 /********************************************************************* 1429 * 1430 * Shutdown entry point 1431 * 1432 **********************************************************************/ 1433 1434 static int 1435 em_if_shutdown(if_ctx_t ctx) 1436 { 1437 return em_if_suspend(ctx); 1438 } 1439 1440 /* 1441 * Suspend/resume device methods. 1442 */ 1443 static int 1444 em_if_suspend(if_ctx_t ctx) 1445 { 1446 struct e1000_softc *sc = iflib_get_softc(ctx); 1447 1448 em_release_manageability(sc); 1449 em_release_hw_control(sc); 1450 em_enable_wakeup(ctx); 1451 return (0); 1452 } 1453 1454 static int 1455 em_if_resume(if_ctx_t ctx) 1456 { 1457 struct e1000_softc *sc = iflib_get_softc(ctx); 1458 1459 if (sc->hw.mac.type == e1000_pch2lan) 1460 e1000_resume_workarounds_pchlan(&sc->hw); 1461 em_if_init(ctx); 1462 em_init_manageability(sc); 1463 1464 return(0); 1465 } 1466 1467 static int 1468 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1469 { 1470 int max_frame_size; 1471 struct e1000_softc *sc = iflib_get_softc(ctx); 1472 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1473 1474 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1475 1476 switch (sc->hw.mac.type) { 1477 case e1000_82571: 1478 case e1000_82572: 1479 case e1000_ich9lan: 1480 case e1000_ich10lan: 1481 case e1000_pch2lan: 1482 case e1000_pch_lpt: 1483 case e1000_pch_spt: 1484 case e1000_pch_cnp: 1485 case e1000_pch_tgp: 1486 case e1000_pch_adp: 1487 case e1000_pch_mtp: 1488 case e1000_pch_ptp: 1489 case e1000_82574: 1490 case e1000_82583: 1491 case e1000_80003es2lan: 1492 /* 9K Jumbo Frame size */ 1493 max_frame_size = 9234; 1494 break; 1495 case e1000_pchlan: 1496 max_frame_size = 4096; 1497 break; 1498 case e1000_82542: 1499 case e1000_ich8lan: 1500 /* Adapters that do not support jumbo frames */ 1501 max_frame_size = ETHER_MAX_LEN; 1502 break; 1503 default: 1504 if (sc->hw.mac.type >= igb_mac_min) 1505 max_frame_size = 9234; 1506 else /* lem */ 1507 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1508 } 1509 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1510 return (EINVAL); 1511 } 1512 1513 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1514 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1515 return (0); 1516 } 1517 1518 /********************************************************************* 1519 * Init entry point 1520 * 1521 * This routine is used in two ways. It is used by the stack as 1522 * init entry point in network interface structure. It is also used 1523 * by the driver as a hw/sw initialization routine to get to a 1524 * consistent state. 1525 * 1526 **********************************************************************/ 1527 static void 1528 em_if_init(if_ctx_t ctx) 1529 { 1530 struct e1000_softc *sc = iflib_get_softc(ctx); 1531 if_softc_ctx_t scctx = sc->shared; 1532 if_t ifp = iflib_get_ifp(ctx); 1533 struct em_tx_queue *tx_que; 1534 int i; 1535 1536 INIT_DEBUGOUT("em_if_init: begin"); 1537 1538 /* Get the latest mac address, User can use a LAA */ 1539 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1540 1541 /* Put the address into the Receive Address Array */ 1542 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1543 1544 /* 1545 * With the 82571 adapter, RAR[0] may be overwritten 1546 * when the other port is reset, we make a duplicate 1547 * in RAR[14] for that eventuality, this assures 1548 * the interface continues to function. 1549 */ 1550 if (sc->hw.mac.type == e1000_82571) { 1551 e1000_set_laa_state_82571(&sc->hw, true); 1552 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1553 E1000_RAR_ENTRIES - 1); 1554 } 1555 1556 /* Initialize the hardware */ 1557 em_reset(ctx); 1558 em_if_update_admin_status(ctx); 1559 1560 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; 1561 i++, tx_que++) { 1562 struct tx_ring *txr = &tx_que->txr; 1563 1564 txr->tx_rs_cidx = txr->tx_rs_pidx; 1565 1566 /* Initialize the last processed descriptor to be the end of 1567 * the ring, rather than the start, so that we avoid an 1568 * off-by-one error when calculating how many descriptors are 1569 * done in the credits_update function. 1570 */ 1571 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1572 } 1573 1574 /* Setup VLAN support, basic and offload if available */ 1575 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1576 1577 /* Clear bad data from Rx FIFOs */ 1578 if (sc->hw.mac.type >= igb_mac_min) 1579 e1000_rx_fifo_flush_base(&sc->hw); 1580 1581 /* Configure for OS presence */ 1582 em_init_manageability(sc); 1583 1584 /* Prepare transmit descriptors and buffers */ 1585 em_initialize_transmit_unit(ctx); 1586 1587 /* Setup Multicast table */ 1588 em_if_multi_set(ctx); 1589 1590 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1591 em_initialize_receive_unit(ctx); 1592 1593 /* Set up VLAN support and filter */ 1594 em_setup_vlan_hw_support(ctx); 1595 1596 /* Don't lose promiscuous settings */ 1597 em_if_set_promisc(ctx, if_getflags(ifp)); 1598 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1599 1600 /* MSI-X configuration for 82574 */ 1601 if (sc->hw.mac.type == e1000_82574) { 1602 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1603 1604 tmp |= E1000_CTRL_EXT_PBA_CLR; 1605 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1606 /* Set the IVAR - interrupt vector routing. */ 1607 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1608 } else if (sc->intr_type == IFLIB_INTR_MSIX) { 1609 /* Set up queue routing */ 1610 igb_configure_queues(sc); 1611 } 1612 1613 /* this clears any pending interrupts */ 1614 E1000_READ_REG(&sc->hw, E1000_ICR); 1615 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1616 1617 /* AMT based hardware can now take control from firmware */ 1618 if (sc->has_manage && sc->has_amt) 1619 em_get_hw_control(sc); 1620 1621 /* Set Energy Efficient Ethernet */ 1622 if (sc->hw.mac.type >= igb_mac_min && 1623 sc->hw.phy.media_type == e1000_media_type_copper) { 1624 if (sc->hw.mac.type == e1000_i354) 1625 e1000_set_eee_i354(&sc->hw, true, true); 1626 else 1627 e1000_set_eee_i350(&sc->hw, true, true); 1628 } 1629 } 1630 1631 enum itr_latency_target { 1632 itr_latency_disabled = 0, 1633 itr_latency_lowest = 1, 1634 itr_latency_low = 2, 1635 itr_latency_bulk = 3 1636 }; 1637 /********************************************************************* 1638 * 1639 * Helper to calculate next (E)ITR value for AIM 1640 * 1641 *********************************************************************/ 1642 static void 1643 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, 1644 struct tx_ring *txr, struct rx_ring *rxr) 1645 { 1646 struct e1000_hw *hw = &sc->hw; 1647 u32 newitr; 1648 u32 bytes; 1649 u32 bytes_packets; 1650 u32 packets; 1651 u8 nextlatency; 1652 1653 /* Idle, do nothing */ 1654 if ((txr->tx_bytes == 0) && (rxr->rx_bytes == 0)) 1655 return; 1656 1657 newitr = 0; 1658 1659 if (sc->enable_aim) { 1660 nextlatency = rxr->rx_nextlatency; 1661 1662 /* Use half default (4K) ITR if sub-gig */ 1663 if (sc->link_speed != 1000) { 1664 newitr = EM_INTS_4K; 1665 goto em_set_next_itr; 1666 } 1667 /* Want at least enough packet buffer for two frames to AIM */ 1668 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1669 newitr = em_max_interrupt_rate; 1670 sc->enable_aim = 0; 1671 goto em_set_next_itr; 1672 } 1673 1674 /* Get largest values from the associated tx and rx ring */ 1675 if (txr->tx_bytes && txr->tx_packets) { 1676 bytes = txr->tx_bytes; 1677 bytes_packets = txr->tx_bytes/txr->tx_packets; 1678 packets = txr->tx_packets; 1679 } 1680 if (rxr->rx_bytes && rxr->rx_packets) { 1681 bytes = max(bytes, rxr->rx_bytes); 1682 bytes_packets = 1683 max(bytes_packets, rxr->rx_bytes/rxr->rx_packets); 1684 packets = max(packets, rxr->rx_packets); 1685 } 1686 1687 /* Latency state machine */ 1688 switch (nextlatency) { 1689 case itr_latency_disabled: /* Bootstrapping */ 1690 nextlatency = itr_latency_low; 1691 break; 1692 case itr_latency_lowest: /* 70k ints/s */ 1693 /* TSO and jumbo frames */ 1694 if (bytes_packets > 8000) 1695 nextlatency = itr_latency_bulk; 1696 else if ((packets < 5) && (bytes > 512)) 1697 nextlatency = itr_latency_low; 1698 break; 1699 case itr_latency_low: /* 20k ints/s */ 1700 if (bytes > 10000) { 1701 /* Handle TSO */ 1702 if (bytes_packets > 8000) 1703 nextlatency = itr_latency_bulk; 1704 else if ((packets < 10) || 1705 (bytes_packets > 1200)) 1706 nextlatency = itr_latency_bulk; 1707 else if (packets > 35) 1708 nextlatency = itr_latency_lowest; 1709 } else if (bytes_packets > 2000) { 1710 nextlatency = itr_latency_bulk; 1711 } else if (packets < 3 && bytes < 512) { 1712 nextlatency = itr_latency_lowest; 1713 } 1714 break; 1715 case itr_latency_bulk: /* 4k ints/s */ 1716 if (bytes > 25000) { 1717 if (packets > 35) 1718 nextlatency = itr_latency_low; 1719 } else if (bytes < 1500) 1720 nextlatency = itr_latency_low; 1721 break; 1722 default: 1723 nextlatency = itr_latency_low; 1724 device_printf(sc->dev, 1725 "Unexpected newitr transition %d\n", nextlatency); 1726 break; 1727 } 1728 1729 /* Trim itr_latency_lowest for default AIM setting */ 1730 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) 1731 nextlatency = itr_latency_low; 1732 1733 /* Request new latency */ 1734 rxr->rx_nextlatency = nextlatency; 1735 } else { 1736 /* We may have toggled to AIM disabled */ 1737 nextlatency = itr_latency_disabled; 1738 rxr->rx_nextlatency = nextlatency; 1739 } 1740 1741 /* ITR state machine */ 1742 switch(nextlatency) { 1743 case itr_latency_lowest: 1744 newitr = EM_INTS_70K; 1745 break; 1746 case itr_latency_low: 1747 newitr = EM_INTS_20K; 1748 break; 1749 case itr_latency_bulk: 1750 newitr = EM_INTS_4K; 1751 break; 1752 case itr_latency_disabled: 1753 default: 1754 newitr = em_max_interrupt_rate; 1755 break; 1756 } 1757 1758 em_set_next_itr: 1759 if (hw->mac.type >= igb_mac_min) { 1760 newitr = IGB_INTS_TO_EITR(newitr); 1761 1762 if (hw->mac.type == e1000_82575) 1763 newitr |= newitr << 16; 1764 else 1765 newitr |= E1000_EITR_CNT_IGNR; 1766 1767 if (newitr != que->itr_setting) { 1768 que->itr_setting = newitr; 1769 E1000_WRITE_REG(hw, E1000_EITR(que->msix), 1770 que->itr_setting); 1771 } 1772 } else { 1773 newitr = EM_INTS_TO_ITR(newitr); 1774 1775 if (newitr != que->itr_setting) { 1776 que->itr_setting = newitr; 1777 if (hw->mac.type == e1000_82574 && que->msix) { 1778 E1000_WRITE_REG(hw, 1779 E1000_EITR_82574(que->msix), 1780 que->itr_setting); 1781 } else { 1782 E1000_WRITE_REG(hw, E1000_ITR, 1783 que->itr_setting); 1784 } 1785 } 1786 } 1787 } 1788 1789 /********************************************************************* 1790 * 1791 * Fast Legacy/MSI Combined Interrupt Service routine 1792 * 1793 *********************************************************************/ 1794 int 1795 em_intr(void *arg) 1796 { 1797 struct e1000_softc *sc = arg; 1798 struct e1000_hw *hw = &sc->hw; 1799 struct em_rx_queue *que = &sc->rx_queues[0]; 1800 struct tx_ring *txr = &sc->tx_queues[0].txr; 1801 struct rx_ring *rxr = &que->rxr; 1802 if_ctx_t ctx = sc->ctx; 1803 u32 reg_icr; 1804 1805 reg_icr = E1000_READ_REG(hw, E1000_ICR); 1806 1807 /* Hot eject? */ 1808 if (reg_icr == 0xffffffff) 1809 return FILTER_STRAY; 1810 1811 /* Definitely not our interrupt. */ 1812 if (reg_icr == 0x0) 1813 return FILTER_STRAY; 1814 1815 /* 1816 * Starting with the 82571 chip, bit 31 should be used to 1817 * determine whether the interrupt belongs to us. 1818 */ 1819 if (hw->mac.type >= e1000_82571 && 1820 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1821 return FILTER_STRAY; 1822 1823 /* 1824 * Only MSI-X interrupts have one-shot behavior by taking advantage 1825 * of the EIAC register. Thus, explicitly disable interrupts. This 1826 * also works around the MSI message reordering errata on certain 1827 * systems. 1828 */ 1829 IFDI_INTR_DISABLE(ctx); 1830 1831 /* Link status change */ 1832 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1833 em_handle_link(ctx); 1834 1835 if (reg_icr & E1000_ICR_RXO) 1836 sc->rx_overruns++; 1837 1838 if (hw->mac.type >= e1000_82540) 1839 em_newitr(sc, que, txr, rxr); 1840 1841 /* Reset state */ 1842 txr->tx_bytes = 0; 1843 txr->tx_packets = 0; 1844 rxr->rx_bytes = 0; 1845 rxr->rx_packets = 0; 1846 1847 return (FILTER_SCHEDULE_THREAD); 1848 } 1849 1850 static int 1851 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1852 { 1853 struct e1000_softc *sc = iflib_get_softc(ctx); 1854 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1855 1856 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1857 return (0); 1858 } 1859 1860 static int 1861 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1862 { 1863 struct e1000_softc *sc = iflib_get_softc(ctx); 1864 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1865 1866 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1867 return (0); 1868 } 1869 1870 static int 1871 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1872 { 1873 struct e1000_softc *sc = iflib_get_softc(ctx); 1874 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1875 1876 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1877 return (0); 1878 } 1879 1880 static int 1881 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1882 { 1883 struct e1000_softc *sc = iflib_get_softc(ctx); 1884 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1885 1886 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1887 return (0); 1888 } 1889 1890 /********************************************************************* 1891 * 1892 * MSI-X RX Interrupt Service routine 1893 * 1894 **********************************************************************/ 1895 static int 1896 em_msix_que(void *arg) 1897 { 1898 struct em_rx_queue *que = arg; 1899 struct e1000_softc *sc = que->sc; 1900 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; 1901 struct rx_ring *rxr = &que->rxr; 1902 1903 ++que->irqs; 1904 1905 em_newitr(sc, que, txr, rxr); 1906 1907 /* Reset state */ 1908 txr->tx_bytes = 0; 1909 txr->tx_packets = 0; 1910 rxr->rx_bytes = 0; 1911 rxr->rx_packets = 0; 1912 1913 return (FILTER_SCHEDULE_THREAD); 1914 } 1915 1916 /********************************************************************* 1917 * 1918 * MSI-X Link Fast Interrupt Service routine 1919 * 1920 **********************************************************************/ 1921 static int 1922 em_msix_link(void *arg) 1923 { 1924 struct e1000_softc *sc = arg; 1925 u32 reg_icr; 1926 1927 ++sc->link_irq; 1928 MPASS(sc->hw.back != NULL); 1929 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1930 1931 if (reg_icr & E1000_ICR_RXO) 1932 sc->rx_overruns++; 1933 1934 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1935 em_handle_link(sc->ctx); 1936 1937 /* Re-arm unconditionally */ 1938 if (sc->hw.mac.type >= igb_mac_min) { 1939 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1940 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1941 } else if (sc->hw.mac.type == e1000_82574) { 1942 E1000_WRITE_REG(&sc->hw, E1000_IMS, 1943 E1000_IMS_LSC | E1000_IMS_OTHER); 1944 /* 1945 * Because we must read the ICR for this interrupt it may 1946 * clear other causes using autoclear, for this reason we 1947 * simply create a soft interrupt for all these vectors. 1948 */ 1949 if (reg_icr) 1950 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1951 } else 1952 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1953 1954 return (FILTER_HANDLED); 1955 } 1956 1957 static void 1958 em_handle_link(void *context) 1959 { 1960 if_ctx_t ctx = context; 1961 struct e1000_softc *sc = iflib_get_softc(ctx); 1962 1963 sc->hw.mac.get_link_status = 1; 1964 iflib_admin_intr_deferred(ctx); 1965 } 1966 1967 /********************************************************************* 1968 * 1969 * Media Ioctl callback 1970 * 1971 * This routine is called whenever the user queries the status of 1972 * the interface using ifconfig. 1973 * 1974 **********************************************************************/ 1975 static void 1976 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1977 { 1978 struct e1000_softc *sc = iflib_get_softc(ctx); 1979 u_char fiber_type = IFM_1000_SX; 1980 1981 INIT_DEBUGOUT("em_if_media_status: begin"); 1982 1983 iflib_admin_intr_deferred(ctx); 1984 1985 ifmr->ifm_status = IFM_AVALID; 1986 ifmr->ifm_active = IFM_ETHER; 1987 1988 if (!sc->link_active) { 1989 return; 1990 } 1991 1992 ifmr->ifm_status |= IFM_ACTIVE; 1993 1994 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1995 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1996 if (sc->hw.mac.type == e1000_82545) 1997 fiber_type = IFM_1000_LX; 1998 switch (sc->link_speed) { 1999 case 10: 2000 ifmr->ifm_active |= IFM_10_FL; 2001 break; 2002 case 100: 2003 ifmr->ifm_active |= IFM_100_FX; 2004 break; 2005 case 1000: 2006 default: 2007 ifmr->ifm_active |= fiber_type | IFM_FDX; 2008 break; 2009 } 2010 } else { 2011 switch (sc->link_speed) { 2012 case 10: 2013 ifmr->ifm_active |= IFM_10_T; 2014 break; 2015 case 100: 2016 ifmr->ifm_active |= IFM_100_TX; 2017 break; 2018 case 1000: 2019 ifmr->ifm_active |= IFM_1000_T; 2020 break; 2021 } 2022 } 2023 2024 if (sc->link_duplex == FULL_DUPLEX) 2025 ifmr->ifm_active |= IFM_FDX; 2026 else 2027 ifmr->ifm_active |= IFM_HDX; 2028 } 2029 2030 /********************************************************************* 2031 * 2032 * Media Ioctl callback 2033 * 2034 * This routine is called when the user changes speed/duplex using 2035 * media/mediopt option with ifconfig. 2036 * 2037 **********************************************************************/ 2038 static int 2039 em_if_media_change(if_ctx_t ctx) 2040 { 2041 struct e1000_softc *sc = iflib_get_softc(ctx); 2042 struct ifmedia *ifm = iflib_get_media(ctx); 2043 2044 INIT_DEBUGOUT("em_if_media_change: begin"); 2045 2046 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2047 return (EINVAL); 2048 2049 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2050 case IFM_AUTO: 2051 sc->hw.mac.autoneg = DO_AUTO_NEG; 2052 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 2053 break; 2054 case IFM_1000_LX: 2055 case IFM_1000_SX: 2056 case IFM_1000_T: 2057 sc->hw.mac.autoneg = DO_AUTO_NEG; 2058 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 2059 break; 2060 case IFM_100_TX: 2061 sc->hw.mac.autoneg = DO_AUTO_NEG; 2062 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2063 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 2064 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2065 } else { 2066 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 2067 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2068 } 2069 break; 2070 case IFM_10_T: 2071 sc->hw.mac.autoneg = DO_AUTO_NEG; 2072 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2073 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 2074 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2075 } else { 2076 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 2077 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2078 } 2079 break; 2080 case IFM_100_FX: 2081 sc->hw.mac.autoneg = false; 2082 sc->hw.phy.autoneg_advertised = 0; 2083 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2084 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2085 else 2086 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2087 break; 2088 case IFM_10_FL: 2089 sc->hw.mac.autoneg = false; 2090 sc->hw.phy.autoneg_advertised = 0; 2091 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2092 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2093 else 2094 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2095 break; 2096 default: 2097 device_printf(sc->dev, "Unsupported media type\n"); 2098 } 2099 2100 em_if_init(ctx); 2101 2102 return (0); 2103 } 2104 2105 static int 2106 em_if_set_promisc(if_ctx_t ctx, int flags) 2107 { 2108 struct e1000_softc *sc = iflib_get_softc(ctx); 2109 if_t ifp = iflib_get_ifp(ctx); 2110 u32 reg_rctl; 2111 int mcnt = 0; 2112 2113 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2114 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 2115 if (flags & IFF_ALLMULTI) 2116 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2117 else 2118 mcnt = min(if_llmaddr_count(ifp), 2119 MAX_NUM_MULTICAST_ADDRESSES); 2120 2121 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2122 reg_rctl &= (~E1000_RCTL_MPE); 2123 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2124 2125 if (flags & IFF_PROMISC) { 2126 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2127 em_if_vlan_filter_disable(sc); 2128 /* Turn this on if you want to see bad packets */ 2129 if (em_debug_sbp) 2130 reg_rctl |= E1000_RCTL_SBP; 2131 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2132 } else { 2133 if (flags & IFF_ALLMULTI) { 2134 reg_rctl |= E1000_RCTL_MPE; 2135 reg_rctl &= ~E1000_RCTL_UPE; 2136 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2137 } 2138 if (em_if_vlan_filter_used(ctx)) 2139 em_if_vlan_filter_enable(sc); 2140 } 2141 return (0); 2142 } 2143 2144 static u_int 2145 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 2146 { 2147 u8 *mta = arg; 2148 2149 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 2150 return (0); 2151 2152 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2153 2154 return (1); 2155 } 2156 2157 /********************************************************************* 2158 * Multicast Update 2159 * 2160 * This routine is called whenever multicast address list is updated. 2161 * 2162 **********************************************************************/ 2163 static void 2164 em_if_multi_set(if_ctx_t ctx) 2165 { 2166 struct e1000_softc *sc = iflib_get_softc(ctx); 2167 if_t ifp = iflib_get_ifp(ctx); 2168 u8 *mta; /* Multicast array memory */ 2169 u32 reg_rctl = 0; 2170 int mcnt = 0; 2171 2172 IOCTL_DEBUGOUT("em_set_multi: begin"); 2173 2174 mta = sc->mta; 2175 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2176 2177 if (sc->hw.mac.type == e1000_82542 && 2178 sc->hw.revision_id == E1000_REVISION_2) { 2179 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2180 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2181 e1000_pci_clear_mwi(&sc->hw); 2182 reg_rctl |= E1000_RCTL_RST; 2183 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2184 msec_delay(5); 2185 } 2186 2187 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 2188 2189 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2190 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 2191 2192 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2193 2194 if (if_getflags(ifp) & IFF_PROMISC) 2195 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2196 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 2197 if_getflags(ifp) & IFF_ALLMULTI) { 2198 reg_rctl |= E1000_RCTL_MPE; 2199 reg_rctl &= ~E1000_RCTL_UPE; 2200 } else 2201 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2202 2203 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2204 2205 if (sc->hw.mac.type == e1000_82542 && 2206 sc->hw.revision_id == E1000_REVISION_2) { 2207 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2208 reg_rctl &= ~E1000_RCTL_RST; 2209 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2210 msec_delay(5); 2211 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2212 e1000_pci_set_mwi(&sc->hw); 2213 } 2214 } 2215 2216 /********************************************************************* 2217 * Timer routine 2218 * 2219 * This routine schedules em_if_update_admin_status() to check for 2220 * link status and to gather statistics as well as to perform some 2221 * controller-specific hardware patting. 2222 * 2223 **********************************************************************/ 2224 static void 2225 em_if_timer(if_ctx_t ctx, uint16_t qid) 2226 { 2227 if (qid != 0) 2228 return; 2229 2230 iflib_admin_intr_deferred(ctx); 2231 } 2232 2233 static void 2234 em_if_update_admin_status(if_ctx_t ctx) 2235 { 2236 struct e1000_softc *sc = iflib_get_softc(ctx); 2237 struct e1000_hw *hw = &sc->hw; 2238 device_t dev = iflib_get_dev(ctx); 2239 u32 link_check, thstat, ctrl; 2240 bool automasked = false; 2241 2242 link_check = thstat = ctrl = 0; 2243 /* Get the cached link value or read phy for real */ 2244 switch (hw->phy.media_type) { 2245 case e1000_media_type_copper: 2246 if (hw->mac.get_link_status) { 2247 if (hw->mac.type == e1000_pch_spt) 2248 msec_delay(50); 2249 /* Do the work to read phy */ 2250 e1000_check_for_link(hw); 2251 link_check = !hw->mac.get_link_status; 2252 if (link_check) /* ESB2 fix */ 2253 e1000_cfg_on_link_up(hw); 2254 } else { 2255 link_check = true; 2256 } 2257 break; 2258 case e1000_media_type_fiber: 2259 e1000_check_for_link(hw); 2260 link_check = 2261 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2262 break; 2263 case e1000_media_type_internal_serdes: 2264 e1000_check_for_link(hw); 2265 link_check = hw->mac.serdes_has_link; 2266 break; 2267 /* VF device is type_unknown */ 2268 case e1000_media_type_unknown: 2269 e1000_check_for_link(hw); 2270 link_check = !hw->mac.get_link_status; 2271 /* FALLTHROUGH */ 2272 default: 2273 break; 2274 } 2275 2276 /* Check for thermal downshift or shutdown */ 2277 if (hw->mac.type == e1000_i350) { 2278 thstat = E1000_READ_REG(hw, E1000_THSTAT); 2279 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 2280 } 2281 2282 /* Now check for a transition */ 2283 if (link_check && (sc->link_active == 0)) { 2284 e1000_get_speed_and_duplex(hw, &sc->link_speed, 2285 &sc->link_duplex); 2286 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2287 if ((sc->link_speed != SPEED_1000) && 2288 ((hw->mac.type == e1000_82571) || 2289 (hw->mac.type == e1000_82572))) { 2290 int tarc0; 2291 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2292 tarc0 &= ~TARC_SPEED_MODE_BIT; 2293 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2294 } 2295 if (bootverbose) 2296 device_printf(dev, "Link is up %d Mbps %s\n", 2297 sc->link_speed, 2298 ((sc->link_duplex == FULL_DUPLEX) ? 2299 "Full Duplex" : "Half Duplex")); 2300 sc->link_active = 1; 2301 sc->smartspeed = 0; 2302 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 2303 E1000_CTRL_EXT_LINK_MODE_GMII && 2304 (thstat & E1000_THSTAT_LINK_THROTTLE)) 2305 device_printf(dev, "Link: thermal downshift\n"); 2306 /* Delay Link Up for Phy update */ 2307 if (((hw->mac.type == e1000_i210) || 2308 (hw->mac.type == e1000_i211)) && 2309 (hw->phy.id == I210_I_PHY_ID)) 2310 msec_delay(I210_LINK_DELAY); 2311 /* Reset if the media type changed. */ 2312 if (hw->dev_spec._82575.media_changed && 2313 hw->mac.type >= igb_mac_min) { 2314 hw->dev_spec._82575.media_changed = false; 2315 sc->flags |= IGB_MEDIA_RESET; 2316 em_reset(ctx); 2317 } 2318 /* Only do TSO on gigabit for older chips due to errata */ 2319 if (hw->mac.type < igb_mac_min) 2320 automasked = em_automask_tso(ctx); 2321 2322 /* Automasking resets the interface so don't mark it up yet */ 2323 if (!automasked) 2324 iflib_link_state_change(ctx, LINK_STATE_UP, 2325 IF_Mbps(sc->link_speed)); 2326 } else if (!link_check && (sc->link_active == 1)) { 2327 sc->link_speed = 0; 2328 sc->link_duplex = 0; 2329 sc->link_active = 0; 2330 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2331 } 2332 em_update_stats_counters(sc); 2333 2334 /* Reset LAA into RAR[0] on 82571 */ 2335 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 2336 e1000_rar_set(hw, hw->mac.addr, 0); 2337 2338 if (hw->mac.type < em_mac_min) 2339 lem_smartspeed(sc); 2340 } 2341 2342 static void 2343 em_if_watchdog_reset(if_ctx_t ctx) 2344 { 2345 struct e1000_softc *sc = iflib_get_softc(ctx); 2346 2347 /* 2348 * Just count the event; iflib(4) will already trigger a 2349 * sufficient reset of the controller. 2350 */ 2351 sc->watchdog_events++; 2352 } 2353 2354 /********************************************************************* 2355 * 2356 * This routine disables all traffic on the adapter by issuing a 2357 * global reset on the MAC. 2358 * 2359 **********************************************************************/ 2360 static void 2361 em_if_stop(if_ctx_t ctx) 2362 { 2363 struct e1000_softc *sc = iflib_get_softc(ctx); 2364 2365 INIT_DEBUGOUT("em_if_stop: begin"); 2366 2367 /* I219 needs special flushing to avoid hangs */ 2368 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2369 em_flush_desc_rings(sc); 2370 2371 e1000_reset_hw(&sc->hw); 2372 if (sc->hw.mac.type >= e1000_82544) 2373 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 2374 2375 e1000_led_off(&sc->hw); 2376 e1000_cleanup_led(&sc->hw); 2377 } 2378 2379 /********************************************************************* 2380 * 2381 * Determine hardware revision. 2382 * 2383 **********************************************************************/ 2384 static void 2385 em_identify_hardware(if_ctx_t ctx) 2386 { 2387 device_t dev = iflib_get_dev(ctx); 2388 struct e1000_softc *sc = iflib_get_softc(ctx); 2389 2390 /* Make sure our PCI config space has the necessary stuff set */ 2391 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2392 2393 /* Save off the information about this board */ 2394 sc->hw.vendor_id = pci_get_vendor(dev); 2395 sc->hw.device_id = pci_get_device(dev); 2396 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2397 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2398 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2399 2400 /* Do Shared Code Init and Setup */ 2401 if (e1000_set_mac_type(&sc->hw)) { 2402 device_printf(dev, "Setup init failure\n"); 2403 return; 2404 } 2405 2406 /* Are we a VF device? */ 2407 if ((sc->hw.mac.type == e1000_vfadapt) || 2408 (sc->hw.mac.type == e1000_vfadapt_i350)) 2409 sc->vf_ifp = 1; 2410 else 2411 sc->vf_ifp = 0; 2412 } 2413 2414 static int 2415 em_allocate_pci_resources(if_ctx_t ctx) 2416 { 2417 struct e1000_softc *sc = iflib_get_softc(ctx); 2418 device_t dev = iflib_get_dev(ctx); 2419 int rid, val; 2420 2421 rid = PCIR_BAR(0); 2422 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2423 RF_ACTIVE); 2424 if (sc->memory == NULL) { 2425 device_printf(dev, 2426 "Unable to allocate bus resource: memory\n"); 2427 return (ENXIO); 2428 } 2429 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2430 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 2431 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2432 2433 /* Only older adapters use IO mapping */ 2434 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2435 /* Figure our where our IO BAR is ? */ 2436 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2437 val = pci_read_config(dev, rid, 4); 2438 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2439 break; 2440 } 2441 rid += 4; 2442 /* check for 64bit BAR */ 2443 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2444 rid += 4; 2445 } 2446 if (rid >= PCIR_CIS) { 2447 device_printf(dev, "Unable to locate IO BAR\n"); 2448 return (ENXIO); 2449 } 2450 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2451 &rid, RF_ACTIVE); 2452 if (sc->ioport == NULL) { 2453 device_printf(dev, 2454 "Unable to allocate bus resource: ioport\n"); 2455 return (ENXIO); 2456 } 2457 sc->hw.io_base = 0; 2458 sc->osdep.io_bus_space_tag = 2459 rman_get_bustag(sc->ioport); 2460 sc->osdep.io_bus_space_handle = 2461 rman_get_bushandle(sc->ioport); 2462 } 2463 2464 sc->hw.back = &sc->osdep; 2465 2466 return (0); 2467 } 2468 2469 /********************************************************************* 2470 * 2471 * Set up the MSI-X Interrupt handlers 2472 * 2473 **********************************************************************/ 2474 static int 2475 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2476 { 2477 struct e1000_softc *sc = iflib_get_softc(ctx); 2478 struct em_rx_queue *rx_que = sc->rx_queues; 2479 struct em_tx_queue *tx_que = sc->tx_queues; 2480 int error, rid, i, vector = 0, rx_vectors; 2481 char buf[16]; 2482 2483 /* First set up ring resources */ 2484 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2485 rid = vector + 1; 2486 snprintf(buf, sizeof(buf), "rxq%d", i); 2487 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2488 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2489 if (error) { 2490 device_printf(iflib_get_dev(ctx), 2491 "Failed to allocate que int %d err: %d", 2492 i, error); 2493 sc->rx_num_queues = i + 1; 2494 goto fail; 2495 } 2496 2497 rx_que->msix = vector; 2498 2499 /* 2500 * Set the bit to enable interrupt 2501 * in E1000_IMS -- bits 20 and 21 2502 * are for RX0 and RX1, note this has 2503 * NOTHING to do with the MSI-X vector 2504 */ 2505 if (sc->hw.mac.type == e1000_82574) { 2506 rx_que->eims = 1 << (20 + i); 2507 sc->ims |= rx_que->eims; 2508 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2509 } else if (sc->hw.mac.type == e1000_82575) 2510 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2511 else 2512 rx_que->eims = 1 << vector; 2513 } 2514 rx_vectors = vector; 2515 2516 vector = 0; 2517 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2518 snprintf(buf, sizeof(buf), "txq%d", i); 2519 tx_que = &sc->tx_queues[i]; 2520 iflib_softirq_alloc_generic(ctx, 2521 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2522 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2523 2524 tx_que->msix = (vector % sc->rx_num_queues); 2525 2526 /* 2527 * Set the bit to enable interrupt 2528 * in E1000_IMS -- bits 22 and 23 2529 * are for TX0 and TX1, note this has 2530 * NOTHING to do with the MSI-X vector 2531 */ 2532 if (sc->hw.mac.type == e1000_82574) { 2533 tx_que->eims = 1 << (22 + i); 2534 sc->ims |= tx_que->eims; 2535 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2536 } else if (sc->hw.mac.type == e1000_82575) { 2537 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2538 } else { 2539 tx_que->eims = 1 << i; 2540 } 2541 } 2542 2543 /* Link interrupt */ 2544 rid = rx_vectors + 1; 2545 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, 2546 em_msix_link, sc, 0, "aq"); 2547 2548 if (error) { 2549 device_printf(iflib_get_dev(ctx), 2550 "Failed to register admin handler"); 2551 goto fail; 2552 } 2553 sc->linkvec = rx_vectors; 2554 if (sc->hw.mac.type < igb_mac_min) { 2555 sc->ivars |= (8 | rx_vectors) << 16; 2556 sc->ivars |= 0x80000000; 2557 /* Enable the "Other" interrupt type for link status change */ 2558 sc->ims |= E1000_IMS_OTHER; 2559 } 2560 2561 return (0); 2562 fail: 2563 iflib_irq_free(ctx, &sc->irq); 2564 rx_que = sc->rx_queues; 2565 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2566 iflib_irq_free(ctx, &rx_que->que_irq); 2567 return (error); 2568 } 2569 2570 static void 2571 igb_configure_queues(struct e1000_softc *sc) 2572 { 2573 struct e1000_hw *hw = &sc->hw; 2574 struct em_rx_queue *rx_que; 2575 struct em_tx_queue *tx_que; 2576 u32 tmp, ivar = 0, newitr = 0; 2577 2578 /* First turn on RSS capability */ 2579 if (hw->mac.type != e1000_82575) 2580 E1000_WRITE_REG(hw, E1000_GPIE, 2581 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2582 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2583 2584 /* Turn on MSI-X */ 2585 switch (hw->mac.type) { 2586 case e1000_82580: 2587 case e1000_i350: 2588 case e1000_i354: 2589 case e1000_i210: 2590 case e1000_i211: 2591 case e1000_vfadapt: 2592 case e1000_vfadapt_i350: 2593 /* RX entries */ 2594 for (int i = 0; i < sc->rx_num_queues; i++) { 2595 u32 index = i >> 1; 2596 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2597 rx_que = &sc->rx_queues[i]; 2598 if (i & 1) { 2599 ivar &= 0xFF00FFFF; 2600 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2601 16; 2602 } else { 2603 ivar &= 0xFFFFFF00; 2604 ivar |= rx_que->msix | E1000_IVAR_VALID; 2605 } 2606 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2607 } 2608 /* TX entries */ 2609 for (int i = 0; i < sc->tx_num_queues; i++) { 2610 u32 index = i >> 1; 2611 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2612 tx_que = &sc->tx_queues[i]; 2613 if (i & 1) { 2614 ivar &= 0x00FFFFFF; 2615 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2616 24; 2617 } else { 2618 ivar &= 0xFFFF00FF; 2619 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2620 8; 2621 } 2622 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2623 sc->que_mask |= tx_que->eims; 2624 } 2625 2626 /* And for the link interrupt */ 2627 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2628 sc->link_mask = 1 << sc->linkvec; 2629 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2630 break; 2631 case e1000_82576: 2632 /* RX entries */ 2633 for (int i = 0; i < sc->rx_num_queues; i++) { 2634 u32 index = i & 0x7; /* Each IVAR has two entries */ 2635 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2636 rx_que = &sc->rx_queues[i]; 2637 if (i < 8) { 2638 ivar &= 0xFFFFFF00; 2639 ivar |= rx_que->msix | E1000_IVAR_VALID; 2640 } else { 2641 ivar &= 0xFF00FFFF; 2642 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2643 16; 2644 } 2645 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2646 sc->que_mask |= rx_que->eims; 2647 } 2648 /* TX entries */ 2649 for (int i = 0; i < sc->tx_num_queues; i++) { 2650 u32 index = i & 0x7; /* Each IVAR has two entries */ 2651 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2652 tx_que = &sc->tx_queues[i]; 2653 if (i < 8) { 2654 ivar &= 0xFFFF00FF; 2655 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2656 8; 2657 } else { 2658 ivar &= 0x00FFFFFF; 2659 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2660 24; 2661 } 2662 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2663 sc->que_mask |= tx_que->eims; 2664 } 2665 2666 /* And for the link interrupt */ 2667 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2668 sc->link_mask = 1 << sc->linkvec; 2669 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2670 break; 2671 2672 case e1000_82575: 2673 /* enable MSI-X support*/ 2674 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2675 tmp |= E1000_CTRL_EXT_PBA_CLR; 2676 /* Auto-Mask interrupts upon ICR read. */ 2677 tmp |= E1000_CTRL_EXT_EIAME; 2678 tmp |= E1000_CTRL_EXT_IRCA; 2679 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2680 2681 /* Queues */ 2682 for (int i = 0; i < sc->rx_num_queues; i++) { 2683 rx_que = &sc->rx_queues[i]; 2684 tmp = E1000_EICR_RX_QUEUE0 << i; 2685 tmp |= E1000_EICR_TX_QUEUE0 << i; 2686 rx_que->eims = tmp; 2687 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i, 2688 rx_que->eims); 2689 sc->que_mask |= rx_que->eims; 2690 } 2691 2692 /* Link */ 2693 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2694 E1000_EIMS_OTHER); 2695 sc->link_mask |= E1000_EIMS_OTHER; 2696 default: 2697 break; 2698 } 2699 2700 /* Set the igb starting interrupt rate */ 2701 if (em_max_interrupt_rate > 0) { 2702 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2703 2704 if (hw->mac.type == e1000_82575) 2705 newitr |= newitr << 16; 2706 else 2707 newitr |= E1000_EITR_CNT_IGNR; 2708 2709 for (int i = 0; i < sc->rx_num_queues; i++) { 2710 rx_que = &sc->rx_queues[i]; 2711 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2712 } 2713 } 2714 2715 return; 2716 } 2717 2718 static void 2719 em_free_pci_resources(if_ctx_t ctx) 2720 { 2721 struct e1000_softc *sc = iflib_get_softc(ctx); 2722 struct em_rx_queue *que = sc->rx_queues; 2723 device_t dev = iflib_get_dev(ctx); 2724 2725 /* Release all MSI-X queue resources */ 2726 if (sc->intr_type == IFLIB_INTR_MSIX) 2727 iflib_irq_free(ctx, &sc->irq); 2728 2729 if (que != NULL) { 2730 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2731 iflib_irq_free(ctx, &que->que_irq); 2732 } 2733 } 2734 2735 if (sc->memory != NULL) { 2736 bus_release_resource(dev, SYS_RES_MEMORY, 2737 rman_get_rid(sc->memory), sc->memory); 2738 sc->memory = NULL; 2739 } 2740 2741 if (sc->flash != NULL) { 2742 bus_release_resource(dev, SYS_RES_MEMORY, 2743 rman_get_rid(sc->flash), sc->flash); 2744 sc->flash = NULL; 2745 } 2746 2747 if (sc->ioport != NULL) { 2748 bus_release_resource(dev, SYS_RES_IOPORT, 2749 rman_get_rid(sc->ioport), sc->ioport); 2750 sc->ioport = NULL; 2751 } 2752 } 2753 2754 /* Set up MSI or MSI-X */ 2755 static int 2756 em_setup_msix(if_ctx_t ctx) 2757 { 2758 struct e1000_softc *sc = iflib_get_softc(ctx); 2759 2760 if (sc->hw.mac.type == e1000_82574) { 2761 em_enable_vectors_82574(ctx); 2762 } 2763 return (0); 2764 } 2765 2766 /********************************************************************* 2767 * 2768 * Workaround for SmartSpeed on 82541 and 82547 controllers 2769 * 2770 **********************************************************************/ 2771 static void 2772 lem_smartspeed(struct e1000_softc *sc) 2773 { 2774 u16 phy_tmp; 2775 2776 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2777 sc->hw.mac.autoneg == 0 || 2778 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2779 return; 2780 2781 if (sc->smartspeed == 0) { 2782 /* If Master/Slave config fault is asserted twice, 2783 * we assume back-to-back */ 2784 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2785 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2786 return; 2787 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2788 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2789 e1000_read_phy_reg(&sc->hw, 2790 PHY_1000T_CTRL, &phy_tmp); 2791 if(phy_tmp & CR_1000T_MS_ENABLE) { 2792 phy_tmp &= ~CR_1000T_MS_ENABLE; 2793 e1000_write_phy_reg(&sc->hw, 2794 PHY_1000T_CTRL, phy_tmp); 2795 sc->smartspeed++; 2796 if(sc->hw.mac.autoneg && 2797 !e1000_copper_link_autoneg(&sc->hw) && 2798 !e1000_read_phy_reg(&sc->hw, 2799 PHY_CONTROL, &phy_tmp)) { 2800 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2801 MII_CR_RESTART_AUTO_NEG); 2802 e1000_write_phy_reg(&sc->hw, 2803 PHY_CONTROL, phy_tmp); 2804 } 2805 } 2806 } 2807 return; 2808 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2809 /* If still no link, perhaps using 2/3 pair cable */ 2810 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2811 phy_tmp |= CR_1000T_MS_ENABLE; 2812 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2813 if(sc->hw.mac.autoneg && 2814 !e1000_copper_link_autoneg(&sc->hw) && 2815 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2816 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2817 MII_CR_RESTART_AUTO_NEG); 2818 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2819 } 2820 } 2821 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2822 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2823 sc->smartspeed = 0; 2824 } 2825 2826 /********************************************************************* 2827 * 2828 * Initialize the DMA Coalescing feature 2829 * 2830 **********************************************************************/ 2831 static void 2832 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2833 { 2834 device_t dev = sc->dev; 2835 struct e1000_hw *hw = &sc->hw; 2836 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2837 u16 hwm; 2838 u16 max_frame_size; 2839 2840 if (hw->mac.type == e1000_i211) 2841 return; 2842 2843 max_frame_size = sc->shared->isc_max_frame_size; 2844 if (hw->mac.type > e1000_82580) { 2845 2846 if (sc->dmac == 0) { /* Disabling it */ 2847 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2848 return; 2849 } else 2850 device_printf(dev, "DMA Coalescing enabled\n"); 2851 2852 /* Set starting threshold */ 2853 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2854 2855 hwm = 64 * pba - max_frame_size / 16; 2856 if (hwm < 64 * (pba - 6)) 2857 hwm = 64 * (pba - 6); 2858 reg = E1000_READ_REG(hw, E1000_FCRTC); 2859 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2860 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2861 & E1000_FCRTC_RTH_COAL_MASK); 2862 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2863 2864 2865 dmac = pba - max_frame_size / 512; 2866 if (dmac < pba - 10) 2867 dmac = pba - 10; 2868 reg = E1000_READ_REG(hw, E1000_DMACR); 2869 reg &= ~E1000_DMACR_DMACTHR_MASK; 2870 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2871 & E1000_DMACR_DMACTHR_MASK); 2872 2873 /* transition to L0x or L1 if available..*/ 2874 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2875 2876 /* Check if status is 2.5Gb backplane connection 2877 * before configuration of watchdog timer, which is 2878 * in msec values in 12.8usec intervals 2879 * watchdog timer= msec values in 32usec intervals 2880 * for non 2.5Gb connection 2881 */ 2882 if (hw->mac.type == e1000_i354) { 2883 int status = E1000_READ_REG(hw, E1000_STATUS); 2884 if ((status & E1000_STATUS_2P5_SKU) && 2885 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2886 reg |= ((sc->dmac * 5) >> 6); 2887 else 2888 reg |= (sc->dmac >> 5); 2889 } else { 2890 reg |= (sc->dmac >> 5); 2891 } 2892 2893 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2894 2895 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2896 2897 /* Set the interval before transition */ 2898 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2899 if (hw->mac.type == e1000_i350) 2900 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2901 /* 2902 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2903 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2904 */ 2905 if (hw->mac.type == e1000_i354) { 2906 int status = E1000_READ_REG(hw, E1000_STATUS); 2907 if ((status & E1000_STATUS_2P5_SKU) && 2908 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2909 reg |= 0xA; 2910 else 2911 reg |= 0x4; 2912 } else { 2913 reg |= 0x4; 2914 } 2915 2916 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2917 2918 /* free space in tx packet buffer to wake from DMA coal */ 2919 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2920 (2 * max_frame_size)) >> 6); 2921 2922 /* make low power state decision controlled by DMA coal */ 2923 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2924 reg &= ~E1000_PCIEMISC_LX_DECISION; 2925 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2926 2927 } else if (hw->mac.type == e1000_82580) { 2928 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2929 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2930 reg & ~E1000_PCIEMISC_LX_DECISION); 2931 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2932 } 2933 } 2934 /********************************************************************* 2935 * The 3 following flush routines are used as a workaround in the 2936 * I219 client parts and only for them. 2937 * 2938 * em_flush_tx_ring - remove all descriptors from the tx_ring 2939 * 2940 * We want to clear all pending descriptors from the TX ring. 2941 * zeroing happens when the HW reads the regs. We assign the ring itself as 2942 * the data of the next descriptor. We don't care about the data we are about 2943 * to reset the HW. 2944 **********************************************************************/ 2945 static void 2946 em_flush_tx_ring(struct e1000_softc *sc) 2947 { 2948 struct e1000_hw *hw = &sc->hw; 2949 struct tx_ring *txr = &sc->tx_queues->txr; 2950 struct e1000_tx_desc *txd; 2951 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2952 u16 size = 512; 2953 2954 tctl = E1000_READ_REG(hw, E1000_TCTL); 2955 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2956 2957 txd = &txr->tx_base[txr->tx_cidx_processed]; 2958 2959 /* Just use the ring as a dummy buffer addr */ 2960 txd->buffer_addr = txr->tx_paddr; 2961 txd->lower.data = htole32(txd_lower | size); 2962 txd->upper.data = 0; 2963 2964 /* flush descriptors to memory before notifying the HW */ 2965 wmb(); 2966 2967 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2968 mb(); 2969 usec_delay(250); 2970 } 2971 2972 /********************************************************************* 2973 * em_flush_rx_ring - remove all descriptors from the rx_ring 2974 * 2975 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2976 **********************************************************************/ 2977 static void 2978 em_flush_rx_ring(struct e1000_softc *sc) 2979 { 2980 struct e1000_hw *hw = &sc->hw; 2981 u32 rctl, rxdctl; 2982 2983 rctl = E1000_READ_REG(hw, E1000_RCTL); 2984 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2985 E1000_WRITE_FLUSH(hw); 2986 usec_delay(150); 2987 2988 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2989 /* zero the lower 14 bits (prefetch and host thresholds) */ 2990 rxdctl &= 0xffffc000; 2991 /* 2992 * update thresholds: prefetch threshold to 31, host threshold to 1 2993 * and make sure the granularity is "descriptors" and not 2994 * "cache lines" 2995 */ 2996 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2997 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2998 2999 /* momentarily enable the RX ring for the changes to take effect */ 3000 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 3001 E1000_WRITE_FLUSH(hw); 3002 usec_delay(150); 3003 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3004 } 3005 3006 /********************************************************************* 3007 * em_flush_desc_rings - remove all descriptors from the descriptor rings 3008 * 3009 * In I219, the descriptor rings must be emptied before resetting the HW 3010 * or before changing the device state to D3 during runtime (runtime PM). 3011 * 3012 * Failure to do this will cause the HW to enter a unit hang state which can 3013 * only be released by PCI reset on the device 3014 * 3015 **********************************************************************/ 3016 static void 3017 em_flush_desc_rings(struct e1000_softc *sc) 3018 { 3019 struct e1000_hw *hw = &sc->hw; 3020 device_t dev = sc->dev; 3021 u16 hang_state; 3022 u32 fext_nvm11, tdlen; 3023 3024 /* First, disable MULR fix in FEXTNVM11 */ 3025 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 3026 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3027 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 3028 3029 /* do nothing if we're not in faulty state, or the queue is empty */ 3030 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 3031 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3032 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3033 return; 3034 em_flush_tx_ring(sc); 3035 3036 /* recheck, maybe the fault is caused by the rx ring */ 3037 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3038 if (hang_state & FLUSH_DESC_REQUIRED) 3039 em_flush_rx_ring(sc); 3040 } 3041 3042 3043 /********************************************************************* 3044 * 3045 * Initialize the hardware to a configuration as specified by the 3046 * sc structure. 3047 * 3048 **********************************************************************/ 3049 static void 3050 em_reset(if_ctx_t ctx) 3051 { 3052 device_t dev = iflib_get_dev(ctx); 3053 struct e1000_softc *sc = iflib_get_softc(ctx); 3054 if_t ifp = iflib_get_ifp(ctx); 3055 struct e1000_hw *hw = &sc->hw; 3056 u32 rx_buffer_size; 3057 u32 pba; 3058 3059 INIT_DEBUGOUT("em_reset: begin"); 3060 /* Let the firmware know the OS is in control */ 3061 em_get_hw_control(sc); 3062 3063 /* Set up smart power down as default off on newer adapters. */ 3064 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 3065 hw->mac.type == e1000_82572)) { 3066 u16 phy_tmp = 0; 3067 3068 /* Speed up time to link by disabling smart power down. */ 3069 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 3070 phy_tmp &= ~IGP02E1000_PM_SPD; 3071 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 3072 } 3073 3074 /* 3075 * Packet Buffer Allocation (PBA) 3076 * Writing PBA sets the receive portion of the buffer 3077 * the remainder is used for the transmit buffer. 3078 */ 3079 switch (hw->mac.type) { 3080 /* 82547: Total Packet Buffer is 40K */ 3081 case e1000_82547: 3082 case e1000_82547_rev_2: 3083 if (hw->mac.max_frame_size > 8192) 3084 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 3085 else 3086 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 3087 break; 3088 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 3089 case e1000_82571: 3090 case e1000_82572: 3091 case e1000_80003es2lan: 3092 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 3093 break; 3094 /* 82573: Total Packet Buffer is 32K */ 3095 case e1000_82573: 3096 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 3097 break; 3098 case e1000_82574: 3099 case e1000_82583: 3100 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 3101 break; 3102 case e1000_ich8lan: 3103 pba = E1000_PBA_8K; 3104 break; 3105 case e1000_ich9lan: 3106 case e1000_ich10lan: 3107 /* Boost Receive side for jumbo frames */ 3108 if (hw->mac.max_frame_size > 4096) 3109 pba = E1000_PBA_14K; 3110 else 3111 pba = E1000_PBA_10K; 3112 break; 3113 case e1000_pchlan: 3114 case e1000_pch2lan: 3115 case e1000_pch_lpt: 3116 case e1000_pch_spt: 3117 case e1000_pch_cnp: 3118 case e1000_pch_tgp: 3119 case e1000_pch_adp: 3120 case e1000_pch_mtp: 3121 case e1000_pch_ptp: 3122 pba = E1000_PBA_26K; 3123 break; 3124 case e1000_82575: 3125 pba = E1000_PBA_32K; 3126 break; 3127 case e1000_82576: 3128 case e1000_vfadapt: 3129 pba = E1000_READ_REG(hw, E1000_RXPBS); 3130 pba &= E1000_RXPBS_SIZE_MASK_82576; 3131 break; 3132 case e1000_82580: 3133 case e1000_i350: 3134 case e1000_i354: 3135 case e1000_vfadapt_i350: 3136 pba = E1000_READ_REG(hw, E1000_RXPBS); 3137 pba = e1000_rxpbs_adjust_82580(pba); 3138 break; 3139 case e1000_i210: 3140 case e1000_i211: 3141 pba = E1000_PBA_34K; 3142 break; 3143 default: 3144 /* Remaining devices assumed to have Packet Buffer of 64K. */ 3145 if (hw->mac.max_frame_size > 8192) 3146 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 3147 else 3148 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 3149 } 3150 3151 /* Special needs in case of Jumbo frames */ 3152 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 3153 u32 tx_space, min_tx, min_rx; 3154 pba = E1000_READ_REG(hw, E1000_PBA); 3155 tx_space = pba >> 16; 3156 pba &= 0xffff; 3157 min_tx = (hw->mac.max_frame_size + 3158 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 3159 min_tx = roundup2(min_tx, 1024); 3160 min_tx >>= 10; 3161 min_rx = hw->mac.max_frame_size; 3162 min_rx = roundup2(min_rx, 1024); 3163 min_rx >>= 10; 3164 if (tx_space < min_tx && 3165 ((min_tx - tx_space) < pba)) { 3166 pba = pba - (min_tx - tx_space); 3167 /* 3168 * if short on rx space, rx wins 3169 * and must trump tx adjustment 3170 */ 3171 if (pba < min_rx) 3172 pba = min_rx; 3173 } 3174 E1000_WRITE_REG(hw, E1000_PBA, pba); 3175 } 3176 3177 if (hw->mac.type < igb_mac_min) 3178 E1000_WRITE_REG(hw, E1000_PBA, pba); 3179 3180 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 3181 3182 /* 3183 * These parameters control the automatic generation (Tx) and 3184 * response (Rx) to Ethernet PAUSE frames. 3185 * - High water mark should allow for at least two frames to be 3186 * received after sending an XOFF. 3187 * - Low water mark works best when it is very near the high water 3188 mark. 3189 * This allows the receiver to restart by sending XON when it has 3190 * drained a bit. Here we use an arbitrary value of 1500 which will 3191 * restart after one full frame is pulled from the buffer. There 3192 * could be several smaller frames in the buffer and if so they will 3193 * not trigger the XON until their total number reduces the buffer 3194 * by 1500. 3195 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 3196 */ 3197 rx_buffer_size = (pba & 0xffff) << 10; 3198 hw->fc.high_water = rx_buffer_size - 3199 roundup2(hw->mac.max_frame_size, 1024); 3200 hw->fc.low_water = hw->fc.high_water - 1500; 3201 3202 if (sc->fc) /* locally set flow control value? */ 3203 hw->fc.requested_mode = sc->fc; 3204 else 3205 hw->fc.requested_mode = e1000_fc_full; 3206 3207 if (hw->mac.type == e1000_80003es2lan) 3208 hw->fc.pause_time = 0xFFFF; 3209 else 3210 hw->fc.pause_time = EM_FC_PAUSE_TIME; 3211 3212 hw->fc.send_xon = true; 3213 3214 /* Device specific overrides/settings */ 3215 switch (hw->mac.type) { 3216 case e1000_pchlan: 3217 /* Workaround: no TX flow ctrl for PCH */ 3218 hw->fc.requested_mode = e1000_fc_rx_pause; 3219 hw->fc.pause_time = 0xFFFF; /* override */ 3220 if (if_getmtu(ifp) > ETHERMTU) { 3221 hw->fc.high_water = 0x3500; 3222 hw->fc.low_water = 0x1500; 3223 } else { 3224 hw->fc.high_water = 0x5000; 3225 hw->fc.low_water = 0x3000; 3226 } 3227 hw->fc.refresh_time = 0x1000; 3228 break; 3229 case e1000_pch2lan: 3230 case e1000_pch_lpt: 3231 case e1000_pch_spt: 3232 case e1000_pch_cnp: 3233 case e1000_pch_tgp: 3234 case e1000_pch_adp: 3235 case e1000_pch_mtp: 3236 case e1000_pch_ptp: 3237 hw->fc.high_water = 0x5C20; 3238 hw->fc.low_water = 0x5048; 3239 hw->fc.pause_time = 0x0650; 3240 hw->fc.refresh_time = 0x0400; 3241 /* Jumbos need adjusted PBA */ 3242 if (if_getmtu(ifp) > ETHERMTU) 3243 E1000_WRITE_REG(hw, E1000_PBA, 12); 3244 else 3245 E1000_WRITE_REG(hw, E1000_PBA, 26); 3246 break; 3247 case e1000_82575: 3248 case e1000_82576: 3249 /* 8-byte granularity */ 3250 hw->fc.low_water = hw->fc.high_water - 8; 3251 break; 3252 case e1000_82580: 3253 case e1000_i350: 3254 case e1000_i354: 3255 case e1000_i210: 3256 case e1000_i211: 3257 case e1000_vfadapt: 3258 case e1000_vfadapt_i350: 3259 /* 16-byte granularity */ 3260 hw->fc.low_water = hw->fc.high_water - 16; 3261 break; 3262 case e1000_ich9lan: 3263 case e1000_ich10lan: 3264 if (if_getmtu(ifp) > ETHERMTU) { 3265 hw->fc.high_water = 0x2800; 3266 hw->fc.low_water = hw->fc.high_water - 8; 3267 break; 3268 } 3269 /* FALLTHROUGH */ 3270 default: 3271 if (hw->mac.type == e1000_80003es2lan) 3272 hw->fc.pause_time = 0xFFFF; 3273 break; 3274 } 3275 3276 /* I219 needs some special flushing to avoid hangs */ 3277 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 3278 em_flush_desc_rings(sc); 3279 3280 /* Issue a global reset */ 3281 e1000_reset_hw(hw); 3282 if (hw->mac.type >= igb_mac_min) { 3283 E1000_WRITE_REG(hw, E1000_WUC, 0); 3284 } else { 3285 E1000_WRITE_REG(hw, E1000_WUFC, 0); 3286 em_disable_aspm(sc); 3287 } 3288 if (sc->flags & IGB_MEDIA_RESET) { 3289 e1000_setup_init_funcs(hw, true); 3290 e1000_get_bus_info(hw); 3291 sc->flags &= ~IGB_MEDIA_RESET; 3292 } 3293 /* and a re-init */ 3294 if (e1000_init_hw(hw) < 0) { 3295 device_printf(dev, "Hardware Initialization Failed\n"); 3296 return; 3297 } 3298 if (hw->mac.type >= igb_mac_min) 3299 igb_init_dmac(sc, pba); 3300 3301 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 3302 sc->pba = pba; 3303 3304 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 3305 e1000_get_phy_info(hw); 3306 e1000_check_for_link(hw); 3307 } 3308 3309 /* 3310 * Initialise the RSS mapping for NICs that support multiple transmit/ 3311 * receive rings. 3312 */ 3313 3314 #define RSSKEYLEN 10 3315 static void 3316 em_initialize_rss_mapping(struct e1000_softc *sc) 3317 { 3318 uint8_t rss_key[4 * RSSKEYLEN]; 3319 uint32_t reta = 0; 3320 struct e1000_hw *hw = &sc->hw; 3321 int i; 3322 3323 /* 3324 * Configure RSS key 3325 */ 3326 arc4rand(rss_key, sizeof(rss_key), 0); 3327 for (i = 0; i < RSSKEYLEN; ++i) { 3328 uint32_t rssrk = 0; 3329 3330 rssrk = EM_RSSRK_VAL(rss_key, i); 3331 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 3332 } 3333 3334 /* 3335 * Configure RSS redirect table in following fashion: 3336 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3337 */ 3338 for (i = 0; i < sizeof(reta); ++i) { 3339 uint32_t q; 3340 3341 q = (i % sc->rx_num_queues) << 7; 3342 reta |= q << (8 * i); 3343 } 3344 3345 for (i = 0; i < 32; ++i) 3346 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 3347 3348 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 3349 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3350 E1000_MRQC_RSS_FIELD_IPV4 | 3351 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 3352 E1000_MRQC_RSS_FIELD_IPV6_EX | 3353 E1000_MRQC_RSS_FIELD_IPV6); 3354 } 3355 3356 static void 3357 igb_initialize_rss_mapping(struct e1000_softc *sc) 3358 { 3359 struct e1000_hw *hw = &sc->hw; 3360 int i; 3361 int queue_id; 3362 u32 reta; 3363 u32 rss_key[10], mrqc, shift = 0; 3364 3365 /* XXX? */ 3366 if (hw->mac.type == e1000_82575) 3367 shift = 6; 3368 3369 /* 3370 * The redirection table controls which destination 3371 * queue each bucket redirects traffic to. 3372 * Each DWORD represents four queues, with the LSB 3373 * being the first queue in the DWORD. 3374 * 3375 * This just allocates buckets to queues using round-robin 3376 * allocation. 3377 * 3378 * NOTE: It Just Happens to line up with the default 3379 * RSS allocation method. 3380 */ 3381 3382 /* Warning FM follows */ 3383 reta = 0; 3384 for (i = 0; i < 128; i++) { 3385 #ifdef RSS 3386 queue_id = rss_get_indirection_to_bucket(i); 3387 /* 3388 * If we have more queues than buckets, we'll 3389 * end up mapping buckets to a subset of the 3390 * queues. 3391 * 3392 * If we have more buckets than queues, we'll 3393 * end up instead assigning multiple buckets 3394 * to queues. 3395 * 3396 * Both are suboptimal, but we need to handle 3397 * the case so we don't go out of bounds 3398 * indexing arrays and such. 3399 */ 3400 queue_id = queue_id % sc->rx_num_queues; 3401 #else 3402 queue_id = (i % sc->rx_num_queues); 3403 #endif 3404 /* Adjust if required */ 3405 queue_id = queue_id << shift; 3406 3407 /* 3408 * The low 8 bits are for hash value (n+0); 3409 * The next 8 bits are for hash value (n+1), etc. 3410 */ 3411 reta = reta >> 8; 3412 reta = reta | ( ((uint32_t) queue_id) << 24); 3413 if ((i & 3) == 3) { 3414 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3415 reta = 0; 3416 } 3417 } 3418 3419 /* Now fill in hash table */ 3420 3421 /* 3422 * MRQC: Multiple Receive Queues Command 3423 * Set queuing to RSS control, number depends on the device. 3424 */ 3425 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3426 3427 #ifdef RSS 3428 /* XXX ew typecasting */ 3429 rss_getkey((uint8_t *) &rss_key); 3430 #else 3431 arc4rand(&rss_key, sizeof(rss_key), 0); 3432 #endif 3433 for (i = 0; i < 10; i++) 3434 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3435 3436 /* 3437 * Configure the RSS fields to hash upon. 3438 */ 3439 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3440 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3441 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3442 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3443 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3444 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3445 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3446 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3447 3448 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3449 } 3450 3451 /********************************************************************* 3452 * 3453 * Setup networking device structure and register interface media. 3454 * 3455 **********************************************************************/ 3456 static int 3457 em_setup_interface(if_ctx_t ctx) 3458 { 3459 if_t ifp = iflib_get_ifp(ctx); 3460 struct e1000_softc *sc = iflib_get_softc(ctx); 3461 if_softc_ctx_t scctx = sc->shared; 3462 3463 INIT_DEBUGOUT("em_setup_interface: begin"); 3464 3465 /* Single Queue */ 3466 if (sc->tx_num_queues == 1) { 3467 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3468 if_setsendqready(ifp); 3469 } 3470 3471 /* 3472 * Specify the media types supported by this adapter and register 3473 * callbacks to update media and link information 3474 */ 3475 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3476 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3477 u_char fiber_type = IFM_1000_SX; /* default type */ 3478 3479 if (sc->hw.mac.type == e1000_82545) 3480 fiber_type = IFM_1000_LX; 3481 ifmedia_add(sc->media, 3482 IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3483 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3484 } else { 3485 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3486 ifmedia_add(sc->media, 3487 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3488 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3489 ifmedia_add(sc->media, 3490 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3491 if (sc->hw.phy.type != e1000_phy_ife) { 3492 ifmedia_add(sc->media, 3493 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3494 ifmedia_add(sc->media, 3495 IFM_ETHER | IFM_1000_T, 0, NULL); 3496 } 3497 } 3498 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3499 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3500 return (0); 3501 } 3502 3503 static int 3504 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3505 int ntxqs, int ntxqsets) 3506 { 3507 struct e1000_softc *sc = iflib_get_softc(ctx); 3508 if_softc_ctx_t scctx = sc->shared; 3509 int error = E1000_SUCCESS; 3510 struct em_tx_queue *que; 3511 int i, j; 3512 3513 MPASS(sc->tx_num_queues > 0); 3514 MPASS(sc->tx_num_queues == ntxqsets); 3515 3516 /* First allocate the top level queue structs */ 3517 if (!(sc->tx_queues = 3518 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3519 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3520 device_printf(iflib_get_dev(ctx), 3521 "Unable to allocate queue memory\n"); 3522 return(ENOMEM); 3523 } 3524 3525 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3526 /* Set up some basics */ 3527 3528 struct tx_ring *txr = &que->txr; 3529 txr->sc = que->sc = sc; 3530 que->me = txr->me = i; 3531 3532 /* Allocate report status array */ 3533 if (!(txr->tx_rsq = 3534 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], 3535 M_DEVBUF, M_NOWAIT | M_ZERO))) { 3536 device_printf(iflib_get_dev(ctx), 3537 "failed to allocate rs_idxs memory\n"); 3538 error = ENOMEM; 3539 goto fail; 3540 } 3541 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3542 txr->tx_rsq[j] = QIDX_INVALID; 3543 /* get the virtual and physical address of hardware queues */ 3544 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3545 txr->tx_paddr = paddrs[i*ntxqs]; 3546 } 3547 3548 if (bootverbose) 3549 device_printf(iflib_get_dev(ctx), 3550 "allocated for %d tx_queues\n", sc->tx_num_queues); 3551 return (0); 3552 fail: 3553 em_if_queues_free(ctx); 3554 return (error); 3555 } 3556 3557 static int 3558 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3559 int nrxqs, int nrxqsets) 3560 { 3561 struct e1000_softc *sc = iflib_get_softc(ctx); 3562 int error = E1000_SUCCESS; 3563 struct em_rx_queue *que; 3564 int i; 3565 3566 MPASS(sc->rx_num_queues > 0); 3567 MPASS(sc->rx_num_queues == nrxqsets); 3568 3569 /* First allocate the top level queue structs */ 3570 if (!(sc->rx_queues = 3571 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3572 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3573 device_printf(iflib_get_dev(ctx), 3574 "Unable to allocate queue memory\n"); 3575 error = ENOMEM; 3576 goto fail; 3577 } 3578 3579 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3580 /* Set up some basics */ 3581 struct rx_ring *rxr = &que->rxr; 3582 rxr->sc = que->sc = sc; 3583 rxr->que = que; 3584 que->me = rxr->me = i; 3585 3586 /* get the virtual and physical address of hardware queues */ 3587 rxr->rx_base = 3588 (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3589 rxr->rx_paddr = paddrs[i*nrxqs]; 3590 } 3591 3592 if (bootverbose) 3593 device_printf(iflib_get_dev(ctx), 3594 "allocated for %d rx_queues\n", sc->rx_num_queues); 3595 3596 return (0); 3597 fail: 3598 em_if_queues_free(ctx); 3599 return (error); 3600 } 3601 3602 static void 3603 em_if_queues_free(if_ctx_t ctx) 3604 { 3605 struct e1000_softc *sc = iflib_get_softc(ctx); 3606 struct em_tx_queue *tx_que = sc->tx_queues; 3607 struct em_rx_queue *rx_que = sc->rx_queues; 3608 3609 if (tx_que != NULL) { 3610 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3611 struct tx_ring *txr = &tx_que->txr; 3612 if (txr->tx_rsq == NULL) 3613 break; 3614 3615 free(txr->tx_rsq, M_DEVBUF); 3616 txr->tx_rsq = NULL; 3617 } 3618 free(sc->tx_queues, M_DEVBUF); 3619 sc->tx_queues = NULL; 3620 } 3621 3622 if (rx_que != NULL) { 3623 free(sc->rx_queues, M_DEVBUF); 3624 sc->rx_queues = NULL; 3625 } 3626 } 3627 3628 /********************************************************************* 3629 * 3630 * Enable transmit unit. 3631 * 3632 **********************************************************************/ 3633 static void 3634 em_initialize_transmit_unit(if_ctx_t ctx) 3635 { 3636 struct e1000_softc *sc = iflib_get_softc(ctx); 3637 if_softc_ctx_t scctx = sc->shared; 3638 struct em_tx_queue *que; 3639 struct tx_ring *txr; 3640 struct e1000_hw *hw = &sc->hw; 3641 u32 tctl, txdctl = 0, tarc, tipg = 0; 3642 3643 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3644 3645 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3646 u64 bus_addr; 3647 caddr_t offp, endp; 3648 3649 que = &sc->tx_queues[i]; 3650 txr = &que->txr; 3651 bus_addr = txr->tx_paddr; 3652 3653 /* Clear checksum offload context. */ 3654 offp = (caddr_t)&txr->csum_flags; 3655 endp = (caddr_t)(txr + 1); 3656 bzero(offp, endp - offp); 3657 3658 /* Base and Len of TX Ring */ 3659 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3660 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3661 E1000_WRITE_REG(hw, E1000_TDBAH(i), (u32)(bus_addr >> 32)); 3662 E1000_WRITE_REG(hw, E1000_TDBAL(i), (u32)bus_addr); 3663 /* Init the HEAD/TAIL indices */ 3664 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3665 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3666 3667 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3668 E1000_READ_REG(hw, E1000_TDBAL(i)), 3669 E1000_READ_REG(hw, E1000_TDLEN(i))); 3670 3671 txdctl = 0; /* clear txdctl */ 3672 txdctl |= 0x1f; /* PTHRESH */ 3673 txdctl |= 1 << 8; /* HTHRESH */ 3674 txdctl |= 1 << 16;/* WTHRESH */ 3675 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3676 txdctl |= E1000_TXDCTL_GRAN; 3677 txdctl |= 1 << 25; /* LWTHRESH */ 3678 3679 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3680 } 3681 3682 /* Set the default values for the Tx Inter Packet Gap timer */ 3683 switch (hw->mac.type) { 3684 case e1000_80003es2lan: 3685 tipg = DEFAULT_82543_TIPG_IPGR1; 3686 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3687 E1000_TIPG_IPGR2_SHIFT; 3688 break; 3689 case e1000_82542: 3690 tipg = DEFAULT_82542_TIPG_IPGT; 3691 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3692 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3693 break; 3694 default: 3695 if (hw->phy.media_type == e1000_media_type_fiber || 3696 hw->phy.media_type == e1000_media_type_internal_serdes) 3697 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3698 else 3699 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3700 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3701 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3702 } 3703 3704 if (hw->mac.type < igb_mac_min) { 3705 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3706 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3707 3708 if (sc->tx_int_delay.value > 0) 3709 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3710 } 3711 3712 if (hw->mac.type >= e1000_82540) 3713 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3714 3715 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3716 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3717 tarc |= TARC_SPEED_MODE_BIT; 3718 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3719 } else if (hw->mac.type == e1000_80003es2lan) { 3720 /* errata: program both queues to unweighted RR */ 3721 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3722 tarc |= 1; 3723 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3724 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3725 tarc |= 1; 3726 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3727 } else if (hw->mac.type == e1000_82574) { 3728 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3729 tarc |= TARC_ERRATA_BIT; 3730 if ( sc->tx_num_queues > 1) { 3731 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3732 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3733 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3734 } else 3735 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3736 } 3737 3738 /* Program the Transmit Control Register */ 3739 tctl = E1000_READ_REG(hw, E1000_TCTL); 3740 tctl &= ~E1000_TCTL_CT; 3741 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3742 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3743 3744 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3745 tctl |= E1000_TCTL_MULR; 3746 3747 /* This write will effectively turn on the transmit unit. */ 3748 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3749 3750 /* SPT and KBL errata workarounds */ 3751 if (hw->mac.type == e1000_pch_spt) { 3752 u32 reg; 3753 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3754 reg |= E1000_RCTL_RDMTS_HEX; 3755 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3756 /* i218-i219 Specification Update 1.5.4.5 */ 3757 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3758 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3759 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3760 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3761 } 3762 } 3763 3764 /********************************************************************* 3765 * 3766 * Enable receive unit. 3767 * 3768 **********************************************************************/ 3769 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3770 3771 static void 3772 em_initialize_receive_unit(if_ctx_t ctx) 3773 { 3774 struct e1000_softc *sc = iflib_get_softc(ctx); 3775 if_softc_ctx_t scctx = sc->shared; 3776 if_t ifp = iflib_get_ifp(ctx); 3777 struct e1000_hw *hw = &sc->hw; 3778 struct em_rx_queue *que; 3779 int i; 3780 uint32_t rctl, rxcsum; 3781 3782 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3783 3784 /* 3785 * Make sure receives are disabled while setting 3786 * up the descriptor ring 3787 */ 3788 rctl = E1000_READ_REG(hw, E1000_RCTL); 3789 /* Do not disable if ever enabled on this hardware */ 3790 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3791 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3792 3793 /* Setup the Receive Control Register */ 3794 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3795 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3796 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3797 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3798 3799 /* Do not store bad packets */ 3800 rctl &= ~E1000_RCTL_SBP; 3801 3802 /* Enable Long Packet receive */ 3803 if (if_getmtu(ifp) > ETHERMTU) 3804 rctl |= E1000_RCTL_LPE; 3805 else 3806 rctl &= ~E1000_RCTL_LPE; 3807 3808 /* Strip the CRC */ 3809 if (!em_disable_crc_stripping) 3810 rctl |= E1000_RCTL_SECRC; 3811 3812 /* lem/em default interrupt moderation */ 3813 if (hw->mac.type < igb_mac_min) { 3814 if (hw->mac.type >= e1000_82540) { 3815 E1000_WRITE_REG(hw, E1000_RADV, 3816 sc->rx_abs_int_delay.value); 3817 3818 /* Set the default interrupt throttling rate */ 3819 E1000_WRITE_REG(hw, E1000_ITR, 3820 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3821 } 3822 3823 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3824 * long latencies are observed, like Lenovo X60. This 3825 * change eliminates the problem, but since having positive 3826 * values in RDTR is a known source of problems on other 3827 * platforms another solution is being sought. 3828 */ 3829 if (hw->mac.type == e1000_82573) 3830 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3831 else 3832 E1000_WRITE_REG(hw, E1000_RDTR, 3833 sc->rx_int_delay.value); 3834 } 3835 3836 if (hw->mac.type >= em_mac_min) { 3837 uint32_t rfctl; 3838 /* Use extended rx descriptor formats */ 3839 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3840 rfctl |= E1000_RFCTL_EXTEN; 3841 3842 /* 3843 * When using MSI-X interrupts we need to throttle 3844 * using the EITR register (82574 only) 3845 */ 3846 if (hw->mac.type == e1000_82574) { 3847 for (int i = 0; i < 4; i++) 3848 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3849 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3850 /* Disable accelerated acknowledge */ 3851 rfctl |= E1000_RFCTL_ACK_DIS; 3852 } 3853 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3854 } 3855 3856 /* Set up L3 and L4 csum Rx descriptor offloads */ 3857 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3858 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3859 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3860 if (hw->mac.type > e1000_82575) 3861 rxcsum |= E1000_RXCSUM_CRCOFL; 3862 else if (hw->mac.type < em_mac_min && 3863 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3864 rxcsum |= E1000_RXCSUM_IPV6OFL; 3865 } else { 3866 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3867 if (hw->mac.type > e1000_82575) 3868 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3869 else if (hw->mac.type < em_mac_min) 3870 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3871 } 3872 3873 if (sc->rx_num_queues > 1) { 3874 /* RSS hash needed in the Rx descriptor */ 3875 rxcsum |= E1000_RXCSUM_PCSD; 3876 3877 if (hw->mac.type >= igb_mac_min) 3878 igb_initialize_rss_mapping(sc); 3879 else 3880 em_initialize_rss_mapping(sc); 3881 } 3882 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3883 3884 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3885 struct rx_ring *rxr = &que->rxr; 3886 /* Setup the Base and Length of the Rx Descriptor Ring */ 3887 u64 bus_addr = rxr->rx_paddr; 3888 #if 0 3889 u32 rdt = sc->rx_num_queues -1; /* default */ 3890 #endif 3891 3892 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3893 scctx->isc_nrxd[0] * 3894 sizeof(union e1000_rx_desc_extended)); 3895 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3896 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3897 /* Setup the Head and Tail Descriptor Pointers */ 3898 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3899 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3900 } 3901 3902 /* 3903 * Set PTHRESH for improved jumbo performance 3904 * According to 10.2.5.11 of Intel 82574 Datasheet, 3905 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3906 * Only write to RXDCTL(1) if there is a need for different 3907 * settings. 3908 */ 3909 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3910 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3911 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3912 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3913 } else if (hw->mac.type == e1000_82574) { 3914 for (int i = 0; i < sc->rx_num_queues; i++) { 3915 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3916 rxdctl |= 0x20; /* PTHRESH */ 3917 rxdctl |= 4 << 8; /* HTHRESH */ 3918 rxdctl |= 4 << 16;/* WTHRESH */ 3919 rxdctl |= 1 << 24; /* Switch to granularity */ 3920 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3921 } 3922 } else if (hw->mac.type >= igb_mac_min) { 3923 u32 psize, srrctl = 0; 3924 3925 if (if_getmtu(ifp) > ETHERMTU) { 3926 psize = scctx->isc_max_frame_size; 3927 /* are we on a vlan? */ 3928 if (if_vlantrunkinuse(ifp)) 3929 psize += VLAN_TAG_SIZE; 3930 3931 if (sc->vf_ifp) 3932 e1000_rlpml_set_vf(hw, psize); 3933 else 3934 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3935 } 3936 3937 /* Set maximum packet buffer len */ 3938 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3939 E1000_SRRCTL_BSIZEPKT_SHIFT; 3940 3941 /* 3942 * If TX flow control is disabled and there's >1 queue 3943 * defined, enable DROP. 3944 * 3945 * This drops frames rather than hanging the RX MAC for all 3946 * queues. 3947 */ 3948 if ((sc->rx_num_queues > 1) && 3949 (sc->fc == e1000_fc_none || 3950 sc->fc == e1000_fc_rx_pause)) { 3951 srrctl |= E1000_SRRCTL_DROP_EN; 3952 } 3953 /* Setup the Base and Length of the Rx Descriptor Rings */ 3954 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; 3955 i++, que++) { 3956 struct rx_ring *rxr = &que->rxr; 3957 u64 bus_addr = rxr->rx_paddr; 3958 u32 rxdctl; 3959 3960 #ifdef notyet 3961 /* Configure for header split? -- ignore for now */ 3962 rxr->hdr_split = igb_header_split; 3963 #else 3964 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3965 #endif 3966 3967 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3968 scctx->isc_nrxd[0] * 3969 sizeof(struct e1000_rx_desc)); 3970 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3971 (uint32_t)(bus_addr >> 32)); 3972 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3973 (uint32_t)bus_addr); 3974 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3975 /* Enable this Queue */ 3976 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3977 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3978 rxdctl &= 0xFFF00000; 3979 rxdctl |= IGB_RX_PTHRESH; 3980 rxdctl |= IGB_RX_HTHRESH << 8; 3981 rxdctl |= IGB_RX_WTHRESH << 16; 3982 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3983 } 3984 } else if (hw->mac.type >= e1000_pch2lan) { 3985 if (if_getmtu(ifp) > ETHERMTU) 3986 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3987 else 3988 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3989 } 3990 3991 /* Make sure VLAN Filters are off */ 3992 rctl &= ~E1000_RCTL_VFE; 3993 3994 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3995 if (hw->mac.type < igb_mac_min) { 3996 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3997 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3998 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3999 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 4000 else if (sc->rx_mbuf_sz > 8192) 4001 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 4002 else { 4003 rctl |= E1000_RCTL_SZ_2048; 4004 rctl &= ~E1000_RCTL_BSEX; 4005 } 4006 } else 4007 rctl |= E1000_RCTL_SZ_2048; 4008 4009 /* 4010 * rctl bits 11:10 are as follows 4011 * lem: reserved 4012 * em: DTYPE 4013 * igb: reserved 4014 * and should be 00 on all of the above 4015 */ 4016 rctl &= ~0x00000C00; 4017 4018 /* Write out the settings */ 4019 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4020 4021 return; 4022 } 4023 4024 static void 4025 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 4026 { 4027 struct e1000_softc *sc = iflib_get_softc(ctx); 4028 u32 index, bit; 4029 4030 index = (vtag >> 5) & 0x7F; 4031 bit = vtag & 0x1F; 4032 sc->shadow_vfta[index] |= (1 << bit); 4033 ++sc->num_vlans; 4034 em_if_vlan_filter_write(sc); 4035 } 4036 4037 static void 4038 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 4039 { 4040 struct e1000_softc *sc = iflib_get_softc(ctx); 4041 u32 index, bit; 4042 4043 index = (vtag >> 5) & 0x7F; 4044 bit = vtag & 0x1F; 4045 sc->shadow_vfta[index] &= ~(1 << bit); 4046 --sc->num_vlans; 4047 em_if_vlan_filter_write(sc); 4048 } 4049 4050 static bool 4051 em_if_vlan_filter_capable(if_ctx_t ctx) 4052 { 4053 if_t ifp = iflib_get_ifp(ctx); 4054 4055 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 4056 !em_disable_crc_stripping) 4057 return (true); 4058 4059 return (false); 4060 } 4061 4062 static bool 4063 em_if_vlan_filter_used(if_ctx_t ctx) 4064 { 4065 struct e1000_softc *sc = iflib_get_softc(ctx); 4066 4067 if (!em_if_vlan_filter_capable(ctx)) 4068 return (false); 4069 4070 for (int i = 0; i < EM_VFTA_SIZE; i++) 4071 if (sc->shadow_vfta[i] != 0) 4072 return (true); 4073 4074 return (false); 4075 } 4076 4077 static void 4078 em_if_vlan_filter_enable(struct e1000_softc *sc) 4079 { 4080 struct e1000_hw *hw = &sc->hw; 4081 u32 reg; 4082 4083 reg = E1000_READ_REG(hw, E1000_RCTL); 4084 reg &= ~E1000_RCTL_CFIEN; 4085 reg |= E1000_RCTL_VFE; 4086 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4087 } 4088 4089 static void 4090 em_if_vlan_filter_disable(struct e1000_softc *sc) 4091 { 4092 struct e1000_hw *hw = &sc->hw; 4093 u32 reg; 4094 4095 reg = E1000_READ_REG(hw, E1000_RCTL); 4096 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 4097 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4098 } 4099 4100 static void 4101 em_if_vlan_filter_write(struct e1000_softc *sc) 4102 { 4103 struct e1000_hw *hw = &sc->hw; 4104 4105 if (sc->vf_ifp) 4106 return; 4107 4108 /* Disable interrupts for lem(4) devices during the filter change */ 4109 if (hw->mac.type < em_mac_min) 4110 em_if_intr_disable(sc->ctx); 4111 4112 for (int i = 0; i < EM_VFTA_SIZE; i++) 4113 if (sc->shadow_vfta[i] != 0) { 4114 /* XXXKB: incomplete VF support, we returned above */ 4115 if (sc->vf_ifp) 4116 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], 4117 true); 4118 else 4119 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 4120 } 4121 4122 /* Re-enable interrupts for lem-class devices */ 4123 if (hw->mac.type < em_mac_min) 4124 em_if_intr_enable(sc->ctx); 4125 } 4126 4127 static void 4128 em_setup_vlan_hw_support(if_ctx_t ctx) 4129 { 4130 struct e1000_softc *sc = iflib_get_softc(ctx); 4131 struct e1000_hw *hw = &sc->hw; 4132 if_t ifp = iflib_get_ifp(ctx); 4133 u32 reg; 4134 4135 /* XXXKB: Return early if we are a VF until VF decap and filter 4136 * management is ready and tested. 4137 */ 4138 if (sc->vf_ifp) 4139 return; 4140 4141 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4142 !em_disable_crc_stripping) { 4143 reg = E1000_READ_REG(hw, E1000_CTRL); 4144 reg |= E1000_CTRL_VME; 4145 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4146 } else { 4147 reg = E1000_READ_REG(hw, E1000_CTRL); 4148 reg &= ~E1000_CTRL_VME; 4149 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4150 } 4151 4152 /* If we aren't doing HW filtering, we're done */ 4153 if (!em_if_vlan_filter_capable(ctx)) { 4154 em_if_vlan_filter_disable(sc); 4155 return; 4156 } 4157 4158 /* 4159 * A soft reset zero's out the VFTA, so 4160 * we need to repopulate it now. 4161 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 4162 * traffic through. This will write the entire table. 4163 */ 4164 em_if_vlan_register(ctx, 0); 4165 4166 /* Enable the Filter Table */ 4167 em_if_vlan_filter_enable(sc); 4168 } 4169 4170 static void 4171 em_if_intr_enable(if_ctx_t ctx) 4172 { 4173 struct e1000_softc *sc = iflib_get_softc(ctx); 4174 struct e1000_hw *hw = &sc->hw; 4175 u32 ims_mask = IMS_ENABLE_MASK; 4176 4177 if (sc->intr_type == IFLIB_INTR_MSIX) { 4178 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 4179 ims_mask |= sc->ims; 4180 } 4181 4182 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 4183 E1000_WRITE_FLUSH(hw); 4184 } 4185 4186 static void 4187 em_if_intr_disable(if_ctx_t ctx) 4188 { 4189 struct e1000_softc *sc = iflib_get_softc(ctx); 4190 struct e1000_hw *hw = &sc->hw; 4191 4192 if (sc->intr_type == IFLIB_INTR_MSIX) 4193 E1000_WRITE_REG(hw, EM_EIAC, 0); 4194 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4195 E1000_WRITE_FLUSH(hw); 4196 } 4197 4198 static void 4199 igb_if_intr_enable(if_ctx_t ctx) 4200 { 4201 struct e1000_softc *sc = iflib_get_softc(ctx); 4202 struct e1000_hw *hw = &sc->hw; 4203 u32 mask; 4204 4205 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4206 mask = (sc->que_mask | sc->link_mask); 4207 E1000_WRITE_REG(hw, E1000_EIAC, mask); 4208 E1000_WRITE_REG(hw, E1000_EIAM, mask); 4209 E1000_WRITE_REG(hw, E1000_EIMS, mask); 4210 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 4211 } else 4212 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 4213 E1000_WRITE_FLUSH(hw); 4214 } 4215 4216 static void 4217 igb_if_intr_disable(if_ctx_t ctx) 4218 { 4219 struct e1000_softc *sc = iflib_get_softc(ctx); 4220 struct e1000_hw *hw = &sc->hw; 4221 4222 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4223 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 4224 E1000_WRITE_REG(hw, E1000_EIAC, 0); 4225 } 4226 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4227 E1000_WRITE_FLUSH(hw); 4228 } 4229 4230 /* 4231 * Bit of a misnomer, what this really means is 4232 * to enable OS management of the system... aka 4233 * to disable special hardware management features 4234 */ 4235 static void 4236 em_init_manageability(struct e1000_softc *sc) 4237 { 4238 /* A shared code workaround */ 4239 #define E1000_82542_MANC2H E1000_MANC2H 4240 if (sc->has_manage) { 4241 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 4242 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4243 4244 /* disable hardware interception of ARP */ 4245 manc &= ~(E1000_MANC_ARP_EN); 4246 4247 /* enable receiving management packets to the host */ 4248 manc |= E1000_MANC_EN_MNG2HOST; 4249 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4250 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4251 manc2h |= E1000_MNG2HOST_PORT_623; 4252 manc2h |= E1000_MNG2HOST_PORT_664; 4253 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 4254 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4255 } 4256 } 4257 4258 /* 4259 * Give control back to hardware management 4260 * controller if there is one. 4261 */ 4262 static void 4263 em_release_manageability(struct e1000_softc *sc) 4264 { 4265 if (sc->has_manage) { 4266 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4267 4268 /* re-enable hardware interception of ARP */ 4269 manc |= E1000_MANC_ARP_EN; 4270 manc &= ~E1000_MANC_EN_MNG2HOST; 4271 4272 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4273 } 4274 } 4275 4276 /* 4277 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 4278 * For ASF and Pass Through versions of f/w this means 4279 * that the driver is loaded. For AMT version type f/w 4280 * this means that the network i/f is open. 4281 */ 4282 static void 4283 em_get_hw_control(struct e1000_softc *sc) 4284 { 4285 u32 ctrl_ext, swsm; 4286 4287 if (sc->vf_ifp) 4288 return; 4289 4290 if (sc->hw.mac.type == e1000_82573) { 4291 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4292 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4293 swsm | E1000_SWSM_DRV_LOAD); 4294 return; 4295 } 4296 /* else */ 4297 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4298 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4299 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4300 } 4301 4302 /* 4303 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4304 * For ASF and Pass Through versions of f/w this means that 4305 * the driver is no longer loaded. For AMT versions of the 4306 * f/w this means that the network i/f is closed. 4307 */ 4308 static void 4309 em_release_hw_control(struct e1000_softc *sc) 4310 { 4311 u32 ctrl_ext, swsm; 4312 4313 if (!sc->has_manage) 4314 return; 4315 4316 if (sc->hw.mac.type == e1000_82573) { 4317 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4318 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4319 swsm & ~E1000_SWSM_DRV_LOAD); 4320 return; 4321 } 4322 /* else */ 4323 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4324 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4325 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4326 return; 4327 } 4328 4329 static int 4330 em_is_valid_ether_addr(u8 *addr) 4331 { 4332 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4333 4334 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4335 return (false); 4336 } 4337 4338 return (true); 4339 } 4340 4341 static bool 4342 em_automask_tso(if_ctx_t ctx) 4343 { 4344 struct e1000_softc *sc = iflib_get_softc(ctx); 4345 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 4346 if_t ifp = iflib_get_ifp(ctx); 4347 4348 if (!em_unsupported_tso && sc->link_speed && 4349 sc->link_speed != SPEED_1000 && 4350 scctx->isc_capenable & IFCAP_TSO) { 4351 device_printf(sc->dev, 4352 "Disabling TSO for 10/100 Ethernet.\n"); 4353 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 4354 scctx->isc_capenable &= ~IFCAP_TSO; 4355 if_setcapenablebit(ifp, 0, IFCAP_TSO); 4356 /* iflib_init_locked handles ifnet hwassistbits */ 4357 iflib_request_reset(ctx); 4358 return true; 4359 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 4360 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 4361 scctx->isc_capenable |= sc->tso_automasked; 4362 if_setcapenablebit(ifp, sc->tso_automasked, 0); 4363 sc->tso_automasked = 0; 4364 /* iflib_init_locked handles ifnet hwassistbits */ 4365 iflib_request_reset(ctx); 4366 return true; 4367 } 4368 4369 return false; 4370 } 4371 4372 /* 4373 ** Parse the interface capabilities with regard 4374 ** to both system management and wake-on-lan for 4375 ** later use. 4376 */ 4377 static void 4378 em_get_wakeup(if_ctx_t ctx) 4379 { 4380 struct e1000_softc *sc = iflib_get_softc(ctx); 4381 device_t dev = iflib_get_dev(ctx); 4382 u16 eeprom_data = 0, device_id, apme_mask; 4383 4384 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 4385 apme_mask = EM_EEPROM_APME; 4386 4387 switch (sc->hw.mac.type) { 4388 case e1000_82542: 4389 case e1000_82543: 4390 break; 4391 case e1000_82544: 4392 e1000_read_nvm(&sc->hw, 4393 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 4394 apme_mask = EM_82544_APME; 4395 break; 4396 case e1000_82546: 4397 case e1000_82546_rev_3: 4398 if (sc->hw.bus.func == 1) { 4399 e1000_read_nvm(&sc->hw, 4400 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4401 break; 4402 } else 4403 e1000_read_nvm(&sc->hw, 4404 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4405 break; 4406 case e1000_82573: 4407 case e1000_82583: 4408 sc->has_amt = true; 4409 /* FALLTHROUGH */ 4410 case e1000_82571: 4411 case e1000_82572: 4412 case e1000_80003es2lan: 4413 if (sc->hw.bus.func == 1) { 4414 e1000_read_nvm(&sc->hw, 4415 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4416 break; 4417 } else 4418 e1000_read_nvm(&sc->hw, 4419 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4420 break; 4421 case e1000_ich8lan: 4422 case e1000_ich9lan: 4423 case e1000_ich10lan: 4424 case e1000_pchlan: 4425 case e1000_pch2lan: 4426 case e1000_pch_lpt: 4427 case e1000_pch_spt: 4428 case e1000_82575: /* listing all igb devices */ 4429 case e1000_82576: 4430 case e1000_82580: 4431 case e1000_i350: 4432 case e1000_i354: 4433 case e1000_i210: 4434 case e1000_i211: 4435 case e1000_vfadapt: 4436 case e1000_vfadapt_i350: 4437 apme_mask = E1000_WUC_APME; 4438 sc->has_amt = true; 4439 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4440 break; 4441 default: 4442 e1000_read_nvm(&sc->hw, 4443 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4444 break; 4445 } 4446 if (eeprom_data & apme_mask) 4447 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4448 /* 4449 * We have the eeprom settings, now apply the special cases 4450 * where the eeprom may be wrong or the board won't support 4451 * wake on lan on a particular port 4452 */ 4453 device_id = pci_get_device(dev); 4454 switch (device_id) { 4455 case E1000_DEV_ID_82546GB_PCIE: 4456 sc->wol = 0; 4457 break; 4458 case E1000_DEV_ID_82546EB_FIBER: 4459 case E1000_DEV_ID_82546GB_FIBER: 4460 /* Wake events only supported on port A for dual fiber 4461 * regardless of eeprom setting */ 4462 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4463 E1000_STATUS_FUNC_1) 4464 sc->wol = 0; 4465 break; 4466 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4467 /* if quad port adapter, disable WoL on all but port A */ 4468 if (global_quad_port_a != 0) 4469 sc->wol = 0; 4470 /* Reset for multiple quad port adapters */ 4471 if (++global_quad_port_a == 4) 4472 global_quad_port_a = 0; 4473 break; 4474 case E1000_DEV_ID_82571EB_FIBER: 4475 /* Wake events only supported on port A for dual fiber 4476 * regardless of eeprom setting */ 4477 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4478 E1000_STATUS_FUNC_1) 4479 sc->wol = 0; 4480 break; 4481 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4482 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4483 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4484 /* if quad port adapter, disable WoL on all but port A */ 4485 if (global_quad_port_a != 0) 4486 sc->wol = 0; 4487 /* Reset for multiple quad port adapters */ 4488 if (++global_quad_port_a == 4) 4489 global_quad_port_a = 0; 4490 break; 4491 } 4492 return; 4493 } 4494 4495 4496 /* 4497 * Enable PCI Wake On Lan capability 4498 */ 4499 static void 4500 em_enable_wakeup(if_ctx_t ctx) 4501 { 4502 struct e1000_softc *sc = iflib_get_softc(ctx); 4503 device_t dev = iflib_get_dev(ctx); 4504 if_t ifp = iflib_get_ifp(ctx); 4505 int error = 0; 4506 u32 pmc, ctrl, ctrl_ext, rctl; 4507 u16 status; 4508 4509 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4510 return; 4511 4512 /* 4513 * Determine type of Wakeup: note that wol 4514 * is set with all bits on by default. 4515 */ 4516 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4517 sc->wol &= ~E1000_WUFC_MAG; 4518 4519 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4520 sc->wol &= ~E1000_WUFC_EX; 4521 4522 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4523 sc->wol &= ~E1000_WUFC_MC; 4524 else { 4525 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4526 rctl |= E1000_RCTL_MPE; 4527 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4528 } 4529 4530 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4531 goto pme; 4532 4533 /* Advertise the wakeup capability */ 4534 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4535 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4536 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4537 4538 /* Keep the laser running on Fiber adapters */ 4539 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4540 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4541 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4542 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4543 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4544 } 4545 4546 if ((sc->hw.mac.type == e1000_ich8lan) || 4547 (sc->hw.mac.type == e1000_pchlan) || 4548 (sc->hw.mac.type == e1000_ich9lan) || 4549 (sc->hw.mac.type == e1000_ich10lan)) 4550 e1000_suspend_workarounds_ich8lan(&sc->hw); 4551 4552 if ( sc->hw.mac.type >= e1000_pchlan) { 4553 error = em_enable_phy_wakeup(sc); 4554 if (error) 4555 goto pme; 4556 } else { 4557 /* Enable wakeup by the MAC */ 4558 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4559 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4560 } 4561 4562 if (sc->hw.phy.type == e1000_phy_igp_3) 4563 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4564 4565 pme: 4566 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4567 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4568 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4569 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4570 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4571 4572 return; 4573 } 4574 4575 /* 4576 * WOL in the newer chipset interfaces (pchlan) 4577 * require thing to be copied into the phy 4578 */ 4579 static int 4580 em_enable_phy_wakeup(struct e1000_softc *sc) 4581 { 4582 struct e1000_hw *hw = &sc->hw; 4583 u32 mreg, ret = 0; 4584 u16 preg; 4585 4586 /* copy MAC RARs to PHY RARs */ 4587 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4588 4589 /* copy MAC MTA to PHY MTA */ 4590 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4591 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4592 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4593 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4594 (u16)((mreg >> 16) & 0xFFFF)); 4595 } 4596 4597 /* configure PHY Rx Control register */ 4598 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4599 mreg = E1000_READ_REG(hw, E1000_RCTL); 4600 if (mreg & E1000_RCTL_UPE) 4601 preg |= BM_RCTL_UPE; 4602 if (mreg & E1000_RCTL_MPE) 4603 preg |= BM_RCTL_MPE; 4604 preg &= ~(BM_RCTL_MO_MASK); 4605 if (mreg & E1000_RCTL_MO_3) 4606 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4607 << BM_RCTL_MO_SHIFT); 4608 if (mreg & E1000_RCTL_BAM) 4609 preg |= BM_RCTL_BAM; 4610 if (mreg & E1000_RCTL_PMCF) 4611 preg |= BM_RCTL_PMCF; 4612 mreg = E1000_READ_REG(hw, E1000_CTRL); 4613 if (mreg & E1000_CTRL_RFCE) 4614 preg |= BM_RCTL_RFCE; 4615 e1000_write_phy_reg(hw, BM_RCTL, preg); 4616 4617 /* enable PHY wakeup in MAC register */ 4618 E1000_WRITE_REG(hw, E1000_WUC, 4619 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4620 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4621 4622 /* configure and enable PHY wakeup in PHY registers */ 4623 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4624 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4625 4626 /* activate PHY wakeup */ 4627 ret = hw->phy.ops.acquire(hw); 4628 if (ret) { 4629 printf("Could not acquire PHY\n"); 4630 return ret; 4631 } 4632 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4633 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4634 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4635 if (ret) { 4636 printf("Could not read PHY page 769\n"); 4637 goto out; 4638 } 4639 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4640 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4641 if (ret) 4642 printf("Could not set PHY Host Wakeup bit\n"); 4643 out: 4644 hw->phy.ops.release(hw); 4645 4646 return ret; 4647 } 4648 4649 static void 4650 em_if_led_func(if_ctx_t ctx, int onoff) 4651 { 4652 struct e1000_softc *sc = iflib_get_softc(ctx); 4653 4654 if (onoff) { 4655 e1000_setup_led(&sc->hw); 4656 e1000_led_on(&sc->hw); 4657 } else { 4658 e1000_led_off(&sc->hw); 4659 e1000_cleanup_led(&sc->hw); 4660 } 4661 } 4662 4663 /* 4664 * Disable the L0S and L1 LINK states 4665 */ 4666 static void 4667 em_disable_aspm(struct e1000_softc *sc) 4668 { 4669 int base, reg; 4670 u16 link_cap,link_ctrl; 4671 device_t dev = sc->dev; 4672 4673 switch (sc->hw.mac.type) { 4674 case e1000_82573: 4675 case e1000_82574: 4676 case e1000_82583: 4677 break; 4678 default: 4679 return; 4680 } 4681 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4682 return; 4683 reg = base + PCIER_LINK_CAP; 4684 link_cap = pci_read_config(dev, reg, 2); 4685 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4686 return; 4687 reg = base + PCIER_LINK_CTL; 4688 link_ctrl = pci_read_config(dev, reg, 2); 4689 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4690 pci_write_config(dev, reg, link_ctrl, 2); 4691 return; 4692 } 4693 4694 /********************************************************************** 4695 * 4696 * Update the board statistics counters. 4697 * 4698 **********************************************************************/ 4699 static void 4700 em_update_stats_counters(struct e1000_softc *sc) 4701 { 4702 u64 prev_xoffrxc = sc->stats.xoffrxc; 4703 4704 if(sc->hw.phy.media_type == e1000_media_type_copper || 4705 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4706 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4707 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4708 } 4709 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4710 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4711 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4712 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4713 4714 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4715 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4716 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4717 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4718 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4719 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4720 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4721 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4722 /* 4723 ** For watchdog management we need to know if we have been 4724 ** paused during the last interval, so capture that here. 4725 */ 4726 if (sc->stats.xoffrxc != prev_xoffrxc) 4727 sc->shared->isc_pause_frames = 1; 4728 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4729 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4730 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4731 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4732 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4733 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4734 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4735 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4736 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4737 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4738 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4739 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4740 4741 /* For the 64-bit byte counters the low dword must be read first. */ 4742 /* Both registers clear on the read of the high dword */ 4743 4744 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4745 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4746 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4747 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4748 4749 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4750 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4751 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4752 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4753 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4754 4755 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4756 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4757 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4758 4759 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4760 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4761 4762 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4763 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4764 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4765 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4766 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4767 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4768 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4769 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4770 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4771 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4772 4773 /* Interrupt Counts */ 4774 4775 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4776 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4777 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4778 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4779 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4780 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4781 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4782 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4783 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4784 4785 if (sc->hw.mac.type >= e1000_82543) { 4786 sc->stats.algnerrc += 4787 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4788 sc->stats.rxerrc += 4789 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4790 sc->stats.tncrs += 4791 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4792 sc->stats.cexterr += 4793 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4794 sc->stats.tsctc += 4795 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4796 sc->stats.tsctfc += 4797 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4798 } 4799 } 4800 4801 static uint64_t 4802 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4803 { 4804 struct e1000_softc *sc = iflib_get_softc(ctx); 4805 if_t ifp = iflib_get_ifp(ctx); 4806 4807 switch (cnt) { 4808 case IFCOUNTER_COLLISIONS: 4809 return (sc->stats.colc); 4810 case IFCOUNTER_IERRORS: 4811 return (sc->dropped_pkts + sc->stats.rxerrc + 4812 sc->stats.crcerrs + sc->stats.algnerrc + 4813 sc->stats.ruc + sc->stats.roc + 4814 sc->stats.mpc + sc->stats.cexterr); 4815 case IFCOUNTER_OERRORS: 4816 return (sc->stats.ecol + sc->stats.latecol + 4817 sc->watchdog_events); 4818 default: 4819 return (if_get_counter_default(ifp, cnt)); 4820 } 4821 } 4822 4823 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4824 * @ctx: iflib context 4825 * @event: event code to check 4826 * 4827 * Defaults to returning false for unknown events. 4828 * 4829 * @returns true if iflib needs to reinit the interface 4830 */ 4831 static bool 4832 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4833 { 4834 switch (event) { 4835 case IFLIB_RESTART_VLAN_CONFIG: 4836 default: 4837 return (false); 4838 } 4839 } 4840 4841 /* Export a single 32-bit register via a read-only sysctl. */ 4842 static int 4843 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4844 { 4845 struct e1000_softc *sc; 4846 u_int val; 4847 4848 sc = oidp->oid_arg1; 4849 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4850 return (sysctl_handle_int(oidp, &val, 0, req)); 4851 } 4852 4853 /* Per queue holdoff interrupt rate handler */ 4854 static int 4855 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 4856 { 4857 struct em_rx_queue *rque; 4858 struct em_tx_queue *tque; 4859 struct e1000_hw *hw; 4860 int error; 4861 u32 reg, usec, rate; 4862 4863 bool tx = oidp->oid_arg2; 4864 4865 if (tx) { 4866 tque = oidp->oid_arg1; 4867 hw = &tque->sc->hw; 4868 if (hw->mac.type >= igb_mac_min) 4869 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); 4870 else if (hw->mac.type == e1000_82574 && tque->msix) 4871 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); 4872 else 4873 reg = E1000_READ_REG(hw, E1000_ITR); 4874 } else { 4875 rque = oidp->oid_arg1; 4876 hw = &rque->sc->hw; 4877 if (hw->mac.type >= igb_mac_min) 4878 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); 4879 else if (hw->mac.type == e1000_82574 && rque->msix) 4880 reg = E1000_READ_REG(hw, 4881 E1000_EITR_82574(rque->msix)); 4882 else 4883 reg = E1000_READ_REG(hw, E1000_ITR); 4884 } 4885 4886 if (hw->mac.type < igb_mac_min) { 4887 if (reg > 0) 4888 rate = EM_INTS_TO_ITR(reg); 4889 else 4890 rate = 0; 4891 } else { 4892 usec = (reg & IGB_QVECTOR_MASK); 4893 if (usec > 0) 4894 rate = IGB_INTS_TO_EITR(usec); 4895 else 4896 rate = 0; 4897 } 4898 4899 error = sysctl_handle_int(oidp, &rate, 0, req); 4900 if (error || !req->newptr) 4901 return error; 4902 return 0; 4903 } 4904 4905 /* 4906 * Add sysctl variables, one per statistic, to the system. 4907 */ 4908 static void 4909 em_add_hw_stats(struct e1000_softc *sc) 4910 { 4911 device_t dev = iflib_get_dev(sc->ctx); 4912 struct em_tx_queue *tx_que = sc->tx_queues; 4913 struct em_rx_queue *rx_que = sc->rx_queues; 4914 4915 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4916 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4917 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4918 struct e1000_hw_stats *stats = &sc->stats; 4919 4920 struct sysctl_oid *stat_node, *queue_node, *int_node; 4921 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4922 4923 #define QUEUE_NAME_LEN 32 4924 char namebuf[QUEUE_NAME_LEN]; 4925 4926 /* Driver Statistics */ 4927 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4928 CTLFLAG_RD, &sc->dropped_pkts, 4929 "Driver dropped packets"); 4930 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4931 CTLFLAG_RD, &sc->link_irq, 4932 "Link MSI-X IRQ Handled"); 4933 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4934 CTLFLAG_RD, &sc->rx_overruns, 4935 "RX overruns"); 4936 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4937 CTLFLAG_RD, &sc->watchdog_events, 4938 "Watchdog timeouts"); 4939 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4940 CTLTYPE_UINT | CTLFLAG_RD, 4941 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4942 "Device Control Register"); 4943 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4944 CTLTYPE_UINT | CTLFLAG_RD, 4945 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4946 "Receiver Control Register"); 4947 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4948 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4949 "Flow Control High Watermark"); 4950 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4951 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4952 "Flow Control Low Watermark"); 4953 4954 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4955 struct tx_ring *txr = &tx_que->txr; 4956 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4957 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4958 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4959 queue_list = SYSCTL_CHILDREN(queue_node); 4960 4961 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4962 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 4963 true, em_sysctl_interrupt_rate_handler, 4964 "IU", "Interrupt Rate"); 4965 4966 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4967 CTLTYPE_UINT | CTLFLAG_RD, sc, 4968 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4969 "Transmit Descriptor Head"); 4970 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4971 CTLTYPE_UINT | CTLFLAG_RD, sc, 4972 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4973 "Transmit Descriptor Tail"); 4974 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4975 CTLFLAG_RD, &txr->tx_irq, 4976 "Queue MSI-X Transmit Interrupts"); 4977 } 4978 4979 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4980 struct rx_ring *rxr = &rx_que->rxr; 4981 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4982 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4983 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4984 queue_list = SYSCTL_CHILDREN(queue_node); 4985 4986 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 4987 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 4988 false, em_sysctl_interrupt_rate_handler, 4989 "IU", "Interrupt Rate"); 4990 4991 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4992 CTLTYPE_UINT | CTLFLAG_RD, sc, 4993 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4994 "Receive Descriptor Head"); 4995 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4996 CTLTYPE_UINT | CTLFLAG_RD, sc, 4997 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4998 "Receive Descriptor Tail"); 4999 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 5000 CTLFLAG_RD, &rxr->rx_irq, 5001 "Queue MSI-X Receive Interrupts"); 5002 } 5003 5004 /* MAC stats get their own sub node */ 5005 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 5006 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 5007 stat_list = SYSCTL_CHILDREN(stat_node); 5008 5009 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 5010 CTLFLAG_RD, &stats->ecol, 5011 "Excessive collisions"); 5012 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 5013 CTLFLAG_RD, &stats->scc, 5014 "Single collisions"); 5015 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 5016 CTLFLAG_RD, &stats->mcc, 5017 "Multiple collisions"); 5018 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 5019 CTLFLAG_RD, &stats->latecol, 5020 "Late collisions"); 5021 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 5022 CTLFLAG_RD, &stats->colc, 5023 "Collision Count"); 5024 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 5025 CTLFLAG_RD, &sc->stats.symerrs, 5026 "Symbol Errors"); 5027 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 5028 CTLFLAG_RD, &sc->stats.sec, 5029 "Sequence Errors"); 5030 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 5031 CTLFLAG_RD, &sc->stats.dc, 5032 "Defer Count"); 5033 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 5034 CTLFLAG_RD, &sc->stats.mpc, 5035 "Missed Packets"); 5036 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 5037 CTLFLAG_RD, &sc->stats.rlec, 5038 "Receive Length Errors"); 5039 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 5040 CTLFLAG_RD, &sc->stats.rnbc, 5041 "Receive No Buffers"); 5042 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 5043 CTLFLAG_RD, &sc->stats.ruc, 5044 "Receive Undersize"); 5045 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 5046 CTLFLAG_RD, &sc->stats.rfc, 5047 "Fragmented Packets Received "); 5048 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 5049 CTLFLAG_RD, &sc->stats.roc, 5050 "Oversized Packets Received"); 5051 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 5052 CTLFLAG_RD, &sc->stats.rjc, 5053 "Recevied Jabber"); 5054 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 5055 CTLFLAG_RD, &sc->stats.rxerrc, 5056 "Receive Errors"); 5057 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 5058 CTLFLAG_RD, &sc->stats.crcerrs, 5059 "CRC errors"); 5060 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 5061 CTLFLAG_RD, &sc->stats.algnerrc, 5062 "Alignment Errors"); 5063 /* On 82575 these are collision counts */ 5064 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 5065 CTLFLAG_RD, &sc->stats.cexterr, 5066 "Collision/Carrier extension errors"); 5067 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 5068 CTLFLAG_RD, &sc->stats.xonrxc, 5069 "XON Received"); 5070 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 5071 CTLFLAG_RD, &sc->stats.xontxc, 5072 "XON Transmitted"); 5073 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 5074 CTLFLAG_RD, &sc->stats.xoffrxc, 5075 "XOFF Received"); 5076 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 5077 CTLFLAG_RD, &sc->stats.xofftxc, 5078 "XOFF Transmitted"); 5079 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 5080 CTLFLAG_RD, &sc->stats.fcruc, 5081 "Unsupported Flow Control Received"); 5082 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 5083 CTLFLAG_RD, &sc->stats.mgprc, 5084 "Management Packets Received"); 5085 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 5086 CTLFLAG_RD, &sc->stats.mgpdc, 5087 "Management Packets Dropped"); 5088 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 5089 CTLFLAG_RD, &sc->stats.mgptc, 5090 "Management Packets Transmitted"); 5091 5092 /* Packet Reception Stats */ 5093 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 5094 CTLFLAG_RD, &sc->stats.tpr, 5095 "Total Packets Received "); 5096 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5097 CTLFLAG_RD, &sc->stats.gprc, 5098 "Good Packets Received"); 5099 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 5100 CTLFLAG_RD, &sc->stats.bprc, 5101 "Broadcast Packets Received"); 5102 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5103 CTLFLAG_RD, &sc->stats.mprc, 5104 "Multicast Packets Received"); 5105 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 5106 CTLFLAG_RD, &sc->stats.prc64, 5107 "64 byte frames received "); 5108 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 5109 CTLFLAG_RD, &sc->stats.prc127, 5110 "65-127 byte frames received"); 5111 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 5112 CTLFLAG_RD, &sc->stats.prc255, 5113 "128-255 byte frames received"); 5114 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 5115 CTLFLAG_RD, &sc->stats.prc511, 5116 "256-511 byte frames received"); 5117 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 5118 CTLFLAG_RD, &sc->stats.prc1023, 5119 "512-1023 byte frames received"); 5120 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 5121 CTLFLAG_RD, &sc->stats.prc1522, 5122 "1023-1522 byte frames received"); 5123 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5124 CTLFLAG_RD, &sc->stats.gorc, 5125 "Good Octets Received"); 5126 5127 /* Packet Transmission Stats */ 5128 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5129 CTLFLAG_RD, &sc->stats.gotc, 5130 "Good Octets Transmitted"); 5131 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 5132 CTLFLAG_RD, &sc->stats.tpt, 5133 "Total Packets Transmitted"); 5134 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5135 CTLFLAG_RD, &sc->stats.gptc, 5136 "Good Packets Transmitted"); 5137 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 5138 CTLFLAG_RD, &sc->stats.bptc, 5139 "Broadcast Packets Transmitted"); 5140 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 5141 CTLFLAG_RD, &sc->stats.mptc, 5142 "Multicast Packets Transmitted"); 5143 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 5144 CTLFLAG_RD, &sc->stats.ptc64, 5145 "64 byte frames transmitted "); 5146 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 5147 CTLFLAG_RD, &sc->stats.ptc127, 5148 "65-127 byte frames transmitted"); 5149 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 5150 CTLFLAG_RD, &sc->stats.ptc255, 5151 "128-255 byte frames transmitted"); 5152 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 5153 CTLFLAG_RD, &sc->stats.ptc511, 5154 "256-511 byte frames transmitted"); 5155 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 5156 CTLFLAG_RD, &sc->stats.ptc1023, 5157 "512-1023 byte frames transmitted"); 5158 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 5159 CTLFLAG_RD, &sc->stats.ptc1522, 5160 "1024-1522 byte frames transmitted"); 5161 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 5162 CTLFLAG_RD, &sc->stats.tsctc, 5163 "TSO Contexts Transmitted"); 5164 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 5165 CTLFLAG_RD, &sc->stats.tsctfc, 5166 "TSO Contexts Failed"); 5167 5168 /* Interrupt Stats */ 5169 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 5170 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 5171 int_list = SYSCTL_CHILDREN(int_node); 5172 5173 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 5174 CTLFLAG_RD, &sc->stats.iac, 5175 "Interrupt Assertion Count"); 5176 5177 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 5178 CTLFLAG_RD, &sc->stats.icrxptc, 5179 "Interrupt Cause Rx Pkt Timer Expire Count"); 5180 5181 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 5182 CTLFLAG_RD, &sc->stats.icrxatc, 5183 "Interrupt Cause Rx Abs Timer Expire Count"); 5184 5185 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 5186 CTLFLAG_RD, &sc->stats.ictxptc, 5187 "Interrupt Cause Tx Pkt Timer Expire Count"); 5188 5189 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 5190 CTLFLAG_RD, &sc->stats.ictxatc, 5191 "Interrupt Cause Tx Abs Timer Expire Count"); 5192 5193 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 5194 CTLFLAG_RD, &sc->stats.ictxqec, 5195 "Interrupt Cause Tx Queue Empty Count"); 5196 5197 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 5198 CTLFLAG_RD, &sc->stats.ictxqmtc, 5199 "Interrupt Cause Tx Queue Min Thresh Count"); 5200 5201 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 5202 CTLFLAG_RD, &sc->stats.icrxdmtc, 5203 "Interrupt Cause Rx Desc Min Thresh Count"); 5204 5205 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 5206 CTLFLAG_RD, &sc->stats.icrxoc, 5207 "Interrupt Cause Receiver Overrun Count"); 5208 } 5209 5210 static void 5211 em_fw_version_locked(if_ctx_t ctx) 5212 { 5213 struct e1000_softc *sc = iflib_get_softc(ctx); 5214 struct e1000_hw *hw = &sc->hw; 5215 struct e1000_fw_version *fw_ver = &sc->fw_ver; 5216 uint16_t eep = 0; 5217 5218 /* 5219 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet 5220 * the NVM locking model, so we do it in em_if_attach_pre() and store 5221 * the info in the softc 5222 */ 5223 ASSERT_CTX_LOCK_HELD(hw); 5224 5225 *fw_ver = (struct e1000_fw_version){0}; 5226 5227 if (hw->mac.type >= igb_mac_min) { 5228 /* 5229 * Use the Shared Code for igb(4) 5230 */ 5231 e1000_get_fw_version(hw, fw_ver); 5232 } else { 5233 /* 5234 * Otherwise, EEPROM version should be present on (almost?) 5235 * all devices here 5236 */ 5237 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 5238 INIT_DEBUGOUT("can't get EEPROM version"); 5239 return; 5240 } 5241 5242 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 5243 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 5244 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 5245 } 5246 } 5247 5248 static void 5249 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 5250 { 5251 const char *space = ""; 5252 5253 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 5254 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 5255 fw_ver->eep_minor, fw_ver->eep_build); 5256 space = " "; 5257 } 5258 5259 if (fw_ver->invm_major || fw_ver->invm_minor || 5260 fw_ver->invm_img_type) { 5261 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 5262 space, fw_ver->invm_major, fw_ver->invm_minor, 5263 fw_ver->invm_img_type); 5264 space = " "; 5265 } 5266 5267 if (fw_ver->or_valid) { 5268 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 5269 space, fw_ver->or_major, fw_ver->or_build, 5270 fw_ver->or_patch); 5271 space = " "; 5272 } 5273 5274 if (fw_ver->etrack_id) 5275 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 5276 } 5277 5278 static void 5279 em_print_fw_version(struct e1000_softc *sc ) 5280 { 5281 device_t dev = sc->dev; 5282 struct sbuf *buf; 5283 int error = 0; 5284 5285 buf = sbuf_new_auto(); 5286 if (!buf) { 5287 device_printf(dev, "Could not allocate sbuf for output.\n"); 5288 return; 5289 } 5290 5291 em_sbuf_fw_version(&sc->fw_ver, buf); 5292 5293 error = sbuf_finish(buf); 5294 if (error) 5295 device_printf(dev, "Error finishing sbuf: %d\n", error); 5296 else if (sbuf_len(buf)) 5297 device_printf(dev, "%s\n", sbuf_data(buf)); 5298 5299 sbuf_delete(buf); 5300 } 5301 5302 static int 5303 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 5304 { 5305 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5306 device_t dev = sc->dev; 5307 struct sbuf *buf; 5308 int error = 0; 5309 5310 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5311 if (!buf) { 5312 device_printf(dev, "Could not allocate sbuf for output.\n"); 5313 return (ENOMEM); 5314 } 5315 5316 em_sbuf_fw_version(&sc->fw_ver, buf); 5317 5318 error = sbuf_finish(buf); 5319 if (error) 5320 device_printf(dev, "Error finishing sbuf: %d\n", error); 5321 5322 sbuf_delete(buf); 5323 5324 return (0); 5325 } 5326 5327 /********************************************************************** 5328 * 5329 * This routine provides a way to dump out the adapter eeprom, 5330 * often a useful debug/service tool. This only dumps the first 5331 * 32 words, stuff that matters is in that extent. 5332 * 5333 **********************************************************************/ 5334 static int 5335 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 5336 { 5337 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5338 int error; 5339 int result; 5340 5341 result = -1; 5342 error = sysctl_handle_int(oidp, &result, 0, req); 5343 5344 if (error || !req->newptr) 5345 return (error); 5346 5347 /* 5348 * This value will cause a hex dump of the 5349 * first 32 16-bit words of the EEPROM to 5350 * the screen. 5351 */ 5352 if (result == 1) 5353 em_print_nvm_info(sc); 5354 5355 return (error); 5356 } 5357 5358 static void 5359 em_print_nvm_info(struct e1000_softc *sc) 5360 { 5361 struct e1000_hw *hw = &sc->hw; 5362 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 5363 u16 eeprom_data; 5364 int i, j, row = 0; 5365 5366 /* Its a bit crude, but it gets the job done */ 5367 printf("\nInterface EEPROM Dump:\n"); 5368 printf("Offset\n0x0000 "); 5369 5370 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 5371 sx_xlock(iflib_ctx_lock); 5372 ASSERT_CTX_LOCK_HELD(hw); 5373 for (i = 0, j = 0; i < 32; i++, j++) { 5374 if (j == 8) { /* Make the offset block */ 5375 j = 0; ++row; 5376 printf("\n0x00%x0 ",row); 5377 } 5378 e1000_read_nvm(hw, i, 1, &eeprom_data); 5379 printf("%04x ", eeprom_data); 5380 } 5381 sx_xunlock(iflib_ctx_lock); 5382 printf("\n"); 5383 } 5384 5385 static int 5386 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5387 { 5388 struct em_int_delay_info *info; 5389 struct e1000_softc *sc; 5390 u32 regval; 5391 int error, usecs, ticks; 5392 5393 info = (struct em_int_delay_info *) arg1; 5394 usecs = info->value; 5395 error = sysctl_handle_int(oidp, &usecs, 0, req); 5396 if (error != 0 || req->newptr == NULL) 5397 return (error); 5398 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5399 return (EINVAL); 5400 info->value = usecs; 5401 ticks = EM_USECS_TO_TICKS(usecs); 5402 5403 sc = info->sc; 5404 5405 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 5406 regval = (regval & ~0xffff) | (ticks & 0xffff); 5407 /* Handle a few special cases. */ 5408 switch (info->offset) { 5409 case E1000_RDTR: 5410 break; 5411 case E1000_TIDV: 5412 if (ticks == 0) { 5413 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 5414 /* Don't write 0 into the TIDV register. */ 5415 regval++; 5416 } else 5417 sc->txd_cmd |= E1000_TXD_CMD_IDE; 5418 break; 5419 } 5420 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 5421 return (0); 5422 } 5423 5424 static int 5425 em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 5426 { 5427 struct e1000_softc *sc; 5428 u32 reg, val, shift; 5429 int error, mask; 5430 5431 sc = oidp->oid_arg1; 5432 switch (oidp->oid_arg2) { 5433 case 0: 5434 reg = E1000_DTXTCPFLGL; 5435 shift = 0; 5436 break; 5437 case 1: 5438 reg = E1000_DTXTCPFLGL; 5439 shift = 16; 5440 break; 5441 case 2: 5442 reg = E1000_DTXTCPFLGH; 5443 shift = 0; 5444 break; 5445 default: 5446 return (EINVAL); 5447 break; 5448 } 5449 val = E1000_READ_REG(&sc->hw, reg); 5450 mask = (val >> shift) & 0xfff; 5451 error = sysctl_handle_int(oidp, &mask, 0, req); 5452 if (error != 0 || req->newptr == NULL) 5453 return (error); 5454 if (mask < 0 || mask > 0xfff) 5455 return (EINVAL); 5456 val = (val & ~(0xfff << shift)) | (mask << shift); 5457 E1000_WRITE_REG(&sc->hw, reg, val); 5458 return (0); 5459 } 5460 5461 static void 5462 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 5463 const char *description, struct em_int_delay_info *info, int offset, 5464 int value) 5465 { 5466 info->sc = sc; 5467 info->offset = offset; 5468 info->value = value; 5469 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5470 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 5471 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 5472 info, 0, em_sysctl_int_delay, "I", description); 5473 } 5474 5475 /* 5476 * Set flow control using sysctl: 5477 * Flow control values: 5478 * 0 - off 5479 * 1 - rx pause 5480 * 2 - tx pause 5481 * 3 - full 5482 */ 5483 static int 5484 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 5485 { 5486 int error; 5487 static int input = 3; /* default is full */ 5488 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5489 5490 error = sysctl_handle_int(oidp, &input, 0, req); 5491 5492 if ((error) || (req->newptr == NULL)) 5493 return (error); 5494 5495 if (input == sc->fc) /* no change? */ 5496 return (error); 5497 5498 switch (input) { 5499 case e1000_fc_rx_pause: 5500 case e1000_fc_tx_pause: 5501 case e1000_fc_full: 5502 case e1000_fc_none: 5503 sc->hw.fc.requested_mode = input; 5504 sc->fc = input; 5505 break; 5506 default: 5507 /* Do nothing */ 5508 return (error); 5509 } 5510 5511 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 5512 e1000_force_mac_fc(&sc->hw); 5513 return (error); 5514 } 5515 5516 /* 5517 * Manage DMA Coalesce: 5518 * Control values: 5519 * 0/1 - off/on 5520 * Legal timer values are: 5521 * 250,500,1000-10000 in thousands 5522 */ 5523 static int 5524 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5525 { 5526 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5527 int error; 5528 5529 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 5530 5531 if ((error) || (req->newptr == NULL)) 5532 return (error); 5533 5534 switch (sc->dmac) { 5535 case 0: 5536 /* Disabling */ 5537 break; 5538 case 1: /* Just enable and use default */ 5539 sc->dmac = 1000; 5540 break; 5541 case 250: 5542 case 500: 5543 case 1000: 5544 case 2000: 5545 case 3000: 5546 case 4000: 5547 case 5000: 5548 case 6000: 5549 case 7000: 5550 case 8000: 5551 case 9000: 5552 case 10000: 5553 /* Legal values - allow */ 5554 break; 5555 default: 5556 /* Do nothing, illegal value */ 5557 sc->dmac = 0; 5558 return (EINVAL); 5559 } 5560 /* Reinit the interface */ 5561 em_if_init(sc->ctx); 5562 return (error); 5563 } 5564 5565 /* 5566 * Manage Energy Efficient Ethernet: 5567 * Control values: 5568 * 0/1 - enabled/disabled 5569 */ 5570 static int 5571 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5572 { 5573 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5574 int error, value; 5575 5576 if (sc->hw.mac.type < igb_mac_min) 5577 value = sc->hw.dev_spec.ich8lan.eee_disable; 5578 else 5579 value = sc->hw.dev_spec._82575.eee_disable; 5580 error = sysctl_handle_int(oidp, &value, 0, req); 5581 if (error || req->newptr == NULL) 5582 return (error); 5583 if (sc->hw.mac.type < igb_mac_min) 5584 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5585 else 5586 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5587 em_if_init(sc->ctx); 5588 5589 return (0); 5590 } 5591 5592 static int 5593 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5594 { 5595 struct e1000_softc *sc; 5596 int error; 5597 int result; 5598 5599 result = -1; 5600 error = sysctl_handle_int(oidp, &result, 0, req); 5601 5602 if (error || !req->newptr) 5603 return (error); 5604 5605 if (result == 1) { 5606 sc = (struct e1000_softc *) arg1; 5607 em_print_debug_info(sc); 5608 } 5609 5610 return (error); 5611 } 5612 5613 static int 5614 em_get_rs(SYSCTL_HANDLER_ARGS) 5615 { 5616 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5617 int error; 5618 int result; 5619 5620 result = 0; 5621 error = sysctl_handle_int(oidp, &result, 0, req); 5622 5623 if (error || !req->newptr || result != 1) 5624 return (error); 5625 em_dump_rs(sc); 5626 5627 return (error); 5628 } 5629 5630 static void 5631 em_if_debug(if_ctx_t ctx) 5632 { 5633 em_dump_rs(iflib_get_softc(ctx)); 5634 } 5635 5636 /* 5637 * This routine is meant to be fluid, add whatever is 5638 * needed for debugging a problem. -jfv 5639 */ 5640 static void 5641 em_print_debug_info(struct e1000_softc *sc) 5642 { 5643 device_t dev = iflib_get_dev(sc->ctx); 5644 if_t ifp = iflib_get_ifp(sc->ctx); 5645 struct tx_ring *txr = &sc->tx_queues->txr; 5646 struct rx_ring *rxr = &sc->rx_queues->rxr; 5647 5648 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5649 printf("Interface is RUNNING "); 5650 else 5651 printf("Interface is NOT RUNNING\n"); 5652 5653 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5654 printf("and INACTIVE\n"); 5655 else 5656 printf("and ACTIVE\n"); 5657 5658 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5659 device_printf(dev, "TX Queue %d ------\n", i); 5660 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5661 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5662 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5663 5664 } 5665 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5666 device_printf(dev, "RX Queue %d ------\n", j); 5667 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5668 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5669 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5670 } 5671 } 5672 5673 /* 5674 * 82574 only: 5675 * Write a new value to the EEPROM increasing the number of MSI-X 5676 * vectors from 3 to 5, for proper multiqueue support. 5677 */ 5678 static void 5679 em_enable_vectors_82574(if_ctx_t ctx) 5680 { 5681 struct e1000_softc *sc = iflib_get_softc(ctx); 5682 struct e1000_hw *hw = &sc->hw; 5683 device_t dev = iflib_get_dev(ctx); 5684 u16 edata; 5685 5686 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5687 if (bootverbose) 5688 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5689 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5690 device_printf(dev, "Writing to eeprom: increasing " 5691 "reported MSI-X vectors from 3 to 5...\n"); 5692 edata &= ~(EM_NVM_MSIX_N_MASK); 5693 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5694 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5695 e1000_update_nvm_checksum(hw); 5696 device_printf(dev, "Writing to eeprom: done\n"); 5697 } 5698 } 5699