1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* $FreeBSD$ */ 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 char em_driver_version[] = "7.7.8-fbsd"; 41 char igb_driver_version[] = "2.5.19-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"), 57 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 58 PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"), 59 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 61 62 PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 63 PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"), 64 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"), 65 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 66 PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"), 67 PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"), 68 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 69 70 PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 71 72 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 73 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 74 75 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 76 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 77 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 78 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 79 80 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 81 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 82 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 83 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 84 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 85 86 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 87 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 88 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 89 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 90 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 91 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 92 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 93 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 94 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 95 96 PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"), 97 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 98 PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"), 99 100 /* Intel(R) - em-class devices */ 101 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 102 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 104 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 105 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 106 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 107 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 108 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 109 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 110 PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 111 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 113 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"), 114 PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"), 115 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"), 116 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 117 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 118 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"), 119 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"), 120 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"), 121 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"), 123 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 124 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 125 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 126 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 127 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 128 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 129 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 130 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"), 131 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"), 132 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 133 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 134 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 135 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 136 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 137 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 138 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 139 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 140 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 141 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 142 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 143 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 144 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 145 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 146 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 147 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 148 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 149 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 150 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 151 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 152 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 153 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 154 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 155 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"), 156 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 157 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 158 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 159 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 160 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 161 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 162 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 163 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"), 164 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"), 165 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"), 166 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"), 167 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 168 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"), 169 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 170 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"), 171 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 172 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"), 173 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 174 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"), 175 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 176 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"), 177 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 178 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"), 179 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"), 180 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"), 181 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"), 182 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"), 183 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"), 184 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"), 185 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"), 186 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"), 187 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"), 188 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"), 189 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"), 190 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"), 191 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"), 192 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"), 193 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"), 194 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"), 195 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"), 196 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"), 197 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"), 198 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"), 199 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"), 200 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"), 201 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"), 202 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"), 203 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"), 204 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"), 205 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"), 206 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"), 207 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"), 208 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"), 209 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"), 210 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"), 211 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"), 212 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"), 213 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"), 214 /* required last entry */ 215 PVID_END 216 }; 217 218 static pci_vendor_info_t igb_vendor_info_array[] = 219 { 220 /* Intel(R) - igb-class devices */ 221 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"), 222 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"), 223 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 224 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 225 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 226 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"), 227 PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 228 PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"), 229 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 230 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 231 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 232 PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"), 233 PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"), 234 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 235 PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"), 236 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 237 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"), 238 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"), 239 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"), 240 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"), 241 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 242 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"), 243 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 244 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 245 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 246 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 247 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 248 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 249 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"), 250 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 251 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"), 252 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"), 253 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"), 254 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 255 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 256 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 257 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 258 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"), 259 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"), 260 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 261 /* required last entry */ 262 PVID_END 263 }; 264 265 /********************************************************************* 266 * Function prototypes 267 *********************************************************************/ 268 static void *em_register(device_t); 269 static void *igb_register(device_t); 270 static int em_if_attach_pre(if_ctx_t); 271 static int em_if_attach_post(if_ctx_t); 272 static int em_if_detach(if_ctx_t); 273 static int em_if_shutdown(if_ctx_t); 274 static int em_if_suspend(if_ctx_t); 275 static int em_if_resume(if_ctx_t); 276 277 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 278 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int); 279 static void em_if_queues_free(if_ctx_t); 280 281 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 282 static void em_if_init(if_ctx_t); 283 static void em_if_stop(if_ctx_t); 284 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 285 static int em_if_media_change(if_ctx_t); 286 static int em_if_mtu_set(if_ctx_t, uint32_t); 287 static void em_if_timer(if_ctx_t, uint16_t); 288 static void em_if_vlan_register(if_ctx_t, u16); 289 static void em_if_vlan_unregister(if_ctx_t, u16); 290 static void em_if_watchdog_reset(if_ctx_t); 291 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 292 293 static void em_identify_hardware(if_ctx_t); 294 static int em_allocate_pci_resources(if_ctx_t); 295 static void em_free_pci_resources(if_ctx_t); 296 static void em_reset(if_ctx_t); 297 static int em_setup_interface(if_ctx_t); 298 static int em_setup_msix(if_ctx_t); 299 300 static void em_initialize_transmit_unit(if_ctx_t); 301 static void em_initialize_receive_unit(if_ctx_t); 302 303 static void em_if_intr_enable(if_ctx_t); 304 static void em_if_intr_disable(if_ctx_t); 305 static void igb_if_intr_enable(if_ctx_t); 306 static void igb_if_intr_disable(if_ctx_t); 307 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 308 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 309 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 310 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 311 static void em_if_multi_set(if_ctx_t); 312 static void em_if_update_admin_status(if_ctx_t); 313 static void em_if_debug(if_ctx_t); 314 static void em_update_stats_counters(struct e1000_softc *); 315 static void em_add_hw_stats(struct e1000_softc *); 316 static int em_if_set_promisc(if_ctx_t, int); 317 static bool em_if_vlan_filter_capable(if_ctx_t); 318 static bool em_if_vlan_filter_used(if_ctx_t); 319 static void em_if_vlan_filter_enable(struct e1000_softc *); 320 static void em_if_vlan_filter_disable(struct e1000_softc *); 321 static void em_if_vlan_filter_write(struct e1000_softc *); 322 static void em_setup_vlan_hw_support(if_ctx_t ctx); 323 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 324 static void em_print_nvm_info(struct e1000_softc *); 325 static void em_fw_version_locked(if_ctx_t); 326 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 327 static void em_print_fw_version(struct e1000_softc *); 328 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 329 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 330 static int em_get_rs(SYSCTL_HANDLER_ARGS); 331 static void em_print_debug_info(struct e1000_softc *); 332 static int em_is_valid_ether_addr(u8 *); 333 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 334 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 335 const char *, struct em_int_delay_info *, int, int); 336 /* Management and WOL Support */ 337 static void em_init_manageability(struct e1000_softc *); 338 static void em_release_manageability(struct e1000_softc *); 339 static void em_get_hw_control(struct e1000_softc *); 340 static void em_release_hw_control(struct e1000_softc *); 341 static void em_get_wakeup(if_ctx_t); 342 static void em_enable_wakeup(if_ctx_t); 343 static int em_enable_phy_wakeup(struct e1000_softc *); 344 static void em_disable_aspm(struct e1000_softc *); 345 346 int em_intr(void *); 347 348 /* MSI-X handlers */ 349 static int em_if_msix_intr_assign(if_ctx_t, int); 350 static int em_msix_link(void *); 351 static void em_handle_link(void *); 352 353 static void em_enable_vectors_82574(if_ctx_t); 354 355 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 356 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 357 static void em_if_led_func(if_ctx_t, int); 358 359 static int em_get_regs(SYSCTL_HANDLER_ARGS); 360 361 static void lem_smartspeed(struct e1000_softc *); 362 static void igb_configure_queues(struct e1000_softc *); 363 static void em_flush_desc_rings(struct e1000_softc *); 364 365 366 /********************************************************************* 367 * FreeBSD Device Interface Entry Points 368 *********************************************************************/ 369 static device_method_t em_methods[] = { 370 /* Device interface */ 371 DEVMETHOD(device_register, em_register), 372 DEVMETHOD(device_probe, iflib_device_probe), 373 DEVMETHOD(device_attach, iflib_device_attach), 374 DEVMETHOD(device_detach, iflib_device_detach), 375 DEVMETHOD(device_shutdown, iflib_device_shutdown), 376 DEVMETHOD(device_suspend, iflib_device_suspend), 377 DEVMETHOD(device_resume, iflib_device_resume), 378 DEVMETHOD_END 379 }; 380 381 static device_method_t igb_methods[] = { 382 /* Device interface */ 383 DEVMETHOD(device_register, igb_register), 384 DEVMETHOD(device_probe, iflib_device_probe), 385 DEVMETHOD(device_attach, iflib_device_attach), 386 DEVMETHOD(device_detach, iflib_device_detach), 387 DEVMETHOD(device_shutdown, iflib_device_shutdown), 388 DEVMETHOD(device_suspend, iflib_device_suspend), 389 DEVMETHOD(device_resume, iflib_device_resume), 390 DEVMETHOD_END 391 }; 392 393 394 static driver_t em_driver = { 395 "em", em_methods, sizeof(struct e1000_softc), 396 }; 397 398 DRIVER_MODULE(em, pci, em_driver, 0, 0); 399 400 MODULE_DEPEND(em, pci, 1, 1, 1); 401 MODULE_DEPEND(em, ether, 1, 1, 1); 402 MODULE_DEPEND(em, iflib, 1, 1, 1); 403 404 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 405 406 static driver_t igb_driver = { 407 "igb", igb_methods, sizeof(struct e1000_softc), 408 }; 409 410 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 411 412 MODULE_DEPEND(igb, pci, 1, 1, 1); 413 MODULE_DEPEND(igb, ether, 1, 1, 1); 414 MODULE_DEPEND(igb, iflib, 1, 1, 1); 415 416 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 417 418 static device_method_t em_if_methods[] = { 419 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 420 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 421 DEVMETHOD(ifdi_detach, em_if_detach), 422 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 423 DEVMETHOD(ifdi_suspend, em_if_suspend), 424 DEVMETHOD(ifdi_resume, em_if_resume), 425 DEVMETHOD(ifdi_init, em_if_init), 426 DEVMETHOD(ifdi_stop, em_if_stop), 427 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 428 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 429 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 430 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 431 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 432 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 433 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 434 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 435 DEVMETHOD(ifdi_media_status, em_if_media_status), 436 DEVMETHOD(ifdi_media_change, em_if_media_change), 437 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 438 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 439 DEVMETHOD(ifdi_timer, em_if_timer), 440 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 441 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 442 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 443 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 444 DEVMETHOD(ifdi_led_func, em_if_led_func), 445 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 446 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 447 DEVMETHOD(ifdi_debug, em_if_debug), 448 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 449 DEVMETHOD_END 450 }; 451 452 static driver_t em_if_driver = { 453 "em_if", em_if_methods, sizeof(struct e1000_softc) 454 }; 455 456 static device_method_t igb_if_methods[] = { 457 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 458 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 459 DEVMETHOD(ifdi_detach, em_if_detach), 460 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 461 DEVMETHOD(ifdi_suspend, em_if_suspend), 462 DEVMETHOD(ifdi_resume, em_if_resume), 463 DEVMETHOD(ifdi_init, em_if_init), 464 DEVMETHOD(ifdi_stop, em_if_stop), 465 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 466 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 467 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 468 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 469 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 470 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 471 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 472 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 473 DEVMETHOD(ifdi_media_status, em_if_media_status), 474 DEVMETHOD(ifdi_media_change, em_if_media_change), 475 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 476 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 477 DEVMETHOD(ifdi_timer, em_if_timer), 478 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 479 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 480 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 481 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 482 DEVMETHOD(ifdi_led_func, em_if_led_func), 483 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 484 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 485 DEVMETHOD(ifdi_debug, em_if_debug), 486 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 487 DEVMETHOD_END 488 }; 489 490 static driver_t igb_if_driver = { 491 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 492 }; 493 494 /********************************************************************* 495 * Tunable default values. 496 *********************************************************************/ 497 498 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 499 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 500 501 #define MAX_INTS_PER_SEC 8000 502 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 503 504 /* Allow common code without TSO */ 505 #ifndef CSUM_TSO 506 #define CSUM_TSO 0 507 #endif 508 509 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 510 "EM driver parameters"); 511 512 static int em_disable_crc_stripping = 0; 513 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 514 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 515 516 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 517 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 518 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt, 519 0, "Default transmit interrupt delay in usecs"); 520 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt, 521 0, "Default receive interrupt delay in usecs"); 522 523 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 524 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 525 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 526 &em_tx_abs_int_delay_dflt, 0, 527 "Default transmit interrupt delay limit in usecs"); 528 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 529 &em_rx_abs_int_delay_dflt, 0, 530 "Default receive interrupt delay limit in usecs"); 531 532 static int em_smart_pwr_down = false; 533 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down, 534 0, "Set to true to leave smart power down enabled on newer adapters"); 535 536 /* Controls whether promiscuous also shows bad packets */ 537 static int em_debug_sbp = false; 538 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 539 "Show bad packets in promiscuous mode"); 540 541 /* How many packets rxeof tries to clean at a time */ 542 static int em_rx_process_limit = 100; 543 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 544 &em_rx_process_limit, 0, 545 "Maximum number of received packets to process " 546 "at a time, -1 means unlimited"); 547 548 /* Energy efficient ethernet - default to OFF */ 549 static int eee_setting = 1; 550 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 551 "Enable Energy Efficient Ethernet"); 552 553 /* 554 ** Tuneable Interrupt rate 555 */ 556 static int em_max_interrupt_rate = 8000; 557 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 558 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 559 560 561 562 /* Global used in WOL setup with multiport cards */ 563 static int global_quad_port_a = 0; 564 565 extern struct if_txrx igb_txrx; 566 extern struct if_txrx em_txrx; 567 extern struct if_txrx lem_txrx; 568 569 static struct if_shared_ctx em_sctx_init = { 570 .isc_magic = IFLIB_MAGIC, 571 .isc_q_align = PAGE_SIZE, 572 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 573 .isc_tx_maxsegsize = PAGE_SIZE, 574 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 575 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 576 .isc_rx_maxsize = MJUM9BYTES, 577 .isc_rx_nsegments = 1, 578 .isc_rx_maxsegsize = MJUM9BYTES, 579 .isc_nfl = 1, 580 .isc_nrxqs = 1, 581 .isc_ntxqs = 1, 582 .isc_admin_intrcnt = 1, 583 .isc_vendor_info = em_vendor_info_array, 584 .isc_driver_version = em_driver_version, 585 .isc_driver = &em_if_driver, 586 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 587 588 .isc_nrxd_min = {EM_MIN_RXD}, 589 .isc_ntxd_min = {EM_MIN_TXD}, 590 .isc_nrxd_max = {EM_MAX_RXD}, 591 .isc_ntxd_max = {EM_MAX_TXD}, 592 .isc_nrxd_default = {EM_DEFAULT_RXD}, 593 .isc_ntxd_default = {EM_DEFAULT_TXD}, 594 }; 595 596 static struct if_shared_ctx igb_sctx_init = { 597 .isc_magic = IFLIB_MAGIC, 598 .isc_q_align = PAGE_SIZE, 599 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 600 .isc_tx_maxsegsize = PAGE_SIZE, 601 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 602 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 603 .isc_rx_maxsize = MJUM9BYTES, 604 .isc_rx_nsegments = 1, 605 .isc_rx_maxsegsize = MJUM9BYTES, 606 .isc_nfl = 1, 607 .isc_nrxqs = 1, 608 .isc_ntxqs = 1, 609 .isc_admin_intrcnt = 1, 610 .isc_vendor_info = igb_vendor_info_array, 611 .isc_driver_version = igb_driver_version, 612 .isc_driver = &igb_if_driver, 613 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 614 615 .isc_nrxd_min = {EM_MIN_RXD}, 616 .isc_ntxd_min = {EM_MIN_TXD}, 617 .isc_nrxd_max = {IGB_MAX_RXD}, 618 .isc_ntxd_max = {IGB_MAX_TXD}, 619 .isc_nrxd_default = {EM_DEFAULT_RXD}, 620 .isc_ntxd_default = {EM_DEFAULT_TXD}, 621 }; 622 623 /***************************************************************** 624 * 625 * Dump Registers 626 * 627 ****************************************************************/ 628 #define IGB_REGS_LEN 739 629 630 static int em_get_regs(SYSCTL_HANDLER_ARGS) 631 { 632 struct e1000_softc *sc = (struct e1000_softc *)arg1; 633 struct e1000_hw *hw = &sc->hw; 634 struct sbuf *sb; 635 u32 *regs_buff; 636 int rc; 637 638 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 639 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 640 641 rc = sysctl_wire_old_buffer(req, 0); 642 MPASS(rc == 0); 643 if (rc != 0) { 644 free(regs_buff, M_DEVBUF); 645 return (rc); 646 } 647 648 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 649 MPASS(sb != NULL); 650 if (sb == NULL) { 651 free(regs_buff, M_DEVBUF); 652 return (ENOMEM); 653 } 654 655 /* General Registers */ 656 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 657 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 658 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 659 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 660 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 661 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 662 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 663 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 664 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 665 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 666 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 667 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 668 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 669 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 670 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 671 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 672 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 673 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 674 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 675 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 676 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 677 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 678 679 sbuf_printf(sb, "General Registers\n"); 680 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 681 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 682 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 683 684 sbuf_printf(sb, "Interrupt Registers\n"); 685 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 686 687 sbuf_printf(sb, "RX Registers\n"); 688 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 689 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 690 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 691 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 692 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 693 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 694 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 695 696 sbuf_printf(sb, "TX Registers\n"); 697 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 698 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 699 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 700 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 701 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 702 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 703 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 704 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 705 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 706 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 707 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 708 709 free(regs_buff, M_DEVBUF); 710 711 #ifdef DUMP_DESCS 712 { 713 if_softc_ctx_t scctx = sc->shared; 714 struct rx_ring *rxr = &rx_que->rxr; 715 struct tx_ring *txr = &tx_que->txr; 716 int ntxd = scctx->isc_ntxd[0]; 717 int nrxd = scctx->isc_nrxd[0]; 718 int j; 719 720 for (j = 0; j < nrxd; j++) { 721 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 722 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 723 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 724 } 725 726 for (j = 0; j < min(ntxd, 256); j++) { 727 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 728 729 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 730 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 731 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0); 732 733 } 734 } 735 #endif 736 737 rc = sbuf_finish(sb); 738 sbuf_delete(sb); 739 return(rc); 740 } 741 742 static void * 743 em_register(device_t dev) 744 { 745 return (&em_sctx_init); 746 } 747 748 static void * 749 igb_register(device_t dev) 750 { 751 return (&igb_sctx_init); 752 } 753 754 static int 755 em_set_num_queues(if_ctx_t ctx) 756 { 757 struct e1000_softc *sc = iflib_get_softc(ctx); 758 int maxqueues; 759 760 /* Sanity check based on HW */ 761 switch (sc->hw.mac.type) { 762 case e1000_82576: 763 case e1000_82580: 764 case e1000_i350: 765 case e1000_i354: 766 maxqueues = 8; 767 break; 768 case e1000_i210: 769 case e1000_82575: 770 maxqueues = 4; 771 break; 772 case e1000_i211: 773 case e1000_82574: 774 maxqueues = 2; 775 break; 776 default: 777 maxqueues = 1; 778 break; 779 } 780 781 return (maxqueues); 782 } 783 784 #define LEM_CAPS \ 785 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 786 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 787 IFCAP_LRO | IFCAP_JUMBO_MTU 788 789 #define EM_CAPS \ 790 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 791 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 792 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 793 IFCAP_TSO6 794 795 #define IGB_CAPS \ 796 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 797 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 798 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 799 IFCAP_TSO6 800 801 /********************************************************************* 802 * Device initialization routine 803 * 804 * The attach entry point is called when the driver is being loaded. 805 * This routine identifies the type of hardware, allocates all resources 806 * and initializes the hardware. 807 * 808 * return 0 on success, positive on failure 809 *********************************************************************/ 810 static int 811 em_if_attach_pre(if_ctx_t ctx) 812 { 813 struct e1000_softc *sc; 814 if_softc_ctx_t scctx; 815 device_t dev; 816 struct e1000_hw *hw; 817 struct sysctl_oid_list *child; 818 struct sysctl_ctx_list *ctx_list; 819 int error = 0; 820 821 INIT_DEBUGOUT("em_if_attach_pre: begin"); 822 dev = iflib_get_dev(ctx); 823 sc = iflib_get_softc(ctx); 824 825 sc->ctx = sc->osdep.ctx = ctx; 826 sc->dev = sc->osdep.dev = dev; 827 scctx = sc->shared = iflib_get_softc_ctx(ctx); 828 sc->media = iflib_get_media(ctx); 829 hw = &sc->hw; 830 831 sc->tx_process_limit = scctx->isc_ntxd[0]; 832 833 /* Determine hardware and mac info */ 834 em_identify_hardware(ctx); 835 836 /* SYSCTL stuff */ 837 ctx_list = device_get_sysctl_ctx(dev); 838 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 839 840 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 841 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 842 em_sysctl_nvm_info, "I", "NVM Information"); 843 844 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 845 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 846 em_sysctl_print_fw_version, "A", 847 "Prints FW/NVM Versions"); 848 849 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 850 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 851 em_sysctl_debug_info, "I", "Debug Information"); 852 853 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 854 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 855 em_set_flowcntl, "I", "Flow Control"); 856 857 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 858 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 859 em_get_regs, "A", "Dump Registers"); 860 861 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 862 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 863 em_get_rs, "I", "Dump RS indexes"); 864 865 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 866 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 867 if (bootverbose) 868 device_printf(dev, "attach_pre capping queues at %d\n", 869 scctx->isc_ntxqsets_max); 870 871 if (hw->mac.type >= igb_mac_min) { 872 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 873 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 874 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 875 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 876 scctx->isc_txrx = &igb_txrx; 877 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 878 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 879 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 880 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 881 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 882 CSUM_IP6_TCP | CSUM_IP6_UDP; 883 if (hw->mac.type != e1000_82575) 884 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 885 /* 886 ** Some new devices, as with ixgbe, now may 887 ** use a different BAR, so we need to keep 888 ** track of which is used. 889 */ 890 scctx->isc_msix_bar = pci_msix_table_bar(dev); 891 } else if (hw->mac.type >= em_mac_min) { 892 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 893 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 894 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 895 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 896 scctx->isc_txrx = &em_txrx; 897 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 898 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 899 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 900 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 901 /* 902 * For EM-class devices, don't enable IFCAP_{TSO4,VLAN_HWTSO,TSO6} 903 * by default as we don't have workarounds for all associated 904 * silicon errata. E. g., with several MACs such as 82573E, 905 * TSO only works at Gigabit speed and otherwise can cause the 906 * hardware to hang (which also would be next to impossible to 907 * work around given that already queued TSO-using descriptors 908 * would need to be flushed and vlan(4) reconfigured at runtime 909 * in case of a link speed change). Moreover, MACs like 82579 910 * still can hang at Gigabit even with all publicly documented 911 * TSO workarounds implemented. Generally, the penality of 912 * these workarounds is rather high and may involve copying 913 * mbuf data around so advantages of TSO lapse. Still, TSO may 914 * work for a few MACs of this class - at least when sticking 915 * with Gigabit - in which case users may enable TSO manually. 916 */ 917 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO | IFCAP_TSO6); 918 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 919 CSUM_IP6_TCP | CSUM_IP6_UDP; 920 /* 921 * We support MSI-X with 82574 only, but indicate to iflib(4) 922 * that it shall give MSI at least a try with other devices. 923 */ 924 if (hw->mac.type == e1000_82574) { 925 scctx->isc_msix_bar = pci_msix_table_bar(dev); 926 } else { 927 scctx->isc_msix_bar = -1; 928 scctx->isc_disable_msix = 1; 929 } 930 } else { 931 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 932 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 933 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 934 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 935 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP; 936 scctx->isc_txrx = &lem_txrx; 937 scctx->isc_capabilities = LEM_CAPS; 938 939 /* 940 * For LEM-class devices, don't enable IFCAP {TSO4,VLAN_HWTSO} 941 * by default as we don't have workarounds for all associated 942 * silicon errata. TSO4 may work on > 82544 but its status 943 * is unknown by the authors. Please report any success or failures. 944 */ 945 scctx->isc_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 946 947 /* 8254x SDM4.0 page 33 - FDX requirement on these chips */ 948 if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2) 949 scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 950 951 if (hw->mac.type < e1000_82543) 952 scctx->isc_capabilities &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM); 953 /* 82541ER doesn't do HW tagging */ 954 if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM) 955 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 956 /* INTx only */ 957 scctx->isc_msix_bar = 0; 958 scctx->isc_capenable = scctx->isc_capabilities; 959 } 960 961 /* Setup PCI resources */ 962 if (em_allocate_pci_resources(ctx)) { 963 device_printf(dev, "Allocation of PCI resources failed\n"); 964 error = ENXIO; 965 goto err_pci; 966 } 967 968 /* 969 ** For ICH8 and family we need to 970 ** map the flash memory, and this 971 ** must happen after the MAC is 972 ** identified 973 */ 974 if ((hw->mac.type == e1000_ich8lan) || 975 (hw->mac.type == e1000_ich9lan) || 976 (hw->mac.type == e1000_ich10lan) || 977 (hw->mac.type == e1000_pchlan) || 978 (hw->mac.type == e1000_pch2lan) || 979 (hw->mac.type == e1000_pch_lpt)) { 980 int rid = EM_BAR_TYPE_FLASH; 981 sc->flash = bus_alloc_resource_any(dev, 982 SYS_RES_MEMORY, &rid, RF_ACTIVE); 983 if (sc->flash == NULL) { 984 device_printf(dev, "Mapping of Flash failed\n"); 985 error = ENXIO; 986 goto err_pci; 987 } 988 /* This is used in the shared code */ 989 hw->flash_address = (u8 *)sc->flash; 990 sc->osdep.flash_bus_space_tag = 991 rman_get_bustag(sc->flash); 992 sc->osdep.flash_bus_space_handle = 993 rman_get_bushandle(sc->flash); 994 } 995 /* 996 ** In the new SPT device flash is not a 997 ** separate BAR, rather it is also in BAR0, 998 ** so use the same tag and an offset handle for the 999 ** FLASH read/write macros in the shared code. 1000 */ 1001 else if (hw->mac.type >= e1000_pch_spt) { 1002 sc->osdep.flash_bus_space_tag = 1003 sc->osdep.mem_bus_space_tag; 1004 sc->osdep.flash_bus_space_handle = 1005 sc->osdep.mem_bus_space_handle 1006 + E1000_FLASH_BASE_ADDR; 1007 } 1008 1009 /* Do Shared Code initialization */ 1010 error = e1000_setup_init_funcs(hw, true); 1011 if (error) { 1012 device_printf(dev, "Setup of Shared code failed, error %d\n", 1013 error); 1014 error = ENXIO; 1015 goto err_pci; 1016 } 1017 1018 em_setup_msix(ctx); 1019 e1000_get_bus_info(hw); 1020 1021 /* Set up some sysctls for the tunable interrupt delays */ 1022 em_add_int_delay_sysctl(sc, "rx_int_delay", 1023 "receive interrupt delay in usecs", &sc->rx_int_delay, 1024 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1025 em_add_int_delay_sysctl(sc, "tx_int_delay", 1026 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1027 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1028 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1029 "receive interrupt delay limit in usecs", 1030 &sc->rx_abs_int_delay, 1031 E1000_REGISTER(hw, E1000_RADV), 1032 em_rx_abs_int_delay_dflt); 1033 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1034 "transmit interrupt delay limit in usecs", 1035 &sc->tx_abs_int_delay, 1036 E1000_REGISTER(hw, E1000_TADV), 1037 em_tx_abs_int_delay_dflt); 1038 em_add_int_delay_sysctl(sc, "itr", 1039 "interrupt delay limit in usecs/4", 1040 &sc->tx_itr, 1041 E1000_REGISTER(hw, E1000_ITR), 1042 DEFAULT_ITR); 1043 1044 hw->mac.autoneg = DO_AUTO_NEG; 1045 hw->phy.autoneg_wait_to_complete = false; 1046 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1047 1048 if (hw->mac.type < em_mac_min) { 1049 e1000_init_script_state_82541(hw, true); 1050 e1000_set_tbi_compatibility_82543(hw, true); 1051 } 1052 /* Copper options */ 1053 if (hw->phy.media_type == e1000_media_type_copper) { 1054 hw->phy.mdix = AUTO_ALL_MODES; 1055 hw->phy.disable_polarity_correction = false; 1056 hw->phy.ms_type = EM_MASTER_SLAVE; 1057 } 1058 1059 /* 1060 * Set the frame limits assuming 1061 * standard ethernet sized frames. 1062 */ 1063 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1064 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1065 1066 /* 1067 * This controls when hardware reports transmit completion 1068 * status. 1069 */ 1070 hw->mac.report_tx_early = 1; 1071 1072 /* Allocate multicast array memory. */ 1073 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1074 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1075 if (sc->mta == NULL) { 1076 device_printf(dev, "Can not allocate multicast setup array\n"); 1077 error = ENOMEM; 1078 goto err_late; 1079 } 1080 1081 /* Check SOL/IDER usage */ 1082 if (e1000_check_reset_block(hw)) 1083 device_printf(dev, "PHY reset is blocked" 1084 " due to SOL/IDER session.\n"); 1085 1086 /* Sysctl for setting Energy Efficient Ethernet */ 1087 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1088 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1089 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1090 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1091 1092 /* 1093 ** Start from a known state, this is 1094 ** important in reading the nvm and 1095 ** mac from that. 1096 */ 1097 e1000_reset_hw(hw); 1098 1099 /* Make sure we have a good EEPROM before we read from it */ 1100 if (e1000_validate_nvm_checksum(hw) < 0) { 1101 /* 1102 ** Some PCI-E parts fail the first check due to 1103 ** the link being in sleep state, call it again, 1104 ** if it fails a second time its a real issue. 1105 */ 1106 if (e1000_validate_nvm_checksum(hw) < 0) { 1107 device_printf(dev, 1108 "The EEPROM Checksum Is Not Valid\n"); 1109 error = EIO; 1110 goto err_late; 1111 } 1112 } 1113 1114 /* Copy the permanent MAC address out of the EEPROM */ 1115 if (e1000_read_mac_addr(hw) < 0) { 1116 device_printf(dev, "EEPROM read error while reading MAC" 1117 " address\n"); 1118 error = EIO; 1119 goto err_late; 1120 } 1121 1122 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1123 if (sc->vf_ifp) { 1124 ether_gen_addr(iflib_get_ifp(ctx), 1125 (struct ether_addr *)hw->mac.addr); 1126 } else { 1127 device_printf(dev, "Invalid MAC address\n"); 1128 error = EIO; 1129 goto err_late; 1130 } 1131 } 1132 1133 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1134 em_fw_version_locked(ctx); 1135 1136 em_print_fw_version(sc); 1137 1138 /* 1139 * Get Wake-on-Lan and Management info for later use 1140 */ 1141 em_get_wakeup(ctx); 1142 1143 /* Enable only WOL MAGIC by default */ 1144 scctx->isc_capenable &= ~IFCAP_WOL; 1145 if (sc->wol != 0) 1146 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1147 1148 iflib_set_mac(ctx, hw->mac.addr); 1149 1150 return (0); 1151 1152 err_late: 1153 em_release_hw_control(sc); 1154 err_pci: 1155 em_free_pci_resources(ctx); 1156 free(sc->mta, M_DEVBUF); 1157 1158 return (error); 1159 } 1160 1161 static int 1162 em_if_attach_post(if_ctx_t ctx) 1163 { 1164 struct e1000_softc *sc = iflib_get_softc(ctx); 1165 struct e1000_hw *hw = &sc->hw; 1166 int error = 0; 1167 1168 /* Setup OS specific network interface */ 1169 error = em_setup_interface(ctx); 1170 if (error != 0) { 1171 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1172 goto err_late; 1173 } 1174 1175 em_reset(ctx); 1176 1177 /* Initialize statistics */ 1178 em_update_stats_counters(sc); 1179 hw->mac.get_link_status = 1; 1180 em_if_update_admin_status(ctx); 1181 em_add_hw_stats(sc); 1182 1183 /* Non-AMT based hardware can now take control from firmware */ 1184 if (sc->has_manage && !sc->has_amt) 1185 em_get_hw_control(sc); 1186 1187 INIT_DEBUGOUT("em_if_attach_post: end"); 1188 1189 return (0); 1190 1191 err_late: 1192 /* upon attach_post() error, iflib calls _if_detach() to free resources. */ 1193 return (error); 1194 } 1195 1196 /********************************************************************* 1197 * Device removal routine 1198 * 1199 * The detach entry point is called when the driver is being removed. 1200 * This routine stops the adapter and deallocates all the resources 1201 * that were allocated for driver operation. 1202 * 1203 * return 0 on success, positive on failure 1204 *********************************************************************/ 1205 static int 1206 em_if_detach(if_ctx_t ctx) 1207 { 1208 struct e1000_softc *sc = iflib_get_softc(ctx); 1209 1210 INIT_DEBUGOUT("em_if_detach: begin"); 1211 1212 e1000_phy_hw_reset(&sc->hw); 1213 1214 em_release_manageability(sc); 1215 em_release_hw_control(sc); 1216 em_free_pci_resources(ctx); 1217 free(sc->mta, M_DEVBUF); 1218 sc->mta = NULL; 1219 1220 return (0); 1221 } 1222 1223 /********************************************************************* 1224 * 1225 * Shutdown entry point 1226 * 1227 **********************************************************************/ 1228 1229 static int 1230 em_if_shutdown(if_ctx_t ctx) 1231 { 1232 return em_if_suspend(ctx); 1233 } 1234 1235 /* 1236 * Suspend/resume device methods. 1237 */ 1238 static int 1239 em_if_suspend(if_ctx_t ctx) 1240 { 1241 struct e1000_softc *sc = iflib_get_softc(ctx); 1242 1243 em_release_manageability(sc); 1244 em_release_hw_control(sc); 1245 em_enable_wakeup(ctx); 1246 return (0); 1247 } 1248 1249 static int 1250 em_if_resume(if_ctx_t ctx) 1251 { 1252 struct e1000_softc *sc = iflib_get_softc(ctx); 1253 1254 if (sc->hw.mac.type == e1000_pch2lan) 1255 e1000_resume_workarounds_pchlan(&sc->hw); 1256 em_if_init(ctx); 1257 em_init_manageability(sc); 1258 1259 return(0); 1260 } 1261 1262 static int 1263 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1264 { 1265 int max_frame_size; 1266 struct e1000_softc *sc = iflib_get_softc(ctx); 1267 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1268 1269 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1270 1271 switch (sc->hw.mac.type) { 1272 case e1000_82571: 1273 case e1000_82572: 1274 case e1000_ich9lan: 1275 case e1000_ich10lan: 1276 case e1000_pch2lan: 1277 case e1000_pch_lpt: 1278 case e1000_pch_spt: 1279 case e1000_pch_cnp: 1280 case e1000_pch_tgp: 1281 case e1000_pch_adp: 1282 case e1000_pch_mtp: 1283 case e1000_pch_ptp: 1284 case e1000_82574: 1285 case e1000_82583: 1286 case e1000_80003es2lan: 1287 /* 9K Jumbo Frame size */ 1288 max_frame_size = 9234; 1289 break; 1290 case e1000_pchlan: 1291 max_frame_size = 4096; 1292 break; 1293 case e1000_82542: 1294 case e1000_ich8lan: 1295 /* Adapters that do not support jumbo frames */ 1296 max_frame_size = ETHER_MAX_LEN; 1297 break; 1298 default: 1299 if (sc->hw.mac.type >= igb_mac_min) 1300 max_frame_size = 9234; 1301 else /* lem */ 1302 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1303 } 1304 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1305 return (EINVAL); 1306 } 1307 1308 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1309 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1310 return (0); 1311 } 1312 1313 /********************************************************************* 1314 * Init entry point 1315 * 1316 * This routine is used in two ways. It is used by the stack as 1317 * init entry point in network interface structure. It is also used 1318 * by the driver as a hw/sw initialization routine to get to a 1319 * consistent state. 1320 * 1321 **********************************************************************/ 1322 static void 1323 em_if_init(if_ctx_t ctx) 1324 { 1325 struct e1000_softc *sc = iflib_get_softc(ctx); 1326 if_softc_ctx_t scctx = sc->shared; 1327 if_t ifp = iflib_get_ifp(ctx); 1328 struct em_tx_queue *tx_que; 1329 int i; 1330 1331 INIT_DEBUGOUT("em_if_init: begin"); 1332 1333 /* Get the latest mac address, User can use a LAA */ 1334 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 1335 ETHER_ADDR_LEN); 1336 1337 /* Put the address into the Receive Address Array */ 1338 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1339 1340 /* 1341 * With the 82571 adapter, RAR[0] may be overwritten 1342 * when the other port is reset, we make a duplicate 1343 * in RAR[14] for that eventuality, this assures 1344 * the interface continues to function. 1345 */ 1346 if (sc->hw.mac.type == e1000_82571) { 1347 e1000_set_laa_state_82571(&sc->hw, true); 1348 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1349 E1000_RAR_ENTRIES - 1); 1350 } 1351 1352 1353 /* Initialize the hardware */ 1354 em_reset(ctx); 1355 em_if_update_admin_status(ctx); 1356 1357 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) { 1358 struct tx_ring *txr = &tx_que->txr; 1359 1360 txr->tx_rs_cidx = txr->tx_rs_pidx; 1361 1362 /* Initialize the last processed descriptor to be the end of 1363 * the ring, rather than the start, so that we avoid an 1364 * off-by-one error when calculating how many descriptors are 1365 * done in the credits_update function. 1366 */ 1367 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1368 } 1369 1370 /* Setup VLAN support, basic and offload if available */ 1371 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1372 1373 /* Clear bad data from Rx FIFOs */ 1374 if (sc->hw.mac.type >= igb_mac_min) 1375 e1000_rx_fifo_flush_base(&sc->hw); 1376 1377 /* Configure for OS presence */ 1378 em_init_manageability(sc); 1379 1380 /* Prepare transmit descriptors and buffers */ 1381 em_initialize_transmit_unit(ctx); 1382 1383 /* Setup Multicast table */ 1384 em_if_multi_set(ctx); 1385 1386 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1387 em_initialize_receive_unit(ctx); 1388 1389 /* Set up VLAN support and filter */ 1390 em_setup_vlan_hw_support(ctx); 1391 1392 /* Don't lose promiscuous settings */ 1393 em_if_set_promisc(ctx, if_getflags(ifp)); 1394 e1000_clear_hw_cntrs_base_generic(&sc->hw); 1395 1396 /* MSI-X configuration for 82574 */ 1397 if (sc->hw.mac.type == e1000_82574) { 1398 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1399 1400 tmp |= E1000_CTRL_EXT_PBA_CLR; 1401 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1402 /* Set the IVAR - interrupt vector routing. */ 1403 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1404 } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 1405 igb_configure_queues(sc); 1406 1407 /* this clears any pending interrupts */ 1408 E1000_READ_REG(&sc->hw, E1000_ICR); 1409 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1410 1411 /* AMT based hardware can now take control from firmware */ 1412 if (sc->has_manage && sc->has_amt) 1413 em_get_hw_control(sc); 1414 1415 /* Set Energy Efficient Ethernet */ 1416 if (sc->hw.mac.type >= igb_mac_min && 1417 sc->hw.phy.media_type == e1000_media_type_copper) { 1418 if (sc->hw.mac.type == e1000_i354) 1419 e1000_set_eee_i354(&sc->hw, true, true); 1420 else 1421 e1000_set_eee_i350(&sc->hw, true, true); 1422 } 1423 } 1424 1425 /********************************************************************* 1426 * 1427 * Fast Legacy/MSI Combined Interrupt Service routine 1428 * 1429 *********************************************************************/ 1430 int 1431 em_intr(void *arg) 1432 { 1433 struct e1000_softc *sc = arg; 1434 if_ctx_t ctx = sc->ctx; 1435 u32 reg_icr; 1436 1437 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1438 1439 /* Hot eject? */ 1440 if (reg_icr == 0xffffffff) 1441 return FILTER_STRAY; 1442 1443 /* Definitely not our interrupt. */ 1444 if (reg_icr == 0x0) 1445 return FILTER_STRAY; 1446 1447 /* 1448 * Starting with the 82571 chip, bit 31 should be used to 1449 * determine whether the interrupt belongs to us. 1450 */ 1451 if (sc->hw.mac.type >= e1000_82571 && 1452 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1453 return FILTER_STRAY; 1454 1455 /* 1456 * Only MSI-X interrupts have one-shot behavior by taking advantage 1457 * of the EIAC register. Thus, explicitly disable interrupts. This 1458 * also works around the MSI message reordering errata on certain 1459 * systems. 1460 */ 1461 IFDI_INTR_DISABLE(ctx); 1462 1463 /* Link status change */ 1464 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1465 em_handle_link(ctx); 1466 1467 if (reg_icr & E1000_ICR_RXO) 1468 sc->rx_overruns++; 1469 1470 return (FILTER_SCHEDULE_THREAD); 1471 } 1472 1473 static int 1474 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1475 { 1476 struct e1000_softc *sc = iflib_get_softc(ctx); 1477 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1478 1479 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1480 return (0); 1481 } 1482 1483 static int 1484 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1485 { 1486 struct e1000_softc *sc = iflib_get_softc(ctx); 1487 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1488 1489 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1490 return (0); 1491 } 1492 1493 static int 1494 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1495 { 1496 struct e1000_softc *sc = iflib_get_softc(ctx); 1497 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1498 1499 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1500 return (0); 1501 } 1502 1503 static int 1504 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1505 { 1506 struct e1000_softc *sc = iflib_get_softc(ctx); 1507 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1508 1509 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1510 return (0); 1511 } 1512 1513 /********************************************************************* 1514 * 1515 * MSI-X RX Interrupt Service routine 1516 * 1517 **********************************************************************/ 1518 static int 1519 em_msix_que(void *arg) 1520 { 1521 struct em_rx_queue *que = arg; 1522 1523 ++que->irqs; 1524 1525 return (FILTER_SCHEDULE_THREAD); 1526 } 1527 1528 /********************************************************************* 1529 * 1530 * MSI-X Link Fast Interrupt Service routine 1531 * 1532 **********************************************************************/ 1533 static int 1534 em_msix_link(void *arg) 1535 { 1536 struct e1000_softc *sc = arg; 1537 u32 reg_icr; 1538 1539 ++sc->link_irq; 1540 MPASS(sc->hw.back != NULL); 1541 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1542 1543 if (reg_icr & E1000_ICR_RXO) 1544 sc->rx_overruns++; 1545 1546 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1547 em_handle_link(sc->ctx); 1548 1549 /* Re-arm unconditionally */ 1550 if (sc->hw.mac.type >= igb_mac_min) { 1551 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1552 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1553 } else if (sc->hw.mac.type == e1000_82574) { 1554 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC | 1555 E1000_IMS_OTHER); 1556 /* 1557 * Because we must read the ICR for this interrupt it may 1558 * clear other causes using autoclear, for this reason we 1559 * simply create a soft interrupt for all these vectors. 1560 */ 1561 if (reg_icr) 1562 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1563 } else 1564 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1565 1566 return (FILTER_HANDLED); 1567 } 1568 1569 static void 1570 em_handle_link(void *context) 1571 { 1572 if_ctx_t ctx = context; 1573 struct e1000_softc *sc = iflib_get_softc(ctx); 1574 1575 sc->hw.mac.get_link_status = 1; 1576 iflib_admin_intr_deferred(ctx); 1577 } 1578 1579 /********************************************************************* 1580 * 1581 * Media Ioctl callback 1582 * 1583 * This routine is called whenever the user queries the status of 1584 * the interface using ifconfig. 1585 * 1586 **********************************************************************/ 1587 static void 1588 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1589 { 1590 struct e1000_softc *sc = iflib_get_softc(ctx); 1591 u_char fiber_type = IFM_1000_SX; 1592 1593 INIT_DEBUGOUT("em_if_media_status: begin"); 1594 1595 iflib_admin_intr_deferred(ctx); 1596 1597 ifmr->ifm_status = IFM_AVALID; 1598 ifmr->ifm_active = IFM_ETHER; 1599 1600 if (!sc->link_active) { 1601 return; 1602 } 1603 1604 ifmr->ifm_status |= IFM_ACTIVE; 1605 1606 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 1607 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1608 if (sc->hw.mac.type == e1000_82545) 1609 fiber_type = IFM_1000_LX; 1610 ifmr->ifm_active |= fiber_type | IFM_FDX; 1611 } else { 1612 switch (sc->link_speed) { 1613 case 10: 1614 ifmr->ifm_active |= IFM_10_T; 1615 break; 1616 case 100: 1617 ifmr->ifm_active |= IFM_100_TX; 1618 break; 1619 case 1000: 1620 ifmr->ifm_active |= IFM_1000_T; 1621 break; 1622 } 1623 if (sc->link_duplex == FULL_DUPLEX) 1624 ifmr->ifm_active |= IFM_FDX; 1625 else 1626 ifmr->ifm_active |= IFM_HDX; 1627 } 1628 } 1629 1630 /********************************************************************* 1631 * 1632 * Media Ioctl callback 1633 * 1634 * This routine is called when the user changes speed/duplex using 1635 * media/mediopt option with ifconfig. 1636 * 1637 **********************************************************************/ 1638 static int 1639 em_if_media_change(if_ctx_t ctx) 1640 { 1641 struct e1000_softc *sc = iflib_get_softc(ctx); 1642 struct ifmedia *ifm = iflib_get_media(ctx); 1643 1644 INIT_DEBUGOUT("em_if_media_change: begin"); 1645 1646 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1647 return (EINVAL); 1648 1649 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1650 case IFM_AUTO: 1651 sc->hw.mac.autoneg = DO_AUTO_NEG; 1652 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1653 break; 1654 case IFM_1000_LX: 1655 case IFM_1000_SX: 1656 case IFM_1000_T: 1657 sc->hw.mac.autoneg = DO_AUTO_NEG; 1658 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1659 break; 1660 case IFM_100_TX: 1661 sc->hw.mac.autoneg = false; 1662 sc->hw.phy.autoneg_advertised = 0; 1663 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1664 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1665 else 1666 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1667 break; 1668 case IFM_10_T: 1669 sc->hw.mac.autoneg = false; 1670 sc->hw.phy.autoneg_advertised = 0; 1671 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1672 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1673 else 1674 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1675 break; 1676 default: 1677 device_printf(sc->dev, "Unsupported media type\n"); 1678 } 1679 1680 em_if_init(ctx); 1681 1682 return (0); 1683 } 1684 1685 static int 1686 em_if_set_promisc(if_ctx_t ctx, int flags) 1687 { 1688 struct e1000_softc *sc = iflib_get_softc(ctx); 1689 if_t ifp = iflib_get_ifp(ctx); 1690 u32 reg_rctl; 1691 int mcnt = 0; 1692 1693 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1694 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 1695 if (flags & IFF_ALLMULTI) 1696 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1697 else 1698 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1699 1700 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1701 reg_rctl &= (~E1000_RCTL_MPE); 1702 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1703 1704 if (flags & IFF_PROMISC) { 1705 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1706 em_if_vlan_filter_disable(sc); 1707 /* Turn this on if you want to see bad packets */ 1708 if (em_debug_sbp) 1709 reg_rctl |= E1000_RCTL_SBP; 1710 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1711 } else { 1712 if (flags & IFF_ALLMULTI) { 1713 reg_rctl |= E1000_RCTL_MPE; 1714 reg_rctl &= ~E1000_RCTL_UPE; 1715 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1716 } 1717 if (em_if_vlan_filter_used(ctx)) 1718 em_if_vlan_filter_enable(sc); 1719 } 1720 return (0); 1721 } 1722 1723 static u_int 1724 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1725 { 1726 u8 *mta = arg; 1727 1728 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1729 return (0); 1730 1731 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1732 1733 return (1); 1734 } 1735 1736 /********************************************************************* 1737 * Multicast Update 1738 * 1739 * This routine is called whenever multicast address list is updated. 1740 * 1741 **********************************************************************/ 1742 static void 1743 em_if_multi_set(if_ctx_t ctx) 1744 { 1745 struct e1000_softc *sc = iflib_get_softc(ctx); 1746 if_t ifp = iflib_get_ifp(ctx); 1747 u8 *mta; /* Multicast array memory */ 1748 u32 reg_rctl = 0; 1749 int mcnt = 0; 1750 1751 IOCTL_DEBUGOUT("em_set_multi: begin"); 1752 1753 mta = sc->mta; 1754 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1755 1756 if (sc->hw.mac.type == e1000_82542 && 1757 sc->hw.revision_id == E1000_REVISION_2) { 1758 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1759 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1760 e1000_pci_clear_mwi(&sc->hw); 1761 reg_rctl |= E1000_RCTL_RST; 1762 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1763 msec_delay(5); 1764 } 1765 1766 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 1767 1768 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1769 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 1770 1771 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1772 1773 if (if_getflags(ifp) & IFF_PROMISC) 1774 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1775 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1776 if_getflags(ifp) & IFF_ALLMULTI) { 1777 reg_rctl |= E1000_RCTL_MPE; 1778 reg_rctl &= ~E1000_RCTL_UPE; 1779 } else 1780 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 1781 1782 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1783 1784 if (sc->hw.mac.type == e1000_82542 && 1785 sc->hw.revision_id == E1000_REVISION_2) { 1786 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 1787 reg_rctl &= ~E1000_RCTL_RST; 1788 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 1789 msec_delay(5); 1790 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1791 e1000_pci_set_mwi(&sc->hw); 1792 } 1793 } 1794 1795 /********************************************************************* 1796 * Timer routine 1797 * 1798 * This routine schedules em_if_update_admin_status() to check for 1799 * link status and to gather statistics as well as to perform some 1800 * controller-specific hardware patting. 1801 * 1802 **********************************************************************/ 1803 static void 1804 em_if_timer(if_ctx_t ctx, uint16_t qid) 1805 { 1806 1807 if (qid != 0) 1808 return; 1809 1810 iflib_admin_intr_deferred(ctx); 1811 } 1812 1813 static void 1814 em_if_update_admin_status(if_ctx_t ctx) 1815 { 1816 struct e1000_softc *sc = iflib_get_softc(ctx); 1817 struct e1000_hw *hw = &sc->hw; 1818 device_t dev = iflib_get_dev(ctx); 1819 u32 link_check, thstat, ctrl; 1820 1821 link_check = thstat = ctrl = 0; 1822 /* Get the cached link value or read phy for real */ 1823 switch (hw->phy.media_type) { 1824 case e1000_media_type_copper: 1825 if (hw->mac.get_link_status) { 1826 if (hw->mac.type == e1000_pch_spt) 1827 msec_delay(50); 1828 /* Do the work to read phy */ 1829 e1000_check_for_link(hw); 1830 link_check = !hw->mac.get_link_status; 1831 if (link_check) /* ESB2 fix */ 1832 e1000_cfg_on_link_up(hw); 1833 } else { 1834 link_check = true; 1835 } 1836 break; 1837 case e1000_media_type_fiber: 1838 e1000_check_for_link(hw); 1839 link_check = (E1000_READ_REG(hw, E1000_STATUS) & 1840 E1000_STATUS_LU); 1841 break; 1842 case e1000_media_type_internal_serdes: 1843 e1000_check_for_link(hw); 1844 link_check = hw->mac.serdes_has_link; 1845 break; 1846 /* VF device is type_unknown */ 1847 case e1000_media_type_unknown: 1848 e1000_check_for_link(hw); 1849 link_check = !hw->mac.get_link_status; 1850 /* FALLTHROUGH */ 1851 default: 1852 break; 1853 } 1854 1855 /* Check for thermal downshift or shutdown */ 1856 if (hw->mac.type == e1000_i350) { 1857 thstat = E1000_READ_REG(hw, E1000_THSTAT); 1858 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 1859 } 1860 1861 /* Now check for a transition */ 1862 if (link_check && (sc->link_active == 0)) { 1863 e1000_get_speed_and_duplex(hw, &sc->link_speed, 1864 &sc->link_duplex); 1865 /* Check if we must disable SPEED_MODE bit on PCI-E */ 1866 if ((sc->link_speed != SPEED_1000) && 1867 ((hw->mac.type == e1000_82571) || 1868 (hw->mac.type == e1000_82572))) { 1869 int tarc0; 1870 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 1871 tarc0 &= ~TARC_SPEED_MODE_BIT; 1872 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 1873 } 1874 if (bootverbose) 1875 device_printf(dev, "Link is up %d Mbps %s\n", 1876 sc->link_speed, 1877 ((sc->link_duplex == FULL_DUPLEX) ? 1878 "Full Duplex" : "Half Duplex")); 1879 sc->link_active = 1; 1880 sc->smartspeed = 0; 1881 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 1882 E1000_CTRL_EXT_LINK_MODE_GMII && 1883 (thstat & E1000_THSTAT_LINK_THROTTLE)) 1884 device_printf(dev, "Link: thermal downshift\n"); 1885 /* Delay Link Up for Phy update */ 1886 if (((hw->mac.type == e1000_i210) || 1887 (hw->mac.type == e1000_i211)) && 1888 (hw->phy.id == I210_I_PHY_ID)) 1889 msec_delay(I210_LINK_DELAY); 1890 /* Reset if the media type changed. */ 1891 if (hw->dev_spec._82575.media_changed && 1892 hw->mac.type >= igb_mac_min) { 1893 hw->dev_spec._82575.media_changed = false; 1894 sc->flags |= IGB_MEDIA_RESET; 1895 em_reset(ctx); 1896 } 1897 iflib_link_state_change(ctx, LINK_STATE_UP, 1898 IF_Mbps(sc->link_speed)); 1899 } else if (!link_check && (sc->link_active == 1)) { 1900 sc->link_speed = 0; 1901 sc->link_duplex = 0; 1902 sc->link_active = 0; 1903 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1904 } 1905 em_update_stats_counters(sc); 1906 1907 /* Reset LAA into RAR[0] on 82571 */ 1908 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 1909 e1000_rar_set(hw, hw->mac.addr, 0); 1910 1911 if (hw->mac.type < em_mac_min) 1912 lem_smartspeed(sc); 1913 } 1914 1915 static void 1916 em_if_watchdog_reset(if_ctx_t ctx) 1917 { 1918 struct e1000_softc *sc = iflib_get_softc(ctx); 1919 1920 /* 1921 * Just count the event; iflib(4) will already trigger a 1922 * sufficient reset of the controller. 1923 */ 1924 sc->watchdog_events++; 1925 } 1926 1927 /********************************************************************* 1928 * 1929 * This routine disables all traffic on the adapter by issuing a 1930 * global reset on the MAC. 1931 * 1932 **********************************************************************/ 1933 static void 1934 em_if_stop(if_ctx_t ctx) 1935 { 1936 struct e1000_softc *sc = iflib_get_softc(ctx); 1937 1938 INIT_DEBUGOUT("em_if_stop: begin"); 1939 1940 /* I219 needs special flushing to avoid hangs */ 1941 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 1942 em_flush_desc_rings(sc); 1943 1944 e1000_reset_hw(&sc->hw); 1945 if (sc->hw.mac.type >= e1000_82544) 1946 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 1947 1948 e1000_led_off(&sc->hw); 1949 e1000_cleanup_led(&sc->hw); 1950 } 1951 1952 /********************************************************************* 1953 * 1954 * Determine hardware revision. 1955 * 1956 **********************************************************************/ 1957 static void 1958 em_identify_hardware(if_ctx_t ctx) 1959 { 1960 device_t dev = iflib_get_dev(ctx); 1961 struct e1000_softc *sc = iflib_get_softc(ctx); 1962 1963 /* Make sure our PCI config space has the necessary stuff set */ 1964 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1965 1966 /* Save off the information about this board */ 1967 sc->hw.vendor_id = pci_get_vendor(dev); 1968 sc->hw.device_id = pci_get_device(dev); 1969 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1970 sc->hw.subsystem_vendor_id = 1971 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1972 sc->hw.subsystem_device_id = 1973 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1974 1975 /* Do Shared Code Init and Setup */ 1976 if (e1000_set_mac_type(&sc->hw)) { 1977 device_printf(dev, "Setup init failure\n"); 1978 return; 1979 } 1980 1981 /* Are we a VF device? */ 1982 if ((sc->hw.mac.type == e1000_vfadapt) || 1983 (sc->hw.mac.type == e1000_vfadapt_i350)) 1984 sc->vf_ifp = 1; 1985 else 1986 sc->vf_ifp = 0; 1987 } 1988 1989 static int 1990 em_allocate_pci_resources(if_ctx_t ctx) 1991 { 1992 struct e1000_softc *sc = iflib_get_softc(ctx); 1993 device_t dev = iflib_get_dev(ctx); 1994 int rid, val; 1995 1996 rid = PCIR_BAR(0); 1997 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1998 &rid, RF_ACTIVE); 1999 if (sc->memory == NULL) { 2000 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2001 return (ENXIO); 2002 } 2003 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2004 sc->osdep.mem_bus_space_handle = 2005 rman_get_bushandle(sc->memory); 2006 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2007 2008 /* Only older adapters use IO mapping */ 2009 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2010 /* Figure our where our IO BAR is ? */ 2011 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2012 val = pci_read_config(dev, rid, 4); 2013 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2014 break; 2015 } 2016 rid += 4; 2017 /* check for 64bit BAR */ 2018 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2019 rid += 4; 2020 } 2021 if (rid >= PCIR_CIS) { 2022 device_printf(dev, "Unable to locate IO BAR\n"); 2023 return (ENXIO); 2024 } 2025 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2026 &rid, RF_ACTIVE); 2027 if (sc->ioport == NULL) { 2028 device_printf(dev, "Unable to allocate bus resource: " 2029 "ioport\n"); 2030 return (ENXIO); 2031 } 2032 sc->hw.io_base = 0; 2033 sc->osdep.io_bus_space_tag = 2034 rman_get_bustag(sc->ioport); 2035 sc->osdep.io_bus_space_handle = 2036 rman_get_bushandle(sc->ioport); 2037 } 2038 2039 sc->hw.back = &sc->osdep; 2040 2041 return (0); 2042 } 2043 2044 /********************************************************************* 2045 * 2046 * Set up the MSI-X Interrupt handlers 2047 * 2048 **********************************************************************/ 2049 static int 2050 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2051 { 2052 struct e1000_softc *sc = iflib_get_softc(ctx); 2053 struct em_rx_queue *rx_que = sc->rx_queues; 2054 struct em_tx_queue *tx_que = sc->tx_queues; 2055 int error, rid, i, vector = 0, rx_vectors; 2056 char buf[16]; 2057 2058 /* First set up ring resources */ 2059 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2060 rid = vector + 1; 2061 snprintf(buf, sizeof(buf), "rxq%d", i); 2062 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2063 if (error) { 2064 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 2065 sc->rx_num_queues = i + 1; 2066 goto fail; 2067 } 2068 2069 rx_que->msix = vector; 2070 2071 /* 2072 * Set the bit to enable interrupt 2073 * in E1000_IMS -- bits 20 and 21 2074 * are for RX0 and RX1, note this has 2075 * NOTHING to do with the MSI-X vector 2076 */ 2077 if (sc->hw.mac.type == e1000_82574) { 2078 rx_que->eims = 1 << (20 + i); 2079 sc->ims |= rx_que->eims; 2080 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2081 } else if (sc->hw.mac.type == e1000_82575) 2082 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2083 else 2084 rx_que->eims = 1 << vector; 2085 } 2086 rx_vectors = vector; 2087 2088 vector = 0; 2089 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2090 snprintf(buf, sizeof(buf), "txq%d", i); 2091 tx_que = &sc->tx_queues[i]; 2092 iflib_softirq_alloc_generic(ctx, 2093 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2094 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2095 2096 tx_que->msix = (vector % sc->rx_num_queues); 2097 2098 /* 2099 * Set the bit to enable interrupt 2100 * in E1000_IMS -- bits 22 and 23 2101 * are for TX0 and TX1, note this has 2102 * NOTHING to do with the MSI-X vector 2103 */ 2104 if (sc->hw.mac.type == e1000_82574) { 2105 tx_que->eims = 1 << (22 + i); 2106 sc->ims |= tx_que->eims; 2107 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2108 } else if (sc->hw.mac.type == e1000_82575) { 2109 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2110 } else { 2111 tx_que->eims = 1 << i; 2112 } 2113 } 2114 2115 /* Link interrupt */ 2116 rid = rx_vectors + 1; 2117 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq"); 2118 2119 if (error) { 2120 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 2121 goto fail; 2122 } 2123 sc->linkvec = rx_vectors; 2124 if (sc->hw.mac.type < igb_mac_min) { 2125 sc->ivars |= (8 | rx_vectors) << 16; 2126 sc->ivars |= 0x80000000; 2127 /* Enable the "Other" interrupt type for link status change */ 2128 sc->ims |= E1000_IMS_OTHER; 2129 } 2130 2131 return (0); 2132 fail: 2133 iflib_irq_free(ctx, &sc->irq); 2134 rx_que = sc->rx_queues; 2135 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2136 iflib_irq_free(ctx, &rx_que->que_irq); 2137 return (error); 2138 } 2139 2140 static void 2141 igb_configure_queues(struct e1000_softc *sc) 2142 { 2143 struct e1000_hw *hw = &sc->hw; 2144 struct em_rx_queue *rx_que; 2145 struct em_tx_queue *tx_que; 2146 u32 tmp, ivar = 0, newitr = 0; 2147 2148 /* First turn on RSS capability */ 2149 if (hw->mac.type != e1000_82575) 2150 E1000_WRITE_REG(hw, E1000_GPIE, 2151 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2152 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2153 2154 /* Turn on MSI-X */ 2155 switch (hw->mac.type) { 2156 case e1000_82580: 2157 case e1000_i350: 2158 case e1000_i354: 2159 case e1000_i210: 2160 case e1000_i211: 2161 case e1000_vfadapt: 2162 case e1000_vfadapt_i350: 2163 /* RX entries */ 2164 for (int i = 0; i < sc->rx_num_queues; i++) { 2165 u32 index = i >> 1; 2166 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2167 rx_que = &sc->rx_queues[i]; 2168 if (i & 1) { 2169 ivar &= 0xFF00FFFF; 2170 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2171 } else { 2172 ivar &= 0xFFFFFF00; 2173 ivar |= rx_que->msix | E1000_IVAR_VALID; 2174 } 2175 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2176 } 2177 /* TX entries */ 2178 for (int i = 0; i < sc->tx_num_queues; i++) { 2179 u32 index = i >> 1; 2180 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2181 tx_que = &sc->tx_queues[i]; 2182 if (i & 1) { 2183 ivar &= 0x00FFFFFF; 2184 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2185 } else { 2186 ivar &= 0xFFFF00FF; 2187 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2188 } 2189 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2190 sc->que_mask |= tx_que->eims; 2191 } 2192 2193 /* And for the link interrupt */ 2194 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2195 sc->link_mask = 1 << sc->linkvec; 2196 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2197 break; 2198 case e1000_82576: 2199 /* RX entries */ 2200 for (int i = 0; i < sc->rx_num_queues; i++) { 2201 u32 index = i & 0x7; /* Each IVAR has two entries */ 2202 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2203 rx_que = &sc->rx_queues[i]; 2204 if (i < 8) { 2205 ivar &= 0xFFFFFF00; 2206 ivar |= rx_que->msix | E1000_IVAR_VALID; 2207 } else { 2208 ivar &= 0xFF00FFFF; 2209 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16; 2210 } 2211 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2212 sc->que_mask |= rx_que->eims; 2213 } 2214 /* TX entries */ 2215 for (int i = 0; i < sc->tx_num_queues; i++) { 2216 u32 index = i & 0x7; /* Each IVAR has two entries */ 2217 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2218 tx_que = &sc->tx_queues[i]; 2219 if (i < 8) { 2220 ivar &= 0xFFFF00FF; 2221 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8; 2222 } else { 2223 ivar &= 0x00FFFFFF; 2224 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24; 2225 } 2226 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2227 sc->que_mask |= tx_que->eims; 2228 } 2229 2230 /* And for the link interrupt */ 2231 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2232 sc->link_mask = 1 << sc->linkvec; 2233 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2234 break; 2235 2236 case e1000_82575: 2237 /* enable MSI-X support*/ 2238 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2239 tmp |= E1000_CTRL_EXT_PBA_CLR; 2240 /* Auto-Mask interrupts upon ICR read. */ 2241 tmp |= E1000_CTRL_EXT_EIAME; 2242 tmp |= E1000_CTRL_EXT_IRCA; 2243 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2244 2245 /* Queues */ 2246 for (int i = 0; i < sc->rx_num_queues; i++) { 2247 rx_que = &sc->rx_queues[i]; 2248 tmp = E1000_EICR_RX_QUEUE0 << i; 2249 tmp |= E1000_EICR_TX_QUEUE0 << i; 2250 rx_que->eims = tmp; 2251 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 2252 i, rx_que->eims); 2253 sc->que_mask |= rx_que->eims; 2254 } 2255 2256 /* Link */ 2257 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2258 E1000_EIMS_OTHER); 2259 sc->link_mask |= E1000_EIMS_OTHER; 2260 default: 2261 break; 2262 } 2263 2264 /* Set the starting interrupt rate */ 2265 if (em_max_interrupt_rate > 0) 2266 newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC; 2267 2268 if (hw->mac.type == e1000_82575) 2269 newitr |= newitr << 16; 2270 else 2271 newitr |= E1000_EITR_CNT_IGNR; 2272 2273 for (int i = 0; i < sc->rx_num_queues; i++) { 2274 rx_que = &sc->rx_queues[i]; 2275 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2276 } 2277 2278 return; 2279 } 2280 2281 static void 2282 em_free_pci_resources(if_ctx_t ctx) 2283 { 2284 struct e1000_softc *sc = iflib_get_softc(ctx); 2285 struct em_rx_queue *que = sc->rx_queues; 2286 device_t dev = iflib_get_dev(ctx); 2287 2288 /* Release all MSI-X queue resources */ 2289 if (sc->intr_type == IFLIB_INTR_MSIX) 2290 iflib_irq_free(ctx, &sc->irq); 2291 2292 if (que != NULL) { 2293 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2294 iflib_irq_free(ctx, &que->que_irq); 2295 } 2296 } 2297 2298 if (sc->memory != NULL) { 2299 bus_release_resource(dev, SYS_RES_MEMORY, 2300 rman_get_rid(sc->memory), sc->memory); 2301 sc->memory = NULL; 2302 } 2303 2304 if (sc->flash != NULL) { 2305 bus_release_resource(dev, SYS_RES_MEMORY, 2306 rman_get_rid(sc->flash), sc->flash); 2307 sc->flash = NULL; 2308 } 2309 2310 if (sc->ioport != NULL) { 2311 bus_release_resource(dev, SYS_RES_IOPORT, 2312 rman_get_rid(sc->ioport), sc->ioport); 2313 sc->ioport = NULL; 2314 } 2315 } 2316 2317 /* Set up MSI or MSI-X */ 2318 static int 2319 em_setup_msix(if_ctx_t ctx) 2320 { 2321 struct e1000_softc *sc = iflib_get_softc(ctx); 2322 2323 if (sc->hw.mac.type == e1000_82574) { 2324 em_enable_vectors_82574(ctx); 2325 } 2326 return (0); 2327 } 2328 2329 /********************************************************************* 2330 * 2331 * Workaround for SmartSpeed on 82541 and 82547 controllers 2332 * 2333 **********************************************************************/ 2334 static void 2335 lem_smartspeed(struct e1000_softc *sc) 2336 { 2337 u16 phy_tmp; 2338 2339 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2340 sc->hw.mac.autoneg == 0 || 2341 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2342 return; 2343 2344 if (sc->smartspeed == 0) { 2345 /* If Master/Slave config fault is asserted twice, 2346 * we assume back-to-back */ 2347 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2348 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2349 return; 2350 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2351 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2352 e1000_read_phy_reg(&sc->hw, 2353 PHY_1000T_CTRL, &phy_tmp); 2354 if(phy_tmp & CR_1000T_MS_ENABLE) { 2355 phy_tmp &= ~CR_1000T_MS_ENABLE; 2356 e1000_write_phy_reg(&sc->hw, 2357 PHY_1000T_CTRL, phy_tmp); 2358 sc->smartspeed++; 2359 if(sc->hw.mac.autoneg && 2360 !e1000_copper_link_autoneg(&sc->hw) && 2361 !e1000_read_phy_reg(&sc->hw, 2362 PHY_CONTROL, &phy_tmp)) { 2363 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2364 MII_CR_RESTART_AUTO_NEG); 2365 e1000_write_phy_reg(&sc->hw, 2366 PHY_CONTROL, phy_tmp); 2367 } 2368 } 2369 } 2370 return; 2371 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2372 /* If still no link, perhaps using 2/3 pair cable */ 2373 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2374 phy_tmp |= CR_1000T_MS_ENABLE; 2375 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2376 if(sc->hw.mac.autoneg && 2377 !e1000_copper_link_autoneg(&sc->hw) && 2378 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2379 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2380 MII_CR_RESTART_AUTO_NEG); 2381 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2382 } 2383 } 2384 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2385 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2386 sc->smartspeed = 0; 2387 } 2388 2389 /********************************************************************* 2390 * 2391 * Initialize the DMA Coalescing feature 2392 * 2393 **********************************************************************/ 2394 static void 2395 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2396 { 2397 device_t dev = sc->dev; 2398 struct e1000_hw *hw = &sc->hw; 2399 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2400 u16 hwm; 2401 u16 max_frame_size; 2402 2403 if (hw->mac.type == e1000_i211) 2404 return; 2405 2406 max_frame_size = sc->shared->isc_max_frame_size; 2407 if (hw->mac.type > e1000_82580) { 2408 2409 if (sc->dmac == 0) { /* Disabling it */ 2410 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2411 return; 2412 } else 2413 device_printf(dev, "DMA Coalescing enabled\n"); 2414 2415 /* Set starting threshold */ 2416 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2417 2418 hwm = 64 * pba - max_frame_size / 16; 2419 if (hwm < 64 * (pba - 6)) 2420 hwm = 64 * (pba - 6); 2421 reg = E1000_READ_REG(hw, E1000_FCRTC); 2422 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2423 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2424 & E1000_FCRTC_RTH_COAL_MASK); 2425 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2426 2427 2428 dmac = pba - max_frame_size / 512; 2429 if (dmac < pba - 10) 2430 dmac = pba - 10; 2431 reg = E1000_READ_REG(hw, E1000_DMACR); 2432 reg &= ~E1000_DMACR_DMACTHR_MASK; 2433 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2434 & E1000_DMACR_DMACTHR_MASK); 2435 2436 /* transition to L0x or L1 if available..*/ 2437 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2438 2439 /* Check if status is 2.5Gb backplane connection 2440 * before configuration of watchdog timer, which is 2441 * in msec values in 12.8usec intervals 2442 * watchdog timer= msec values in 32usec intervals 2443 * for non 2.5Gb connection 2444 */ 2445 if (hw->mac.type == e1000_i354) { 2446 int status = E1000_READ_REG(hw, E1000_STATUS); 2447 if ((status & E1000_STATUS_2P5_SKU) && 2448 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2449 reg |= ((sc->dmac * 5) >> 6); 2450 else 2451 reg |= (sc->dmac >> 5); 2452 } else { 2453 reg |= (sc->dmac >> 5); 2454 } 2455 2456 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2457 2458 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2459 2460 /* Set the interval before transition */ 2461 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2462 if (hw->mac.type == e1000_i350) 2463 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2464 /* 2465 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2466 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2467 */ 2468 if (hw->mac.type == e1000_i354) { 2469 int status = E1000_READ_REG(hw, E1000_STATUS); 2470 if ((status & E1000_STATUS_2P5_SKU) && 2471 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2472 reg |= 0xA; 2473 else 2474 reg |= 0x4; 2475 } else { 2476 reg |= 0x4; 2477 } 2478 2479 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2480 2481 /* free space in tx packet buffer to wake from DMA coal */ 2482 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2483 (2 * max_frame_size)) >> 6); 2484 2485 /* make low power state decision controlled by DMA coal */ 2486 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2487 reg &= ~E1000_PCIEMISC_LX_DECISION; 2488 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2489 2490 } else if (hw->mac.type == e1000_82580) { 2491 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2492 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2493 reg & ~E1000_PCIEMISC_LX_DECISION); 2494 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2495 } 2496 } 2497 /********************************************************************* 2498 * The 3 following flush routines are used as a workaround in the 2499 * I219 client parts and only for them. 2500 * 2501 * em_flush_tx_ring - remove all descriptors from the tx_ring 2502 * 2503 * We want to clear all pending descriptors from the TX ring. 2504 * zeroing happens when the HW reads the regs. We assign the ring itself as 2505 * the data of the next descriptor. We don't care about the data we are about 2506 * to reset the HW. 2507 **********************************************************************/ 2508 static void 2509 em_flush_tx_ring(struct e1000_softc *sc) 2510 { 2511 struct e1000_hw *hw = &sc->hw; 2512 struct tx_ring *txr = &sc->tx_queues->txr; 2513 struct e1000_tx_desc *txd; 2514 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2515 u16 size = 512; 2516 2517 tctl = E1000_READ_REG(hw, E1000_TCTL); 2518 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2519 2520 txd = &txr->tx_base[txr->tx_cidx_processed]; 2521 2522 /* Just use the ring as a dummy buffer addr */ 2523 txd->buffer_addr = txr->tx_paddr; 2524 txd->lower.data = htole32(txd_lower | size); 2525 txd->upper.data = 0; 2526 2527 /* flush descriptors to memory before notifying the HW */ 2528 wmb(); 2529 2530 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2531 mb(); 2532 usec_delay(250); 2533 } 2534 2535 /********************************************************************* 2536 * em_flush_rx_ring - remove all descriptors from the rx_ring 2537 * 2538 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2539 **********************************************************************/ 2540 static void 2541 em_flush_rx_ring(struct e1000_softc *sc) 2542 { 2543 struct e1000_hw *hw = &sc->hw; 2544 u32 rctl, rxdctl; 2545 2546 rctl = E1000_READ_REG(hw, E1000_RCTL); 2547 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2548 E1000_WRITE_FLUSH(hw); 2549 usec_delay(150); 2550 2551 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2552 /* zero the lower 14 bits (prefetch and host thresholds) */ 2553 rxdctl &= 0xffffc000; 2554 /* 2555 * update thresholds: prefetch threshold to 31, host threshold to 1 2556 * and make sure the granularity is "descriptors" and not "cache lines" 2557 */ 2558 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2559 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2560 2561 /* momentarily enable the RX ring for the changes to take effect */ 2562 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2563 E1000_WRITE_FLUSH(hw); 2564 usec_delay(150); 2565 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2566 } 2567 2568 /********************************************************************* 2569 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2570 * 2571 * In I219, the descriptor rings must be emptied before resetting the HW 2572 * or before changing the device state to D3 during runtime (runtime PM). 2573 * 2574 * Failure to do this will cause the HW to enter a unit hang state which can 2575 * only be released by PCI reset on the device 2576 * 2577 **********************************************************************/ 2578 static void 2579 em_flush_desc_rings(struct e1000_softc *sc) 2580 { 2581 struct e1000_hw *hw = &sc->hw; 2582 device_t dev = sc->dev; 2583 u16 hang_state; 2584 u32 fext_nvm11, tdlen; 2585 2586 /* First, disable MULR fix in FEXTNVM11 */ 2587 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 2588 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 2589 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 2590 2591 /* do nothing if we're not in faulty state, or if the queue is empty */ 2592 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 2593 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2594 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 2595 return; 2596 em_flush_tx_ring(sc); 2597 2598 /* recheck, maybe the fault is caused by the rx ring */ 2599 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 2600 if (hang_state & FLUSH_DESC_REQUIRED) 2601 em_flush_rx_ring(sc); 2602 } 2603 2604 2605 /********************************************************************* 2606 * 2607 * Initialize the hardware to a configuration as specified by the 2608 * sc structure. 2609 * 2610 **********************************************************************/ 2611 static void 2612 em_reset(if_ctx_t ctx) 2613 { 2614 device_t dev = iflib_get_dev(ctx); 2615 struct e1000_softc *sc = iflib_get_softc(ctx); 2616 if_t ifp = iflib_get_ifp(ctx); 2617 struct e1000_hw *hw = &sc->hw; 2618 u32 rx_buffer_size; 2619 u32 pba; 2620 2621 INIT_DEBUGOUT("em_reset: begin"); 2622 /* Let the firmware know the OS is in control */ 2623 em_get_hw_control(sc); 2624 2625 /* Set up smart power down as default off on newer adapters. */ 2626 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 2627 hw->mac.type == e1000_82572)) { 2628 u16 phy_tmp = 0; 2629 2630 /* Speed up time to link by disabling smart power down. */ 2631 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2632 phy_tmp &= ~IGP02E1000_PM_SPD; 2633 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2634 } 2635 2636 /* 2637 * Packet Buffer Allocation (PBA) 2638 * Writing PBA sets the receive portion of the buffer 2639 * the remainder is used for the transmit buffer. 2640 */ 2641 switch (hw->mac.type) { 2642 /* 82547: Total Packet Buffer is 40K */ 2643 case e1000_82547: 2644 case e1000_82547_rev_2: 2645 if (hw->mac.max_frame_size > 8192) 2646 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 2647 else 2648 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 2649 break; 2650 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 2651 case e1000_82571: 2652 case e1000_82572: 2653 case e1000_80003es2lan: 2654 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 2655 break; 2656 /* 82573: Total Packet Buffer is 32K */ 2657 case e1000_82573: 2658 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 2659 break; 2660 case e1000_82574: 2661 case e1000_82583: 2662 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 2663 break; 2664 case e1000_ich8lan: 2665 pba = E1000_PBA_8K; 2666 break; 2667 case e1000_ich9lan: 2668 case e1000_ich10lan: 2669 /* Boost Receive side for jumbo frames */ 2670 if (hw->mac.max_frame_size > 4096) 2671 pba = E1000_PBA_14K; 2672 else 2673 pba = E1000_PBA_10K; 2674 break; 2675 case e1000_pchlan: 2676 case e1000_pch2lan: 2677 case e1000_pch_lpt: 2678 case e1000_pch_spt: 2679 case e1000_pch_cnp: 2680 case e1000_pch_tgp: 2681 case e1000_pch_adp: 2682 case e1000_pch_mtp: 2683 case e1000_pch_ptp: 2684 pba = E1000_PBA_26K; 2685 break; 2686 case e1000_82575: 2687 pba = E1000_PBA_32K; 2688 break; 2689 case e1000_82576: 2690 case e1000_vfadapt: 2691 pba = E1000_READ_REG(hw, E1000_RXPBS); 2692 pba &= E1000_RXPBS_SIZE_MASK_82576; 2693 break; 2694 case e1000_82580: 2695 case e1000_i350: 2696 case e1000_i354: 2697 case e1000_vfadapt_i350: 2698 pba = E1000_READ_REG(hw, E1000_RXPBS); 2699 pba = e1000_rxpbs_adjust_82580(pba); 2700 break; 2701 case e1000_i210: 2702 case e1000_i211: 2703 pba = E1000_PBA_34K; 2704 break; 2705 default: 2706 /* Remaining devices assumed to have a Packet Buffer of 64K. */ 2707 if (hw->mac.max_frame_size > 8192) 2708 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 2709 else 2710 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 2711 } 2712 2713 /* Special needs in case of Jumbo frames */ 2714 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 2715 u32 tx_space, min_tx, min_rx; 2716 pba = E1000_READ_REG(hw, E1000_PBA); 2717 tx_space = pba >> 16; 2718 pba &= 0xffff; 2719 min_tx = (hw->mac.max_frame_size + 2720 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 2721 min_tx = roundup2(min_tx, 1024); 2722 min_tx >>= 10; 2723 min_rx = hw->mac.max_frame_size; 2724 min_rx = roundup2(min_rx, 1024); 2725 min_rx >>= 10; 2726 if (tx_space < min_tx && 2727 ((min_tx - tx_space) < pba)) { 2728 pba = pba - (min_tx - tx_space); 2729 /* 2730 * if short on rx space, rx wins 2731 * and must trump tx adjustment 2732 */ 2733 if (pba < min_rx) 2734 pba = min_rx; 2735 } 2736 E1000_WRITE_REG(hw, E1000_PBA, pba); 2737 } 2738 2739 if (hw->mac.type < igb_mac_min) 2740 E1000_WRITE_REG(hw, E1000_PBA, pba); 2741 2742 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 2743 2744 /* 2745 * These parameters control the automatic generation (Tx) and 2746 * response (Rx) to Ethernet PAUSE frames. 2747 * - High water mark should allow for at least two frames to be 2748 * received after sending an XOFF. 2749 * - Low water mark works best when it is very near the high water mark. 2750 * This allows the receiver to restart by sending XON when it has 2751 * drained a bit. Here we use an arbitrary value of 1500 which will 2752 * restart after one full frame is pulled from the buffer. There 2753 * could be several smaller frames in the buffer and if so they will 2754 * not trigger the XON until their total number reduces the buffer 2755 * by 1500. 2756 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2757 */ 2758 rx_buffer_size = (pba & 0xffff) << 10; 2759 hw->fc.high_water = rx_buffer_size - 2760 roundup2(hw->mac.max_frame_size, 1024); 2761 hw->fc.low_water = hw->fc.high_water - 1500; 2762 2763 if (sc->fc) /* locally set flow control value? */ 2764 hw->fc.requested_mode = sc->fc; 2765 else 2766 hw->fc.requested_mode = e1000_fc_full; 2767 2768 if (hw->mac.type == e1000_80003es2lan) 2769 hw->fc.pause_time = 0xFFFF; 2770 else 2771 hw->fc.pause_time = EM_FC_PAUSE_TIME; 2772 2773 hw->fc.send_xon = true; 2774 2775 /* Device specific overrides/settings */ 2776 switch (hw->mac.type) { 2777 case e1000_pchlan: 2778 /* Workaround: no TX flow ctrl for PCH */ 2779 hw->fc.requested_mode = e1000_fc_rx_pause; 2780 hw->fc.pause_time = 0xFFFF; /* override */ 2781 if (if_getmtu(ifp) > ETHERMTU) { 2782 hw->fc.high_water = 0x3500; 2783 hw->fc.low_water = 0x1500; 2784 } else { 2785 hw->fc.high_water = 0x5000; 2786 hw->fc.low_water = 0x3000; 2787 } 2788 hw->fc.refresh_time = 0x1000; 2789 break; 2790 case e1000_pch2lan: 2791 case e1000_pch_lpt: 2792 case e1000_pch_spt: 2793 case e1000_pch_cnp: 2794 case e1000_pch_tgp: 2795 case e1000_pch_adp: 2796 case e1000_pch_mtp: 2797 case e1000_pch_ptp: 2798 hw->fc.high_water = 0x5C20; 2799 hw->fc.low_water = 0x5048; 2800 hw->fc.pause_time = 0x0650; 2801 hw->fc.refresh_time = 0x0400; 2802 /* Jumbos need adjusted PBA */ 2803 if (if_getmtu(ifp) > ETHERMTU) 2804 E1000_WRITE_REG(hw, E1000_PBA, 12); 2805 else 2806 E1000_WRITE_REG(hw, E1000_PBA, 26); 2807 break; 2808 case e1000_82575: 2809 case e1000_82576: 2810 /* 8-byte granularity */ 2811 hw->fc.low_water = hw->fc.high_water - 8; 2812 break; 2813 case e1000_82580: 2814 case e1000_i350: 2815 case e1000_i354: 2816 case e1000_i210: 2817 case e1000_i211: 2818 case e1000_vfadapt: 2819 case e1000_vfadapt_i350: 2820 /* 16-byte granularity */ 2821 hw->fc.low_water = hw->fc.high_water - 16; 2822 break; 2823 case e1000_ich9lan: 2824 case e1000_ich10lan: 2825 if (if_getmtu(ifp) > ETHERMTU) { 2826 hw->fc.high_water = 0x2800; 2827 hw->fc.low_water = hw->fc.high_water - 8; 2828 break; 2829 } 2830 /* FALLTHROUGH */ 2831 default: 2832 if (hw->mac.type == e1000_80003es2lan) 2833 hw->fc.pause_time = 0xFFFF; 2834 break; 2835 } 2836 2837 /* I219 needs some special flushing to avoid hangs */ 2838 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2839 em_flush_desc_rings(sc); 2840 2841 /* Issue a global reset */ 2842 e1000_reset_hw(hw); 2843 if (hw->mac.type >= igb_mac_min) { 2844 E1000_WRITE_REG(hw, E1000_WUC, 0); 2845 } else { 2846 E1000_WRITE_REG(hw, E1000_WUFC, 0); 2847 em_disable_aspm(sc); 2848 } 2849 if (sc->flags & IGB_MEDIA_RESET) { 2850 e1000_setup_init_funcs(hw, true); 2851 e1000_get_bus_info(hw); 2852 sc->flags &= ~IGB_MEDIA_RESET; 2853 } 2854 /* and a re-init */ 2855 if (e1000_init_hw(hw) < 0) { 2856 device_printf(dev, "Hardware Initialization Failed\n"); 2857 return; 2858 } 2859 if (hw->mac.type >= igb_mac_min) 2860 igb_init_dmac(sc, pba); 2861 2862 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 2863 e1000_get_phy_info(hw); 2864 e1000_check_for_link(hw); 2865 } 2866 2867 /* 2868 * Initialise the RSS mapping for NICs that support multiple transmit/ 2869 * receive rings. 2870 */ 2871 2872 #define RSSKEYLEN 10 2873 static void 2874 em_initialize_rss_mapping(struct e1000_softc *sc) 2875 { 2876 uint8_t rss_key[4 * RSSKEYLEN]; 2877 uint32_t reta = 0; 2878 struct e1000_hw *hw = &sc->hw; 2879 int i; 2880 2881 /* 2882 * Configure RSS key 2883 */ 2884 arc4rand(rss_key, sizeof(rss_key), 0); 2885 for (i = 0; i < RSSKEYLEN; ++i) { 2886 uint32_t rssrk = 0; 2887 2888 rssrk = EM_RSSRK_VAL(rss_key, i); 2889 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 2890 } 2891 2892 /* 2893 * Configure RSS redirect table in following fashion: 2894 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 2895 */ 2896 for (i = 0; i < sizeof(reta); ++i) { 2897 uint32_t q; 2898 2899 q = (i % sc->rx_num_queues) << 7; 2900 reta |= q << (8 * i); 2901 } 2902 2903 for (i = 0; i < 32; ++i) 2904 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 2905 2906 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 2907 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2908 E1000_MRQC_RSS_FIELD_IPV4 | 2909 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 2910 E1000_MRQC_RSS_FIELD_IPV6_EX | 2911 E1000_MRQC_RSS_FIELD_IPV6); 2912 } 2913 2914 static void 2915 igb_initialize_rss_mapping(struct e1000_softc *sc) 2916 { 2917 struct e1000_hw *hw = &sc->hw; 2918 int i; 2919 int queue_id; 2920 u32 reta; 2921 u32 rss_key[10], mrqc, shift = 0; 2922 2923 /* XXX? */ 2924 if (hw->mac.type == e1000_82575) 2925 shift = 6; 2926 2927 /* 2928 * The redirection table controls which destination 2929 * queue each bucket redirects traffic to. 2930 * Each DWORD represents four queues, with the LSB 2931 * being the first queue in the DWORD. 2932 * 2933 * This just allocates buckets to queues using round-robin 2934 * allocation. 2935 * 2936 * NOTE: It Just Happens to line up with the default 2937 * RSS allocation method. 2938 */ 2939 2940 /* Warning FM follows */ 2941 reta = 0; 2942 for (i = 0; i < 128; i++) { 2943 #ifdef RSS 2944 queue_id = rss_get_indirection_to_bucket(i); 2945 /* 2946 * If we have more queues than buckets, we'll 2947 * end up mapping buckets to a subset of the 2948 * queues. 2949 * 2950 * If we have more buckets than queues, we'll 2951 * end up instead assigning multiple buckets 2952 * to queues. 2953 * 2954 * Both are suboptimal, but we need to handle 2955 * the case so we don't go out of bounds 2956 * indexing arrays and such. 2957 */ 2958 queue_id = queue_id % sc->rx_num_queues; 2959 #else 2960 queue_id = (i % sc->rx_num_queues); 2961 #endif 2962 /* Adjust if required */ 2963 queue_id = queue_id << shift; 2964 2965 /* 2966 * The low 8 bits are for hash value (n+0); 2967 * The next 8 bits are for hash value (n+1), etc. 2968 */ 2969 reta = reta >> 8; 2970 reta = reta | ( ((uint32_t) queue_id) << 24); 2971 if ((i & 3) == 3) { 2972 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 2973 reta = 0; 2974 } 2975 } 2976 2977 /* Now fill in hash table */ 2978 2979 /* 2980 * MRQC: Multiple Receive Queues Command 2981 * Set queuing to RSS control, number depends on the device. 2982 */ 2983 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 2984 2985 #ifdef RSS 2986 /* XXX ew typecasting */ 2987 rss_getkey((uint8_t *) &rss_key); 2988 #else 2989 arc4rand(&rss_key, sizeof(rss_key), 0); 2990 #endif 2991 for (i = 0; i < 10; i++) 2992 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 2993 2994 /* 2995 * Configure the RSS fields to hash upon. 2996 */ 2997 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2998 E1000_MRQC_RSS_FIELD_IPV4_TCP); 2999 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3000 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3001 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3002 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3003 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3004 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3005 3006 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3007 } 3008 3009 /********************************************************************* 3010 * 3011 * Setup networking device structure and register interface media. 3012 * 3013 **********************************************************************/ 3014 static int 3015 em_setup_interface(if_ctx_t ctx) 3016 { 3017 if_t ifp = iflib_get_ifp(ctx); 3018 struct e1000_softc *sc = iflib_get_softc(ctx); 3019 if_softc_ctx_t scctx = sc->shared; 3020 3021 INIT_DEBUGOUT("em_setup_interface: begin"); 3022 3023 /* Single Queue */ 3024 if (sc->tx_num_queues == 1) { 3025 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3026 if_setsendqready(ifp); 3027 } 3028 3029 /* 3030 * Specify the media types supported by this adapter and register 3031 * callbacks to update media and link information 3032 */ 3033 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3034 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3035 u_char fiber_type = IFM_1000_SX; /* default type */ 3036 3037 if (sc->hw.mac.type == e1000_82545) 3038 fiber_type = IFM_1000_LX; 3039 ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3040 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3041 } else { 3042 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3043 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3044 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3045 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3046 if (sc->hw.phy.type != e1000_phy_ife) { 3047 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3048 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 3049 } 3050 } 3051 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3052 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3053 return (0); 3054 } 3055 3056 static int 3057 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 3058 { 3059 struct e1000_softc *sc = iflib_get_softc(ctx); 3060 if_softc_ctx_t scctx = sc->shared; 3061 int error = E1000_SUCCESS; 3062 struct em_tx_queue *que; 3063 int i, j; 3064 3065 MPASS(sc->tx_num_queues > 0); 3066 MPASS(sc->tx_num_queues == ntxqsets); 3067 3068 /* First allocate the top level queue structs */ 3069 if (!(sc->tx_queues = 3070 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3071 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3072 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3073 return(ENOMEM); 3074 } 3075 3076 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3077 /* Set up some basics */ 3078 3079 struct tx_ring *txr = &que->txr; 3080 txr->sc = que->sc = sc; 3081 que->me = txr->me = i; 3082 3083 /* Allocate report status array */ 3084 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 3085 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 3086 error = ENOMEM; 3087 goto fail; 3088 } 3089 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3090 txr->tx_rsq[j] = QIDX_INVALID; 3091 /* get the virtual and physical address of the hardware queues */ 3092 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3093 txr->tx_paddr = paddrs[i*ntxqs]; 3094 } 3095 3096 if (bootverbose) 3097 device_printf(iflib_get_dev(ctx), 3098 "allocated for %d tx_queues\n", sc->tx_num_queues); 3099 return (0); 3100 fail: 3101 em_if_queues_free(ctx); 3102 return (error); 3103 } 3104 3105 static int 3106 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 3107 { 3108 struct e1000_softc *sc = iflib_get_softc(ctx); 3109 int error = E1000_SUCCESS; 3110 struct em_rx_queue *que; 3111 int i; 3112 3113 MPASS(sc->rx_num_queues > 0); 3114 MPASS(sc->rx_num_queues == nrxqsets); 3115 3116 /* First allocate the top level queue structs */ 3117 if (!(sc->rx_queues = 3118 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3119 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3120 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 3121 error = ENOMEM; 3122 goto fail; 3123 } 3124 3125 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3126 /* Set up some basics */ 3127 struct rx_ring *rxr = &que->rxr; 3128 rxr->sc = que->sc = sc; 3129 rxr->que = que; 3130 que->me = rxr->me = i; 3131 3132 /* get the virtual and physical address of the hardware queues */ 3133 rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3134 rxr->rx_paddr = paddrs[i*nrxqs]; 3135 } 3136 3137 if (bootverbose) 3138 device_printf(iflib_get_dev(ctx), 3139 "allocated for %d rx_queues\n", sc->rx_num_queues); 3140 3141 return (0); 3142 fail: 3143 em_if_queues_free(ctx); 3144 return (error); 3145 } 3146 3147 static void 3148 em_if_queues_free(if_ctx_t ctx) 3149 { 3150 struct e1000_softc *sc = iflib_get_softc(ctx); 3151 struct em_tx_queue *tx_que = sc->tx_queues; 3152 struct em_rx_queue *rx_que = sc->rx_queues; 3153 3154 if (tx_que != NULL) { 3155 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3156 struct tx_ring *txr = &tx_que->txr; 3157 if (txr->tx_rsq == NULL) 3158 break; 3159 3160 free(txr->tx_rsq, M_DEVBUF); 3161 txr->tx_rsq = NULL; 3162 } 3163 free(sc->tx_queues, M_DEVBUF); 3164 sc->tx_queues = NULL; 3165 } 3166 3167 if (rx_que != NULL) { 3168 free(sc->rx_queues, M_DEVBUF); 3169 sc->rx_queues = NULL; 3170 } 3171 } 3172 3173 /********************************************************************* 3174 * 3175 * Enable transmit unit. 3176 * 3177 **********************************************************************/ 3178 static void 3179 em_initialize_transmit_unit(if_ctx_t ctx) 3180 { 3181 struct e1000_softc *sc = iflib_get_softc(ctx); 3182 if_softc_ctx_t scctx = sc->shared; 3183 struct em_tx_queue *que; 3184 struct tx_ring *txr; 3185 struct e1000_hw *hw = &sc->hw; 3186 u32 tctl, txdctl = 0, tarc, tipg = 0; 3187 3188 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3189 3190 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3191 u64 bus_addr; 3192 caddr_t offp, endp; 3193 3194 que = &sc->tx_queues[i]; 3195 txr = &que->txr; 3196 bus_addr = txr->tx_paddr; 3197 3198 /* Clear checksum offload context. */ 3199 offp = (caddr_t)&txr->csum_flags; 3200 endp = (caddr_t)(txr + 1); 3201 bzero(offp, endp - offp); 3202 3203 /* Base and Len of TX Ring */ 3204 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3205 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3206 E1000_WRITE_REG(hw, E1000_TDBAH(i), 3207 (u32)(bus_addr >> 32)); 3208 E1000_WRITE_REG(hw, E1000_TDBAL(i), 3209 (u32)bus_addr); 3210 /* Init the HEAD/TAIL indices */ 3211 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3212 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3213 3214 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3215 E1000_READ_REG(hw, E1000_TDBAL(i)), 3216 E1000_READ_REG(hw, E1000_TDLEN(i))); 3217 3218 txdctl = 0; /* clear txdctl */ 3219 txdctl |= 0x1f; /* PTHRESH */ 3220 txdctl |= 1 << 8; /* HTHRESH */ 3221 txdctl |= 1 << 16;/* WTHRESH */ 3222 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3223 txdctl |= E1000_TXDCTL_GRAN; 3224 txdctl |= 1 << 25; /* LWTHRESH */ 3225 3226 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3227 } 3228 3229 /* Set the default values for the Tx Inter Packet Gap timer */ 3230 switch (hw->mac.type) { 3231 case e1000_80003es2lan: 3232 tipg = DEFAULT_82543_TIPG_IPGR1; 3233 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3234 E1000_TIPG_IPGR2_SHIFT; 3235 break; 3236 case e1000_82542: 3237 tipg = DEFAULT_82542_TIPG_IPGT; 3238 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3239 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3240 break; 3241 default: 3242 if (hw->phy.media_type == e1000_media_type_fiber || 3243 hw->phy.media_type == e1000_media_type_internal_serdes) 3244 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3245 else 3246 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3247 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3248 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3249 } 3250 3251 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3252 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3253 3254 if(hw->mac.type >= e1000_82540) 3255 E1000_WRITE_REG(hw, E1000_TADV, 3256 sc->tx_abs_int_delay.value); 3257 3258 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3259 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3260 tarc |= TARC_SPEED_MODE_BIT; 3261 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3262 } else if (hw->mac.type == e1000_80003es2lan) { 3263 /* errata: program both queues to unweighted RR */ 3264 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3265 tarc |= 1; 3266 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3267 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3268 tarc |= 1; 3269 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3270 } else if (hw->mac.type == e1000_82574) { 3271 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3272 tarc |= TARC_ERRATA_BIT; 3273 if ( sc->tx_num_queues > 1) { 3274 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3275 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3276 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3277 } else 3278 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3279 } 3280 3281 if (sc->tx_int_delay.value > 0) 3282 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3283 3284 /* Program the Transmit Control Register */ 3285 tctl = E1000_READ_REG(hw, E1000_TCTL); 3286 tctl &= ~E1000_TCTL_CT; 3287 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3288 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3289 3290 if (hw->mac.type >= e1000_82571) 3291 tctl |= E1000_TCTL_MULR; 3292 3293 /* This write will effectively turn on the transmit unit. */ 3294 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3295 3296 /* SPT and KBL errata workarounds */ 3297 if (hw->mac.type == e1000_pch_spt) { 3298 u32 reg; 3299 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3300 reg |= E1000_RCTL_RDMTS_HEX; 3301 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3302 /* i218-i219 Specification Update 1.5.4.5 */ 3303 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3304 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3305 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3306 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3307 } 3308 } 3309 3310 /********************************************************************* 3311 * 3312 * Enable receive unit. 3313 * 3314 **********************************************************************/ 3315 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3316 3317 static void 3318 em_initialize_receive_unit(if_ctx_t ctx) 3319 { 3320 struct e1000_softc *sc = iflib_get_softc(ctx); 3321 if_softc_ctx_t scctx = sc->shared; 3322 if_t ifp = iflib_get_ifp(ctx); 3323 struct e1000_hw *hw = &sc->hw; 3324 struct em_rx_queue *que; 3325 int i; 3326 uint32_t rctl, rxcsum; 3327 3328 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3329 3330 /* 3331 * Make sure receives are disabled while setting 3332 * up the descriptor ring 3333 */ 3334 rctl = E1000_READ_REG(hw, E1000_RCTL); 3335 /* Do not disable if ever enabled on this hardware */ 3336 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3337 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3338 3339 /* Setup the Receive Control Register */ 3340 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3341 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3342 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3343 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3344 3345 /* Do not store bad packets */ 3346 rctl &= ~E1000_RCTL_SBP; 3347 3348 /* Enable Long Packet receive */ 3349 if (if_getmtu(ifp) > ETHERMTU) 3350 rctl |= E1000_RCTL_LPE; 3351 else 3352 rctl &= ~E1000_RCTL_LPE; 3353 3354 /* Strip the CRC */ 3355 if (!em_disable_crc_stripping) 3356 rctl |= E1000_RCTL_SECRC; 3357 3358 if (hw->mac.type >= e1000_82540) { 3359 E1000_WRITE_REG(hw, E1000_RADV, 3360 sc->rx_abs_int_delay.value); 3361 3362 /* 3363 * Set the interrupt throttling rate. Value is calculated 3364 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3365 */ 3366 E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR); 3367 } 3368 E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value); 3369 3370 if (hw->mac.type >= em_mac_min) { 3371 uint32_t rfctl; 3372 /* Use extended rx descriptor formats */ 3373 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3374 rfctl |= E1000_RFCTL_EXTEN; 3375 3376 /* 3377 * When using MSI-X interrupts we need to throttle 3378 * using the EITR register (82574 only) 3379 */ 3380 if (hw->mac.type == e1000_82574) { 3381 for (int i = 0; i < 4; i++) 3382 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3383 DEFAULT_ITR); 3384 /* Disable accelerated acknowledge */ 3385 rfctl |= E1000_RFCTL_ACK_DIS; 3386 } 3387 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3388 } 3389 3390 /* Set up L3 and L4 csum Rx descriptor offloads */ 3391 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3392 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3393 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3394 if (hw->mac.type > e1000_82575) 3395 rxcsum |= E1000_RXCSUM_CRCOFL; 3396 else if (hw->mac.type < em_mac_min && 3397 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3398 rxcsum |= E1000_RXCSUM_IPV6OFL; 3399 } else { 3400 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3401 if (hw->mac.type > e1000_82575) 3402 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3403 else if (hw->mac.type < em_mac_min) 3404 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3405 } 3406 3407 if (sc->rx_num_queues > 1) { 3408 /* RSS hash needed in the Rx descriptor */ 3409 rxcsum |= E1000_RXCSUM_PCSD; 3410 3411 if (hw->mac.type >= igb_mac_min) 3412 igb_initialize_rss_mapping(sc); 3413 else 3414 em_initialize_rss_mapping(sc); 3415 } 3416 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3417 3418 /* 3419 * XXX TEMPORARY WORKAROUND: on some systems with 82573 3420 * long latencies are observed, like Lenovo X60. This 3421 * change eliminates the problem, but since having positive 3422 * values in RDTR is a known source of problems on other 3423 * platforms another solution is being sought. 3424 */ 3425 if (hw->mac.type == e1000_82573) 3426 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3427 3428 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3429 struct rx_ring *rxr = &que->rxr; 3430 /* Setup the Base and Length of the Rx Descriptor Ring */ 3431 u64 bus_addr = rxr->rx_paddr; 3432 #if 0 3433 u32 rdt = sc->rx_num_queues -1; /* default */ 3434 #endif 3435 3436 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3437 scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended)); 3438 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3439 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3440 /* Setup the Head and Tail Descriptor Pointers */ 3441 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3442 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3443 } 3444 3445 /* 3446 * Set PTHRESH for improved jumbo performance 3447 * According to 10.2.5.11 of Intel 82574 Datasheet, 3448 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3449 * Only write to RXDCTL(1) if there is a need for different 3450 * settings. 3451 */ 3452 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3453 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3454 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3455 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3456 } else if (hw->mac.type == e1000_82574) { 3457 for (int i = 0; i < sc->rx_num_queues; i++) { 3458 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3459 rxdctl |= 0x20; /* PTHRESH */ 3460 rxdctl |= 4 << 8; /* HTHRESH */ 3461 rxdctl |= 4 << 16;/* WTHRESH */ 3462 rxdctl |= 1 << 24; /* Switch to granularity */ 3463 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3464 } 3465 } else if (hw->mac.type >= igb_mac_min) { 3466 u32 psize, srrctl = 0; 3467 3468 if (if_getmtu(ifp) > ETHERMTU) { 3469 psize = scctx->isc_max_frame_size; 3470 /* are we on a vlan? */ 3471 if (if_vlantrunkinuse(ifp)) 3472 psize += VLAN_TAG_SIZE; 3473 3474 if (sc->vf_ifp) 3475 e1000_rlpml_set_vf(hw, psize); 3476 else 3477 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3478 } 3479 3480 /* Set maximum packet buffer len */ 3481 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3482 E1000_SRRCTL_BSIZEPKT_SHIFT; 3483 3484 /* 3485 * If TX flow control is disabled and there's >1 queue defined, 3486 * enable DROP. 3487 * 3488 * This drops frames rather than hanging the RX MAC for all queues. 3489 */ 3490 if ((sc->rx_num_queues > 1) && 3491 (sc->fc == e1000_fc_none || 3492 sc->fc == e1000_fc_rx_pause)) { 3493 srrctl |= E1000_SRRCTL_DROP_EN; 3494 } 3495 /* Setup the Base and Length of the Rx Descriptor Rings */ 3496 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3497 struct rx_ring *rxr = &que->rxr; 3498 u64 bus_addr = rxr->rx_paddr; 3499 u32 rxdctl; 3500 3501 #ifdef notyet 3502 /* Configure for header split? -- ignore for now */ 3503 rxr->hdr_split = igb_header_split; 3504 #else 3505 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3506 #endif 3507 3508 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3509 scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc)); 3510 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3511 (uint32_t)(bus_addr >> 32)); 3512 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3513 (uint32_t)bus_addr); 3514 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3515 /* Enable this Queue */ 3516 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3517 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3518 rxdctl &= 0xFFF00000; 3519 rxdctl |= IGB_RX_PTHRESH; 3520 rxdctl |= IGB_RX_HTHRESH << 8; 3521 rxdctl |= IGB_RX_WTHRESH << 16; 3522 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3523 } 3524 } else if (hw->mac.type >= e1000_pch2lan) { 3525 if (if_getmtu(ifp) > ETHERMTU) 3526 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3527 else 3528 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3529 } 3530 3531 /* Make sure VLAN Filters are off */ 3532 rctl &= ~E1000_RCTL_VFE; 3533 3534 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3535 if (hw->mac.type < igb_mac_min) { 3536 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3537 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3538 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3539 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3540 else if (sc->rx_mbuf_sz > 8192) 3541 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3542 else { 3543 rctl |= E1000_RCTL_SZ_2048; 3544 rctl &= ~E1000_RCTL_BSEX; 3545 } 3546 } else 3547 rctl |= E1000_RCTL_SZ_2048; 3548 3549 /* 3550 * rctl bits 11:10 are as follows 3551 * lem: reserved 3552 * em: DTYPE 3553 * igb: reserved 3554 * and should be 00 on all of the above 3555 */ 3556 rctl &= ~0x00000C00; 3557 3558 /* Write out the settings */ 3559 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3560 3561 return; 3562 } 3563 3564 static void 3565 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 3566 { 3567 struct e1000_softc *sc = iflib_get_softc(ctx); 3568 u32 index, bit; 3569 3570 index = (vtag >> 5) & 0x7F; 3571 bit = vtag & 0x1F; 3572 sc->shadow_vfta[index] |= (1 << bit); 3573 ++sc->num_vlans; 3574 em_if_vlan_filter_write(sc); 3575 } 3576 3577 static void 3578 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 3579 { 3580 struct e1000_softc *sc = iflib_get_softc(ctx); 3581 u32 index, bit; 3582 3583 index = (vtag >> 5) & 0x7F; 3584 bit = vtag & 0x1F; 3585 sc->shadow_vfta[index] &= ~(1 << bit); 3586 --sc->num_vlans; 3587 em_if_vlan_filter_write(sc); 3588 } 3589 3590 static bool 3591 em_if_vlan_filter_capable(if_ctx_t ctx) 3592 { 3593 if_t ifp = iflib_get_ifp(ctx); 3594 3595 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 3596 !em_disable_crc_stripping) 3597 return (true); 3598 3599 return (false); 3600 } 3601 3602 static bool 3603 em_if_vlan_filter_used(if_ctx_t ctx) 3604 { 3605 struct e1000_softc *sc = iflib_get_softc(ctx); 3606 3607 if (!em_if_vlan_filter_capable(ctx)) 3608 return (false); 3609 3610 for (int i = 0; i < EM_VFTA_SIZE; i++) 3611 if (sc->shadow_vfta[i] != 0) 3612 return (true); 3613 3614 return (false); 3615 } 3616 3617 static void 3618 em_if_vlan_filter_enable(struct e1000_softc *sc) 3619 { 3620 struct e1000_hw *hw = &sc->hw; 3621 u32 reg; 3622 3623 reg = E1000_READ_REG(hw, E1000_RCTL); 3624 reg &= ~E1000_RCTL_CFIEN; 3625 reg |= E1000_RCTL_VFE; 3626 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3627 } 3628 3629 static void 3630 em_if_vlan_filter_disable(struct e1000_softc *sc) 3631 { 3632 struct e1000_hw *hw = &sc->hw; 3633 u32 reg; 3634 3635 reg = E1000_READ_REG(hw, E1000_RCTL); 3636 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 3637 E1000_WRITE_REG(hw, E1000_RCTL, reg); 3638 } 3639 3640 static void 3641 em_if_vlan_filter_write(struct e1000_softc *sc) 3642 { 3643 struct e1000_hw *hw = &sc->hw; 3644 3645 if (sc->vf_ifp) 3646 return; 3647 3648 /* Disable interrupts for lem-class devices during the filter change */ 3649 if (hw->mac.type < em_mac_min) 3650 em_if_intr_disable(sc->ctx); 3651 3652 for (int i = 0; i < EM_VFTA_SIZE; i++) 3653 if (sc->shadow_vfta[i] != 0) { 3654 /* XXXKB: incomplete VF support, we return early above */ 3655 if (sc->vf_ifp) 3656 e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true); 3657 else 3658 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 3659 } 3660 3661 /* Re-enable interrupts for lem-class devices */ 3662 if (hw->mac.type < em_mac_min) 3663 em_if_intr_enable(sc->ctx); 3664 } 3665 3666 static void 3667 em_setup_vlan_hw_support(if_ctx_t ctx) 3668 { 3669 struct e1000_softc *sc = iflib_get_softc(ctx); 3670 struct e1000_hw *hw = &sc->hw; 3671 if_t ifp = iflib_get_ifp(ctx); 3672 u32 reg; 3673 3674 /* XXXKB: Return early if we are a VF until VF decap and filter management 3675 * is ready and tested. 3676 */ 3677 if (sc->vf_ifp) 3678 return; 3679 3680 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 3681 !em_disable_crc_stripping) { 3682 reg = E1000_READ_REG(hw, E1000_CTRL); 3683 reg |= E1000_CTRL_VME; 3684 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3685 } else { 3686 reg = E1000_READ_REG(hw, E1000_CTRL); 3687 reg &= ~E1000_CTRL_VME; 3688 E1000_WRITE_REG(hw, E1000_CTRL, reg); 3689 } 3690 3691 /* If we aren't doing HW filtering, we're done */ 3692 if (!em_if_vlan_filter_capable(ctx)) { 3693 em_if_vlan_filter_disable(sc); 3694 return; 3695 } 3696 3697 /* 3698 * A soft reset zero's out the VFTA, so 3699 * we need to repopulate it now. 3700 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 3701 * traffic through. This will write the entire table. 3702 */ 3703 em_if_vlan_register(ctx, 0); 3704 3705 /* Enable the Filter Table */ 3706 em_if_vlan_filter_enable(sc); 3707 } 3708 3709 static void 3710 em_if_intr_enable(if_ctx_t ctx) 3711 { 3712 struct e1000_softc *sc = iflib_get_softc(ctx); 3713 struct e1000_hw *hw = &sc->hw; 3714 u32 ims_mask = IMS_ENABLE_MASK; 3715 3716 if (sc->intr_type == IFLIB_INTR_MSIX) { 3717 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 3718 ims_mask |= sc->ims; 3719 } 3720 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 3721 E1000_WRITE_FLUSH(hw); 3722 } 3723 3724 static void 3725 em_if_intr_disable(if_ctx_t ctx) 3726 { 3727 struct e1000_softc *sc = iflib_get_softc(ctx); 3728 struct e1000_hw *hw = &sc->hw; 3729 3730 if (sc->intr_type == IFLIB_INTR_MSIX) 3731 E1000_WRITE_REG(hw, EM_EIAC, 0); 3732 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3733 E1000_WRITE_FLUSH(hw); 3734 } 3735 3736 static void 3737 igb_if_intr_enable(if_ctx_t ctx) 3738 { 3739 struct e1000_softc *sc = iflib_get_softc(ctx); 3740 struct e1000_hw *hw = &sc->hw; 3741 u32 mask; 3742 3743 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3744 mask = (sc->que_mask | sc->link_mask); 3745 E1000_WRITE_REG(hw, E1000_EIAC, mask); 3746 E1000_WRITE_REG(hw, E1000_EIAM, mask); 3747 E1000_WRITE_REG(hw, E1000_EIMS, mask); 3748 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3749 } else 3750 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3751 E1000_WRITE_FLUSH(hw); 3752 } 3753 3754 static void 3755 igb_if_intr_disable(if_ctx_t ctx) 3756 { 3757 struct e1000_softc *sc = iflib_get_softc(ctx); 3758 struct e1000_hw *hw = &sc->hw; 3759 3760 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 3761 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 3762 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3763 } 3764 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 3765 E1000_WRITE_FLUSH(hw); 3766 } 3767 3768 /* 3769 * Bit of a misnomer, what this really means is 3770 * to enable OS management of the system... aka 3771 * to disable special hardware management features 3772 */ 3773 static void 3774 em_init_manageability(struct e1000_softc *sc) 3775 { 3776 /* A shared code workaround */ 3777 #define E1000_82542_MANC2H E1000_MANC2H 3778 if (sc->has_manage) { 3779 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 3780 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3781 3782 /* disable hardware interception of ARP */ 3783 manc &= ~(E1000_MANC_ARP_EN); 3784 3785 /* enable receiving management packets to the host */ 3786 manc |= E1000_MANC_EN_MNG2HOST; 3787 #define E1000_MNG2HOST_PORT_623 (1 << 5) 3788 #define E1000_MNG2HOST_PORT_664 (1 << 6) 3789 manc2h |= E1000_MNG2HOST_PORT_623; 3790 manc2h |= E1000_MNG2HOST_PORT_664; 3791 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 3792 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3793 } 3794 } 3795 3796 /* 3797 * Give control back to hardware management 3798 * controller if there is one. 3799 */ 3800 static void 3801 em_release_manageability(struct e1000_softc *sc) 3802 { 3803 if (sc->has_manage) { 3804 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 3805 3806 /* re-enable hardware interception of ARP */ 3807 manc |= E1000_MANC_ARP_EN; 3808 manc &= ~E1000_MANC_EN_MNG2HOST; 3809 3810 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 3811 } 3812 } 3813 3814 /* 3815 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 3816 * For ASF and Pass Through versions of f/w this means 3817 * that the driver is loaded. For AMT version type f/w 3818 * this means that the network i/f is open. 3819 */ 3820 static void 3821 em_get_hw_control(struct e1000_softc *sc) 3822 { 3823 u32 ctrl_ext, swsm; 3824 3825 if (sc->vf_ifp) 3826 return; 3827 3828 if (sc->hw.mac.type == e1000_82573) { 3829 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3830 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3831 swsm | E1000_SWSM_DRV_LOAD); 3832 return; 3833 } 3834 /* else */ 3835 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3836 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3837 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 3838 } 3839 3840 /* 3841 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 3842 * For ASF and Pass Through versions of f/w this means that 3843 * the driver is no longer loaded. For AMT versions of the 3844 * f/w this means that the network i/f is closed. 3845 */ 3846 static void 3847 em_release_hw_control(struct e1000_softc *sc) 3848 { 3849 u32 ctrl_ext, swsm; 3850 3851 if (!sc->has_manage) 3852 return; 3853 3854 if (sc->hw.mac.type == e1000_82573) { 3855 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 3856 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 3857 swsm & ~E1000_SWSM_DRV_LOAD); 3858 return; 3859 } 3860 /* else */ 3861 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 3862 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 3863 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 3864 return; 3865 } 3866 3867 static int 3868 em_is_valid_ether_addr(u8 *addr) 3869 { 3870 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3871 3872 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3873 return (false); 3874 } 3875 3876 return (true); 3877 } 3878 3879 /* 3880 ** Parse the interface capabilities with regard 3881 ** to both system management and wake-on-lan for 3882 ** later use. 3883 */ 3884 static void 3885 em_get_wakeup(if_ctx_t ctx) 3886 { 3887 struct e1000_softc *sc = iflib_get_softc(ctx); 3888 device_t dev = iflib_get_dev(ctx); 3889 u16 eeprom_data = 0, device_id, apme_mask; 3890 3891 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 3892 apme_mask = EM_EEPROM_APME; 3893 3894 switch (sc->hw.mac.type) { 3895 case e1000_82542: 3896 case e1000_82543: 3897 break; 3898 case e1000_82544: 3899 e1000_read_nvm(&sc->hw, 3900 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 3901 apme_mask = EM_82544_APME; 3902 break; 3903 case e1000_82546: 3904 case e1000_82546_rev_3: 3905 if (sc->hw.bus.func == 1) { 3906 e1000_read_nvm(&sc->hw, 3907 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3908 break; 3909 } else 3910 e1000_read_nvm(&sc->hw, 3911 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3912 break; 3913 case e1000_82573: 3914 case e1000_82583: 3915 sc->has_amt = true; 3916 /* FALLTHROUGH */ 3917 case e1000_82571: 3918 case e1000_82572: 3919 case e1000_80003es2lan: 3920 if (sc->hw.bus.func == 1) { 3921 e1000_read_nvm(&sc->hw, 3922 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 3923 break; 3924 } else 3925 e1000_read_nvm(&sc->hw, 3926 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3927 break; 3928 case e1000_ich8lan: 3929 case e1000_ich9lan: 3930 case e1000_ich10lan: 3931 case e1000_pchlan: 3932 case e1000_pch2lan: 3933 case e1000_pch_lpt: 3934 case e1000_pch_spt: 3935 case e1000_82575: /* listing all igb devices */ 3936 case e1000_82576: 3937 case e1000_82580: 3938 case e1000_i350: 3939 case e1000_i354: 3940 case e1000_i210: 3941 case e1000_i211: 3942 case e1000_vfadapt: 3943 case e1000_vfadapt_i350: 3944 apme_mask = E1000_WUC_APME; 3945 sc->has_amt = true; 3946 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 3947 break; 3948 default: 3949 e1000_read_nvm(&sc->hw, 3950 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 3951 break; 3952 } 3953 if (eeprom_data & apme_mask) 3954 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 3955 /* 3956 * We have the eeprom settings, now apply the special cases 3957 * where the eeprom may be wrong or the board won't support 3958 * wake on lan on a particular port 3959 */ 3960 device_id = pci_get_device(dev); 3961 switch (device_id) { 3962 case E1000_DEV_ID_82546GB_PCIE: 3963 sc->wol = 0; 3964 break; 3965 case E1000_DEV_ID_82546EB_FIBER: 3966 case E1000_DEV_ID_82546GB_FIBER: 3967 /* Wake events only supported on port A for dual fiber 3968 * regardless of eeprom setting */ 3969 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3970 E1000_STATUS_FUNC_1) 3971 sc->wol = 0; 3972 break; 3973 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 3974 /* if quad port adapter, disable WoL on all but port A */ 3975 if (global_quad_port_a != 0) 3976 sc->wol = 0; 3977 /* Reset for multiple quad port adapters */ 3978 if (++global_quad_port_a == 4) 3979 global_quad_port_a = 0; 3980 break; 3981 case E1000_DEV_ID_82571EB_FIBER: 3982 /* Wake events only supported on port A for dual fiber 3983 * regardless of eeprom setting */ 3984 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 3985 E1000_STATUS_FUNC_1) 3986 sc->wol = 0; 3987 break; 3988 case E1000_DEV_ID_82571EB_QUAD_COPPER: 3989 case E1000_DEV_ID_82571EB_QUAD_FIBER: 3990 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 3991 /* if quad port adapter, disable WoL on all but port A */ 3992 if (global_quad_port_a != 0) 3993 sc->wol = 0; 3994 /* Reset for multiple quad port adapters */ 3995 if (++global_quad_port_a == 4) 3996 global_quad_port_a = 0; 3997 break; 3998 } 3999 return; 4000 } 4001 4002 4003 /* 4004 * Enable PCI Wake On Lan capability 4005 */ 4006 static void 4007 em_enable_wakeup(if_ctx_t ctx) 4008 { 4009 struct e1000_softc *sc = iflib_get_softc(ctx); 4010 device_t dev = iflib_get_dev(ctx); 4011 if_t ifp = iflib_get_ifp(ctx); 4012 int error = 0; 4013 u32 pmc, ctrl, ctrl_ext, rctl; 4014 u16 status; 4015 4016 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 4017 return; 4018 4019 /* 4020 * Determine type of Wakeup: note that wol 4021 * is set with all bits on by default. 4022 */ 4023 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4024 sc->wol &= ~E1000_WUFC_MAG; 4025 4026 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4027 sc->wol &= ~E1000_WUFC_EX; 4028 4029 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4030 sc->wol &= ~E1000_WUFC_MC; 4031 else { 4032 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4033 rctl |= E1000_RCTL_MPE; 4034 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4035 } 4036 4037 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4038 goto pme; 4039 4040 /* Advertise the wakeup capability */ 4041 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4042 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4043 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4044 4045 /* Keep the laser running on Fiber adapters */ 4046 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4047 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4048 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4049 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4050 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4051 } 4052 4053 if ((sc->hw.mac.type == e1000_ich8lan) || 4054 (sc->hw.mac.type == e1000_pchlan) || 4055 (sc->hw.mac.type == e1000_ich9lan) || 4056 (sc->hw.mac.type == e1000_ich10lan)) 4057 e1000_suspend_workarounds_ich8lan(&sc->hw); 4058 4059 if ( sc->hw.mac.type >= e1000_pchlan) { 4060 error = em_enable_phy_wakeup(sc); 4061 if (error) 4062 goto pme; 4063 } else { 4064 /* Enable wakeup by the MAC */ 4065 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4066 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4067 } 4068 4069 if (sc->hw.phy.type == e1000_phy_igp_3) 4070 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4071 4072 pme: 4073 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 4074 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 4075 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4076 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4077 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 4078 4079 return; 4080 } 4081 4082 /* 4083 * WOL in the newer chipset interfaces (pchlan) 4084 * require thing to be copied into the phy 4085 */ 4086 static int 4087 em_enable_phy_wakeup(struct e1000_softc *sc) 4088 { 4089 struct e1000_hw *hw = &sc->hw; 4090 u32 mreg, ret = 0; 4091 u16 preg; 4092 4093 /* copy MAC RARs to PHY RARs */ 4094 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4095 4096 /* copy MAC MTA to PHY MTA */ 4097 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4098 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4099 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4100 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4101 (u16)((mreg >> 16) & 0xFFFF)); 4102 } 4103 4104 /* configure PHY Rx Control register */ 4105 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4106 mreg = E1000_READ_REG(hw, E1000_RCTL); 4107 if (mreg & E1000_RCTL_UPE) 4108 preg |= BM_RCTL_UPE; 4109 if (mreg & E1000_RCTL_MPE) 4110 preg |= BM_RCTL_MPE; 4111 preg &= ~(BM_RCTL_MO_MASK); 4112 if (mreg & E1000_RCTL_MO_3) 4113 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4114 << BM_RCTL_MO_SHIFT); 4115 if (mreg & E1000_RCTL_BAM) 4116 preg |= BM_RCTL_BAM; 4117 if (mreg & E1000_RCTL_PMCF) 4118 preg |= BM_RCTL_PMCF; 4119 mreg = E1000_READ_REG(hw, E1000_CTRL); 4120 if (mreg & E1000_CTRL_RFCE) 4121 preg |= BM_RCTL_RFCE; 4122 e1000_write_phy_reg(hw, BM_RCTL, preg); 4123 4124 /* enable PHY wakeup in MAC register */ 4125 E1000_WRITE_REG(hw, E1000_WUC, 4126 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4127 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4128 4129 /* configure and enable PHY wakeup in PHY registers */ 4130 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4131 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4132 4133 /* activate PHY wakeup */ 4134 ret = hw->phy.ops.acquire(hw); 4135 if (ret) { 4136 printf("Could not acquire PHY\n"); 4137 return ret; 4138 } 4139 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4140 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4141 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4142 if (ret) { 4143 printf("Could not read PHY page 769\n"); 4144 goto out; 4145 } 4146 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4147 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4148 if (ret) 4149 printf("Could not set PHY Host Wakeup bit\n"); 4150 out: 4151 hw->phy.ops.release(hw); 4152 4153 return ret; 4154 } 4155 4156 static void 4157 em_if_led_func(if_ctx_t ctx, int onoff) 4158 { 4159 struct e1000_softc *sc = iflib_get_softc(ctx); 4160 4161 if (onoff) { 4162 e1000_setup_led(&sc->hw); 4163 e1000_led_on(&sc->hw); 4164 } else { 4165 e1000_led_off(&sc->hw); 4166 e1000_cleanup_led(&sc->hw); 4167 } 4168 } 4169 4170 /* 4171 * Disable the L0S and L1 LINK states 4172 */ 4173 static void 4174 em_disable_aspm(struct e1000_softc *sc) 4175 { 4176 int base, reg; 4177 u16 link_cap,link_ctrl; 4178 device_t dev = sc->dev; 4179 4180 switch (sc->hw.mac.type) { 4181 case e1000_82573: 4182 case e1000_82574: 4183 case e1000_82583: 4184 break; 4185 default: 4186 return; 4187 } 4188 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4189 return; 4190 reg = base + PCIER_LINK_CAP; 4191 link_cap = pci_read_config(dev, reg, 2); 4192 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4193 return; 4194 reg = base + PCIER_LINK_CTL; 4195 link_ctrl = pci_read_config(dev, reg, 2); 4196 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4197 pci_write_config(dev, reg, link_ctrl, 2); 4198 return; 4199 } 4200 4201 /********************************************************************** 4202 * 4203 * Update the board statistics counters. 4204 * 4205 **********************************************************************/ 4206 static void 4207 em_update_stats_counters(struct e1000_softc *sc) 4208 { 4209 u64 prev_xoffrxc = sc->stats.xoffrxc; 4210 4211 if(sc->hw.phy.media_type == e1000_media_type_copper || 4212 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4213 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4214 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4215 } 4216 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4217 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4218 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4219 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4220 4221 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4222 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4223 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4224 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC); 4225 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4226 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4227 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4228 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4229 /* 4230 ** For watchdog management we need to know if we have been 4231 ** paused during the last interval, so capture that here. 4232 */ 4233 if (sc->stats.xoffrxc != prev_xoffrxc) 4234 sc->shared->isc_pause_frames = 1; 4235 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4236 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4237 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4238 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4239 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4240 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4241 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4242 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4243 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4244 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4245 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4246 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4247 4248 /* For the 64-bit byte counters the low dword must be read first. */ 4249 /* Both registers clear on the read of the high dword */ 4250 4251 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4252 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4253 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4254 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4255 4256 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4257 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4258 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4259 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4260 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4261 4262 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4263 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4264 4265 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4266 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4267 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4268 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4269 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4270 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4271 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4272 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4273 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4274 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4275 4276 /* Interrupt Counts */ 4277 4278 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4279 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4280 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4281 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4282 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4283 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4284 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4285 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4286 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4287 4288 if (sc->hw.mac.type >= e1000_82543) { 4289 sc->stats.algnerrc += 4290 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4291 sc->stats.rxerrc += 4292 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4293 sc->stats.tncrs += 4294 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4295 sc->stats.cexterr += 4296 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4297 sc->stats.tsctc += 4298 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4299 sc->stats.tsctfc += 4300 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4301 } 4302 } 4303 4304 static uint64_t 4305 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4306 { 4307 struct e1000_softc *sc = iflib_get_softc(ctx); 4308 if_t ifp = iflib_get_ifp(ctx); 4309 4310 switch (cnt) { 4311 case IFCOUNTER_COLLISIONS: 4312 return (sc->stats.colc); 4313 case IFCOUNTER_IERRORS: 4314 return (sc->dropped_pkts + sc->stats.rxerrc + 4315 sc->stats.crcerrs + sc->stats.algnerrc + 4316 sc->stats.ruc + sc->stats.roc + 4317 sc->stats.mpc + sc->stats.cexterr); 4318 case IFCOUNTER_OERRORS: 4319 return (sc->stats.ecol + sc->stats.latecol + 4320 sc->watchdog_events); 4321 default: 4322 return (if_get_counter_default(ifp, cnt)); 4323 } 4324 } 4325 4326 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4327 * @ctx: iflib context 4328 * @event: event code to check 4329 * 4330 * Defaults to returning true for unknown events. 4331 * 4332 * @returns true if iflib needs to reinit the interface 4333 */ 4334 static bool 4335 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4336 { 4337 switch (event) { 4338 case IFLIB_RESTART_VLAN_CONFIG: 4339 return (false); 4340 default: 4341 return (true); 4342 } 4343 } 4344 4345 /* Export a single 32-bit register via a read-only sysctl. */ 4346 static int 4347 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4348 { 4349 struct e1000_softc *sc; 4350 u_int val; 4351 4352 sc = oidp->oid_arg1; 4353 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4354 return (sysctl_handle_int(oidp, &val, 0, req)); 4355 } 4356 4357 /* 4358 * Add sysctl variables, one per statistic, to the system. 4359 */ 4360 static void 4361 em_add_hw_stats(struct e1000_softc *sc) 4362 { 4363 device_t dev = iflib_get_dev(sc->ctx); 4364 struct em_tx_queue *tx_que = sc->tx_queues; 4365 struct em_rx_queue *rx_que = sc->rx_queues; 4366 4367 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4368 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4369 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4370 struct e1000_hw_stats *stats = &sc->stats; 4371 4372 struct sysctl_oid *stat_node, *queue_node, *int_node; 4373 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4374 4375 #define QUEUE_NAME_LEN 32 4376 char namebuf[QUEUE_NAME_LEN]; 4377 4378 /* Driver Statistics */ 4379 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4380 CTLFLAG_RD, &sc->dropped_pkts, 4381 "Driver dropped packets"); 4382 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4383 CTLFLAG_RD, &sc->link_irq, 4384 "Link MSI-X IRQ Handled"); 4385 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4386 CTLFLAG_RD, &sc->rx_overruns, 4387 "RX overruns"); 4388 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4389 CTLFLAG_RD, &sc->watchdog_events, 4390 "Watchdog timeouts"); 4391 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4392 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4393 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4394 "Device Control Register"); 4395 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4396 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 4397 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4398 "Receiver Control Register"); 4399 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4400 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 4401 "Flow Control High Watermark"); 4402 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 4403 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 4404 "Flow Control Low Watermark"); 4405 4406 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 4407 struct tx_ring *txr = &tx_que->txr; 4408 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 4409 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4410 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 4411 queue_list = SYSCTL_CHILDREN(queue_node); 4412 4413 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 4414 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4415 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 4416 "Transmit Descriptor Head"); 4417 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 4418 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4419 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 4420 "Transmit Descriptor Tail"); 4421 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 4422 CTLFLAG_RD, &txr->tx_irq, 4423 "Queue MSI-X Transmit Interrupts"); 4424 } 4425 4426 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 4427 struct rx_ring *rxr = &rx_que->rxr; 4428 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 4429 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 4430 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 4431 queue_list = SYSCTL_CHILDREN(queue_node); 4432 4433 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 4434 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4435 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 4436 "Receive Descriptor Head"); 4437 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 4438 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 4439 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 4440 "Receive Descriptor Tail"); 4441 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 4442 CTLFLAG_RD, &rxr->rx_irq, 4443 "Queue MSI-X Receive Interrupts"); 4444 } 4445 4446 /* MAC stats get their own sub node */ 4447 4448 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 4449 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 4450 stat_list = SYSCTL_CHILDREN(stat_node); 4451 4452 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 4453 CTLFLAG_RD, &stats->ecol, 4454 "Excessive collisions"); 4455 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 4456 CTLFLAG_RD, &stats->scc, 4457 "Single collisions"); 4458 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 4459 CTLFLAG_RD, &stats->mcc, 4460 "Multiple collisions"); 4461 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 4462 CTLFLAG_RD, &stats->latecol, 4463 "Late collisions"); 4464 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 4465 CTLFLAG_RD, &stats->colc, 4466 "Collision Count"); 4467 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 4468 CTLFLAG_RD, &sc->stats.symerrs, 4469 "Symbol Errors"); 4470 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 4471 CTLFLAG_RD, &sc->stats.sec, 4472 "Sequence Errors"); 4473 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 4474 CTLFLAG_RD, &sc->stats.dc, 4475 "Defer Count"); 4476 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 4477 CTLFLAG_RD, &sc->stats.mpc, 4478 "Missed Packets"); 4479 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 4480 CTLFLAG_RD, &sc->stats.rnbc, 4481 "Receive No Buffers"); 4482 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 4483 CTLFLAG_RD, &sc->stats.ruc, 4484 "Receive Undersize"); 4485 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 4486 CTLFLAG_RD, &sc->stats.rfc, 4487 "Fragmented Packets Received "); 4488 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 4489 CTLFLAG_RD, &sc->stats.roc, 4490 "Oversized Packets Received"); 4491 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 4492 CTLFLAG_RD, &sc->stats.rjc, 4493 "Recevied Jabber"); 4494 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 4495 CTLFLAG_RD, &sc->stats.rxerrc, 4496 "Receive Errors"); 4497 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 4498 CTLFLAG_RD, &sc->stats.crcerrs, 4499 "CRC errors"); 4500 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 4501 CTLFLAG_RD, &sc->stats.algnerrc, 4502 "Alignment Errors"); 4503 /* On 82575 these are collision counts */ 4504 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 4505 CTLFLAG_RD, &sc->stats.cexterr, 4506 "Collision/Carrier extension errors"); 4507 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 4508 CTLFLAG_RD, &sc->stats.xonrxc, 4509 "XON Received"); 4510 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 4511 CTLFLAG_RD, &sc->stats.xontxc, 4512 "XON Transmitted"); 4513 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 4514 CTLFLAG_RD, &sc->stats.xoffrxc, 4515 "XOFF Received"); 4516 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 4517 CTLFLAG_RD, &sc->stats.xofftxc, 4518 "XOFF Transmitted"); 4519 4520 /* Packet Reception Stats */ 4521 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 4522 CTLFLAG_RD, &sc->stats.tpr, 4523 "Total Packets Received "); 4524 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 4525 CTLFLAG_RD, &sc->stats.gprc, 4526 "Good Packets Received"); 4527 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 4528 CTLFLAG_RD, &sc->stats.bprc, 4529 "Broadcast Packets Received"); 4530 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 4531 CTLFLAG_RD, &sc->stats.mprc, 4532 "Multicast Packets Received"); 4533 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 4534 CTLFLAG_RD, &sc->stats.prc64, 4535 "64 byte frames received "); 4536 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 4537 CTLFLAG_RD, &sc->stats.prc127, 4538 "65-127 byte frames received"); 4539 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 4540 CTLFLAG_RD, &sc->stats.prc255, 4541 "128-255 byte frames received"); 4542 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 4543 CTLFLAG_RD, &sc->stats.prc511, 4544 "256-511 byte frames received"); 4545 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 4546 CTLFLAG_RD, &sc->stats.prc1023, 4547 "512-1023 byte frames received"); 4548 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 4549 CTLFLAG_RD, &sc->stats.prc1522, 4550 "1023-1522 byte frames received"); 4551 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 4552 CTLFLAG_RD, &sc->stats.gorc, 4553 "Good Octets Received"); 4554 4555 /* Packet Transmission Stats */ 4556 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 4557 CTLFLAG_RD, &sc->stats.gotc, 4558 "Good Octets Transmitted"); 4559 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 4560 CTLFLAG_RD, &sc->stats.tpt, 4561 "Total Packets Transmitted"); 4562 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 4563 CTLFLAG_RD, &sc->stats.gptc, 4564 "Good Packets Transmitted"); 4565 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 4566 CTLFLAG_RD, &sc->stats.bptc, 4567 "Broadcast Packets Transmitted"); 4568 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 4569 CTLFLAG_RD, &sc->stats.mptc, 4570 "Multicast Packets Transmitted"); 4571 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 4572 CTLFLAG_RD, &sc->stats.ptc64, 4573 "64 byte frames transmitted "); 4574 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 4575 CTLFLAG_RD, &sc->stats.ptc127, 4576 "65-127 byte frames transmitted"); 4577 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 4578 CTLFLAG_RD, &sc->stats.ptc255, 4579 "128-255 byte frames transmitted"); 4580 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 4581 CTLFLAG_RD, &sc->stats.ptc511, 4582 "256-511 byte frames transmitted"); 4583 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 4584 CTLFLAG_RD, &sc->stats.ptc1023, 4585 "512-1023 byte frames transmitted"); 4586 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 4587 CTLFLAG_RD, &sc->stats.ptc1522, 4588 "1024-1522 byte frames transmitted"); 4589 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 4590 CTLFLAG_RD, &sc->stats.tsctc, 4591 "TSO Contexts Transmitted"); 4592 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 4593 CTLFLAG_RD, &sc->stats.tsctfc, 4594 "TSO Contexts Failed"); 4595 4596 4597 /* Interrupt Stats */ 4598 4599 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 4600 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 4601 int_list = SYSCTL_CHILDREN(int_node); 4602 4603 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 4604 CTLFLAG_RD, &sc->stats.iac, 4605 "Interrupt Assertion Count"); 4606 4607 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 4608 CTLFLAG_RD, &sc->stats.icrxptc, 4609 "Interrupt Cause Rx Pkt Timer Expire Count"); 4610 4611 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 4612 CTLFLAG_RD, &sc->stats.icrxatc, 4613 "Interrupt Cause Rx Abs Timer Expire Count"); 4614 4615 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 4616 CTLFLAG_RD, &sc->stats.ictxptc, 4617 "Interrupt Cause Tx Pkt Timer Expire Count"); 4618 4619 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 4620 CTLFLAG_RD, &sc->stats.ictxatc, 4621 "Interrupt Cause Tx Abs Timer Expire Count"); 4622 4623 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 4624 CTLFLAG_RD, &sc->stats.ictxqec, 4625 "Interrupt Cause Tx Queue Empty Count"); 4626 4627 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 4628 CTLFLAG_RD, &sc->stats.ictxqmtc, 4629 "Interrupt Cause Tx Queue Min Thresh Count"); 4630 4631 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 4632 CTLFLAG_RD, &sc->stats.icrxdmtc, 4633 "Interrupt Cause Rx Desc Min Thresh Count"); 4634 4635 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 4636 CTLFLAG_RD, &sc->stats.icrxoc, 4637 "Interrupt Cause Receiver Overrun Count"); 4638 } 4639 4640 static void 4641 em_fw_version_locked(if_ctx_t ctx) 4642 { 4643 struct e1000_softc *sc = iflib_get_softc(ctx); 4644 struct e1000_hw *hw = &sc->hw; 4645 struct e1000_fw_version *fw_ver = &sc->fw_ver; 4646 uint16_t eep = 0; 4647 4648 /* 4649 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the 4650 * NVM locking model, so we do it in em_if_attach_pre() and store the 4651 * info in the softc 4652 */ 4653 ASSERT_CTX_LOCK_HELD(hw); 4654 4655 *fw_ver = (struct e1000_fw_version){0}; 4656 4657 if (hw->mac.type >= igb_mac_min) { 4658 /* 4659 * Use the Shared Code for igb(4) 4660 */ 4661 e1000_get_fw_version(hw, fw_ver); 4662 } else { 4663 /* 4664 * Otherwise, EEPROM version should be present on (almost?) all 4665 * devices here 4666 */ 4667 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 4668 INIT_DEBUGOUT("can't get EEPROM version"); 4669 return; 4670 } 4671 4672 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 4673 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 4674 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 4675 } 4676 } 4677 4678 static void 4679 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 4680 { 4681 const char *space = ""; 4682 4683 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 4684 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 4685 fw_ver->eep_minor, fw_ver->eep_build); 4686 space = " "; 4687 } 4688 4689 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 4690 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 4691 space, fw_ver->invm_major, fw_ver->invm_minor, 4692 fw_ver->invm_img_type); 4693 space = " "; 4694 } 4695 4696 if (fw_ver->or_valid) { 4697 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 4698 space, fw_ver->or_major, fw_ver->or_build, 4699 fw_ver->or_patch); 4700 space = " "; 4701 } 4702 4703 if (fw_ver->etrack_id) 4704 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 4705 } 4706 4707 static void 4708 em_print_fw_version(struct e1000_softc *sc ) 4709 { 4710 device_t dev = sc->dev; 4711 struct sbuf *buf; 4712 int error = 0; 4713 4714 buf = sbuf_new_auto(); 4715 if (!buf) { 4716 device_printf(dev, "Could not allocate sbuf for output.\n"); 4717 return; 4718 } 4719 4720 em_sbuf_fw_version(&sc->fw_ver, buf); 4721 4722 error = sbuf_finish(buf); 4723 if (error) 4724 device_printf(dev, "Error finishing sbuf: %d\n", error); 4725 else if (sbuf_len(buf)) 4726 device_printf(dev, "%s\n", sbuf_data(buf)); 4727 4728 sbuf_delete(buf); 4729 } 4730 4731 static int 4732 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 4733 { 4734 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4735 device_t dev = sc->dev; 4736 struct sbuf *buf; 4737 int error = 0; 4738 4739 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 4740 if (!buf) { 4741 device_printf(dev, "Could not allocate sbuf for output.\n"); 4742 return (ENOMEM); 4743 } 4744 4745 em_sbuf_fw_version(&sc->fw_ver, buf); 4746 4747 error = sbuf_finish(buf); 4748 if (error) 4749 device_printf(dev, "Error finishing sbuf: %d\n", error); 4750 4751 sbuf_delete(buf); 4752 4753 return (0); 4754 } 4755 4756 /********************************************************************** 4757 * 4758 * This routine provides a way to dump out the adapter eeprom, 4759 * often a useful debug/service tool. This only dumps the first 4760 * 32 words, stuff that matters is in that extent. 4761 * 4762 **********************************************************************/ 4763 static int 4764 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 4765 { 4766 struct e1000_softc *sc = (struct e1000_softc *)arg1; 4767 int error; 4768 int result; 4769 4770 result = -1; 4771 error = sysctl_handle_int(oidp, &result, 0, req); 4772 4773 if (error || !req->newptr) 4774 return (error); 4775 4776 /* 4777 * This value will cause a hex dump of the 4778 * first 32 16-bit words of the EEPROM to 4779 * the screen. 4780 */ 4781 if (result == 1) 4782 em_print_nvm_info(sc); 4783 4784 return (error); 4785 } 4786 4787 static void 4788 em_print_nvm_info(struct e1000_softc *sc) 4789 { 4790 struct e1000_hw *hw = &sc->hw; 4791 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 4792 u16 eeprom_data; 4793 int i, j, row = 0; 4794 4795 /* Its a bit crude, but it gets the job done */ 4796 printf("\nInterface EEPROM Dump:\n"); 4797 printf("Offset\n0x0000 "); 4798 4799 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 4800 sx_xlock(iflib_ctx_lock); 4801 ASSERT_CTX_LOCK_HELD(hw); 4802 for (i = 0, j = 0; i < 32; i++, j++) { 4803 if (j == 8) { /* Make the offset block */ 4804 j = 0; ++row; 4805 printf("\n0x00%x0 ",row); 4806 } 4807 e1000_read_nvm(hw, i, 1, &eeprom_data); 4808 printf("%04x ", eeprom_data); 4809 } 4810 sx_xunlock(iflib_ctx_lock); 4811 printf("\n"); 4812 } 4813 4814 static int 4815 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4816 { 4817 struct em_int_delay_info *info; 4818 struct e1000_softc *sc; 4819 u32 regval; 4820 int error, usecs, ticks; 4821 4822 info = (struct em_int_delay_info *) arg1; 4823 usecs = info->value; 4824 error = sysctl_handle_int(oidp, &usecs, 0, req); 4825 if (error != 0 || req->newptr == NULL) 4826 return (error); 4827 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 4828 return (EINVAL); 4829 info->value = usecs; 4830 ticks = EM_USECS_TO_TICKS(usecs); 4831 if (info->offset == E1000_ITR) /* units are 256ns here */ 4832 ticks *= 4; 4833 4834 sc = info->sc; 4835 4836 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 4837 regval = (regval & ~0xffff) | (ticks & 0xffff); 4838 /* Handle a few special cases. */ 4839 switch (info->offset) { 4840 case E1000_RDTR: 4841 break; 4842 case E1000_TIDV: 4843 if (ticks == 0) { 4844 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 4845 /* Don't write 0 into the TIDV register. */ 4846 regval++; 4847 } else 4848 sc->txd_cmd |= E1000_TXD_CMD_IDE; 4849 break; 4850 } 4851 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 4852 return (0); 4853 } 4854 4855 static void 4856 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 4857 const char *description, struct em_int_delay_info *info, 4858 int offset, int value) 4859 { 4860 info->sc = sc; 4861 info->offset = offset; 4862 info->value = value; 4863 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 4864 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 4865 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 4866 info, 0, em_sysctl_int_delay, "I", description); 4867 } 4868 4869 /* 4870 * Set flow control using sysctl: 4871 * Flow control values: 4872 * 0 - off 4873 * 1 - rx pause 4874 * 2 - tx pause 4875 * 3 - full 4876 */ 4877 static int 4878 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 4879 { 4880 int error; 4881 static int input = 3; /* default is full */ 4882 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4883 4884 error = sysctl_handle_int(oidp, &input, 0, req); 4885 4886 if ((error) || (req->newptr == NULL)) 4887 return (error); 4888 4889 if (input == sc->fc) /* no change? */ 4890 return (error); 4891 4892 switch (input) { 4893 case e1000_fc_rx_pause: 4894 case e1000_fc_tx_pause: 4895 case e1000_fc_full: 4896 case e1000_fc_none: 4897 sc->hw.fc.requested_mode = input; 4898 sc->fc = input; 4899 break; 4900 default: 4901 /* Do nothing */ 4902 return (error); 4903 } 4904 4905 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 4906 e1000_force_mac_fc(&sc->hw); 4907 return (error); 4908 } 4909 4910 /* 4911 * Manage Energy Efficient Ethernet: 4912 * Control values: 4913 * 0/1 - enabled/disabled 4914 */ 4915 static int 4916 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 4917 { 4918 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4919 int error, value; 4920 4921 value = sc->hw.dev_spec.ich8lan.eee_disable; 4922 error = sysctl_handle_int(oidp, &value, 0, req); 4923 if (error || req->newptr == NULL) 4924 return (error); 4925 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 4926 em_if_init(sc->ctx); 4927 4928 return (0); 4929 } 4930 4931 static int 4932 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4933 { 4934 struct e1000_softc *sc; 4935 int error; 4936 int result; 4937 4938 result = -1; 4939 error = sysctl_handle_int(oidp, &result, 0, req); 4940 4941 if (error || !req->newptr) 4942 return (error); 4943 4944 if (result == 1) { 4945 sc = (struct e1000_softc *) arg1; 4946 em_print_debug_info(sc); 4947 } 4948 4949 return (error); 4950 } 4951 4952 static int 4953 em_get_rs(SYSCTL_HANDLER_ARGS) 4954 { 4955 struct e1000_softc *sc = (struct e1000_softc *) arg1; 4956 int error; 4957 int result; 4958 4959 result = 0; 4960 error = sysctl_handle_int(oidp, &result, 0, req); 4961 4962 if (error || !req->newptr || result != 1) 4963 return (error); 4964 em_dump_rs(sc); 4965 4966 return (error); 4967 } 4968 4969 static void 4970 em_if_debug(if_ctx_t ctx) 4971 { 4972 em_dump_rs(iflib_get_softc(ctx)); 4973 } 4974 4975 /* 4976 * This routine is meant to be fluid, add whatever is 4977 * needed for debugging a problem. -jfv 4978 */ 4979 static void 4980 em_print_debug_info(struct e1000_softc *sc) 4981 { 4982 device_t dev = iflib_get_dev(sc->ctx); 4983 if_t ifp = iflib_get_ifp(sc->ctx); 4984 struct tx_ring *txr = &sc->tx_queues->txr; 4985 struct rx_ring *rxr = &sc->rx_queues->rxr; 4986 4987 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 4988 printf("Interface is RUNNING "); 4989 else 4990 printf("Interface is NOT RUNNING\n"); 4991 4992 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 4993 printf("and INACTIVE\n"); 4994 else 4995 printf("and ACTIVE\n"); 4996 4997 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 4998 device_printf(dev, "TX Queue %d ------\n", i); 4999 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5000 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5001 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5002 5003 } 5004 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5005 device_printf(dev, "RX Queue %d ------\n", j); 5006 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5007 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5008 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5009 } 5010 } 5011 5012 /* 5013 * 82574 only: 5014 * Write a new value to the EEPROM increasing the number of MSI-X 5015 * vectors from 3 to 5, for proper multiqueue support. 5016 */ 5017 static void 5018 em_enable_vectors_82574(if_ctx_t ctx) 5019 { 5020 struct e1000_softc *sc = iflib_get_softc(ctx); 5021 struct e1000_hw *hw = &sc->hw; 5022 device_t dev = iflib_get_dev(ctx); 5023 u16 edata; 5024 5025 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5026 if (bootverbose) 5027 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5028 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5029 device_printf(dev, "Writing to eeprom: increasing " 5030 "reported MSI-X vectors from 3 to 5...\n"); 5031 edata &= ~(EM_NVM_MSIX_N_MASK); 5032 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5033 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5034 e1000_update_nvm_checksum(hw); 5035 device_printf(dev, "Writing to eeprom: done\n"); 5036 } 5037 } 5038