1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include "if_em.h" 31 #include <sys/sbuf.h> 32 #include <machine/_inttypes.h> 33 34 #define em_mac_min e1000_82571 35 #define igb_mac_min e1000_82575 36 37 /********************************************************************* 38 * Driver version: 39 *********************************************************************/ 40 static const char em_driver_version[] = "7.7.8-fbsd"; 41 static const char igb_driver_version[] = "2.5.28-fbsd"; 42 43 /********************************************************************* 44 * PCI Device ID Table 45 * 46 * Used by probe to select devices to load on 47 * Last field stores an index into e1000_strings 48 * Last entry must be all 0s 49 * 50 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 51 *********************************************************************/ 52 53 static const pci_vendor_info_t em_vendor_info_array[] = 54 { 55 /* Intel(R) - lem-class legacy devices */ 56 PVID(0x8086, E1000_DEV_ID_82540EM, 57 "Intel(R) Legacy PRO/1000 MT 82540EM"), 58 PVID(0x8086, E1000_DEV_ID_82540EM_LOM, 59 "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"), 60 PVID(0x8086, E1000_DEV_ID_82540EP, 61 "Intel(R) Legacy PRO/1000 MT 82540EP"), 62 PVID(0x8086, E1000_DEV_ID_82540EP_LOM, 63 "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"), 64 PVID(0x8086, E1000_DEV_ID_82540EP_LP, 65 "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"), 66 67 PVID(0x8086, E1000_DEV_ID_82541EI, 68 "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"), 69 PVID(0x8086, E1000_DEV_ID_82541ER, 70 "Intel(R) Legacy PRO/1000 82541ER"), 71 PVID(0x8086, E1000_DEV_ID_82541ER_LOM, 72 "Intel(R) Legacy PRO/1000 MT 82541ER"), 73 PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, 74 "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"), 75 PVID(0x8086, E1000_DEV_ID_82541GI, 76 "Intel(R) Legacy PRO/1000 MT 82541GI"), 77 PVID(0x8086, E1000_DEV_ID_82541GI_LF, 78 "Intel(R) Legacy PRO/1000 GT 82541PI"), 79 PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, 80 "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"), 81 82 PVID(0x8086, E1000_DEV_ID_82542, 83 "Intel(R) Legacy PRO/1000 82542 (Fiber)"), 84 85 PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, 86 "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"), 87 PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, 88 "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"), 89 90 PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, 91 "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"), 92 PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, 93 "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"), 94 PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, 95 "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"), 96 PVID(0x8086, E1000_DEV_ID_82544GC_LOM, 97 "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"), 98 99 PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, 100 "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"), 101 PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, 102 "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"), 103 PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, 104 "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"), 105 PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, 106 "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"), 107 PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, 108 "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"), 109 110 PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, 111 "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"), 112 PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, 113 "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"), 114 PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, 115 "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"), 116 PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, 117 "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"), 118 PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, 119 "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"), 120 PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, 121 "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"), 122 PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, 123 "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"), 124 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, 125 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 126 PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 127 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"), 128 129 PVID(0x8086, E1000_DEV_ID_82547EI, 130 "Intel(R) Legacy PRO/1000 CT 82547EI"), 131 PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, 132 "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"), 133 PVID(0x8086, E1000_DEV_ID_82547GI, 134 "Intel(R) Legacy PRO/1000 CT 82547GI"), 135 136 /* Intel(R) - em-class devices */ 137 PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, 138 "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"), 139 PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, 140 "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"), 141 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, 142 "Intel(R) PRO/1000 PB 82571EB (SERDES)"), 143 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, 144 "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"), 145 PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, 146 "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"), 147 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 148 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 149 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 150 "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"), 151 PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 152 "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"), 153 PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 154 "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"), 155 PVID(0x8086, E1000_DEV_ID_82572EI, 156 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 157 PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, 158 "Intel(R) PRO/1000 PT 82572EI (Copper)"), 159 PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, 160 "Intel(R) PRO/1000 PF 82572EI (Fiber)"), 161 PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, 162 "Intel(R) PRO/1000 82572EI (SERDES)"), 163 PVID(0x8086, E1000_DEV_ID_82573E, 164 "Intel(R) PRO/1000 82573E (Copper)"), 165 PVID(0x8086, E1000_DEV_ID_82573E_IAMT, 166 "Intel(R) PRO/1000 82573E AMT (Copper)"), 167 PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"), 168 PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"), 169 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 170 "Intel(R) 80003ES2LAN (Copper)"), 171 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 172 "Intel(R) 80003ES2LAN (SERDES)"), 173 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 174 "Intel(R) 80003ES2LAN (Dual Copper)"), 175 PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 176 "Intel(R) 80003ES2LAN (Dual SERDES)"), 177 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, 178 "Intel(R) 82566MM ICH8 AMT (Mobile)"), 179 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"), 180 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"), 181 PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"), 182 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_GT, "Intel(R) 82562GT ICH8"), 183 PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"), 184 PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"), 185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"), 186 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, 187 "Intel(R) 82567LM ICH9 AMT"), 188 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, 189 "Intel(R) 82566DM-2 ICH9 AMT"), 190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"), 191 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"), 192 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"), 193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"), 194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"), 195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"), 196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"), 197 PVID(0x8086, E1000_DEV_ID_82574L, "Intel(R) Gigabit CT 82574L"), 198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"), 199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"), 200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"), 201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"), 202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"), 203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"), 204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"), 205 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LM, "Intel(R) 82577LM"), 206 PVID(0x8086, E1000_DEV_ID_PCH_M_HV_LC, "Intel(R) 82577LC"), 207 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DM, "Intel(R) 82578DM"), 208 PVID(0x8086, E1000_DEV_ID_PCH_D_HV_DC, "Intel(R) 82578DC"), 209 PVID(0x8086, E1000_DEV_ID_PCH2_LV_LM, "Intel(R) 82579LM"), 210 PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"), 211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"), 212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"), 213 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, 214 "Intel(R) I218-LM LPTLP"), 215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"), 216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"), 217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"), 218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"), 219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"), 220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"), 221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"), 222 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, 223 "Intel(R) I219-LM SPT-H(2)"), 224 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, 225 "Intel(R) I219-V SPT-H(2)"), 226 PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, 227 "Intel(R) I219-LM LBG(3)"), 228 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, 229 "Intel(R) I219-LM SPT(4)"), 230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"), 231 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, 232 "Intel(R) I219-LM SPT(5)"), 233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"), 234 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, 235 "Intel(R) I219-LM CNP(6)"), 236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"), 237 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, 238 "Intel(R) I219-LM CNP(7)"), 239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"), 240 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, 241 "Intel(R) I219-LM ICP(8)"), 242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"), 243 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, 244 "Intel(R) I219-LM ICP(9)"), 245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"), 246 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, 247 "Intel(R) I219-LM CMP(10)"), 248 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, 249 "Intel(R) I219-V CMP(10)"), 250 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, 251 "Intel(R) I219-LM CMP(11)"), 252 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, 253 "Intel(R) I219-V CMP(11)"), 254 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, 255 "Intel(R) I219-LM CMP(12)"), 256 PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, 257 "Intel(R) I219-V CMP(12)"), 258 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, 259 "Intel(R) I219-LM TGP(13)"), 260 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, 261 "Intel(R) I219-V TGP(13)"), 262 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, 263 "Intel(R) I219-LM TGP(14)"), 264 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, 265 "Intel(R) I219-V GTP(14)"), 266 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, 267 "Intel(R) I219-LM TGP(15)"), 268 PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, 269 "Intel(R) I219-V TGP(15)"), 270 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, 271 "Intel(R) I219-LM ADL(16)"), 272 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, 273 "Intel(R) I219-V ADL(16)"), 274 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, 275 "Intel(R) I219-LM ADL(17)"), 276 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, 277 "Intel(R) I219-V ADL(17)"), 278 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, 279 "Intel(R) I219-LM MTP(18)"), 280 PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, 281 "Intel(R) I219-V MTP(18)"), 282 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19, 283 "Intel(R) I219-LM ADL(19)"), 284 PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19, 285 "Intel(R) I219-V ADL(19)"), 286 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, 287 "Intel(R) I219-LM LNL(20)"), 288 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, 289 "Intel(R) I219-V LNL(20)"), 290 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, 291 "Intel(R) I219-LM LNL(21)"), 292 PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, 293 "Intel(R) I219-V LNL(21)"), 294 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, 295 "Intel(R) I219-LM RPL(22)"), 296 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, 297 "Intel(R) I219-V RPL(22)"), 298 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, 299 "Intel(R) I219-LM RPL(23)"), 300 PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, 301 "Intel(R) I219-V RPL(23)"), 302 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, 303 "Intel(R) I219-LM ARL(24)"), 304 PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, 305 "Intel(R) I219-V ARL(24)"), 306 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, 307 "Intel(R) I219-LM PTP(25)"), 308 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, 309 "Intel(R) I219-V PTP(25)"), 310 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, 311 "Intel(R) I219-LM PTP(26)"), 312 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, 313 "Intel(R) I219-V PTP(26)"), 314 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, 315 "Intel(R) I219-LM PTP(27)"), 316 PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, 317 "Intel(R) I219-V PTP(27)"), 318 /* required last entry */ 319 PVID_END 320 }; 321 322 static const pci_vendor_info_t igb_vendor_info_array[] = 323 { 324 /* Intel(R) - igb-class devices */ 325 PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, 326 "Intel(R) PRO/1000 82575EB (Copper)"), 327 PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 328 "Intel(R) PRO/1000 82575EB (SERDES)"), 329 PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 330 "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"), 331 PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"), 332 PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"), 333 PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, 334 "Intel(R) PRO/1000 82576NS (SERDES)"), 335 PVID(0x8086, E1000_DEV_ID_82576_FIBER, 336 "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"), 337 PVID(0x8086, E1000_DEV_ID_82576_SERDES, 338 "Intel(R) PRO/1000 82576 (Dual SERDES)"), 339 PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, 340 "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"), 341 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, 342 "Intel(R) PRO/1000 ET 82576 (Quad Copper)"), 343 PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, 344 "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"), 345 PVID(0x8086, E1000_DEV_ID_82576_VF, 346 "Intel(R) PRO/1000 82576 Virtual Function"), 347 PVID(0x8086, E1000_DEV_ID_82580_COPPER, 348 "Intel(R) I340 82580 (Copper)"), 349 PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"), 350 PVID(0x8086, E1000_DEV_ID_82580_SERDES, 351 "Intel(R) I340 82580 (SERDES)"), 352 PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"), 353 PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, 354 "Intel(R) I340-T2 82580 (Dual Copper)"), 355 PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, 356 "Intel(R) I340-F4 82580 (Quad Fiber)"), 357 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, 358 "Intel(R) DH89XXCC (SERDES)"), 359 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, 360 "Intel(R) I347-AT4 DH89XXCC"), 361 PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"), 362 PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, 363 "Intel(R) DH89XXCC (Backplane)"), 364 PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"), 365 PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"), 366 PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"), 367 PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"), 368 PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"), 369 PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"), 370 PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, 371 "Intel(R) I210 IT (Copper)"), 372 PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"), 373 PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, 374 "Intel(R) I210 Flashless (Copper)"), 375 PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, 376 "Intel(R) I210 Flashless (SERDES)"), 377 PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, 378 "Intel(R) I210 Flashless (SGMII)"), 379 PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"), 380 PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"), 381 PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"), 382 PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"), 383 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, 384 "Intel(R) I354 (1.0 GbE Backplane)"), 385 PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, 386 "Intel(R) I354 (2.5 GbE Backplane)"), 387 PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"), 388 /* required last entry */ 389 PVID_END 390 }; 391 392 /********************************************************************* 393 * Function prototypes 394 *********************************************************************/ 395 static void *em_register(device_t); 396 static void *igb_register(device_t); 397 static int em_if_attach_pre(if_ctx_t); 398 static int em_if_attach_post(if_ctx_t); 399 static int em_if_detach(if_ctx_t); 400 static int em_if_shutdown(if_ctx_t); 401 static int em_if_suspend(if_ctx_t); 402 static int em_if_resume(if_ctx_t); 403 404 static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 405 int); 406 static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 407 int); 408 static void em_if_queues_free(if_ctx_t); 409 410 static uint64_t em_if_get_vf_counter(if_ctx_t, ift_counter); 411 static uint64_t em_if_get_counter(if_ctx_t, ift_counter); 412 static void em_if_init(if_ctx_t); 413 static void em_if_stop(if_ctx_t); 414 static void em_if_media_status(if_ctx_t, struct ifmediareq *); 415 static int em_if_media_change(if_ctx_t); 416 static int em_if_mtu_set(if_ctx_t, uint32_t); 417 static void em_if_timer(if_ctx_t, uint16_t); 418 static void em_if_vlan_register(if_ctx_t, u16); 419 static void em_if_vlan_unregister(if_ctx_t, u16); 420 static void em_if_watchdog_reset(if_ctx_t); 421 static bool em_if_needs_restart(if_ctx_t, enum iflib_restart_event); 422 423 static void em_identify_hardware(if_ctx_t); 424 static int em_allocate_pci_resources(if_ctx_t); 425 static void em_free_pci_resources(if_ctx_t); 426 static void em_reset(if_ctx_t); 427 static int em_setup_interface(if_ctx_t); 428 static int em_setup_msix(if_ctx_t); 429 430 static void em_initialize_transmit_unit(if_ctx_t); 431 static void em_initialize_receive_unit(if_ctx_t); 432 433 static void em_if_intr_enable(if_ctx_t); 434 static void em_if_intr_disable(if_ctx_t); 435 static void igb_if_intr_enable(if_ctx_t); 436 static void igb_if_intr_disable(if_ctx_t); 437 static int em_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 438 static int em_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 439 static int igb_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 440 static int igb_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 441 static void em_if_multi_set(if_ctx_t); 442 static void em_if_update_admin_status(if_ctx_t); 443 static void em_if_debug(if_ctx_t); 444 static void em_update_vf_stats_counters(struct e1000_softc *); 445 static void em_update_stats_counters(struct e1000_softc *); 446 static void em_add_hw_stats(struct e1000_softc *); 447 static int em_if_set_promisc(if_ctx_t, int); 448 static bool em_if_vlan_filter_capable(if_ctx_t); 449 static bool em_if_vlan_filter_used(if_ctx_t); 450 static void em_if_vlan_filter_enable(struct e1000_softc *); 451 static void em_if_vlan_filter_disable(struct e1000_softc *); 452 static void em_if_vlan_filter_write(struct e1000_softc *); 453 static void em_setup_vlan_hw_support(if_ctx_t ctx); 454 static int em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 455 static void em_print_nvm_info(struct e1000_softc *); 456 static void em_fw_version_locked(if_ctx_t); 457 static void em_sbuf_fw_version(struct e1000_fw_version *, struct sbuf *); 458 static void em_print_fw_version(struct e1000_softc *); 459 static int em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 460 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 461 static int em_get_rs(SYSCTL_HANDLER_ARGS); 462 static void em_print_debug_info(struct e1000_softc *); 463 static int em_is_valid_ether_addr(u8 *); 464 static void em_newitr(struct e1000_softc *, struct em_rx_queue *, 465 struct tx_ring *, struct rx_ring *); 466 static bool em_automask_tso(if_ctx_t); 467 static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 468 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 469 static void em_add_int_delay_sysctl(struct e1000_softc *, const char *, 470 const char *, struct em_int_delay_info *, int, int); 471 /* Management and WOL Support */ 472 static void em_init_manageability(struct e1000_softc *); 473 static void em_release_manageability(struct e1000_softc *); 474 static void em_get_hw_control(struct e1000_softc *); 475 static void em_release_hw_control(struct e1000_softc *); 476 static void em_get_wakeup(if_ctx_t); 477 static void em_enable_wakeup(if_ctx_t); 478 static int em_enable_phy_wakeup(struct e1000_softc *); 479 static void em_disable_aspm(struct e1000_softc *); 480 481 int em_intr(void *); 482 483 /* MSI-X handlers */ 484 static int em_if_msix_intr_assign(if_ctx_t, int); 485 static int em_msix_link(void *); 486 static void em_handle_link(void *); 487 488 static void em_enable_vectors_82574(if_ctx_t); 489 490 static int em_set_flowcntl(SYSCTL_HANDLER_ARGS); 491 static int em_sysctl_eee(SYSCTL_HANDLER_ARGS); 492 static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS); 493 static void em_if_led_func(if_ctx_t, int); 494 495 static int em_get_regs(SYSCTL_HANDLER_ARGS); 496 497 static void lem_smartspeed(struct e1000_softc *); 498 static void igb_configure_queues(struct e1000_softc *); 499 static void em_flush_desc_rings(struct e1000_softc *); 500 501 502 /********************************************************************* 503 * FreeBSD Device Interface Entry Points 504 *********************************************************************/ 505 static device_method_t em_methods[] = { 506 /* Device interface */ 507 DEVMETHOD(device_register, em_register), 508 DEVMETHOD(device_probe, iflib_device_probe), 509 DEVMETHOD(device_attach, iflib_device_attach), 510 DEVMETHOD(device_detach, iflib_device_detach), 511 DEVMETHOD(device_shutdown, iflib_device_shutdown), 512 DEVMETHOD(device_suspend, iflib_device_suspend), 513 DEVMETHOD(device_resume, iflib_device_resume), 514 DEVMETHOD_END 515 }; 516 517 static device_method_t igb_methods[] = { 518 /* Device interface */ 519 DEVMETHOD(device_register, igb_register), 520 DEVMETHOD(device_probe, iflib_device_probe), 521 DEVMETHOD(device_attach, iflib_device_attach), 522 DEVMETHOD(device_detach, iflib_device_detach), 523 DEVMETHOD(device_shutdown, iflib_device_shutdown), 524 DEVMETHOD(device_suspend, iflib_device_suspend), 525 DEVMETHOD(device_resume, iflib_device_resume), 526 DEVMETHOD_END 527 }; 528 529 530 static driver_t em_driver = { 531 "em", em_methods, sizeof(struct e1000_softc), 532 }; 533 534 DRIVER_MODULE(em, pci, em_driver, 0, 0); 535 536 MODULE_DEPEND(em, pci, 1, 1, 1); 537 MODULE_DEPEND(em, ether, 1, 1, 1); 538 MODULE_DEPEND(em, iflib, 1, 1, 1); 539 540 IFLIB_PNP_INFO(pci, em, em_vendor_info_array); 541 542 static driver_t igb_driver = { 543 "igb", igb_methods, sizeof(struct e1000_softc), 544 }; 545 546 DRIVER_MODULE(igb, pci, igb_driver, 0, 0); 547 548 MODULE_DEPEND(igb, pci, 1, 1, 1); 549 MODULE_DEPEND(igb, ether, 1, 1, 1); 550 MODULE_DEPEND(igb, iflib, 1, 1, 1); 551 552 IFLIB_PNP_INFO(pci, igb, igb_vendor_info_array); 553 554 static device_method_t em_if_methods[] = { 555 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 556 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 557 DEVMETHOD(ifdi_detach, em_if_detach), 558 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 559 DEVMETHOD(ifdi_suspend, em_if_suspend), 560 DEVMETHOD(ifdi_resume, em_if_resume), 561 DEVMETHOD(ifdi_init, em_if_init), 562 DEVMETHOD(ifdi_stop, em_if_stop), 563 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 564 DEVMETHOD(ifdi_intr_enable, em_if_intr_enable), 565 DEVMETHOD(ifdi_intr_disable, em_if_intr_disable), 566 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 567 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 568 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 569 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 570 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 571 DEVMETHOD(ifdi_media_status, em_if_media_status), 572 DEVMETHOD(ifdi_media_change, em_if_media_change), 573 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 574 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 575 DEVMETHOD(ifdi_timer, em_if_timer), 576 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 577 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 578 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 579 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 580 DEVMETHOD(ifdi_led_func, em_if_led_func), 581 DEVMETHOD(ifdi_rx_queue_intr_enable, em_if_rx_queue_intr_enable), 582 DEVMETHOD(ifdi_tx_queue_intr_enable, em_if_tx_queue_intr_enable), 583 DEVMETHOD(ifdi_debug, em_if_debug), 584 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 585 DEVMETHOD_END 586 }; 587 588 static driver_t em_if_driver = { 589 "em_if", em_if_methods, sizeof(struct e1000_softc) 590 }; 591 592 static device_method_t igb_if_methods[] = { 593 DEVMETHOD(ifdi_attach_pre, em_if_attach_pre), 594 DEVMETHOD(ifdi_attach_post, em_if_attach_post), 595 DEVMETHOD(ifdi_detach, em_if_detach), 596 DEVMETHOD(ifdi_shutdown, em_if_shutdown), 597 DEVMETHOD(ifdi_suspend, em_if_suspend), 598 DEVMETHOD(ifdi_resume, em_if_resume), 599 DEVMETHOD(ifdi_init, em_if_init), 600 DEVMETHOD(ifdi_stop, em_if_stop), 601 DEVMETHOD(ifdi_msix_intr_assign, em_if_msix_intr_assign), 602 DEVMETHOD(ifdi_intr_enable, igb_if_intr_enable), 603 DEVMETHOD(ifdi_intr_disable, igb_if_intr_disable), 604 DEVMETHOD(ifdi_tx_queues_alloc, em_if_tx_queues_alloc), 605 DEVMETHOD(ifdi_rx_queues_alloc, em_if_rx_queues_alloc), 606 DEVMETHOD(ifdi_queues_free, em_if_queues_free), 607 DEVMETHOD(ifdi_update_admin_status, em_if_update_admin_status), 608 DEVMETHOD(ifdi_multi_set, em_if_multi_set), 609 DEVMETHOD(ifdi_media_status, em_if_media_status), 610 DEVMETHOD(ifdi_media_change, em_if_media_change), 611 DEVMETHOD(ifdi_mtu_set, em_if_mtu_set), 612 DEVMETHOD(ifdi_promisc_set, em_if_set_promisc), 613 DEVMETHOD(ifdi_timer, em_if_timer), 614 DEVMETHOD(ifdi_watchdog_reset, em_if_watchdog_reset), 615 DEVMETHOD(ifdi_vlan_register, em_if_vlan_register), 616 DEVMETHOD(ifdi_vlan_unregister, em_if_vlan_unregister), 617 DEVMETHOD(ifdi_get_counter, em_if_get_counter), 618 DEVMETHOD(ifdi_led_func, em_if_led_func), 619 DEVMETHOD(ifdi_rx_queue_intr_enable, igb_if_rx_queue_intr_enable), 620 DEVMETHOD(ifdi_tx_queue_intr_enable, igb_if_tx_queue_intr_enable), 621 DEVMETHOD(ifdi_debug, em_if_debug), 622 DEVMETHOD(ifdi_needs_restart, em_if_needs_restart), 623 DEVMETHOD_END 624 }; 625 626 static driver_t igb_if_driver = { 627 "igb_if", igb_if_methods, sizeof(struct e1000_softc) 628 }; 629 630 /********************************************************************* 631 * Tunable default values. 632 *********************************************************************/ 633 634 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 635 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 636 637 /* Allow common code without TSO */ 638 #ifndef CSUM_TSO 639 #define CSUM_TSO 0 640 #endif 641 642 static SYSCTL_NODE(_hw, OID_AUTO, em, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 643 "EM driver parameters"); 644 645 static int em_disable_crc_stripping = 0; 646 SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 647 &em_disable_crc_stripping, 0, "Disable CRC Stripping"); 648 649 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 650 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 651 SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, 652 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs"); 653 SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, 654 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs"); 655 656 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 657 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 658 SYSCTL_INT(_hw_em, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 659 &em_tx_abs_int_delay_dflt, 0, 660 "Default transmit interrupt delay limit in usecs"); 661 SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 662 &em_rx_abs_int_delay_dflt, 0, 663 "Default receive interrupt delay limit in usecs"); 664 665 static int em_smart_pwr_down = false; 666 SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, 667 &em_smart_pwr_down, 668 0, "Set to true to leave smart power down enabled on newer adapters"); 669 670 static bool em_unsupported_tso = false; 671 SYSCTL_BOOL(_hw_em, OID_AUTO, unsupported_tso, CTLFLAG_RDTUN, 672 &em_unsupported_tso, 0, "Allow unsupported em(4) TSO configurations"); 673 674 /* Controls whether promiscuous also shows bad packets */ 675 static int em_debug_sbp = false; 676 SYSCTL_INT(_hw_em, OID_AUTO, sbp, CTLFLAG_RDTUN, &em_debug_sbp, 0, 677 "Show bad packets in promiscuous mode"); 678 679 /* Energy efficient ethernet - default to OFF */ 680 static int eee_setting = 1; 681 SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0, 682 "Enable Energy Efficient Ethernet"); 683 684 /* 685 * AIM: Adaptive Interrupt Moderation 686 * which means that the interrupt rate is varied over time based on the 687 * traffic for that interrupt vector 688 */ 689 static int em_enable_aim = 1; 690 SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim, 691 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 692 693 /* 694 ** Tuneable Interrupt rate 695 */ 696 static int em_max_interrupt_rate = EM_INTS_DEFAULT; 697 SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 698 &em_max_interrupt_rate, 0, "Maximum interrupts per second"); 699 700 /* Global used in WOL setup with multiport cards */ 701 static int global_quad_port_a = 0; 702 703 extern struct if_txrx igb_txrx; 704 extern struct if_txrx em_txrx; 705 extern struct if_txrx lem_txrx; 706 707 static struct if_shared_ctx em_sctx_init = { 708 .isc_magic = IFLIB_MAGIC, 709 .isc_q_align = PAGE_SIZE, 710 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 711 .isc_tx_maxsegsize = PAGE_SIZE, 712 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 713 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 714 .isc_rx_maxsize = MJUM9BYTES, 715 .isc_rx_nsegments = 1, 716 .isc_rx_maxsegsize = MJUM9BYTES, 717 .isc_nfl = 1, 718 .isc_nrxqs = 1, 719 .isc_ntxqs = 1, 720 .isc_admin_intrcnt = 1, 721 .isc_vendor_info = em_vendor_info_array, 722 .isc_driver_version = em_driver_version, 723 .isc_driver = &em_if_driver, 724 .isc_flags = 725 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 726 727 .isc_nrxd_min = {EM_MIN_RXD}, 728 .isc_ntxd_min = {EM_MIN_TXD}, 729 .isc_nrxd_max = {EM_MAX_RXD}, 730 .isc_ntxd_max = {EM_MAX_TXD}, 731 .isc_nrxd_default = {EM_DEFAULT_RXD}, 732 .isc_ntxd_default = {EM_DEFAULT_TXD}, 733 }; 734 735 static struct if_shared_ctx igb_sctx_init = { 736 .isc_magic = IFLIB_MAGIC, 737 .isc_q_align = PAGE_SIZE, 738 .isc_tx_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 739 .isc_tx_maxsegsize = PAGE_SIZE, 740 .isc_tso_maxsize = EM_TSO_SIZE + sizeof(struct ether_vlan_header), 741 .isc_tso_maxsegsize = EM_TSO_SEG_SIZE, 742 .isc_rx_maxsize = MJUM9BYTES, 743 .isc_rx_nsegments = 1, 744 .isc_rx_maxsegsize = MJUM9BYTES, 745 .isc_nfl = 1, 746 .isc_nrxqs = 1, 747 .isc_ntxqs = 1, 748 .isc_admin_intrcnt = 1, 749 .isc_vendor_info = igb_vendor_info_array, 750 .isc_driver_version = igb_driver_version, 751 .isc_driver = &igb_if_driver, 752 .isc_flags = 753 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 754 755 .isc_nrxd_min = {EM_MIN_RXD}, 756 .isc_ntxd_min = {EM_MIN_TXD}, 757 .isc_nrxd_max = {IGB_MAX_RXD}, 758 .isc_ntxd_max = {IGB_MAX_TXD}, 759 .isc_nrxd_default = {EM_DEFAULT_RXD}, 760 .isc_ntxd_default = {EM_DEFAULT_TXD}, 761 }; 762 763 /***************************************************************** 764 * 765 * Dump Registers 766 * 767 ****************************************************************/ 768 #define IGB_REGS_LEN 739 769 770 static int em_get_regs(SYSCTL_HANDLER_ARGS) 771 { 772 struct e1000_softc *sc = (struct e1000_softc *)arg1; 773 struct e1000_hw *hw = &sc->hw; 774 struct sbuf *sb; 775 u32 *regs_buff; 776 int rc; 777 778 regs_buff = malloc(sizeof(u32) * IGB_REGS_LEN, M_DEVBUF, M_WAITOK); 779 memset(regs_buff, 0, IGB_REGS_LEN * sizeof(u32)); 780 781 rc = sysctl_wire_old_buffer(req, 0); 782 MPASS(rc == 0); 783 if (rc != 0) { 784 free(regs_buff, M_DEVBUF); 785 return (rc); 786 } 787 788 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 789 MPASS(sb != NULL); 790 if (sb == NULL) { 791 free(regs_buff, M_DEVBUF); 792 return (ENOMEM); 793 } 794 795 /* General Registers */ 796 regs_buff[0] = E1000_READ_REG(hw, E1000_CTRL); 797 regs_buff[1] = E1000_READ_REG(hw, E1000_STATUS); 798 regs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT); 799 regs_buff[3] = E1000_READ_REG(hw, E1000_ICR); 800 regs_buff[4] = E1000_READ_REG(hw, E1000_RCTL); 801 regs_buff[5] = E1000_READ_REG(hw, E1000_RDLEN(0)); 802 regs_buff[6] = E1000_READ_REG(hw, E1000_RDH(0)); 803 regs_buff[7] = E1000_READ_REG(hw, E1000_RDT(0)); 804 regs_buff[8] = E1000_READ_REG(hw, E1000_RXDCTL(0)); 805 regs_buff[9] = E1000_READ_REG(hw, E1000_RDBAL(0)); 806 regs_buff[10] = E1000_READ_REG(hw, E1000_RDBAH(0)); 807 regs_buff[11] = E1000_READ_REG(hw, E1000_TCTL); 808 regs_buff[12] = E1000_READ_REG(hw, E1000_TDBAL(0)); 809 regs_buff[13] = E1000_READ_REG(hw, E1000_TDBAH(0)); 810 regs_buff[14] = E1000_READ_REG(hw, E1000_TDLEN(0)); 811 regs_buff[15] = E1000_READ_REG(hw, E1000_TDH(0)); 812 regs_buff[16] = E1000_READ_REG(hw, E1000_TDT(0)); 813 regs_buff[17] = E1000_READ_REG(hw, E1000_TXDCTL(0)); 814 regs_buff[18] = E1000_READ_REG(hw, E1000_TDFH); 815 regs_buff[19] = E1000_READ_REG(hw, E1000_TDFT); 816 regs_buff[20] = E1000_READ_REG(hw, E1000_TDFHS); 817 regs_buff[21] = E1000_READ_REG(hw, E1000_TDFPC); 818 819 sbuf_printf(sb, "General Registers\n"); 820 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 821 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 822 sbuf_printf(sb, "\tCTRL_EXT\t %08x\n\n", regs_buff[2]); 823 824 sbuf_printf(sb, "Interrupt Registers\n"); 825 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 826 827 sbuf_printf(sb, "RX Registers\n"); 828 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 829 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 830 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 831 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 832 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 833 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 834 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 835 836 sbuf_printf(sb, "TX Registers\n"); 837 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 838 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 839 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 840 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 841 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 842 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 843 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 844 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 845 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 846 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 847 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 848 849 free(regs_buff, M_DEVBUF); 850 851 #ifdef DUMP_DESCS 852 { 853 if_softc_ctx_t scctx = sc->shared; 854 struct rx_ring *rxr = &rx_que->rxr; 855 struct tx_ring *txr = &tx_que->txr; 856 int ntxd = scctx->isc_ntxd[0]; 857 int nrxd = scctx->isc_nrxd[0]; 858 int j; 859 860 for (j = 0; j < nrxd; j++) { 861 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 862 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 863 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" 864 PRIx64 " Error:%d Length:%d\n", 865 j, rxr->rx_base[j].read.buffer_addr, staterr, length); 866 } 867 868 for (j = 0; j < min(ntxd, 256); j++) { 869 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 870 871 sbuf_printf(sb, 872 "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x" 873 " eop: %d DD=%d\n", 874 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 875 buf->eop != -1 ? 876 txr->tx_base[buf->eop].upper.fields.status & 877 E1000_TXD_STAT_DD : 0); 878 879 } 880 } 881 #endif 882 883 rc = sbuf_finish(sb); 884 sbuf_delete(sb); 885 return(rc); 886 } 887 888 static void * 889 em_register(device_t dev) 890 { 891 return (&em_sctx_init); 892 } 893 894 static void * 895 igb_register(device_t dev) 896 { 897 return (&igb_sctx_init); 898 } 899 900 static int 901 em_set_num_queues(if_ctx_t ctx) 902 { 903 struct e1000_softc *sc = iflib_get_softc(ctx); 904 int maxqueues; 905 906 /* Sanity check based on HW */ 907 switch (sc->hw.mac.type) { 908 case e1000_82576: 909 case e1000_82580: 910 case e1000_i350: 911 case e1000_i354: 912 maxqueues = 8; 913 break; 914 case e1000_i210: 915 case e1000_82575: 916 maxqueues = 4; 917 break; 918 case e1000_i211: 919 case e1000_82574: 920 maxqueues = 2; 921 break; 922 default: 923 maxqueues = 1; 924 break; 925 } 926 927 return (maxqueues); 928 } 929 930 #define LEM_CAPS \ 931 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 932 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 933 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 934 935 #define EM_CAPS \ 936 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 937 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 938 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 939 IFCAP_TSO6 940 941 #define IGB_CAPS \ 942 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 943 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 944 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | \ 945 IFCAP_TSO6 946 947 /********************************************************************* 948 * Device initialization routine 949 * 950 * The attach entry point is called when the driver is being loaded. 951 * This routine identifies the type of hardware, allocates all resources 952 * and initializes the hardware. 953 * 954 * return 0 on success, positive on failure 955 *********************************************************************/ 956 static int 957 em_if_attach_pre(if_ctx_t ctx) 958 { 959 struct e1000_softc *sc; 960 if_softc_ctx_t scctx; 961 device_t dev; 962 struct e1000_hw *hw; 963 struct sysctl_oid_list *child; 964 struct sysctl_ctx_list *ctx_list; 965 int error = 0; 966 967 INIT_DEBUGOUT("em_if_attach_pre: begin"); 968 dev = iflib_get_dev(ctx); 969 sc = iflib_get_softc(ctx); 970 971 sc->ctx = sc->osdep.ctx = ctx; 972 sc->dev = sc->osdep.dev = dev; 973 scctx = sc->shared = iflib_get_softc_ctx(ctx); 974 sc->media = iflib_get_media(ctx); 975 hw = &sc->hw; 976 977 /* Determine hardware and mac info */ 978 em_identify_hardware(ctx); 979 980 /* SYSCTL stuff */ 981 ctx_list = device_get_sysctl_ctx(dev); 982 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 983 984 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm", 985 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 986 em_sysctl_nvm_info, "I", "NVM Information"); 987 988 sc->enable_aim = em_enable_aim; 989 SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim", 990 CTLFLAG_RW, &sc->enable_aim, 0, 991 "Interrupt Moderation (1=normal, 2=lowlatency)"); 992 993 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version", 994 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 995 em_sysctl_print_fw_version, "A", 996 "Prints FW/NVM Versions"); 997 998 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug", 999 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1000 em_sysctl_debug_info, "I", "Debug Information"); 1001 1002 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc", 1003 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1004 em_set_flowcntl, "I", "Flow Control"); 1005 1006 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "reg_dump", 1007 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 1008 em_get_regs, "A", "Dump Registers"); 1009 1010 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "rs_dump", 1011 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1012 em_get_rs, "I", "Dump RS indexes"); 1013 1014 if (hw->mac.type >= e1000_i350) { 1015 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac", 1016 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 1017 igb_sysctl_dmac, "I", "DMA Coalesce"); 1018 } 1019 1020 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1021 "tso_tcp_flags_mask_first_segment", 1022 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1023 sc, 0, em_sysctl_tso_tcp_flags_mask, "IU", 1024 "TSO TCP flags mask for first segment"); 1025 1026 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1027 "tso_tcp_flags_mask_middle_segment", 1028 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1029 sc, 1, em_sysctl_tso_tcp_flags_mask, "IU", 1030 "TSO TCP flags mask for middle segment"); 1031 1032 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, 1033 "tso_tcp_flags_mask_last_segment", 1034 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1035 sc, 2, em_sysctl_tso_tcp_flags_mask, "IU", 1036 "TSO TCP flags mask for last segment"); 1037 1038 scctx->isc_tx_nsegments = EM_MAX_SCATTER; 1039 scctx->isc_nrxqsets_max = 1040 scctx->isc_ntxqsets_max = em_set_num_queues(ctx); 1041 if (bootverbose) 1042 device_printf(dev, "attach_pre capping queues at %d\n", 1043 scctx->isc_ntxqsets_max); 1044 1045 if (hw->mac.type >= igb_mac_min) { 1046 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1047 sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN); 1048 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1049 sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN); 1050 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc); 1051 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc); 1052 scctx->isc_txrx = &igb_txrx; 1053 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1054 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1055 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1056 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS; 1057 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 1058 CSUM_IP6_TCP | CSUM_IP6_UDP; 1059 if (hw->mac.type != e1000_82575) 1060 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP; 1061 /* 1062 ** Some new devices, as with ixgbe, now may 1063 ** use a different BAR, so we need to keep 1064 ** track of which is used. 1065 */ 1066 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1067 } else if (hw->mac.type >= em_mac_min) { 1068 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 1069 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1070 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 1071 sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN); 1072 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1073 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended); 1074 scctx->isc_txrx = &em_txrx; 1075 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1076 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1077 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1078 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS; 1079 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1080 CSUM_IP6_TCP | CSUM_IP6_UDP; 1081 1082 /* Disable TSO on all em(4) until ring stalls are debugged */ 1083 scctx->isc_capenable &= ~IFCAP_TSO; 1084 1085 /* 1086 * Disable TSO on SPT due to errata that downclocks DMA 1087 * performance 1088 * i218-i219 Specification Update 1.5.4.5 1089 */ 1090 if (hw->mac.type == e1000_pch_spt) 1091 scctx->isc_capenable &= ~IFCAP_TSO; 1092 1093 /* 1094 * We support MSI-X with 82574 only, but indicate to iflib(4) 1095 * that it shall give MSI at least a try with other devices. 1096 */ 1097 if (hw->mac.type == e1000_82574) { 1098 scctx->isc_msix_bar = pci_msix_table_bar(dev); 1099 } else { 1100 scctx->isc_msix_bar = -1; 1101 scctx->isc_disable_msix = 1; 1102 } 1103 } else { 1104 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * 1105 sizeof(struct e1000_tx_desc), EM_DBA_ALIGN); 1106 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * 1107 sizeof(struct e1000_rx_desc), EM_DBA_ALIGN); 1108 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc); 1109 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc); 1110 scctx->isc_txrx = &lem_txrx; 1111 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER; 1112 scctx->isc_tx_tso_size_max = EM_TSO_SIZE; 1113 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE; 1114 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS; 1115 if (em_unsupported_tso) 1116 scctx->isc_capabilities |= IFCAP_TSO6; 1117 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO | 1118 CSUM_IP6_TCP | CSUM_IP6_UDP; 1119 1120 /* Disable TSO on all lem(4) until ring stalls debugged */ 1121 scctx->isc_capenable &= ~IFCAP_TSO; 1122 1123 /* 82541ER doesn't do HW tagging */ 1124 if (hw->device_id == E1000_DEV_ID_82541ER || 1125 hw->device_id == E1000_DEV_ID_82541ER_LOM) { 1126 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING; 1127 scctx->isc_capenable = scctx->isc_capabilities; 1128 } 1129 /* This is the first e1000 chip and it does not do offloads */ 1130 if (hw->mac.type == e1000_82542) { 1131 scctx->isc_capabilities &= ~(IFCAP_HWCSUM | 1132 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 | 1133 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER | 1134 IFCAP_TSO | IFCAP_VLAN_HWTSO); 1135 scctx->isc_capenable = scctx->isc_capabilities; 1136 } 1137 /* These can't do TSO for various reasons */ 1138 if (hw->mac.type < e1000_82544 || 1139 hw->mac.type == e1000_82547 || 1140 hw->mac.type == e1000_82547_rev_2) { 1141 scctx->isc_capabilities &= 1142 ~(IFCAP_TSO |IFCAP_VLAN_HWTSO); 1143 scctx->isc_capenable = scctx->isc_capabilities; 1144 } 1145 /* XXXKB: No IPv6 before this? */ 1146 if (hw->mac.type < e1000_82545){ 1147 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6; 1148 scctx->isc_capenable = scctx->isc_capabilities; 1149 } 1150 /* 1151 * "PCI/PCI-X SDM 4.0" page 33 (b): 1152 * FDX requirement on these chips 1153 */ 1154 if (hw->mac.type == e1000_82547 || 1155 hw->mac.type == e1000_82547_rev_2) 1156 scctx->isc_capenable &= ~(IFCAP_HWCSUM | 1157 IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6); 1158 1159 /* INTx only */ 1160 scctx->isc_msix_bar = 0; 1161 } 1162 1163 /* Setup PCI resources */ 1164 if (em_allocate_pci_resources(ctx)) { 1165 device_printf(dev, "Allocation of PCI resources failed\n"); 1166 error = ENXIO; 1167 goto err_pci; 1168 } 1169 1170 /* 1171 ** For ICH8 and family we need to 1172 ** map the flash memory, and this 1173 ** must happen after the MAC is 1174 ** identified 1175 */ 1176 if ((hw->mac.type == e1000_ich8lan) || 1177 (hw->mac.type == e1000_ich9lan) || 1178 (hw->mac.type == e1000_ich10lan) || 1179 (hw->mac.type == e1000_pchlan) || 1180 (hw->mac.type == e1000_pch2lan) || 1181 (hw->mac.type == e1000_pch_lpt)) { 1182 int rid = EM_BAR_TYPE_FLASH; 1183 sc->flash = bus_alloc_resource_any(dev, 1184 SYS_RES_MEMORY, &rid, RF_ACTIVE); 1185 if (sc->flash == NULL) { 1186 device_printf(dev, "Mapping of Flash failed\n"); 1187 error = ENXIO; 1188 goto err_pci; 1189 } 1190 /* This is used in the shared code */ 1191 hw->flash_address = (u8 *)sc->flash; 1192 sc->osdep.flash_bus_space_tag = 1193 rman_get_bustag(sc->flash); 1194 sc->osdep.flash_bus_space_handle = 1195 rman_get_bushandle(sc->flash); 1196 } 1197 /* 1198 ** In the new SPT device flash is not a 1199 ** separate BAR, rather it is also in BAR0, 1200 ** so use the same tag and an offset handle for the 1201 ** FLASH read/write macros in the shared code. 1202 */ 1203 else if (hw->mac.type >= e1000_pch_spt) { 1204 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag; 1205 sc->osdep.flash_bus_space_handle = 1206 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR; 1207 } 1208 1209 /* Do Shared Code initialization */ 1210 error = e1000_setup_init_funcs(hw, true); 1211 if (error) { 1212 device_printf(dev, "Setup of Shared code failed, error %d\n", 1213 error); 1214 error = ENXIO; 1215 goto err_pci; 1216 } 1217 1218 em_setup_msix(ctx); 1219 e1000_get_bus_info(hw); 1220 1221 /* Set up some sysctls for the tunable interrupt delays */ 1222 if (hw->mac.type < igb_mac_min) { 1223 em_add_int_delay_sysctl(sc, "rx_int_delay", 1224 "receive interrupt delay in usecs", &sc->rx_int_delay, 1225 E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt); 1226 em_add_int_delay_sysctl(sc, "tx_int_delay", 1227 "transmit interrupt delay in usecs", &sc->tx_int_delay, 1228 E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt); 1229 } 1230 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) { 1231 em_add_int_delay_sysctl(sc, "rx_abs_int_delay", 1232 "receive interrupt delay limit in usecs", 1233 &sc->rx_abs_int_delay, 1234 E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt); 1235 em_add_int_delay_sysctl(sc, "tx_abs_int_delay", 1236 "transmit interrupt delay limit in usecs", 1237 &sc->tx_abs_int_delay, 1238 E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt); 1239 } 1240 1241 hw->mac.autoneg = DO_AUTO_NEG; 1242 hw->phy.autoneg_wait_to_complete = false; 1243 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1244 1245 if (hw->mac.type < em_mac_min) { 1246 e1000_init_script_state_82541(hw, true); 1247 e1000_set_tbi_compatibility_82543(hw, true); 1248 } 1249 /* Copper options */ 1250 if (hw->phy.media_type == e1000_media_type_copper) { 1251 hw->phy.mdix = AUTO_ALL_MODES; 1252 hw->phy.disable_polarity_correction = false; 1253 hw->phy.ms_type = EM_MASTER_SLAVE; 1254 } 1255 1256 /* 1257 * Set the frame limits assuming 1258 * standard ethernet sized frames. 1259 */ 1260 scctx->isc_max_frame_size = hw->mac.max_frame_size = 1261 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 1262 1263 /* 1264 * This controls when hardware reports transmit completion 1265 * status. 1266 */ 1267 hw->mac.report_tx_early = 1; 1268 1269 /* Allocate multicast array memory. */ 1270 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 1271 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 1272 if (sc->mta == NULL) { 1273 device_printf(dev, 1274 "Can not allocate multicast setup array\n"); 1275 error = ENOMEM; 1276 goto err_late; 1277 } 1278 1279 /* Clear the IFCAP_TSO auto mask */ 1280 sc->tso_automasked = 0; 1281 1282 /* Check SOL/IDER usage */ 1283 if (e1000_check_reset_block(hw)) 1284 device_printf(dev, 1285 "PHY reset is blocked due to SOL/IDER session.\n"); 1286 1287 /* Sysctl for setting Energy Efficient Ethernet */ 1288 if (hw->mac.type < igb_mac_min) 1289 hw->dev_spec.ich8lan.eee_disable = eee_setting; 1290 else 1291 hw->dev_spec._82575.eee_disable = eee_setting; 1292 SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control", 1293 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 1294 em_sysctl_eee, "I", "Disable Energy Efficient Ethernet"); 1295 1296 /* 1297 ** Start from a known state, this is 1298 ** important in reading the nvm and 1299 ** mac from that. 1300 */ 1301 e1000_reset_hw(hw); 1302 1303 /* Make sure we have a good EEPROM before we read from it */ 1304 if (e1000_validate_nvm_checksum(hw) < 0) { 1305 /* 1306 ** Some PCI-E parts fail the first check due to 1307 ** the link being in sleep state, call it again, 1308 ** if it fails a second time its a real issue. 1309 */ 1310 if (e1000_validate_nvm_checksum(hw) < 0) { 1311 device_printf(dev, 1312 "The EEPROM Checksum Is Not Valid\n"); 1313 error = EIO; 1314 goto err_late; 1315 } 1316 } 1317 1318 /* Copy the permanent MAC address out of the EEPROM */ 1319 if (e1000_read_mac_addr(hw) < 0) { 1320 device_printf(dev, 1321 "EEPROM read error while reading MAC address\n"); 1322 error = EIO; 1323 goto err_late; 1324 } 1325 1326 if (!em_is_valid_ether_addr(hw->mac.addr)) { 1327 if (sc->vf_ifp) { 1328 ether_gen_addr(iflib_get_ifp(ctx), 1329 (struct ether_addr *)hw->mac.addr); 1330 } else { 1331 device_printf(dev, "Invalid MAC address\n"); 1332 error = EIO; 1333 goto err_late; 1334 } 1335 } 1336 1337 /* Save the EEPROM/NVM versions, must be done under IFLIB_CTX_LOCK */ 1338 em_fw_version_locked(ctx); 1339 1340 em_print_fw_version(sc); 1341 1342 /* 1343 * Get Wake-on-Lan and Management info for later use 1344 */ 1345 em_get_wakeup(ctx); 1346 1347 /* Enable only WOL MAGIC by default */ 1348 scctx->isc_capenable &= ~IFCAP_WOL; 1349 if (sc->wol != 0) 1350 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 1351 1352 iflib_set_mac(ctx, hw->mac.addr); 1353 1354 return (0); 1355 1356 err_late: 1357 em_release_hw_control(sc); 1358 err_pci: 1359 em_free_pci_resources(ctx); 1360 free(sc->mta, M_DEVBUF); 1361 1362 return (error); 1363 } 1364 1365 static int 1366 em_if_attach_post(if_ctx_t ctx) 1367 { 1368 struct e1000_softc *sc = iflib_get_softc(ctx); 1369 struct e1000_hw *hw = &sc->hw; 1370 int error = 0; 1371 1372 /* Setup OS specific network interface */ 1373 error = em_setup_interface(ctx); 1374 if (error != 0) { 1375 device_printf(sc->dev, "Interface setup failed: %d\n", error); 1376 goto err_late; 1377 } 1378 1379 em_reset(ctx); 1380 1381 /* Initialize statistics */ 1382 if (sc->vf_ifp) 1383 sc->ustats.vf_stats = (struct e1000_vf_stats){}; 1384 else 1385 sc->ustats.stats = (struct e1000_hw_stats){}; 1386 1387 em_update_stats_counters(sc); 1388 hw->mac.get_link_status = 1; 1389 em_if_update_admin_status(ctx); 1390 em_add_hw_stats(sc); 1391 1392 /* Non-AMT based hardware can now take control from firmware */ 1393 if (sc->has_manage && !sc->has_amt) 1394 em_get_hw_control(sc); 1395 1396 INIT_DEBUGOUT("em_if_attach_post: end"); 1397 1398 return (0); 1399 1400 err_late: 1401 /* 1402 * Upon em_if_attach_post() error, iflib calls em_if_detach() to 1403 * free resources 1404 */ 1405 return (error); 1406 } 1407 1408 /********************************************************************* 1409 * Device removal routine 1410 * 1411 * The detach entry point is called when the driver is being removed. 1412 * This routine stops the adapter and deallocates all the resources 1413 * that were allocated for driver operation. 1414 * 1415 * return 0 on success, positive on failure 1416 *********************************************************************/ 1417 static int 1418 em_if_detach(if_ctx_t ctx) 1419 { 1420 struct e1000_softc *sc = iflib_get_softc(ctx); 1421 1422 INIT_DEBUGOUT("em_if_detach: begin"); 1423 1424 e1000_phy_hw_reset(&sc->hw); 1425 1426 em_release_manageability(sc); 1427 em_release_hw_control(sc); 1428 em_free_pci_resources(ctx); 1429 free(sc->mta, M_DEVBUF); 1430 sc->mta = NULL; 1431 1432 return (0); 1433 } 1434 1435 /********************************************************************* 1436 * 1437 * Shutdown entry point 1438 * 1439 **********************************************************************/ 1440 1441 static int 1442 em_if_shutdown(if_ctx_t ctx) 1443 { 1444 return em_if_suspend(ctx); 1445 } 1446 1447 /* 1448 * Suspend/resume device methods. 1449 */ 1450 static int 1451 em_if_suspend(if_ctx_t ctx) 1452 { 1453 struct e1000_softc *sc = iflib_get_softc(ctx); 1454 1455 em_release_manageability(sc); 1456 em_release_hw_control(sc); 1457 em_enable_wakeup(ctx); 1458 return (0); 1459 } 1460 1461 static int 1462 em_if_resume(if_ctx_t ctx) 1463 { 1464 struct e1000_softc *sc = iflib_get_softc(ctx); 1465 1466 if (sc->hw.mac.type == e1000_pch2lan) 1467 e1000_resume_workarounds_pchlan(&sc->hw); 1468 em_if_init(ctx); 1469 em_init_manageability(sc); 1470 1471 return(0); 1472 } 1473 1474 static int 1475 em_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 1476 { 1477 int max_frame_size; 1478 struct e1000_softc *sc = iflib_get_softc(ctx); 1479 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 1480 1481 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1482 1483 switch (sc->hw.mac.type) { 1484 case e1000_82571: 1485 case e1000_82572: 1486 case e1000_ich9lan: 1487 case e1000_ich10lan: 1488 case e1000_pch2lan: 1489 case e1000_pch_lpt: 1490 case e1000_pch_spt: 1491 case e1000_pch_cnp: 1492 case e1000_pch_tgp: 1493 case e1000_pch_adp: 1494 case e1000_pch_mtp: 1495 case e1000_pch_ptp: 1496 case e1000_82574: 1497 case e1000_82583: 1498 case e1000_80003es2lan: 1499 /* 9K Jumbo Frame size */ 1500 max_frame_size = 9234; 1501 break; 1502 case e1000_pchlan: 1503 max_frame_size = 4096; 1504 break; 1505 case e1000_82542: 1506 case e1000_ich8lan: 1507 /* Adapters that do not support jumbo frames */ 1508 max_frame_size = ETHER_MAX_LEN; 1509 break; 1510 default: 1511 if (sc->hw.mac.type >= igb_mac_min) 1512 max_frame_size = 9234; 1513 else /* lem */ 1514 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1515 } 1516 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 1517 return (EINVAL); 1518 } 1519 1520 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 1521 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1522 return (0); 1523 } 1524 1525 /********************************************************************* 1526 * Init entry point 1527 * 1528 * This routine is used in two ways. It is used by the stack as 1529 * init entry point in network interface structure. It is also used 1530 * by the driver as a hw/sw initialization routine to get to a 1531 * consistent state. 1532 * 1533 **********************************************************************/ 1534 static void 1535 em_if_init(if_ctx_t ctx) 1536 { 1537 struct e1000_softc *sc = iflib_get_softc(ctx); 1538 if_softc_ctx_t scctx = sc->shared; 1539 if_t ifp = iflib_get_ifp(ctx); 1540 struct em_tx_queue *tx_que; 1541 int i; 1542 1543 INIT_DEBUGOUT("em_if_init: begin"); 1544 1545 /* Get the latest mac address, User can use a LAA */ 1546 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 1547 1548 /* Put the address into the Receive Address Array */ 1549 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0); 1550 1551 /* 1552 * With the 82571 adapter, RAR[0] may be overwritten 1553 * when the other port is reset, we make a duplicate 1554 * in RAR[14] for that eventuality, this assures 1555 * the interface continues to function. 1556 */ 1557 if (sc->hw.mac.type == e1000_82571) { 1558 e1000_set_laa_state_82571(&sc->hw, true); 1559 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 1560 E1000_RAR_ENTRIES - 1); 1561 } 1562 1563 /* Initialize the hardware */ 1564 em_reset(ctx); 1565 em_if_update_admin_status(ctx); 1566 1567 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; 1568 i++, tx_que++) { 1569 struct tx_ring *txr = &tx_que->txr; 1570 1571 txr->tx_rs_cidx = txr->tx_rs_pidx; 1572 1573 /* Initialize the last processed descriptor to be the end of 1574 * the ring, rather than the start, so that we avoid an 1575 * off-by-one error when calculating how many descriptors are 1576 * done in the credits_update function. 1577 */ 1578 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 1579 } 1580 1581 /* Setup VLAN support, basic and offload if available */ 1582 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN); 1583 1584 /* Clear bad data from Rx FIFOs */ 1585 if (sc->hw.mac.type >= igb_mac_min && !sc->vf_ifp) 1586 e1000_rx_fifo_flush_base(&sc->hw); 1587 1588 /* Configure for OS presence */ 1589 em_init_manageability(sc); 1590 1591 /* Prepare transmit descriptors and buffers */ 1592 em_initialize_transmit_unit(ctx); 1593 1594 /* Setup Multicast table */ 1595 em_if_multi_set(ctx); 1596 1597 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 1598 em_initialize_receive_unit(ctx); 1599 1600 /* Set up VLAN support and filter */ 1601 em_setup_vlan_hw_support(ctx); 1602 1603 /* Don't lose promiscuous settings */ 1604 em_if_set_promisc(ctx, if_getflags(ifp)); 1605 1606 if (sc->hw.mac.ops.clear_hw_cntrs != NULL) 1607 sc->hw.mac.ops.clear_hw_cntrs(&sc->hw); 1608 1609 /* MSI-X configuration for 82574 */ 1610 if (sc->hw.mac.type == e1000_82574) { 1611 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 1612 1613 tmp |= E1000_CTRL_EXT_PBA_CLR; 1614 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp); 1615 /* Set the IVAR - interrupt vector routing. */ 1616 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars); 1617 } else if (sc->intr_type == IFLIB_INTR_MSIX) { 1618 /* Set up queue routing */ 1619 igb_configure_queues(sc); 1620 } 1621 1622 /* this clears any pending interrupts */ 1623 E1000_READ_REG(&sc->hw, E1000_ICR); 1624 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC); 1625 1626 /* AMT based hardware can now take control from firmware */ 1627 if (sc->has_manage && sc->has_amt) 1628 em_get_hw_control(sc); 1629 1630 /* Set Energy Efficient Ethernet */ 1631 if (sc->hw.mac.type >= igb_mac_min && 1632 sc->hw.phy.media_type == e1000_media_type_copper) { 1633 if (sc->hw.mac.type == e1000_i354) 1634 e1000_set_eee_i354(&sc->hw, true, true); 1635 else 1636 e1000_set_eee_i350(&sc->hw, true, true); 1637 } 1638 } 1639 1640 enum itr_latency_target { 1641 itr_latency_disabled = 0, 1642 itr_latency_lowest = 1, 1643 itr_latency_low = 2, 1644 itr_latency_bulk = 3 1645 }; 1646 /********************************************************************* 1647 * 1648 * Helper to calculate next (E)ITR value for AIM 1649 * 1650 *********************************************************************/ 1651 static void 1652 em_newitr(struct e1000_softc *sc, struct em_rx_queue *que, 1653 struct tx_ring *txr, struct rx_ring *rxr) 1654 { 1655 struct e1000_hw *hw = &sc->hw; 1656 unsigned long bytes, bytes_per_packet, packets; 1657 unsigned long rxbytes, rxpackets, txbytes, txpackets; 1658 u32 newitr; 1659 u8 nextlatency; 1660 1661 rxbytes = atomic_load_long(&rxr->rx_bytes); 1662 txbytes = atomic_load_long(&txr->tx_bytes); 1663 1664 /* Idle, do nothing */ 1665 if (txbytes == 0 && rxbytes == 0) 1666 return; 1667 1668 newitr = 0; 1669 1670 if (sc->enable_aim) { 1671 nextlatency = rxr->rx_nextlatency; 1672 1673 /* Use half default (4K) ITR if sub-gig */ 1674 if (sc->link_speed != 1000) { 1675 newitr = EM_INTS_4K; 1676 goto em_set_next_itr; 1677 } 1678 /* Want at least enough packet buffer for two frames to AIM */ 1679 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1680 newitr = em_max_interrupt_rate; 1681 sc->enable_aim = 0; 1682 goto em_set_next_itr; 1683 } 1684 1685 bytes = bytes_per_packet = 0; 1686 /* Get largest values from the associated tx and rx ring */ 1687 txpackets = atomic_load_long(&txr->tx_packets); 1688 if (txpackets != 0) { 1689 bytes = txbytes; 1690 bytes_per_packet = txbytes / txpackets; 1691 packets = txpackets; 1692 } 1693 rxpackets = atomic_load_long(&rxr->rx_packets); 1694 if (rxpackets != 0) { 1695 bytes = lmax(bytes, rxbytes); 1696 bytes_per_packet = 1697 lmax(bytes_per_packet, rxbytes / rxpackets); 1698 packets = lmax(packets, rxpackets); 1699 } 1700 1701 /* Latency state machine */ 1702 switch (nextlatency) { 1703 case itr_latency_disabled: /* Bootstrapping */ 1704 nextlatency = itr_latency_low; 1705 break; 1706 case itr_latency_lowest: /* 70k ints/s */ 1707 /* TSO and jumbo frames */ 1708 if (bytes_per_packet > 8000) 1709 nextlatency = itr_latency_bulk; 1710 else if ((packets < 5) && (bytes > 512)) 1711 nextlatency = itr_latency_low; 1712 break; 1713 case itr_latency_low: /* 20k ints/s */ 1714 if (bytes > 10000) { 1715 /* Handle TSO */ 1716 if (bytes_per_packet > 8000) 1717 nextlatency = itr_latency_bulk; 1718 else if ((packets < 10) || 1719 (bytes_per_packet > 1200)) 1720 nextlatency = itr_latency_bulk; 1721 else if (packets > 35) 1722 nextlatency = itr_latency_lowest; 1723 } else if (bytes_per_packet > 2000) { 1724 nextlatency = itr_latency_bulk; 1725 } else if (packets < 3 && bytes < 512) { 1726 nextlatency = itr_latency_lowest; 1727 } 1728 break; 1729 case itr_latency_bulk: /* 4k ints/s */ 1730 if (bytes > 25000) { 1731 if (packets > 35) 1732 nextlatency = itr_latency_low; 1733 } else if (bytes < 1500) 1734 nextlatency = itr_latency_low; 1735 break; 1736 default: 1737 nextlatency = itr_latency_low; 1738 device_printf(sc->dev, 1739 "Unexpected newitr transition %d\n", nextlatency); 1740 break; 1741 } 1742 1743 /* Trim itr_latency_lowest for default AIM setting */ 1744 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest) 1745 nextlatency = itr_latency_low; 1746 1747 /* Request new latency */ 1748 rxr->rx_nextlatency = nextlatency; 1749 } else { 1750 /* We may have toggled to AIM disabled */ 1751 nextlatency = itr_latency_disabled; 1752 rxr->rx_nextlatency = nextlatency; 1753 } 1754 1755 /* ITR state machine */ 1756 switch(nextlatency) { 1757 case itr_latency_lowest: 1758 newitr = EM_INTS_70K; 1759 break; 1760 case itr_latency_low: 1761 newitr = EM_INTS_20K; 1762 break; 1763 case itr_latency_bulk: 1764 newitr = EM_INTS_4K; 1765 break; 1766 case itr_latency_disabled: 1767 default: 1768 newitr = em_max_interrupt_rate; 1769 break; 1770 } 1771 1772 em_set_next_itr: 1773 if (hw->mac.type >= igb_mac_min) { 1774 newitr = IGB_INTS_TO_EITR(newitr); 1775 1776 if (hw->mac.type == e1000_82575) 1777 newitr |= newitr << 16; 1778 else 1779 newitr |= E1000_EITR_CNT_IGNR; 1780 1781 if (newitr != que->itr_setting) { 1782 que->itr_setting = newitr; 1783 E1000_WRITE_REG(hw, E1000_EITR(que->msix), 1784 que->itr_setting); 1785 } 1786 } else { 1787 newitr = EM_INTS_TO_ITR(newitr); 1788 1789 if (newitr != que->itr_setting) { 1790 que->itr_setting = newitr; 1791 if (hw->mac.type == e1000_82574 && que->msix) { 1792 E1000_WRITE_REG(hw, 1793 E1000_EITR_82574(que->msix), 1794 que->itr_setting); 1795 } else { 1796 E1000_WRITE_REG(hw, E1000_ITR, 1797 que->itr_setting); 1798 } 1799 } 1800 } 1801 } 1802 1803 /********************************************************************* 1804 * 1805 * Fast Legacy/MSI Combined Interrupt Service routine 1806 * 1807 *********************************************************************/ 1808 int 1809 em_intr(void *arg) 1810 { 1811 struct e1000_softc *sc = arg; 1812 struct e1000_hw *hw = &sc->hw; 1813 struct em_rx_queue *que = &sc->rx_queues[0]; 1814 struct tx_ring *txr = &sc->tx_queues[0].txr; 1815 struct rx_ring *rxr = &que->rxr; 1816 if_ctx_t ctx = sc->ctx; 1817 u32 reg_icr; 1818 1819 reg_icr = E1000_READ_REG(hw, E1000_ICR); 1820 1821 /* Hot eject? */ 1822 if (reg_icr == 0xffffffff) 1823 return FILTER_STRAY; 1824 1825 /* Definitely not our interrupt. */ 1826 if (reg_icr == 0x0) 1827 return FILTER_STRAY; 1828 1829 /* 1830 * Starting with the 82571 chip, bit 31 should be used to 1831 * determine whether the interrupt belongs to us. 1832 */ 1833 if (hw->mac.type >= e1000_82571 && 1834 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1835 return FILTER_STRAY; 1836 1837 /* 1838 * Only MSI-X interrupts have one-shot behavior by taking advantage 1839 * of the EIAC register. Thus, explicitly disable interrupts. This 1840 * also works around the MSI message reordering errata on certain 1841 * systems. 1842 */ 1843 IFDI_INTR_DISABLE(ctx); 1844 1845 /* Link status change */ 1846 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1847 em_handle_link(ctx); 1848 1849 if (reg_icr & E1000_ICR_RXO) 1850 sc->rx_overruns++; 1851 1852 if (hw->mac.type >= e1000_82540) 1853 em_newitr(sc, que, txr, rxr); 1854 1855 /* Reset state */ 1856 txr->tx_bytes = 0; 1857 txr->tx_packets = 0; 1858 rxr->rx_bytes = 0; 1859 rxr->rx_packets = 0; 1860 1861 return (FILTER_SCHEDULE_THREAD); 1862 } 1863 1864 static int 1865 em_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1866 { 1867 struct e1000_softc *sc = iflib_get_softc(ctx); 1868 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1869 1870 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims); 1871 return (0); 1872 } 1873 1874 static int 1875 em_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1876 { 1877 struct e1000_softc *sc = iflib_get_softc(ctx); 1878 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1879 1880 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims); 1881 return (0); 1882 } 1883 1884 static int 1885 igb_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1886 { 1887 struct e1000_softc *sc = iflib_get_softc(ctx); 1888 struct em_rx_queue *rxq = &sc->rx_queues[rxqid]; 1889 1890 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims); 1891 return (0); 1892 } 1893 1894 static int 1895 igb_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1896 { 1897 struct e1000_softc *sc = iflib_get_softc(ctx); 1898 struct em_tx_queue *txq = &sc->tx_queues[txqid]; 1899 1900 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims); 1901 return (0); 1902 } 1903 1904 /********************************************************************* 1905 * 1906 * MSI-X RX Interrupt Service routine 1907 * 1908 **********************************************************************/ 1909 static int 1910 em_msix_que(void *arg) 1911 { 1912 struct em_rx_queue *que = arg; 1913 struct e1000_softc *sc = que->sc; 1914 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; 1915 struct rx_ring *rxr = &que->rxr; 1916 1917 ++que->irqs; 1918 1919 em_newitr(sc, que, txr, rxr); 1920 1921 /* Reset state */ 1922 txr->tx_bytes = 0; 1923 txr->tx_packets = 0; 1924 rxr->rx_bytes = 0; 1925 rxr->rx_packets = 0; 1926 1927 return (FILTER_SCHEDULE_THREAD); 1928 } 1929 1930 /********************************************************************* 1931 * 1932 * MSI-X Link Fast Interrupt Service routine 1933 * 1934 **********************************************************************/ 1935 static int 1936 em_msix_link(void *arg) 1937 { 1938 struct e1000_softc *sc = arg; 1939 u32 reg_icr; 1940 1941 ++sc->link_irq; 1942 MPASS(sc->hw.back != NULL); 1943 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR); 1944 1945 if (reg_icr & E1000_ICR_RXO) 1946 sc->rx_overruns++; 1947 1948 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1949 em_handle_link(sc->ctx); 1950 1951 /* Re-arm unconditionally */ 1952 if (sc->hw.mac.type >= igb_mac_min) { 1953 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1954 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask); 1955 } else if (sc->hw.mac.type == e1000_82574) { 1956 E1000_WRITE_REG(&sc->hw, E1000_IMS, 1957 E1000_IMS_LSC | E1000_IMS_OTHER); 1958 /* 1959 * Because we must read the ICR for this interrupt it may 1960 * clear other causes using autoclear, for this reason we 1961 * simply create a soft interrupt for all these vectors. 1962 */ 1963 if (reg_icr) 1964 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims); 1965 } else 1966 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC); 1967 1968 return (FILTER_HANDLED); 1969 } 1970 1971 static void 1972 em_handle_link(void *context) 1973 { 1974 if_ctx_t ctx = context; 1975 struct e1000_softc *sc = iflib_get_softc(ctx); 1976 1977 sc->hw.mac.get_link_status = 1; 1978 iflib_admin_intr_deferred(ctx); 1979 } 1980 1981 /********************************************************************* 1982 * 1983 * Media Ioctl callback 1984 * 1985 * This routine is called whenever the user queries the status of 1986 * the interface using ifconfig. 1987 * 1988 **********************************************************************/ 1989 static void 1990 em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1991 { 1992 struct e1000_softc *sc = iflib_get_softc(ctx); 1993 u_char fiber_type = IFM_1000_SX; 1994 1995 INIT_DEBUGOUT("em_if_media_status: begin"); 1996 1997 iflib_admin_intr_deferred(ctx); 1998 1999 ifmr->ifm_status = IFM_AVALID; 2000 ifmr->ifm_active = IFM_ETHER; 2001 2002 if (!sc->link_active) { 2003 return; 2004 } 2005 2006 ifmr->ifm_status |= IFM_ACTIVE; 2007 2008 if ((sc->hw.phy.media_type == e1000_media_type_fiber) || 2009 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2010 if (sc->hw.mac.type == e1000_82545) 2011 fiber_type = IFM_1000_LX; 2012 ifmr->ifm_active |= fiber_type | IFM_FDX; 2013 } else { 2014 switch (sc->link_speed) { 2015 case 10: 2016 ifmr->ifm_active |= IFM_10_T; 2017 break; 2018 case 100: 2019 ifmr->ifm_active |= IFM_100_TX; 2020 break; 2021 case 1000: 2022 ifmr->ifm_active |= IFM_1000_T; 2023 break; 2024 } 2025 if (sc->link_duplex == FULL_DUPLEX) 2026 ifmr->ifm_active |= IFM_FDX; 2027 else 2028 ifmr->ifm_active |= IFM_HDX; 2029 } 2030 } 2031 2032 /********************************************************************* 2033 * 2034 * Media Ioctl callback 2035 * 2036 * This routine is called when the user changes speed/duplex using 2037 * media/mediopt option with ifconfig. 2038 * 2039 **********************************************************************/ 2040 static int 2041 em_if_media_change(if_ctx_t ctx) 2042 { 2043 struct e1000_softc *sc = iflib_get_softc(ctx); 2044 struct ifmedia *ifm = iflib_get_media(ctx); 2045 2046 INIT_DEBUGOUT("em_if_media_change: begin"); 2047 2048 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2049 return (EINVAL); 2050 2051 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2052 case IFM_AUTO: 2053 sc->hw.mac.autoneg = DO_AUTO_NEG; 2054 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 2055 break; 2056 case IFM_1000_LX: 2057 case IFM_1000_SX: 2058 case IFM_1000_T: 2059 sc->hw.mac.autoneg = DO_AUTO_NEG; 2060 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 2061 break; 2062 case IFM_100_TX: 2063 sc->hw.mac.autoneg = false; 2064 sc->hw.phy.autoneg_advertised = 0; 2065 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2066 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 2067 else 2068 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 2069 break; 2070 case IFM_10_T: 2071 sc->hw.mac.autoneg = false; 2072 sc->hw.phy.autoneg_advertised = 0; 2073 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 2074 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 2075 else 2076 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 2077 break; 2078 default: 2079 device_printf(sc->dev, "Unsupported media type\n"); 2080 } 2081 2082 em_if_init(ctx); 2083 2084 return (0); 2085 } 2086 2087 static int 2088 em_if_set_promisc(if_ctx_t ctx, int flags) 2089 { 2090 struct e1000_softc *sc = iflib_get_softc(ctx); 2091 if_t ifp = iflib_get_ifp(ctx); 2092 u32 reg_rctl; 2093 int mcnt = 0; 2094 2095 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2096 reg_rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_UPE); 2097 if (flags & IFF_ALLMULTI) 2098 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 2099 else 2100 mcnt = min(if_llmaddr_count(ifp), 2101 MAX_NUM_MULTICAST_ADDRESSES); 2102 2103 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2104 reg_rctl &= (~E1000_RCTL_MPE); 2105 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2106 2107 if (flags & IFF_PROMISC) { 2108 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2109 em_if_vlan_filter_disable(sc); 2110 /* Turn this on if you want to see bad packets */ 2111 if (em_debug_sbp) 2112 reg_rctl |= E1000_RCTL_SBP; 2113 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2114 } else { 2115 if (flags & IFF_ALLMULTI) { 2116 reg_rctl |= E1000_RCTL_MPE; 2117 reg_rctl &= ~E1000_RCTL_UPE; 2118 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2119 } 2120 if (em_if_vlan_filter_used(ctx)) 2121 em_if_vlan_filter_enable(sc); 2122 } 2123 return (0); 2124 } 2125 2126 static u_int 2127 em_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 2128 { 2129 u8 *mta = arg; 2130 2131 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 2132 return (0); 2133 2134 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 2135 2136 return (1); 2137 } 2138 2139 /********************************************************************* 2140 * Multicast Update 2141 * 2142 * This routine is called whenever multicast address list is updated. 2143 * 2144 **********************************************************************/ 2145 static void 2146 em_if_multi_set(if_ctx_t ctx) 2147 { 2148 struct e1000_softc *sc = iflib_get_softc(ctx); 2149 if_t ifp = iflib_get_ifp(ctx); 2150 u8 *mta; /* Multicast array memory */ 2151 u32 reg_rctl = 0; 2152 int mcnt = 0; 2153 2154 IOCTL_DEBUGOUT("em_set_multi: begin"); 2155 2156 mta = sc->mta; 2157 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 2158 2159 if (sc->hw.mac.type == e1000_82542 && 2160 sc->hw.revision_id == E1000_REVISION_2) { 2161 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2162 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2163 e1000_pci_clear_mwi(&sc->hw); 2164 reg_rctl |= E1000_RCTL_RST; 2165 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2166 msec_delay(5); 2167 } 2168 2169 mcnt = if_foreach_llmaddr(ifp, em_copy_maddr, mta); 2170 2171 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2172 e1000_update_mc_addr_list(&sc->hw, mta, mcnt); 2173 2174 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2175 2176 if (if_getflags(ifp) & IFF_PROMISC) 2177 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2178 else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 2179 if_getflags(ifp) & IFF_ALLMULTI) { 2180 reg_rctl |= E1000_RCTL_MPE; 2181 reg_rctl &= ~E1000_RCTL_UPE; 2182 } else 2183 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); 2184 2185 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2186 2187 if (sc->hw.mac.type == e1000_82542 && 2188 sc->hw.revision_id == E1000_REVISION_2) { 2189 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 2190 reg_rctl &= ~E1000_RCTL_RST; 2191 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl); 2192 msec_delay(5); 2193 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2194 e1000_pci_set_mwi(&sc->hw); 2195 } 2196 } 2197 2198 /********************************************************************* 2199 * Timer routine 2200 * 2201 * This routine schedules em_if_update_admin_status() to check for 2202 * link status and to gather statistics as well as to perform some 2203 * controller-specific hardware patting. 2204 * 2205 **********************************************************************/ 2206 static void 2207 em_if_timer(if_ctx_t ctx, uint16_t qid) 2208 { 2209 if (qid != 0) 2210 return; 2211 2212 iflib_admin_intr_deferred(ctx); 2213 } 2214 2215 static void 2216 em_if_update_admin_status(if_ctx_t ctx) 2217 { 2218 struct e1000_softc *sc = iflib_get_softc(ctx); 2219 struct e1000_hw *hw = &sc->hw; 2220 device_t dev = iflib_get_dev(ctx); 2221 u32 link_check, thstat, ctrl; 2222 bool automasked = false; 2223 2224 link_check = thstat = ctrl = 0; 2225 /* Get the cached link value or read phy for real */ 2226 switch (hw->phy.media_type) { 2227 case e1000_media_type_copper: 2228 if (hw->mac.get_link_status) { 2229 if (hw->mac.type == e1000_pch_spt) 2230 msec_delay(50); 2231 /* Do the work to read phy */ 2232 e1000_check_for_link(hw); 2233 link_check = !hw->mac.get_link_status; 2234 if (link_check) /* ESB2 fix */ 2235 e1000_cfg_on_link_up(hw); 2236 } else { 2237 link_check = true; 2238 } 2239 break; 2240 case e1000_media_type_fiber: 2241 e1000_check_for_link(hw); 2242 link_check = 2243 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 2244 break; 2245 case e1000_media_type_internal_serdes: 2246 e1000_check_for_link(hw); 2247 link_check = hw->mac.serdes_has_link; 2248 break; 2249 /* VF device is type_unknown */ 2250 case e1000_media_type_unknown: 2251 e1000_check_for_link(hw); 2252 link_check = !hw->mac.get_link_status; 2253 /* FALLTHROUGH */ 2254 default: 2255 break; 2256 } 2257 2258 /* Check for thermal downshift or shutdown */ 2259 if (hw->mac.type == e1000_i350) { 2260 thstat = E1000_READ_REG(hw, E1000_THSTAT); 2261 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT); 2262 } 2263 2264 /* Now check for a transition */ 2265 if (link_check && (sc->link_active == 0)) { 2266 e1000_get_speed_and_duplex(hw, &sc->link_speed, 2267 &sc->link_duplex); 2268 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2269 if ((sc->link_speed != SPEED_1000) && 2270 ((hw->mac.type == e1000_82571) || 2271 (hw->mac.type == e1000_82572))) { 2272 int tarc0; 2273 tarc0 = E1000_READ_REG(hw, E1000_TARC(0)); 2274 tarc0 &= ~TARC_SPEED_MODE_BIT; 2275 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0); 2276 } 2277 if (bootverbose) 2278 device_printf(dev, "Link is up %d Mbps %s\n", 2279 sc->link_speed, 2280 ((sc->link_duplex == FULL_DUPLEX) ? 2281 "Full Duplex" : "Half Duplex")); 2282 sc->link_active = 1; 2283 sc->smartspeed = 0; 2284 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_MASK) == 2285 E1000_CTRL_EXT_LINK_MODE_GMII && 2286 (thstat & E1000_THSTAT_LINK_THROTTLE)) 2287 device_printf(dev, "Link: thermal downshift\n"); 2288 /* Delay Link Up for Phy update */ 2289 if (((hw->mac.type == e1000_i210) || 2290 (hw->mac.type == e1000_i211)) && 2291 (hw->phy.id == I210_I_PHY_ID)) 2292 msec_delay(I210_LINK_DELAY); 2293 /* Reset if the media type changed. */ 2294 if (hw->dev_spec._82575.media_changed && 2295 hw->mac.type >= igb_mac_min) { 2296 hw->dev_spec._82575.media_changed = false; 2297 sc->flags |= IGB_MEDIA_RESET; 2298 em_reset(ctx); 2299 } 2300 /* Only do TSO on gigabit for older chips due to errata */ 2301 if (hw->mac.type < igb_mac_min) 2302 automasked = em_automask_tso(ctx); 2303 2304 /* Automasking resets the interface so don't mark it up yet */ 2305 if (!automasked) 2306 iflib_link_state_change(ctx, LINK_STATE_UP, 2307 IF_Mbps(sc->link_speed)); 2308 } else if (!link_check && (sc->link_active == 1)) { 2309 sc->link_speed = 0; 2310 sc->link_duplex = 0; 2311 sc->link_active = 0; 2312 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 2313 } 2314 em_update_stats_counters(sc); 2315 2316 /* Reset LAA into RAR[0] on 82571 */ 2317 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw)) 2318 e1000_rar_set(hw, hw->mac.addr, 0); 2319 2320 if (hw->mac.type < em_mac_min) 2321 lem_smartspeed(sc); 2322 } 2323 2324 static void 2325 em_if_watchdog_reset(if_ctx_t ctx) 2326 { 2327 struct e1000_softc *sc = iflib_get_softc(ctx); 2328 2329 /* 2330 * Just count the event; iflib(4) will already trigger a 2331 * sufficient reset of the controller. 2332 */ 2333 sc->watchdog_events++; 2334 } 2335 2336 /********************************************************************* 2337 * 2338 * This routine disables all traffic on the adapter by issuing a 2339 * global reset on the MAC. 2340 * 2341 **********************************************************************/ 2342 static void 2343 em_if_stop(if_ctx_t ctx) 2344 { 2345 struct e1000_softc *sc = iflib_get_softc(ctx); 2346 2347 INIT_DEBUGOUT("em_if_stop: begin"); 2348 2349 /* I219 needs special flushing to avoid hangs */ 2350 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 2351 em_flush_desc_rings(sc); 2352 2353 e1000_reset_hw(&sc->hw); 2354 if (sc->hw.mac.type >= e1000_82544 && !sc->vf_ifp) 2355 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0); 2356 2357 e1000_led_off(&sc->hw); 2358 e1000_cleanup_led(&sc->hw); 2359 } 2360 2361 /********************************************************************* 2362 * 2363 * Determine hardware revision. 2364 * 2365 **********************************************************************/ 2366 static void 2367 em_identify_hardware(if_ctx_t ctx) 2368 { 2369 device_t dev = iflib_get_dev(ctx); 2370 struct e1000_softc *sc = iflib_get_softc(ctx); 2371 2372 /* Make sure our PCI config space has the necessary stuff set */ 2373 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2374 2375 /* Save off the information about this board */ 2376 sc->hw.vendor_id = pci_get_vendor(dev); 2377 sc->hw.device_id = pci_get_device(dev); 2378 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2379 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2380 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2381 2382 /* Do Shared Code Init and Setup */ 2383 if (e1000_set_mac_type(&sc->hw)) { 2384 device_printf(dev, "Setup init failure\n"); 2385 return; 2386 } 2387 2388 /* Are we a VF device? */ 2389 if ((sc->hw.mac.type == e1000_vfadapt) || 2390 (sc->hw.mac.type == e1000_vfadapt_i350)) 2391 sc->vf_ifp = 1; 2392 else 2393 sc->vf_ifp = 0; 2394 } 2395 2396 static int 2397 em_allocate_pci_resources(if_ctx_t ctx) 2398 { 2399 struct e1000_softc *sc = iflib_get_softc(ctx); 2400 device_t dev = iflib_get_dev(ctx); 2401 int rid, val; 2402 2403 rid = PCIR_BAR(0); 2404 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2405 RF_ACTIVE); 2406 if (sc->memory == NULL) { 2407 device_printf(dev, 2408 "Unable to allocate bus resource: memory\n"); 2409 return (ENXIO); 2410 } 2411 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 2412 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory); 2413 #ifdef INVARIANTS 2414 sc->osdep.mem_bus_space_size = rman_get_size(sc->memory); 2415 #endif 2416 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 2417 2418 /* Only older adapters use IO mapping */ 2419 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) { 2420 /* Figure our where our IO BAR is ? */ 2421 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2422 val = pci_read_config(dev, rid, 4); 2423 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2424 break; 2425 } 2426 rid += 4; 2427 /* check for 64bit BAR */ 2428 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2429 rid += 4; 2430 } 2431 if (rid >= PCIR_CIS) { 2432 device_printf(dev, "Unable to locate IO BAR\n"); 2433 return (ENXIO); 2434 } 2435 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 2436 &rid, RF_ACTIVE); 2437 if (sc->ioport == NULL) { 2438 device_printf(dev, 2439 "Unable to allocate bus resource: ioport\n"); 2440 return (ENXIO); 2441 } 2442 sc->hw.io_base = 0; 2443 sc->osdep.io_bus_space_tag = 2444 rman_get_bustag(sc->ioport); 2445 sc->osdep.io_bus_space_handle = 2446 rman_get_bushandle(sc->ioport); 2447 } 2448 2449 sc->hw.back = &sc->osdep; 2450 2451 return (0); 2452 } 2453 2454 /********************************************************************* 2455 * 2456 * Set up the MSI-X Interrupt handlers 2457 * 2458 **********************************************************************/ 2459 static int 2460 em_if_msix_intr_assign(if_ctx_t ctx, int msix) 2461 { 2462 struct e1000_softc *sc = iflib_get_softc(ctx); 2463 struct em_rx_queue *rx_que = sc->rx_queues; 2464 struct em_tx_queue *tx_que = sc->tx_queues; 2465 int error, rid, i, vector = 0, rx_vectors; 2466 char buf[16]; 2467 2468 /* First set up ring resources */ 2469 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 2470 rid = vector + 1; 2471 snprintf(buf, sizeof(buf), "rxq%d", i); 2472 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 2473 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf); 2474 if (error) { 2475 device_printf(iflib_get_dev(ctx), 2476 "Failed to allocate que int %d err: %d", 2477 i, error); 2478 sc->rx_num_queues = i + 1; 2479 goto fail; 2480 } 2481 2482 rx_que->msix = vector; 2483 2484 /* 2485 * Set the bit to enable interrupt 2486 * in E1000_IMS -- bits 20 and 21 2487 * are for RX0 and RX1, note this has 2488 * NOTHING to do with the MSI-X vector 2489 */ 2490 if (sc->hw.mac.type == e1000_82574) { 2491 rx_que->eims = 1 << (20 + i); 2492 sc->ims |= rx_que->eims; 2493 sc->ivars |= (8 | rx_que->msix) << (i * 4); 2494 } else if (sc->hw.mac.type == e1000_82575) 2495 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector; 2496 else 2497 rx_que->eims = 1 << vector; 2498 } 2499 rx_vectors = vector; 2500 2501 vector = 0; 2502 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 2503 snprintf(buf, sizeof(buf), "txq%d", i); 2504 tx_que = &sc->tx_queues[i]; 2505 iflib_softirq_alloc_generic(ctx, 2506 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 2507 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 2508 2509 tx_que->msix = (vector % sc->rx_num_queues); 2510 2511 /* 2512 * Set the bit to enable interrupt 2513 * in E1000_IMS -- bits 22 and 23 2514 * are for TX0 and TX1, note this has 2515 * NOTHING to do with the MSI-X vector 2516 */ 2517 if (sc->hw.mac.type == e1000_82574) { 2518 tx_que->eims = 1 << (22 + i); 2519 sc->ims |= tx_que->eims; 2520 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); 2521 } else if (sc->hw.mac.type == e1000_82575) { 2522 tx_que->eims = E1000_EICR_TX_QUEUE0 << i; 2523 } else { 2524 tx_que->eims = 1 << i; 2525 } 2526 } 2527 2528 /* Link interrupt */ 2529 rid = rx_vectors + 1; 2530 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, 2531 em_msix_link, sc, 0, "aq"); 2532 2533 if (error) { 2534 device_printf(iflib_get_dev(ctx), 2535 "Failed to register admin handler"); 2536 goto fail; 2537 } 2538 sc->linkvec = rx_vectors; 2539 if (sc->hw.mac.type < igb_mac_min) { 2540 sc->ivars |= (8 | rx_vectors) << 16; 2541 sc->ivars |= 0x80000000; 2542 /* Enable the "Other" interrupt type for link status change */ 2543 sc->ims |= E1000_IMS_OTHER; 2544 } 2545 2546 return (0); 2547 fail: 2548 iflib_irq_free(ctx, &sc->irq); 2549 rx_que = sc->rx_queues; 2550 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 2551 iflib_irq_free(ctx, &rx_que->que_irq); 2552 return (error); 2553 } 2554 2555 static void 2556 igb_configure_queues(struct e1000_softc *sc) 2557 { 2558 struct e1000_hw *hw = &sc->hw; 2559 struct em_rx_queue *rx_que; 2560 struct em_tx_queue *tx_que; 2561 u32 tmp, ivar = 0, newitr = 0; 2562 2563 /* First turn on RSS capability */ 2564 if (hw->mac.type != e1000_82575) 2565 E1000_WRITE_REG(hw, E1000_GPIE, 2566 E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME | 2567 E1000_GPIE_PBA | E1000_GPIE_NSICR); 2568 2569 /* Turn on MSI-X */ 2570 switch (hw->mac.type) { 2571 case e1000_82580: 2572 case e1000_i350: 2573 case e1000_i354: 2574 case e1000_i210: 2575 case e1000_i211: 2576 case e1000_vfadapt: 2577 case e1000_vfadapt_i350: 2578 /* RX entries */ 2579 for (int i = 0; i < sc->rx_num_queues; i++) { 2580 u32 index = i >> 1; 2581 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2582 rx_que = &sc->rx_queues[i]; 2583 if (i & 1) { 2584 ivar &= 0xFF00FFFF; 2585 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2586 16; 2587 } else { 2588 ivar &= 0xFFFFFF00; 2589 ivar |= rx_que->msix | E1000_IVAR_VALID; 2590 } 2591 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2592 } 2593 /* TX entries */ 2594 for (int i = 0; i < sc->tx_num_queues; i++) { 2595 u32 index = i >> 1; 2596 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2597 tx_que = &sc->tx_queues[i]; 2598 if (i & 1) { 2599 ivar &= 0x00FFFFFF; 2600 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2601 24; 2602 } else { 2603 ivar &= 0xFFFF00FF; 2604 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2605 8; 2606 } 2607 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2608 sc->que_mask |= tx_que->eims; 2609 } 2610 2611 /* And for the link interrupt */ 2612 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2613 sc->link_mask = 1 << sc->linkvec; 2614 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2615 break; 2616 case e1000_82576: 2617 /* RX entries */ 2618 for (int i = 0; i < sc->rx_num_queues; i++) { 2619 u32 index = i & 0x7; /* Each IVAR has two entries */ 2620 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2621 rx_que = &sc->rx_queues[i]; 2622 if (i < 8) { 2623 ivar &= 0xFFFFFF00; 2624 ivar |= rx_que->msix | E1000_IVAR_VALID; 2625 } else { 2626 ivar &= 0xFF00FFFF; 2627 ivar |= (rx_que->msix | E1000_IVAR_VALID) << 2628 16; 2629 } 2630 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2631 sc->que_mask |= rx_que->eims; 2632 } 2633 /* TX entries */ 2634 for (int i = 0; i < sc->tx_num_queues; i++) { 2635 u32 index = i & 0x7; /* Each IVAR has two entries */ 2636 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 2637 tx_que = &sc->tx_queues[i]; 2638 if (i < 8) { 2639 ivar &= 0xFFFF00FF; 2640 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2641 8; 2642 } else { 2643 ivar &= 0x00FFFFFF; 2644 ivar |= (tx_que->msix | E1000_IVAR_VALID) << 2645 24; 2646 } 2647 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 2648 sc->que_mask |= tx_que->eims; 2649 } 2650 2651 /* And for the link interrupt */ 2652 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8; 2653 sc->link_mask = 1 << sc->linkvec; 2654 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 2655 break; 2656 2657 case e1000_82575: 2658 /* enable MSI-X support*/ 2659 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT); 2660 tmp |= E1000_CTRL_EXT_PBA_CLR; 2661 /* Auto-Mask interrupts upon ICR read. */ 2662 tmp |= E1000_CTRL_EXT_EIAME; 2663 tmp |= E1000_CTRL_EXT_IRCA; 2664 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp); 2665 2666 /* Queues */ 2667 for (int i = 0; i < sc->rx_num_queues; i++) { 2668 rx_que = &sc->rx_queues[i]; 2669 tmp = E1000_EICR_RX_QUEUE0 << i; 2670 tmp |= E1000_EICR_TX_QUEUE0 << i; 2671 rx_que->eims = tmp; 2672 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i, 2673 rx_que->eims); 2674 sc->que_mask |= rx_que->eims; 2675 } 2676 2677 /* Link */ 2678 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec), 2679 E1000_EIMS_OTHER); 2680 sc->link_mask |= E1000_EIMS_OTHER; 2681 default: 2682 break; 2683 } 2684 2685 /* Set the igb starting interrupt rate */ 2686 if (em_max_interrupt_rate > 0) { 2687 newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate); 2688 2689 if (hw->mac.type == e1000_82575) 2690 newitr |= newitr << 16; 2691 else 2692 newitr |= E1000_EITR_CNT_IGNR; 2693 2694 for (int i = 0; i < sc->rx_num_queues; i++) { 2695 rx_que = &sc->rx_queues[i]; 2696 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr); 2697 } 2698 } 2699 2700 return; 2701 } 2702 2703 static void 2704 em_free_pci_resources(if_ctx_t ctx) 2705 { 2706 struct e1000_softc *sc = iflib_get_softc(ctx); 2707 struct em_rx_queue *que = sc->rx_queues; 2708 device_t dev = iflib_get_dev(ctx); 2709 2710 /* Release all MSI-X queue resources */ 2711 if (sc->intr_type == IFLIB_INTR_MSIX) 2712 iflib_irq_free(ctx, &sc->irq); 2713 2714 if (que != NULL) { 2715 for (int i = 0; i < sc->rx_num_queues; i++, que++) { 2716 iflib_irq_free(ctx, &que->que_irq); 2717 } 2718 } 2719 2720 if (sc->memory != NULL) { 2721 bus_release_resource(dev, SYS_RES_MEMORY, 2722 rman_get_rid(sc->memory), sc->memory); 2723 sc->memory = NULL; 2724 } 2725 2726 if (sc->flash != NULL) { 2727 bus_release_resource(dev, SYS_RES_MEMORY, 2728 rman_get_rid(sc->flash), sc->flash); 2729 sc->flash = NULL; 2730 } 2731 2732 if (sc->ioport != NULL) { 2733 bus_release_resource(dev, SYS_RES_IOPORT, 2734 rman_get_rid(sc->ioport), sc->ioport); 2735 sc->ioport = NULL; 2736 } 2737 } 2738 2739 /* Set up MSI or MSI-X */ 2740 static int 2741 em_setup_msix(if_ctx_t ctx) 2742 { 2743 struct e1000_softc *sc = iflib_get_softc(ctx); 2744 2745 if (sc->hw.mac.type == e1000_82574) { 2746 em_enable_vectors_82574(ctx); 2747 } 2748 return (0); 2749 } 2750 2751 /********************************************************************* 2752 * 2753 * Workaround for SmartSpeed on 82541 and 82547 controllers 2754 * 2755 **********************************************************************/ 2756 static void 2757 lem_smartspeed(struct e1000_softc *sc) 2758 { 2759 u16 phy_tmp; 2760 2761 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) || 2762 sc->hw.mac.autoneg == 0 || 2763 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2764 return; 2765 2766 if (sc->smartspeed == 0) { 2767 /* If Master/Slave config fault is asserted twice, 2768 * we assume back-to-back */ 2769 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2770 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2771 return; 2772 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp); 2773 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2774 e1000_read_phy_reg(&sc->hw, 2775 PHY_1000T_CTRL, &phy_tmp); 2776 if(phy_tmp & CR_1000T_MS_ENABLE) { 2777 phy_tmp &= ~CR_1000T_MS_ENABLE; 2778 e1000_write_phy_reg(&sc->hw, 2779 PHY_1000T_CTRL, phy_tmp); 2780 sc->smartspeed++; 2781 if(sc->hw.mac.autoneg && 2782 !e1000_copper_link_autoneg(&sc->hw) && 2783 !e1000_read_phy_reg(&sc->hw, 2784 PHY_CONTROL, &phy_tmp)) { 2785 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2786 MII_CR_RESTART_AUTO_NEG); 2787 e1000_write_phy_reg(&sc->hw, 2788 PHY_CONTROL, phy_tmp); 2789 } 2790 } 2791 } 2792 return; 2793 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2794 /* If still no link, perhaps using 2/3 pair cable */ 2795 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp); 2796 phy_tmp |= CR_1000T_MS_ENABLE; 2797 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp); 2798 if(sc->hw.mac.autoneg && 2799 !e1000_copper_link_autoneg(&sc->hw) && 2800 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) { 2801 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2802 MII_CR_RESTART_AUTO_NEG); 2803 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp); 2804 } 2805 } 2806 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2807 if(sc->smartspeed++ == EM_SMARTSPEED_MAX) 2808 sc->smartspeed = 0; 2809 } 2810 2811 /********************************************************************* 2812 * 2813 * Initialize the DMA Coalescing feature 2814 * 2815 **********************************************************************/ 2816 static void 2817 igb_init_dmac(struct e1000_softc *sc, u32 pba) 2818 { 2819 device_t dev = sc->dev; 2820 struct e1000_hw *hw = &sc->hw; 2821 u32 dmac, reg = ~E1000_DMACR_DMAC_EN; 2822 u16 hwm; 2823 u16 max_frame_size; 2824 2825 if (hw->mac.type == e1000_i211) 2826 return; 2827 2828 max_frame_size = sc->shared->isc_max_frame_size; 2829 if (hw->mac.type > e1000_82580) { 2830 2831 if (sc->dmac == 0) { /* Disabling it */ 2832 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2833 return; 2834 } else 2835 device_printf(dev, "DMA Coalescing enabled\n"); 2836 2837 /* Set starting threshold */ 2838 E1000_WRITE_REG(hw, E1000_DMCTXTH, 0); 2839 2840 hwm = 64 * pba - max_frame_size / 16; 2841 if (hwm < 64 * (pba - 6)) 2842 hwm = 64 * (pba - 6); 2843 reg = E1000_READ_REG(hw, E1000_FCRTC); 2844 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 2845 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 2846 & E1000_FCRTC_RTH_COAL_MASK); 2847 E1000_WRITE_REG(hw, E1000_FCRTC, reg); 2848 2849 2850 dmac = pba - max_frame_size / 512; 2851 if (dmac < pba - 10) 2852 dmac = pba - 10; 2853 reg = E1000_READ_REG(hw, E1000_DMACR); 2854 reg &= ~E1000_DMACR_DMACTHR_MASK; 2855 reg |= ((dmac << E1000_DMACR_DMACTHR_SHIFT) 2856 & E1000_DMACR_DMACTHR_MASK); 2857 2858 /* transition to L0x or L1 if available..*/ 2859 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 2860 2861 /* Check if status is 2.5Gb backplane connection 2862 * before configuration of watchdog timer, which is 2863 * in msec values in 12.8usec intervals 2864 * watchdog timer= msec values in 32usec intervals 2865 * for non 2.5Gb connection 2866 */ 2867 if (hw->mac.type == e1000_i354) { 2868 int status = E1000_READ_REG(hw, E1000_STATUS); 2869 if ((status & E1000_STATUS_2P5_SKU) && 2870 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2871 reg |= ((sc->dmac * 5) >> 6); 2872 else 2873 reg |= (sc->dmac >> 5); 2874 } else { 2875 reg |= (sc->dmac >> 5); 2876 } 2877 2878 E1000_WRITE_REG(hw, E1000_DMACR, reg); 2879 2880 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0); 2881 2882 /* Set the interval before transition */ 2883 reg = E1000_READ_REG(hw, E1000_DMCTLX); 2884 if (hw->mac.type == e1000_i350) 2885 reg |= IGB_DMCTLX_DCFLUSH_DIS; 2886 /* 2887 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2888 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2889 */ 2890 if (hw->mac.type == e1000_i354) { 2891 int status = E1000_READ_REG(hw, E1000_STATUS); 2892 if ((status & E1000_STATUS_2P5_SKU) && 2893 (!(status & E1000_STATUS_2P5_SKU_OVER))) 2894 reg |= 0xA; 2895 else 2896 reg |= 0x4; 2897 } else { 2898 reg |= 0x4; 2899 } 2900 2901 E1000_WRITE_REG(hw, E1000_DMCTLX, reg); 2902 2903 /* free space in tx packet buffer to wake from DMA coal */ 2904 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE - 2905 (2 * max_frame_size)) >> 6); 2906 2907 /* make low power state decision controlled by DMA coal */ 2908 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2909 reg &= ~E1000_PCIEMISC_LX_DECISION; 2910 E1000_WRITE_REG(hw, E1000_PCIEMISC, reg); 2911 2912 } else if (hw->mac.type == e1000_82580) { 2913 u32 reg = E1000_READ_REG(hw, E1000_PCIEMISC); 2914 E1000_WRITE_REG(hw, E1000_PCIEMISC, 2915 reg & ~E1000_PCIEMISC_LX_DECISION); 2916 E1000_WRITE_REG(hw, E1000_DMACR, 0); 2917 } 2918 } 2919 /********************************************************************* 2920 * The 3 following flush routines are used as a workaround in the 2921 * I219 client parts and only for them. 2922 * 2923 * em_flush_tx_ring - remove all descriptors from the tx_ring 2924 * 2925 * We want to clear all pending descriptors from the TX ring. 2926 * zeroing happens when the HW reads the regs. We assign the ring itself as 2927 * the data of the next descriptor. We don't care about the data we are about 2928 * to reset the HW. 2929 **********************************************************************/ 2930 static void 2931 em_flush_tx_ring(struct e1000_softc *sc) 2932 { 2933 struct e1000_hw *hw = &sc->hw; 2934 struct tx_ring *txr = &sc->tx_queues->txr; 2935 struct e1000_tx_desc *txd; 2936 u32 tctl, txd_lower = E1000_TXD_CMD_IFCS; 2937 u16 size = 512; 2938 2939 tctl = E1000_READ_REG(hw, E1000_TCTL); 2940 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN); 2941 2942 txd = &txr->tx_base[txr->tx_cidx_processed]; 2943 2944 /* Just use the ring as a dummy buffer addr */ 2945 txd->buffer_addr = txr->tx_paddr; 2946 txd->lower.data = htole32(txd_lower | size); 2947 txd->upper.data = 0; 2948 2949 /* flush descriptors to memory before notifying the HW */ 2950 wmb(); 2951 2952 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed); 2953 mb(); 2954 usec_delay(250); 2955 } 2956 2957 /********************************************************************* 2958 * em_flush_rx_ring - remove all descriptors from the rx_ring 2959 * 2960 * Mark all descriptors in the RX ring as consumed and disable the rx ring 2961 **********************************************************************/ 2962 static void 2963 em_flush_rx_ring(struct e1000_softc *sc) 2964 { 2965 struct e1000_hw *hw = &sc->hw; 2966 u32 rctl, rxdctl; 2967 2968 rctl = E1000_READ_REG(hw, E1000_RCTL); 2969 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2970 E1000_WRITE_FLUSH(hw); 2971 usec_delay(150); 2972 2973 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 2974 /* zero the lower 14 bits (prefetch and host thresholds) */ 2975 rxdctl &= 0xffffc000; 2976 /* 2977 * update thresholds: prefetch threshold to 31, host threshold to 1 2978 * and make sure the granularity is "descriptors" and not 2979 * "cache lines" 2980 */ 2981 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC); 2982 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl); 2983 2984 /* momentarily enable the RX ring for the changes to take effect */ 2985 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN); 2986 E1000_WRITE_FLUSH(hw); 2987 usec_delay(150); 2988 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 2989 } 2990 2991 /********************************************************************* 2992 * em_flush_desc_rings - remove all descriptors from the descriptor rings 2993 * 2994 * In I219, the descriptor rings must be emptied before resetting the HW 2995 * or before changing the device state to D3 during runtime (runtime PM). 2996 * 2997 * Failure to do this will cause the HW to enter a unit hang state which can 2998 * only be released by PCI reset on the device 2999 * 3000 **********************************************************************/ 3001 static void 3002 em_flush_desc_rings(struct e1000_softc *sc) 3003 { 3004 struct e1000_hw *hw = &sc->hw; 3005 device_t dev = sc->dev; 3006 u16 hang_state; 3007 u32 fext_nvm11, tdlen; 3008 3009 /* First, disable MULR fix in FEXTNVM11 */ 3010 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11); 3011 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; 3012 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11); 3013 3014 /* do nothing if we're not in faulty state, or the queue is empty */ 3015 tdlen = E1000_READ_REG(hw, E1000_TDLEN(0)); 3016 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3017 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) 3018 return; 3019 em_flush_tx_ring(sc); 3020 3021 /* recheck, maybe the fault is caused by the rx ring */ 3022 hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2); 3023 if (hang_state & FLUSH_DESC_REQUIRED) 3024 em_flush_rx_ring(sc); 3025 } 3026 3027 3028 /********************************************************************* 3029 * 3030 * Initialize the hardware to a configuration as specified by the 3031 * sc structure. 3032 * 3033 **********************************************************************/ 3034 static void 3035 em_reset(if_ctx_t ctx) 3036 { 3037 device_t dev = iflib_get_dev(ctx); 3038 struct e1000_softc *sc = iflib_get_softc(ctx); 3039 if_t ifp = iflib_get_ifp(ctx); 3040 struct e1000_hw *hw = &sc->hw; 3041 u32 rx_buffer_size; 3042 u32 pba; 3043 3044 INIT_DEBUGOUT("em_reset: begin"); 3045 /* Let the firmware know the OS is in control */ 3046 em_get_hw_control(sc); 3047 3048 /* Set up smart power down as default off on newer adapters. */ 3049 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 || 3050 hw->mac.type == e1000_82572)) { 3051 u16 phy_tmp = 0; 3052 3053 /* Speed up time to link by disabling smart power down. */ 3054 e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 3055 phy_tmp &= ~IGP02E1000_PM_SPD; 3056 e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_tmp); 3057 } 3058 3059 /* 3060 * Packet Buffer Allocation (PBA) 3061 * Writing PBA sets the receive portion of the buffer 3062 * the remainder is used for the transmit buffer. 3063 */ 3064 switch (hw->mac.type) { 3065 /* 82547: Total Packet Buffer is 40K */ 3066 case e1000_82547: 3067 case e1000_82547_rev_2: 3068 if (hw->mac.max_frame_size > 8192) 3069 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 3070 else 3071 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 3072 break; 3073 /* 82571/82572/80003es2lan: Total Packet Buffer is 48K */ 3074 case e1000_82571: 3075 case e1000_82572: 3076 case e1000_80003es2lan: 3077 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 3078 break; 3079 /* 82573: Total Packet Buffer is 32K */ 3080 case e1000_82573: 3081 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 3082 break; 3083 /* 82574/82583: Total Packet Buffer is 40K */ 3084 case e1000_82574: 3085 case e1000_82583: 3086 if (hw->mac.max_frame_size > 8192) 3087 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 3088 else 3089 pba = E1000_PBA_32K; /* 32K for RX, 8K for Tx */ 3090 break; 3091 case e1000_ich8lan: 3092 pba = E1000_PBA_8K; 3093 break; 3094 case e1000_ich9lan: 3095 case e1000_ich10lan: 3096 /* Boost Receive side for jumbo frames */ 3097 if (hw->mac.max_frame_size > 4096) 3098 pba = E1000_PBA_14K; 3099 else 3100 pba = E1000_PBA_10K; 3101 break; 3102 case e1000_pchlan: 3103 case e1000_pch2lan: 3104 case e1000_pch_lpt: 3105 case e1000_pch_spt: 3106 case e1000_pch_cnp: 3107 case e1000_pch_tgp: 3108 case e1000_pch_adp: 3109 case e1000_pch_mtp: 3110 case e1000_pch_ptp: 3111 pba = E1000_PBA_26K; 3112 break; 3113 case e1000_82575: 3114 pba = E1000_PBA_32K; 3115 break; 3116 case e1000_82576: 3117 case e1000_vfadapt: 3118 pba = E1000_READ_REG(hw, E1000_RXPBS); 3119 pba &= E1000_RXPBS_SIZE_MASK_82576; 3120 break; 3121 case e1000_82580: 3122 case e1000_i350: 3123 case e1000_i354: 3124 case e1000_vfadapt_i350: 3125 pba = E1000_READ_REG(hw, E1000_RXPBS); 3126 pba = e1000_rxpbs_adjust_82580(pba); 3127 break; 3128 case e1000_i210: 3129 case e1000_i211: 3130 pba = E1000_PBA_34K; 3131 break; 3132 default: 3133 /* Remaining devices assumed to have Packet Buffer of 64K. */ 3134 if (hw->mac.max_frame_size > 8192) 3135 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 3136 else 3137 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 3138 } 3139 3140 /* Special needs in case of Jumbo frames */ 3141 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) { 3142 u32 tx_space, min_tx, min_rx; 3143 pba = E1000_READ_REG(hw, E1000_PBA); 3144 tx_space = pba >> 16; 3145 pba &= 0xffff; 3146 min_tx = (hw->mac.max_frame_size + 3147 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 3148 min_tx = roundup2(min_tx, 1024); 3149 min_tx >>= 10; 3150 min_rx = hw->mac.max_frame_size; 3151 min_rx = roundup2(min_rx, 1024); 3152 min_rx >>= 10; 3153 if (tx_space < min_tx && 3154 ((min_tx - tx_space) < pba)) { 3155 pba = pba - (min_tx - tx_space); 3156 /* 3157 * if short on rx space, rx wins 3158 * and must trump tx adjustment 3159 */ 3160 if (pba < min_rx) 3161 pba = min_rx; 3162 } 3163 E1000_WRITE_REG(hw, E1000_PBA, pba); 3164 } 3165 3166 if (hw->mac.type < igb_mac_min) 3167 E1000_WRITE_REG(hw, E1000_PBA, pba); 3168 3169 INIT_DEBUGOUT1("em_reset: pba=%dK",pba); 3170 3171 /* 3172 * These parameters control the automatic generation (Tx) and 3173 * response (Rx) to Ethernet PAUSE frames. 3174 * - High water mark should allow for at least two frames to be 3175 * received after sending an XOFF. 3176 * - Low water mark works best when it is very near the high water 3177 mark. 3178 * This allows the receiver to restart by sending XON when it has 3179 * drained a bit. Here we use an arbitrary value of 1500 which will 3180 * restart after one full frame is pulled from the buffer. There 3181 * could be several smaller frames in the buffer and if so they will 3182 * not trigger the XON until their total number reduces the buffer 3183 * by 1500. 3184 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 3185 */ 3186 rx_buffer_size = (pba & 0xffff) << 10; 3187 hw->fc.high_water = rx_buffer_size - 3188 roundup2(hw->mac.max_frame_size, 1024); 3189 hw->fc.low_water = hw->fc.high_water - 1500; 3190 3191 if (sc->fc) /* locally set flow control value? */ 3192 hw->fc.requested_mode = sc->fc; 3193 else 3194 hw->fc.requested_mode = e1000_fc_full; 3195 3196 if (hw->mac.type == e1000_80003es2lan) 3197 hw->fc.pause_time = 0xFFFF; 3198 else 3199 hw->fc.pause_time = EM_FC_PAUSE_TIME; 3200 3201 hw->fc.send_xon = true; 3202 3203 /* Device specific overrides/settings */ 3204 switch (hw->mac.type) { 3205 case e1000_pchlan: 3206 /* Workaround: no TX flow ctrl for PCH */ 3207 hw->fc.requested_mode = e1000_fc_rx_pause; 3208 hw->fc.pause_time = 0xFFFF; /* override */ 3209 if (if_getmtu(ifp) > ETHERMTU) { 3210 hw->fc.high_water = 0x3500; 3211 hw->fc.low_water = 0x1500; 3212 } else { 3213 hw->fc.high_water = 0x5000; 3214 hw->fc.low_water = 0x3000; 3215 } 3216 hw->fc.refresh_time = 0x1000; 3217 break; 3218 case e1000_pch2lan: 3219 case e1000_pch_lpt: 3220 case e1000_pch_spt: 3221 case e1000_pch_cnp: 3222 case e1000_pch_tgp: 3223 case e1000_pch_adp: 3224 case e1000_pch_mtp: 3225 case e1000_pch_ptp: 3226 hw->fc.high_water = 0x5C20; 3227 hw->fc.low_water = 0x5048; 3228 hw->fc.pause_time = 0x0650; 3229 hw->fc.refresh_time = 0x0400; 3230 /* Jumbos need adjusted PBA */ 3231 if (if_getmtu(ifp) > ETHERMTU) 3232 E1000_WRITE_REG(hw, E1000_PBA, 12); 3233 else 3234 E1000_WRITE_REG(hw, E1000_PBA, 26); 3235 break; 3236 case e1000_82575: 3237 case e1000_82576: 3238 /* 8-byte granularity */ 3239 hw->fc.low_water = hw->fc.high_water - 8; 3240 break; 3241 case e1000_82580: 3242 case e1000_i350: 3243 case e1000_i354: 3244 case e1000_i210: 3245 case e1000_i211: 3246 case e1000_vfadapt: 3247 case e1000_vfadapt_i350: 3248 /* 16-byte granularity */ 3249 hw->fc.low_water = hw->fc.high_water - 16; 3250 break; 3251 case e1000_ich9lan: 3252 case e1000_ich10lan: 3253 if (if_getmtu(ifp) > ETHERMTU) { 3254 hw->fc.high_water = 0x2800; 3255 hw->fc.low_water = hw->fc.high_water - 8; 3256 break; 3257 } 3258 /* FALLTHROUGH */ 3259 default: 3260 if (hw->mac.type == e1000_80003es2lan) 3261 hw->fc.pause_time = 0xFFFF; 3262 break; 3263 } 3264 3265 /* I219 needs some special flushing to avoid hangs */ 3266 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min) 3267 em_flush_desc_rings(sc); 3268 3269 /* Issue a global reset */ 3270 e1000_reset_hw(hw); 3271 if (!sc->vf_ifp) { 3272 if (hw->mac.type >= igb_mac_min) { 3273 E1000_WRITE_REG(hw, E1000_WUC, 0); 3274 } else { 3275 E1000_WRITE_REG(hw, E1000_WUFC, 0); 3276 em_disable_aspm(sc); 3277 } 3278 } 3279 if (sc->flags & IGB_MEDIA_RESET) { 3280 e1000_setup_init_funcs(hw, true); 3281 e1000_get_bus_info(hw); 3282 sc->flags &= ~IGB_MEDIA_RESET; 3283 } 3284 /* and a re-init */ 3285 if (e1000_init_hw(hw) < 0) { 3286 device_printf(dev, "Hardware Initialization Failed\n"); 3287 return; 3288 } 3289 if (hw->mac.type >= igb_mac_min) 3290 igb_init_dmac(sc, pba); 3291 3292 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 3293 sc->pba = pba; 3294 3295 E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN); 3296 e1000_get_phy_info(hw); 3297 e1000_check_for_link(hw); 3298 } 3299 3300 /* 3301 * Initialise the RSS mapping for NICs that support multiple transmit/ 3302 * receive rings. 3303 */ 3304 3305 #define RSSKEYLEN 10 3306 static void 3307 em_initialize_rss_mapping(struct e1000_softc *sc) 3308 { 3309 uint8_t rss_key[4 * RSSKEYLEN]; 3310 uint32_t reta = 0; 3311 struct e1000_hw *hw = &sc->hw; 3312 int i; 3313 3314 /* 3315 * Configure RSS key 3316 */ 3317 arc4rand(rss_key, sizeof(rss_key), 0); 3318 for (i = 0; i < RSSKEYLEN; ++i) { 3319 uint32_t rssrk = 0; 3320 3321 rssrk = EM_RSSRK_VAL(rss_key, i); 3322 E1000_WRITE_REG(hw,E1000_RSSRK(i), rssrk); 3323 } 3324 3325 /* 3326 * Configure RSS redirect table in following fashion: 3327 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3328 */ 3329 for (i = 0; i < sizeof(reta); ++i) { 3330 uint32_t q; 3331 3332 q = (i % sc->rx_num_queues) << 7; 3333 reta |= q << (8 * i); 3334 } 3335 3336 for (i = 0; i < 32; ++i) 3337 E1000_WRITE_REG(hw, E1000_RETA(i), reta); 3338 3339 E1000_WRITE_REG(hw, E1000_MRQC, E1000_MRQC_RSS_ENABLE_2Q | 3340 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3341 E1000_MRQC_RSS_FIELD_IPV4 | 3342 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX | 3343 E1000_MRQC_RSS_FIELD_IPV6_EX | 3344 E1000_MRQC_RSS_FIELD_IPV6); 3345 } 3346 3347 static void 3348 igb_initialize_rss_mapping(struct e1000_softc *sc) 3349 { 3350 struct e1000_hw *hw = &sc->hw; 3351 int i; 3352 int queue_id; 3353 u32 reta; 3354 u32 rss_key[10], mrqc, shift = 0; 3355 3356 /* XXX? */ 3357 if (hw->mac.type == e1000_82575) 3358 shift = 6; 3359 3360 /* 3361 * The redirection table controls which destination 3362 * queue each bucket redirects traffic to. 3363 * Each DWORD represents four queues, with the LSB 3364 * being the first queue in the DWORD. 3365 * 3366 * This just allocates buckets to queues using round-robin 3367 * allocation. 3368 * 3369 * NOTE: It Just Happens to line up with the default 3370 * RSS allocation method. 3371 */ 3372 3373 /* Warning FM follows */ 3374 reta = 0; 3375 for (i = 0; i < 128; i++) { 3376 #ifdef RSS 3377 queue_id = rss_get_indirection_to_bucket(i); 3378 /* 3379 * If we have more queues than buckets, we'll 3380 * end up mapping buckets to a subset of the 3381 * queues. 3382 * 3383 * If we have more buckets than queues, we'll 3384 * end up instead assigning multiple buckets 3385 * to queues. 3386 * 3387 * Both are suboptimal, but we need to handle 3388 * the case so we don't go out of bounds 3389 * indexing arrays and such. 3390 */ 3391 queue_id = queue_id % sc->rx_num_queues; 3392 #else 3393 queue_id = (i % sc->rx_num_queues); 3394 #endif 3395 /* Adjust if required */ 3396 queue_id = queue_id << shift; 3397 3398 /* 3399 * The low 8 bits are for hash value (n+0); 3400 * The next 8 bits are for hash value (n+1), etc. 3401 */ 3402 reta = reta >> 8; 3403 reta = reta | ( ((uint32_t) queue_id) << 24); 3404 if ((i & 3) == 3) { 3405 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta); 3406 reta = 0; 3407 } 3408 } 3409 3410 /* Now fill in hash table */ 3411 3412 /* 3413 * MRQC: Multiple Receive Queues Command 3414 * Set queuing to RSS control, number depends on the device. 3415 */ 3416 mrqc = E1000_MRQC_ENABLE_RSS_MQ; 3417 3418 #ifdef RSS 3419 /* XXX ew typecasting */ 3420 rss_getkey((uint8_t *) &rss_key); 3421 #else 3422 arc4rand(&rss_key, sizeof(rss_key), 0); 3423 #endif 3424 for (i = 0; i < 10; i++) 3425 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key[i]); 3426 3427 /* 3428 * Configure the RSS fields to hash upon. 3429 */ 3430 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 3431 E1000_MRQC_RSS_FIELD_IPV4_TCP); 3432 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 | 3433 E1000_MRQC_RSS_FIELD_IPV6_TCP); 3434 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP | 3435 E1000_MRQC_RSS_FIELD_IPV6_UDP); 3436 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 3437 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 3438 3439 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 3440 } 3441 3442 /********************************************************************* 3443 * 3444 * Setup networking device structure and register interface media. 3445 * 3446 **********************************************************************/ 3447 static int 3448 em_setup_interface(if_ctx_t ctx) 3449 { 3450 if_t ifp = iflib_get_ifp(ctx); 3451 struct e1000_softc *sc = iflib_get_softc(ctx); 3452 if_softc_ctx_t scctx = sc->shared; 3453 3454 INIT_DEBUGOUT("em_setup_interface: begin"); 3455 3456 /* Single Queue */ 3457 if (sc->tx_num_queues == 1) { 3458 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 3459 if_setsendqready(ifp); 3460 } 3461 3462 /* 3463 * Specify the media types supported by this adapter and register 3464 * callbacks to update media and link information 3465 */ 3466 if (sc->hw.phy.media_type == e1000_media_type_fiber || 3467 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 3468 u_char fiber_type = IFM_1000_SX; /* default type */ 3469 3470 if (sc->hw.mac.type == e1000_82545) 3471 fiber_type = IFM_1000_LX; 3472 ifmedia_add(sc->media, 3473 IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); 3474 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL); 3475 } else { 3476 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 3477 ifmedia_add(sc->media, 3478 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3479 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 3480 ifmedia_add(sc->media, 3481 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3482 if (sc->hw.phy.type != e1000_phy_ife) { 3483 ifmedia_add(sc->media, 3484 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3485 ifmedia_add(sc->media, 3486 IFM_ETHER | IFM_1000_T, 0, NULL); 3487 } 3488 } 3489 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3490 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 3491 return (0); 3492 } 3493 3494 static int 3495 em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3496 int ntxqs, int ntxqsets) 3497 { 3498 struct e1000_softc *sc = iflib_get_softc(ctx); 3499 if_softc_ctx_t scctx = sc->shared; 3500 int error = E1000_SUCCESS; 3501 struct em_tx_queue *que; 3502 int i, j; 3503 3504 MPASS(sc->tx_num_queues > 0); 3505 MPASS(sc->tx_num_queues == ntxqsets); 3506 3507 /* First allocate the top level queue structs */ 3508 if (!(sc->tx_queues = 3509 (struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) * 3510 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3511 device_printf(iflib_get_dev(ctx), 3512 "Unable to allocate queue memory\n"); 3513 return(ENOMEM); 3514 } 3515 3516 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 3517 /* Set up some basics */ 3518 3519 struct tx_ring *txr = &que->txr; 3520 txr->sc = que->sc = sc; 3521 que->me = txr->me = i; 3522 3523 /* Allocate report status array */ 3524 if (!(txr->tx_rsq = 3525 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], 3526 M_DEVBUF, M_NOWAIT | M_ZERO))) { 3527 device_printf(iflib_get_dev(ctx), 3528 "failed to allocate rs_idxs memory\n"); 3529 error = ENOMEM; 3530 goto fail; 3531 } 3532 for (j = 0; j < scctx->isc_ntxd[0]; j++) 3533 txr->tx_rsq[j] = QIDX_INVALID; 3534 /* get the virtual and physical address of hardware queues */ 3535 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs]; 3536 txr->tx_paddr = paddrs[i*ntxqs]; 3537 } 3538 3539 if (bootverbose) 3540 device_printf(iflib_get_dev(ctx), 3541 "allocated for %d tx_queues\n", sc->tx_num_queues); 3542 return (0); 3543 fail: 3544 em_if_queues_free(ctx); 3545 return (error); 3546 } 3547 3548 static int 3549 em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 3550 int nrxqs, int nrxqsets) 3551 { 3552 struct e1000_softc *sc = iflib_get_softc(ctx); 3553 int error = E1000_SUCCESS; 3554 struct em_rx_queue *que; 3555 int i; 3556 3557 MPASS(sc->rx_num_queues > 0); 3558 MPASS(sc->rx_num_queues == nrxqsets); 3559 3560 /* First allocate the top level queue structs */ 3561 if (!(sc->rx_queues = 3562 (struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) * 3563 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 3564 device_printf(iflib_get_dev(ctx), 3565 "Unable to allocate queue memory\n"); 3566 error = ENOMEM; 3567 goto fail; 3568 } 3569 3570 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 3571 /* Set up some basics */ 3572 struct rx_ring *rxr = &que->rxr; 3573 rxr->sc = que->sc = sc; 3574 rxr->que = que; 3575 que->me = rxr->me = i; 3576 3577 /* get the virtual and physical address of hardware queues */ 3578 rxr->rx_base = 3579 (union e1000_rx_desc_extended *)vaddrs[i*nrxqs]; 3580 rxr->rx_paddr = paddrs[i*nrxqs]; 3581 } 3582 3583 if (bootverbose) 3584 device_printf(iflib_get_dev(ctx), 3585 "allocated for %d rx_queues\n", sc->rx_num_queues); 3586 3587 return (0); 3588 fail: 3589 em_if_queues_free(ctx); 3590 return (error); 3591 } 3592 3593 static void 3594 em_if_queues_free(if_ctx_t ctx) 3595 { 3596 struct e1000_softc *sc = iflib_get_softc(ctx); 3597 struct em_tx_queue *tx_que = sc->tx_queues; 3598 struct em_rx_queue *rx_que = sc->rx_queues; 3599 3600 if (tx_que != NULL) { 3601 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3602 struct tx_ring *txr = &tx_que->txr; 3603 if (txr->tx_rsq == NULL) 3604 break; 3605 3606 free(txr->tx_rsq, M_DEVBUF); 3607 txr->tx_rsq = NULL; 3608 } 3609 free(sc->tx_queues, M_DEVBUF); 3610 sc->tx_queues = NULL; 3611 } 3612 3613 if (rx_que != NULL) { 3614 free(sc->rx_queues, M_DEVBUF); 3615 sc->rx_queues = NULL; 3616 } 3617 } 3618 3619 /********************************************************************* 3620 * 3621 * Enable transmit unit. 3622 * 3623 **********************************************************************/ 3624 static void 3625 em_initialize_transmit_unit(if_ctx_t ctx) 3626 { 3627 struct e1000_softc *sc = iflib_get_softc(ctx); 3628 if_softc_ctx_t scctx = sc->shared; 3629 struct em_tx_queue *que; 3630 struct tx_ring *txr; 3631 struct e1000_hw *hw = &sc->hw; 3632 u32 tctl, txdctl = 0, tarc, tipg = 0; 3633 3634 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3635 3636 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 3637 u64 bus_addr; 3638 caddr_t offp, endp; 3639 3640 que = &sc->tx_queues[i]; 3641 txr = &que->txr; 3642 bus_addr = txr->tx_paddr; 3643 3644 /* Clear checksum offload context. */ 3645 offp = (caddr_t)&txr->csum_flags; 3646 endp = (caddr_t)(txr + 1); 3647 bzero(offp, endp - offp); 3648 3649 /* Base and Len of TX Ring */ 3650 E1000_WRITE_REG(hw, E1000_TDLEN(i), 3651 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc)); 3652 E1000_WRITE_REG(hw, E1000_TDBAH(i), (u32)(bus_addr >> 32)); 3653 E1000_WRITE_REG(hw, E1000_TDBAL(i), (u32)bus_addr); 3654 /* Init the HEAD/TAIL indices */ 3655 E1000_WRITE_REG(hw, E1000_TDT(i), 0); 3656 E1000_WRITE_REG(hw, E1000_TDH(i), 0); 3657 3658 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3659 E1000_READ_REG(hw, E1000_TDBAL(i)), 3660 E1000_READ_REG(hw, E1000_TDLEN(i))); 3661 3662 txdctl = 0; /* clear txdctl */ 3663 txdctl |= 0x1f; /* PTHRESH */ 3664 txdctl |= 1 << 8; /* HTHRESH */ 3665 txdctl |= 1 << 16;/* WTHRESH */ 3666 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 3667 txdctl |= E1000_TXDCTL_GRAN; 3668 txdctl |= 1 << 25; /* LWTHRESH */ 3669 3670 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); 3671 } 3672 3673 /* Set the default values for the Tx Inter Packet Gap timer */ 3674 switch (hw->mac.type) { 3675 case e1000_80003es2lan: 3676 tipg = DEFAULT_82543_TIPG_IPGR1; 3677 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3678 E1000_TIPG_IPGR2_SHIFT; 3679 break; 3680 case e1000_82542: 3681 tipg = DEFAULT_82542_TIPG_IPGT; 3682 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3683 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3684 break; 3685 default: 3686 if (hw->phy.media_type == e1000_media_type_fiber || 3687 hw->phy.media_type == e1000_media_type_internal_serdes) 3688 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3689 else 3690 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3691 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3692 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3693 } 3694 3695 if (hw->mac.type < igb_mac_min) { 3696 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 3697 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value); 3698 3699 if (sc->tx_int_delay.value > 0) 3700 sc->txd_cmd |= E1000_TXD_CMD_IDE; 3701 } 3702 3703 if (hw->mac.type >= e1000_82540) 3704 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value); 3705 3706 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) { 3707 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3708 tarc |= TARC_SPEED_MODE_BIT; 3709 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3710 } else if (hw->mac.type == e1000_80003es2lan) { 3711 /* errata: program both queues to unweighted RR */ 3712 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3713 tarc |= 1; 3714 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3715 tarc = E1000_READ_REG(hw, E1000_TARC(1)); 3716 tarc |= 1; 3717 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3718 } else if (hw->mac.type == e1000_82574) { 3719 tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3720 tarc |= TARC_ERRATA_BIT; 3721 if ( sc->tx_num_queues > 1) { 3722 tarc |= (TARC_COMPENSATION_MODE | TARC_MQ_FIX); 3723 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3724 E1000_WRITE_REG(hw, E1000_TARC(1), tarc); 3725 } else 3726 E1000_WRITE_REG(hw, E1000_TARC(0), tarc); 3727 } 3728 3729 /* Program the Transmit Control Register */ 3730 tctl = E1000_READ_REG(hw, E1000_TCTL); 3731 tctl &= ~E1000_TCTL_CT; 3732 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3733 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3734 3735 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min) 3736 tctl |= E1000_TCTL_MULR; 3737 3738 /* This write will effectively turn on the transmit unit. */ 3739 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 3740 3741 /* SPT and KBL errata workarounds */ 3742 if (hw->mac.type == e1000_pch_spt) { 3743 u32 reg; 3744 reg = E1000_READ_REG(hw, E1000_IOSFPC); 3745 reg |= E1000_RCTL_RDMTS_HEX; 3746 E1000_WRITE_REG(hw, E1000_IOSFPC, reg); 3747 /* i218-i219 Specification Update 1.5.4.5 */ 3748 reg = E1000_READ_REG(hw, E1000_TARC(0)); 3749 reg &= ~E1000_TARC0_CB_MULTIQ_3_REQ; 3750 reg |= E1000_TARC0_CB_MULTIQ_2_REQ; 3751 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 3752 } 3753 } 3754 3755 /********************************************************************* 3756 * 3757 * Enable receive unit. 3758 * 3759 **********************************************************************/ 3760 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1) 3761 3762 static void 3763 em_initialize_receive_unit(if_ctx_t ctx) 3764 { 3765 struct e1000_softc *sc = iflib_get_softc(ctx); 3766 if_softc_ctx_t scctx = sc->shared; 3767 if_t ifp = iflib_get_ifp(ctx); 3768 struct e1000_hw *hw = &sc->hw; 3769 struct em_rx_queue *que; 3770 int i; 3771 uint32_t rctl, rxcsum; 3772 3773 INIT_DEBUGOUT("em_initialize_receive_units: begin"); 3774 3775 /* 3776 * Make sure receives are disabled while setting 3777 * up the descriptor ring 3778 */ 3779 rctl = E1000_READ_REG(hw, E1000_RCTL); 3780 /* Do not disable if ever enabled on this hardware */ 3781 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583)) 3782 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN); 3783 3784 /* Setup the Receive Control Register */ 3785 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3786 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | 3787 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | 3788 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3789 3790 /* Do not store bad packets */ 3791 rctl &= ~E1000_RCTL_SBP; 3792 3793 /* Enable Long Packet receive */ 3794 if (if_getmtu(ifp) > ETHERMTU) 3795 rctl |= E1000_RCTL_LPE; 3796 else 3797 rctl &= ~E1000_RCTL_LPE; 3798 3799 /* Strip the CRC */ 3800 if (!em_disable_crc_stripping) 3801 rctl |= E1000_RCTL_SECRC; 3802 3803 /* lem/em default interrupt moderation */ 3804 if (hw->mac.type < igb_mac_min) { 3805 if (hw->mac.type >= e1000_82540) { 3806 E1000_WRITE_REG(hw, E1000_RADV, 3807 sc->rx_abs_int_delay.value); 3808 3809 /* Set the default interrupt throttling rate */ 3810 E1000_WRITE_REG(hw, E1000_ITR, 3811 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3812 } 3813 3814 /* XXX TEMPORARY WORKAROUND: on some systems with 82573 3815 * long latencies are observed, like Lenovo X60. This 3816 * change eliminates the problem, but since having positive 3817 * values in RDTR is a known source of problems on other 3818 * platforms another solution is being sought. 3819 */ 3820 if (hw->mac.type == e1000_82573) 3821 E1000_WRITE_REG(hw, E1000_RDTR, 0x20); 3822 else 3823 E1000_WRITE_REG(hw, E1000_RDTR, 3824 sc->rx_int_delay.value); 3825 } 3826 3827 if (hw->mac.type >= em_mac_min && !sc->vf_ifp) { 3828 uint32_t rfctl; 3829 /* Use extended rx descriptor formats */ 3830 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 3831 rfctl |= E1000_RFCTL_EXTEN; 3832 3833 /* 3834 * When using MSI-X interrupts we need to throttle 3835 * using the EITR register (82574 only) 3836 */ 3837 if (hw->mac.type == e1000_82574) { 3838 for (int i = 0; i < 4; i++) 3839 E1000_WRITE_REG(hw, E1000_EITR_82574(i), 3840 EM_INTS_TO_ITR(em_max_interrupt_rate)); 3841 /* Disable accelerated acknowledge */ 3842 rfctl |= E1000_RFCTL_ACK_DIS; 3843 } 3844 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 3845 } 3846 3847 /* 3848 * Set up L3 and L4 csum Rx descriptor offloads only on Physical 3849 * Functions. Virtual Functions have no access to this register. 3850 */ 3851 if (!sc->vf_ifp) { 3852 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 3853 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3854 rxcsum |= E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPOFL; 3855 if (hw->mac.type > e1000_82575) 3856 rxcsum |= E1000_RXCSUM_CRCOFL; 3857 else if (hw->mac.type < em_mac_min && 3858 if_getcapenable(ifp) & IFCAP_HWCSUM_IPV6) 3859 rxcsum |= E1000_RXCSUM_IPV6OFL; 3860 } else { 3861 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3862 if (hw->mac.type > e1000_82575) 3863 rxcsum &= ~E1000_RXCSUM_CRCOFL; 3864 else if (hw->mac.type < em_mac_min) 3865 rxcsum &= ~E1000_RXCSUM_IPV6OFL; 3866 } 3867 3868 if (sc->rx_num_queues > 1) { 3869 /* RSS hash needed in the Rx descriptor */ 3870 rxcsum |= E1000_RXCSUM_PCSD; 3871 3872 if (hw->mac.type >= igb_mac_min) 3873 igb_initialize_rss_mapping(sc); 3874 else 3875 em_initialize_rss_mapping(sc); 3876 } 3877 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 3878 } 3879 3880 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 3881 struct rx_ring *rxr = &que->rxr; 3882 /* Setup the Base and Length of the Rx Descriptor Ring */ 3883 u64 bus_addr = rxr->rx_paddr; 3884 #if 0 3885 u32 rdt = sc->rx_num_queues -1; /* default */ 3886 #endif 3887 3888 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3889 scctx->isc_nrxd[0] * 3890 sizeof(union e1000_rx_desc_extended)); 3891 E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32)); 3892 E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr); 3893 /* Setup the Head and Tail Descriptor Pointers */ 3894 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 3895 E1000_WRITE_REG(hw, E1000_RDT(i), 0); 3896 } 3897 3898 /* 3899 * Set PTHRESH for improved jumbo performance 3900 * According to 10.2.5.11 of Intel 82574 Datasheet, 3901 * RXDCTL(1) is written whenever RXDCTL(0) is written. 3902 * Only write to RXDCTL(1) if there is a need for different 3903 * settings. 3904 */ 3905 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan || 3906 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) { 3907 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0)); 3908 E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3); 3909 } else if (hw->mac.type == e1000_82574) { 3910 for (int i = 0; i < sc->rx_num_queues; i++) { 3911 u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3912 rxdctl |= 0x20; /* PTHRESH */ 3913 rxdctl |= 4 << 8; /* HTHRESH */ 3914 rxdctl |= 4 << 16;/* WTHRESH */ 3915 rxdctl |= 1 << 24; /* Switch to granularity */ 3916 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3917 } 3918 } else if (hw->mac.type >= igb_mac_min) { 3919 u32 psize, srrctl = 0; 3920 3921 if (if_getmtu(ifp) > ETHERMTU) { 3922 psize = scctx->isc_max_frame_size; 3923 /* are we on a vlan? */ 3924 if (if_vlantrunkinuse(ifp)) 3925 psize += VLAN_TAG_SIZE; 3926 3927 if (sc->vf_ifp) 3928 e1000_rlpml_set_vf(hw, psize); 3929 else 3930 E1000_WRITE_REG(hw, E1000_RLPML, psize); 3931 } 3932 3933 /* Set maximum packet buffer len */ 3934 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 3935 E1000_SRRCTL_BSIZEPKT_SHIFT; 3936 3937 /* 3938 * If TX flow control is disabled and there's >1 queue 3939 * defined, enable DROP. 3940 * 3941 * This drops frames rather than hanging the RX MAC for all 3942 * queues. 3943 */ 3944 if ((sc->rx_num_queues > 1) && 3945 (sc->fc == e1000_fc_none || 3946 sc->fc == e1000_fc_rx_pause)) { 3947 srrctl |= E1000_SRRCTL_DROP_EN; 3948 } 3949 /* Setup the Base and Length of the Rx Descriptor Rings */ 3950 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; 3951 i++, que++) { 3952 struct rx_ring *rxr = &que->rxr; 3953 u64 bus_addr = rxr->rx_paddr; 3954 u32 rxdctl; 3955 3956 #ifdef notyet 3957 /* Configure for header split? -- ignore for now */ 3958 rxr->hdr_split = igb_header_split; 3959 #else 3960 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3961 #endif 3962 3963 E1000_WRITE_REG(hw, E1000_RDLEN(i), 3964 scctx->isc_nrxd[0] * 3965 sizeof(struct e1000_rx_desc)); 3966 E1000_WRITE_REG(hw, E1000_RDBAH(i), 3967 (uint32_t)(bus_addr >> 32)); 3968 E1000_WRITE_REG(hw, E1000_RDBAL(i), 3969 (uint32_t)bus_addr); 3970 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl); 3971 /* Enable this Queue */ 3972 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i)); 3973 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3974 rxdctl &= 0xFFF00000; 3975 rxdctl |= IGB_RX_PTHRESH; 3976 rxdctl |= IGB_RX_HTHRESH << 8; 3977 rxdctl |= IGB_RX_WTHRESH << 16; 3978 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl); 3979 } 3980 } else if (hw->mac.type >= e1000_pch2lan) { 3981 if (if_getmtu(ifp) > ETHERMTU) 3982 e1000_lv_jumbo_workaround_ich8lan(hw, true); 3983 else 3984 e1000_lv_jumbo_workaround_ich8lan(hw, false); 3985 } 3986 3987 /* Make sure VLAN Filters are off */ 3988 rctl &= ~E1000_RCTL_VFE; 3989 3990 /* Set up packet buffer size, overridden by per queue srrctl on igb */ 3991 if (hw->mac.type < igb_mac_min) { 3992 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096) 3993 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 3994 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192) 3995 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 3996 else if (sc->rx_mbuf_sz > 8192) 3997 rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 3998 else { 3999 rctl |= E1000_RCTL_SZ_2048; 4000 rctl &= ~E1000_RCTL_BSEX; 4001 } 4002 } else 4003 rctl |= E1000_RCTL_SZ_2048; 4004 4005 /* 4006 * rctl bits 11:10 are as follows 4007 * lem: reserved 4008 * em: DTYPE 4009 * igb: reserved 4010 * and should be 00 on all of the above 4011 */ 4012 rctl &= ~0x00000C00; 4013 4014 /* Write out the settings */ 4015 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4016 4017 return; 4018 } 4019 4020 static void 4021 em_if_vlan_register(if_ctx_t ctx, u16 vtag) 4022 { 4023 struct e1000_softc *sc = iflib_get_softc(ctx); 4024 u32 index, bit; 4025 4026 index = (vtag >> 5) & 0x7F; 4027 bit = vtag & 0x1F; 4028 sc->shadow_vfta[index] |= (1 << bit); 4029 ++sc->num_vlans; 4030 if (!sc->vf_ifp) 4031 em_if_vlan_filter_write(sc); 4032 else 4033 /* 4034 * Physical funtion may reject registering VLAN 4035 * but we have no way to inform the stack 4036 * about that. 4037 */ 4038 e1000_vfta_set_vf(&sc->hw, vtag, true); 4039 } 4040 4041 static void 4042 em_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 4043 { 4044 struct e1000_softc *sc = iflib_get_softc(ctx); 4045 u32 index, bit; 4046 4047 index = (vtag >> 5) & 0x7F; 4048 bit = vtag & 0x1F; 4049 sc->shadow_vfta[index] &= ~(1 << bit); 4050 --sc->num_vlans; 4051 if (!sc->vf_ifp) 4052 em_if_vlan_filter_write(sc); 4053 else 4054 e1000_vfta_set_vf(&sc->hw, vtag, false); 4055 } 4056 4057 static bool 4058 em_if_vlan_filter_capable(if_ctx_t ctx) 4059 { 4060 if_t ifp = iflib_get_ifp(ctx); 4061 4062 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) && 4063 !em_disable_crc_stripping) 4064 return (true); 4065 4066 return (false); 4067 } 4068 4069 static bool 4070 em_if_vlan_filter_used(if_ctx_t ctx) 4071 { 4072 struct e1000_softc *sc = iflib_get_softc(ctx); 4073 4074 if (!em_if_vlan_filter_capable(ctx)) 4075 return (false); 4076 4077 for (int i = 0; i < EM_VFTA_SIZE; i++) 4078 if (sc->shadow_vfta[i] != 0) 4079 return (true); 4080 4081 return (false); 4082 } 4083 4084 static void 4085 em_if_vlan_filter_enable(struct e1000_softc *sc) 4086 { 4087 struct e1000_hw *hw = &sc->hw; 4088 u32 reg; 4089 4090 reg = E1000_READ_REG(hw, E1000_RCTL); 4091 reg &= ~E1000_RCTL_CFIEN; 4092 reg |= E1000_RCTL_VFE; 4093 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4094 } 4095 4096 static void 4097 em_if_vlan_filter_disable(struct e1000_softc *sc) 4098 { 4099 struct e1000_hw *hw = &sc->hw; 4100 u32 reg; 4101 4102 reg = E1000_READ_REG(hw, E1000_RCTL); 4103 reg &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); 4104 E1000_WRITE_REG(hw, E1000_RCTL, reg); 4105 } 4106 4107 static void 4108 em_if_vlan_filter_write(struct e1000_softc *sc) 4109 { 4110 struct e1000_hw *hw = &sc->hw; 4111 4112 KASSERT(!sc->vf_ifp, ("VLAN filter write on VF\n")); 4113 4114 /* Disable interrupts for lem(4) devices during the filter change */ 4115 if (hw->mac.type < em_mac_min) 4116 em_if_intr_disable(sc->ctx); 4117 4118 for (int i = 0; i < EM_VFTA_SIZE; i++) 4119 if (sc->shadow_vfta[i] != 0) 4120 e1000_write_vfta(hw, i, sc->shadow_vfta[i]); 4121 4122 /* Re-enable interrupts for lem-class devices */ 4123 if (hw->mac.type < em_mac_min) 4124 em_if_intr_enable(sc->ctx); 4125 } 4126 4127 static void 4128 em_setup_vlan_hw_support(if_ctx_t ctx) 4129 { 4130 struct e1000_softc *sc = iflib_get_softc(ctx); 4131 struct e1000_hw *hw = &sc->hw; 4132 if_t ifp = iflib_get_ifp(ctx); 4133 u32 reg; 4134 4135 /* 4136 * Only PFs have control over VLAN HW filtering 4137 * configuration. VFs have to act as if it's always 4138 * enabled. 4139 */ 4140 if (sc->vf_ifp) 4141 return; 4142 4143 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 4144 !em_disable_crc_stripping) { 4145 reg = E1000_READ_REG(hw, E1000_CTRL); 4146 reg |= E1000_CTRL_VME; 4147 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4148 } else { 4149 reg = E1000_READ_REG(hw, E1000_CTRL); 4150 reg &= ~E1000_CTRL_VME; 4151 E1000_WRITE_REG(hw, E1000_CTRL, reg); 4152 } 4153 4154 /* If we aren't doing HW filtering, we're done */ 4155 if (!em_if_vlan_filter_capable(ctx)) { 4156 em_if_vlan_filter_disable(sc); 4157 return; 4158 } 4159 4160 /* 4161 * A soft reset zero's out the VFTA, so 4162 * we need to repopulate it now. 4163 * We also insert VLAN 0 in the filter list, so we pass VLAN 0 tagged 4164 * traffic through. This will write the entire table. 4165 */ 4166 em_if_vlan_register(ctx, 0); 4167 4168 /* Enable the Filter Table */ 4169 em_if_vlan_filter_enable(sc); 4170 } 4171 4172 static void 4173 em_if_intr_enable(if_ctx_t ctx) 4174 { 4175 struct e1000_softc *sc = iflib_get_softc(ctx); 4176 struct e1000_hw *hw = &sc->hw; 4177 u32 ims_mask = IMS_ENABLE_MASK; 4178 4179 if (sc->intr_type == IFLIB_INTR_MSIX) { 4180 E1000_WRITE_REG(hw, EM_EIAC, sc->ims); 4181 ims_mask |= sc->ims; 4182 } 4183 4184 E1000_WRITE_REG(hw, E1000_IMS, ims_mask); 4185 E1000_WRITE_FLUSH(hw); 4186 } 4187 4188 static void 4189 em_if_intr_disable(if_ctx_t ctx) 4190 { 4191 struct e1000_softc *sc = iflib_get_softc(ctx); 4192 struct e1000_hw *hw = &sc->hw; 4193 4194 if (sc->intr_type == IFLIB_INTR_MSIX) 4195 E1000_WRITE_REG(hw, EM_EIAC, 0); 4196 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4197 E1000_WRITE_FLUSH(hw); 4198 } 4199 4200 static void 4201 igb_if_intr_enable(if_ctx_t ctx) 4202 { 4203 struct e1000_softc *sc = iflib_get_softc(ctx); 4204 struct e1000_hw *hw = &sc->hw; 4205 u32 mask; 4206 4207 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4208 mask = (sc->que_mask | sc->link_mask); 4209 E1000_WRITE_REG(hw, E1000_EIAC, mask); 4210 E1000_WRITE_REG(hw, E1000_EIAM, mask); 4211 E1000_WRITE_REG(hw, E1000_EIMS, mask); 4212 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 4213 } else 4214 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 4215 E1000_WRITE_FLUSH(hw); 4216 } 4217 4218 static void 4219 igb_if_intr_disable(if_ctx_t ctx) 4220 { 4221 struct e1000_softc *sc = iflib_get_softc(ctx); 4222 struct e1000_hw *hw = &sc->hw; 4223 4224 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 4225 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 4226 E1000_WRITE_REG(hw, E1000_EIAC, 0); 4227 } 4228 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 4229 E1000_WRITE_FLUSH(hw); 4230 } 4231 4232 /* 4233 * Bit of a misnomer, what this really means is 4234 * to enable OS management of the system... aka 4235 * to disable special hardware management features 4236 */ 4237 static void 4238 em_init_manageability(struct e1000_softc *sc) 4239 { 4240 /* A shared code workaround */ 4241 #define E1000_82542_MANC2H E1000_MANC2H 4242 if (sc->has_manage) { 4243 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H); 4244 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4245 4246 /* disable hardware interception of ARP */ 4247 manc &= ~(E1000_MANC_ARP_EN); 4248 4249 /* enable receiving management packets to the host */ 4250 manc |= E1000_MANC_EN_MNG2HOST; 4251 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4252 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4253 manc2h |= E1000_MNG2HOST_PORT_623; 4254 manc2h |= E1000_MNG2HOST_PORT_664; 4255 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h); 4256 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4257 } 4258 } 4259 4260 /* 4261 * Give control back to hardware management 4262 * controller if there is one. 4263 */ 4264 static void 4265 em_release_manageability(struct e1000_softc *sc) 4266 { 4267 if (sc->has_manage) { 4268 int manc = E1000_READ_REG(&sc->hw, E1000_MANC); 4269 4270 /* re-enable hardware interception of ARP */ 4271 manc |= E1000_MANC_ARP_EN; 4272 manc &= ~E1000_MANC_EN_MNG2HOST; 4273 4274 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc); 4275 } 4276 } 4277 4278 /* 4279 * em_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 4280 * For ASF and Pass Through versions of f/w this means 4281 * that the driver is loaded. For AMT version type f/w 4282 * this means that the network i/f is open. 4283 */ 4284 static void 4285 em_get_hw_control(struct e1000_softc *sc) 4286 { 4287 u32 ctrl_ext, swsm; 4288 4289 if (sc->vf_ifp) 4290 return; 4291 4292 if (sc->hw.mac.type == e1000_82573) { 4293 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4294 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4295 swsm | E1000_SWSM_DRV_LOAD); 4296 return; 4297 } 4298 /* else */ 4299 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4300 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4301 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4302 } 4303 4304 /* 4305 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4306 * For ASF and Pass Through versions of f/w this means that 4307 * the driver is no longer loaded. For AMT versions of the 4308 * f/w this means that the network i/f is closed. 4309 */ 4310 static void 4311 em_release_hw_control(struct e1000_softc *sc) 4312 { 4313 u32 ctrl_ext, swsm; 4314 4315 if (!sc->has_manage) 4316 return; 4317 4318 if (sc->hw.mac.type == e1000_82573) { 4319 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM); 4320 E1000_WRITE_REG(&sc->hw, E1000_SWSM, 4321 swsm & ~E1000_SWSM_DRV_LOAD); 4322 return; 4323 } 4324 /* else */ 4325 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4326 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, 4327 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4328 return; 4329 } 4330 4331 static int 4332 em_is_valid_ether_addr(u8 *addr) 4333 { 4334 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4335 4336 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4337 return (false); 4338 } 4339 4340 return (true); 4341 } 4342 4343 static bool 4344 em_automask_tso(if_ctx_t ctx) 4345 { 4346 struct e1000_softc *sc = iflib_get_softc(ctx); 4347 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 4348 if_t ifp = iflib_get_ifp(ctx); 4349 4350 if (!em_unsupported_tso && sc->link_speed && 4351 sc->link_speed != SPEED_1000 && 4352 scctx->isc_capenable & IFCAP_TSO) { 4353 device_printf(sc->dev, 4354 "Disabling TSO for 10/100 Ethernet.\n"); 4355 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO; 4356 scctx->isc_capenable &= ~IFCAP_TSO; 4357 if_setcapenablebit(ifp, 0, IFCAP_TSO); 4358 /* iflib_init_locked handles ifnet hwassistbits */ 4359 iflib_request_reset(ctx); 4360 return true; 4361 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) { 4362 device_printf(sc->dev, "Re-enabling TSO for GbE.\n"); 4363 scctx->isc_capenable |= sc->tso_automasked; 4364 if_setcapenablebit(ifp, sc->tso_automasked, 0); 4365 sc->tso_automasked = 0; 4366 /* iflib_init_locked handles ifnet hwassistbits */ 4367 iflib_request_reset(ctx); 4368 return true; 4369 } 4370 4371 return false; 4372 } 4373 4374 /* 4375 ** Parse the interface capabilities with regard 4376 ** to both system management and wake-on-lan for 4377 ** later use. 4378 */ 4379 static void 4380 em_get_wakeup(if_ctx_t ctx) 4381 { 4382 struct e1000_softc *sc = iflib_get_softc(ctx); 4383 device_t dev = iflib_get_dev(ctx); 4384 u16 eeprom_data = 0, device_id, apme_mask; 4385 4386 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw); 4387 apme_mask = EM_EEPROM_APME; 4388 4389 switch (sc->hw.mac.type) { 4390 case e1000_82542: 4391 case e1000_82543: 4392 case e1000_vfadapt: 4393 case e1000_vfadapt_i350: 4394 break; 4395 case e1000_82544: 4396 e1000_read_nvm(&sc->hw, 4397 NVM_INIT_CONTROL2_REG, 1, &eeprom_data); 4398 apme_mask = EM_82544_APME; 4399 break; 4400 case e1000_82546: 4401 case e1000_82546_rev_3: 4402 if (sc->hw.bus.func == 1) { 4403 e1000_read_nvm(&sc->hw, 4404 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4405 break; 4406 } else 4407 e1000_read_nvm(&sc->hw, 4408 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4409 break; 4410 case e1000_82573: 4411 case e1000_82583: 4412 sc->has_amt = true; 4413 /* FALLTHROUGH */ 4414 case e1000_82571: 4415 case e1000_82572: 4416 case e1000_80003es2lan: 4417 if (sc->hw.bus.func == 1) { 4418 e1000_read_nvm(&sc->hw, 4419 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 4420 break; 4421 } else 4422 e1000_read_nvm(&sc->hw, 4423 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4424 break; 4425 case e1000_ich8lan: 4426 case e1000_ich9lan: 4427 case e1000_ich10lan: 4428 case e1000_pchlan: 4429 case e1000_pch2lan: 4430 case e1000_pch_lpt: 4431 case e1000_pch_spt: 4432 case e1000_82575: /* listing all igb devices */ 4433 case e1000_82576: 4434 case e1000_82580: 4435 case e1000_i350: 4436 case e1000_i354: 4437 case e1000_i210: 4438 case e1000_i211: 4439 apme_mask = E1000_WUC_APME; 4440 sc->has_amt = true; 4441 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC); 4442 break; 4443 default: 4444 e1000_read_nvm(&sc->hw, 4445 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 4446 break; 4447 } 4448 if (eeprom_data & apme_mask) 4449 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC); 4450 /* 4451 * We have the eeprom settings, now apply the special cases 4452 * where the eeprom may be wrong or the board won't support 4453 * wake on lan on a particular port 4454 */ 4455 device_id = pci_get_device(dev); 4456 switch (device_id) { 4457 case E1000_DEV_ID_82546GB_PCIE: 4458 sc->wol = 0; 4459 break; 4460 case E1000_DEV_ID_82546EB_FIBER: 4461 case E1000_DEV_ID_82546GB_FIBER: 4462 /* Wake events only supported on port A for dual fiber 4463 * regardless of eeprom setting */ 4464 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4465 E1000_STATUS_FUNC_1) 4466 sc->wol = 0; 4467 break; 4468 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 4469 /* if quad port adapter, disable WoL on all but port A */ 4470 if (global_quad_port_a != 0) 4471 sc->wol = 0; 4472 /* Reset for multiple quad port adapters */ 4473 if (++global_quad_port_a == 4) 4474 global_quad_port_a = 0; 4475 break; 4476 case E1000_DEV_ID_82571EB_FIBER: 4477 /* Wake events only supported on port A for dual fiber 4478 * regardless of eeprom setting */ 4479 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & 4480 E1000_STATUS_FUNC_1) 4481 sc->wol = 0; 4482 break; 4483 case E1000_DEV_ID_82571EB_QUAD_COPPER: 4484 case E1000_DEV_ID_82571EB_QUAD_FIBER: 4485 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 4486 /* if quad port adapter, disable WoL on all but port A */ 4487 if (global_quad_port_a != 0) 4488 sc->wol = 0; 4489 /* Reset for multiple quad port adapters */ 4490 if (++global_quad_port_a == 4) 4491 global_quad_port_a = 0; 4492 break; 4493 } 4494 } 4495 4496 4497 /* 4498 * Enable PCI Wake On Lan capability 4499 */ 4500 static void 4501 em_enable_wakeup(if_ctx_t ctx) 4502 { 4503 struct e1000_softc *sc = iflib_get_softc(ctx); 4504 device_t dev = iflib_get_dev(ctx); 4505 if_t ifp = iflib_get_ifp(ctx); 4506 int error = 0; 4507 u32 ctrl, ctrl_ext, rctl; 4508 4509 if (!pci_has_pm(dev)) 4510 return; 4511 4512 /* 4513 * Determine type of Wakeup: note that wol 4514 * is set with all bits on by default. 4515 */ 4516 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 4517 sc->wol &= ~E1000_WUFC_MAG; 4518 4519 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 4520 sc->wol &= ~E1000_WUFC_EX; 4521 4522 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 4523 sc->wol &= ~E1000_WUFC_MC; 4524 else { 4525 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL); 4526 rctl |= E1000_RCTL_MPE; 4527 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl); 4528 } 4529 4530 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC))) 4531 goto pme; 4532 4533 /* Advertise the wakeup capability */ 4534 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL); 4535 ctrl |= (E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN3); 4536 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl); 4537 4538 /* Keep the laser running on Fiber adapters */ 4539 if (sc->hw.phy.media_type == e1000_media_type_fiber || 4540 sc->hw.phy.media_type == e1000_media_type_internal_serdes) { 4541 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT); 4542 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; 4543 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext); 4544 } 4545 4546 if ((sc->hw.mac.type == e1000_ich8lan) || 4547 (sc->hw.mac.type == e1000_pchlan) || 4548 (sc->hw.mac.type == e1000_ich9lan) || 4549 (sc->hw.mac.type == e1000_ich10lan)) 4550 e1000_suspend_workarounds_ich8lan(&sc->hw); 4551 4552 if ( sc->hw.mac.type >= e1000_pchlan) { 4553 error = em_enable_phy_wakeup(sc); 4554 if (error) 4555 goto pme; 4556 } else { 4557 /* Enable wakeup by the MAC */ 4558 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN); 4559 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol); 4560 } 4561 4562 if (sc->hw.phy.type == e1000_phy_igp_3) 4563 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw); 4564 4565 pme: 4566 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 4567 pci_enable_pme(dev); 4568 4569 return; 4570 } 4571 4572 /* 4573 * WOL in the newer chipset interfaces (pchlan) 4574 * require thing to be copied into the phy 4575 */ 4576 static int 4577 em_enable_phy_wakeup(struct e1000_softc *sc) 4578 { 4579 struct e1000_hw *hw = &sc->hw; 4580 u32 mreg, ret = 0; 4581 u16 preg; 4582 4583 /* copy MAC RARs to PHY RARs */ 4584 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 4585 4586 /* copy MAC MTA to PHY MTA */ 4587 for (int i = 0; i < hw->mac.mta_reg_count; i++) { 4588 mreg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); 4589 e1000_write_phy_reg(hw, BM_MTA(i), (u16)(mreg & 0xFFFF)); 4590 e1000_write_phy_reg(hw, BM_MTA(i) + 1, 4591 (u16)((mreg >> 16) & 0xFFFF)); 4592 } 4593 4594 /* configure PHY Rx Control register */ 4595 e1000_read_phy_reg(hw, BM_RCTL, &preg); 4596 mreg = E1000_READ_REG(hw, E1000_RCTL); 4597 if (mreg & E1000_RCTL_UPE) 4598 preg |= BM_RCTL_UPE; 4599 if (mreg & E1000_RCTL_MPE) 4600 preg |= BM_RCTL_MPE; 4601 preg &= ~(BM_RCTL_MO_MASK); 4602 if (mreg & E1000_RCTL_MO_3) 4603 preg |= (((mreg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) 4604 << BM_RCTL_MO_SHIFT); 4605 if (mreg & E1000_RCTL_BAM) 4606 preg |= BM_RCTL_BAM; 4607 if (mreg & E1000_RCTL_PMCF) 4608 preg |= BM_RCTL_PMCF; 4609 mreg = E1000_READ_REG(hw, E1000_CTRL); 4610 if (mreg & E1000_CTRL_RFCE) 4611 preg |= BM_RCTL_RFCE; 4612 e1000_write_phy_reg(hw, BM_RCTL, preg); 4613 4614 /* enable PHY wakeup in MAC register */ 4615 E1000_WRITE_REG(hw, E1000_WUC, 4616 E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN | E1000_WUC_APME); 4617 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol); 4618 4619 /* configure and enable PHY wakeup in PHY registers */ 4620 e1000_write_phy_reg(hw, BM_WUFC, sc->wol); 4621 e1000_write_phy_reg(hw, BM_WUC, E1000_WUC_PME_EN); 4622 4623 /* activate PHY wakeup */ 4624 ret = hw->phy.ops.acquire(hw); 4625 if (ret) { 4626 printf("Could not acquire PHY\n"); 4627 return ret; 4628 } 4629 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 4630 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 4631 ret = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &preg); 4632 if (ret) { 4633 printf("Could not read PHY page 769\n"); 4634 goto out; 4635 } 4636 preg |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; 4637 ret = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, preg); 4638 if (ret) 4639 printf("Could not set PHY Host Wakeup bit\n"); 4640 out: 4641 hw->phy.ops.release(hw); 4642 4643 return ret; 4644 } 4645 4646 static void 4647 em_if_led_func(if_ctx_t ctx, int onoff) 4648 { 4649 struct e1000_softc *sc = iflib_get_softc(ctx); 4650 4651 if (onoff) { 4652 e1000_setup_led(&sc->hw); 4653 e1000_led_on(&sc->hw); 4654 } else { 4655 e1000_led_off(&sc->hw); 4656 e1000_cleanup_led(&sc->hw); 4657 } 4658 } 4659 4660 /* 4661 * Disable the L0S and L1 LINK states 4662 */ 4663 static void 4664 em_disable_aspm(struct e1000_softc *sc) 4665 { 4666 int base, reg; 4667 u16 link_cap,link_ctrl; 4668 device_t dev = sc->dev; 4669 4670 switch (sc->hw.mac.type) { 4671 case e1000_82573: 4672 case e1000_82574: 4673 case e1000_82583: 4674 break; 4675 default: 4676 return; 4677 } 4678 if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) 4679 return; 4680 reg = base + PCIER_LINK_CAP; 4681 link_cap = pci_read_config(dev, reg, 2); 4682 if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) 4683 return; 4684 reg = base + PCIER_LINK_CTL; 4685 link_ctrl = pci_read_config(dev, reg, 2); 4686 link_ctrl &= ~PCIEM_LINK_CTL_ASPMC; 4687 pci_write_config(dev, reg, link_ctrl, 2); 4688 return; 4689 } 4690 4691 /********************************************************************** 4692 * 4693 * Update the board statistics counters. 4694 * 4695 **********************************************************************/ 4696 static void 4697 em_update_stats_counters(struct e1000_softc *sc) 4698 { 4699 struct e1000_hw_stats *stats; 4700 u64 prev_xoffrxc; 4701 4702 if (sc->vf_ifp) { 4703 em_update_vf_stats_counters(sc); 4704 return; 4705 } 4706 4707 stats = &sc->ustats.stats; 4708 prev_xoffrxc = stats->xoffrxc; 4709 4710 if(sc->hw.phy.media_type == e1000_media_type_copper || 4711 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4712 stats->symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS); 4713 stats->sec += E1000_READ_REG(&sc->hw, E1000_SEC); 4714 } 4715 stats->crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS); 4716 stats->mpc += E1000_READ_REG(&sc->hw, E1000_MPC); 4717 stats->scc += E1000_READ_REG(&sc->hw, E1000_SCC); 4718 stats->ecol += E1000_READ_REG(&sc->hw, E1000_ECOL); 4719 4720 stats->mcc += E1000_READ_REG(&sc->hw, E1000_MCC); 4721 stats->latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL); 4722 stats->colc += E1000_READ_REG(&sc->hw, E1000_COLC); 4723 stats->dc += E1000_READ_REG(&sc->hw, E1000_DC); 4724 stats->rlec += E1000_READ_REG(&sc->hw, E1000_RLEC); 4725 stats->xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC); 4726 stats->xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC); 4727 stats->xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC); 4728 /* 4729 ** For watchdog management we need to know if we have been 4730 ** paused during the last interval, so capture that here. 4731 */ 4732 if (stats->xoffrxc != prev_xoffrxc) 4733 sc->shared->isc_pause_frames = 1; 4734 stats->xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC); 4735 stats->fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC); 4736 stats->prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64); 4737 stats->prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127); 4738 stats->prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255); 4739 stats->prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511); 4740 stats->prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023); 4741 stats->prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522); 4742 stats->gprc += E1000_READ_REG(&sc->hw, E1000_GPRC); 4743 stats->bprc += E1000_READ_REG(&sc->hw, E1000_BPRC); 4744 stats->mprc += E1000_READ_REG(&sc->hw, E1000_MPRC); 4745 stats->gptc += E1000_READ_REG(&sc->hw, E1000_GPTC); 4746 4747 /* For the 64-bit byte counters the low dword must be read first. */ 4748 /* Both registers clear on the read of the high dword */ 4749 4750 stats->gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) + 4751 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32); 4752 stats->gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) + 4753 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32); 4754 4755 stats->rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC); 4756 stats->ruc += E1000_READ_REG(&sc->hw, E1000_RUC); 4757 stats->rfc += E1000_READ_REG(&sc->hw, E1000_RFC); 4758 stats->roc += E1000_READ_REG(&sc->hw, E1000_ROC); 4759 stats->rjc += E1000_READ_REG(&sc->hw, E1000_RJC); 4760 4761 stats->mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC); 4762 stats->mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC); 4763 stats->mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC); 4764 4765 stats->tor += E1000_READ_REG(&sc->hw, E1000_TORH); 4766 stats->tot += E1000_READ_REG(&sc->hw, E1000_TOTH); 4767 4768 stats->tpr += E1000_READ_REG(&sc->hw, E1000_TPR); 4769 stats->tpt += E1000_READ_REG(&sc->hw, E1000_TPT); 4770 stats->ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64); 4771 stats->ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127); 4772 stats->ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255); 4773 stats->ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511); 4774 stats->ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023); 4775 stats->ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522); 4776 stats->mptc += E1000_READ_REG(&sc->hw, E1000_MPTC); 4777 stats->bptc += E1000_READ_REG(&sc->hw, E1000_BPTC); 4778 4779 /* Interrupt Counts */ 4780 4781 stats->iac += E1000_READ_REG(&sc->hw, E1000_IAC); 4782 stats->icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC); 4783 stats->icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC); 4784 stats->ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC); 4785 stats->ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC); 4786 stats->ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC); 4787 stats->ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC); 4788 stats->icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC); 4789 stats->icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC); 4790 4791 if (sc->hw.mac.type >= e1000_82543) { 4792 stats->algnerrc += 4793 E1000_READ_REG(&sc->hw, E1000_ALGNERRC); 4794 stats->rxerrc += 4795 E1000_READ_REG(&sc->hw, E1000_RXERRC); 4796 stats->tncrs += 4797 E1000_READ_REG(&sc->hw, E1000_TNCRS); 4798 stats->cexterr += 4799 E1000_READ_REG(&sc->hw, E1000_CEXTERR); 4800 stats->tsctc += 4801 E1000_READ_REG(&sc->hw, E1000_TSCTC); 4802 stats->tsctfc += 4803 E1000_READ_REG(&sc->hw, E1000_TSCTFC); 4804 } 4805 } 4806 4807 static void 4808 em_update_vf_stats_counters(struct e1000_softc *sc) 4809 { 4810 struct e1000_vf_stats *stats; 4811 4812 if (sc->link_speed == 0) 4813 return; 4814 4815 stats = &sc->ustats.vf_stats; 4816 4817 UPDATE_VF_REG(E1000_VFGPRC, 4818 stats->last_gprc, stats->gprc); 4819 UPDATE_VF_REG(E1000_VFGORC, 4820 stats->last_gorc, stats->gorc); 4821 UPDATE_VF_REG(E1000_VFGPTC, 4822 stats->last_gptc, stats->gptc); 4823 UPDATE_VF_REG(E1000_VFGOTC, 4824 stats->last_gotc, stats->gotc); 4825 UPDATE_VF_REG(E1000_VFMPRC, 4826 stats->last_mprc, stats->mprc); 4827 } 4828 4829 static uint64_t 4830 em_if_get_vf_counter(if_ctx_t ctx, ift_counter cnt) 4831 { 4832 struct e1000_softc *sc = iflib_get_softc(ctx); 4833 if_t ifp = iflib_get_ifp(ctx); 4834 4835 switch (cnt) { 4836 case IFCOUNTER_IERRORS: 4837 return sc->dropped_pkts; 4838 case IFCOUNTER_OERRORS: 4839 return (if_get_counter_default(ifp, cnt) + 4840 sc->watchdog_events); 4841 default: 4842 return (if_get_counter_default(ifp, cnt)); 4843 } 4844 } 4845 4846 static uint64_t 4847 em_if_get_counter(if_ctx_t ctx, ift_counter cnt) 4848 { 4849 struct e1000_softc *sc = iflib_get_softc(ctx); 4850 struct e1000_hw_stats *stats; 4851 if_t ifp = iflib_get_ifp(ctx); 4852 4853 if (sc->vf_ifp) 4854 return (em_if_get_vf_counter(ctx, cnt)); 4855 4856 stats = &sc->ustats.stats; 4857 4858 switch (cnt) { 4859 case IFCOUNTER_COLLISIONS: 4860 return (stats->colc); 4861 case IFCOUNTER_IERRORS: 4862 return (sc->dropped_pkts + stats->rxerrc + 4863 stats->crcerrs + stats->algnerrc + 4864 stats->ruc + stats->roc + 4865 stats->mpc + stats->cexterr); 4866 case IFCOUNTER_OERRORS: 4867 return (if_get_counter_default(ifp, cnt) + 4868 stats->ecol + stats->latecol + sc->watchdog_events); 4869 default: 4870 return (if_get_counter_default(ifp, cnt)); 4871 } 4872 } 4873 4874 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized 4875 * @ctx: iflib context 4876 * @event: event code to check 4877 * 4878 * Defaults to returning false for unknown events. 4879 * 4880 * @returns true if iflib needs to reinit the interface 4881 */ 4882 static bool 4883 em_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 4884 { 4885 switch (event) { 4886 case IFLIB_RESTART_VLAN_CONFIG: 4887 default: 4888 return (false); 4889 } 4890 } 4891 4892 /* Export a single 32-bit register via a read-only sysctl. */ 4893 static int 4894 em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 4895 { 4896 struct e1000_softc *sc; 4897 u_int val; 4898 4899 sc = oidp->oid_arg1; 4900 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2); 4901 return (sysctl_handle_int(oidp, &val, 0, req)); 4902 } 4903 4904 /* Per queue holdoff interrupt rate handler */ 4905 static int 4906 em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 4907 { 4908 struct em_rx_queue *rque; 4909 struct em_tx_queue *tque; 4910 struct e1000_hw *hw; 4911 int error; 4912 u32 reg, usec, rate; 4913 4914 bool tx = oidp->oid_arg2; 4915 4916 if (tx) { 4917 tque = oidp->oid_arg1; 4918 hw = &tque->sc->hw; 4919 if (hw->mac.type >= igb_mac_min) 4920 reg = E1000_READ_REG(hw, E1000_EITR(tque->me)); 4921 else if (hw->mac.type == e1000_82574 && tque->msix) 4922 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me)); 4923 else 4924 reg = E1000_READ_REG(hw, E1000_ITR); 4925 } else { 4926 rque = oidp->oid_arg1; 4927 hw = &rque->sc->hw; 4928 if (hw->mac.type >= igb_mac_min) 4929 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix)); 4930 else if (hw->mac.type == e1000_82574 && rque->msix) 4931 reg = E1000_READ_REG(hw, 4932 E1000_EITR_82574(rque->msix)); 4933 else 4934 reg = E1000_READ_REG(hw, E1000_ITR); 4935 } 4936 4937 if (hw->mac.type < igb_mac_min) { 4938 if (reg > 0) 4939 rate = EM_INTS_TO_ITR(reg); 4940 else 4941 rate = 0; 4942 } else { 4943 usec = (reg & IGB_QVECTOR_MASK); 4944 if (usec > 0) 4945 rate = IGB_INTS_TO_EITR(usec); 4946 else 4947 rate = 0; 4948 } 4949 4950 error = sysctl_handle_int(oidp, &rate, 0, req); 4951 if (error || !req->newptr) 4952 return error; 4953 return 0; 4954 } 4955 4956 /* 4957 * Add sysctl variables, one per statistic, to the system. 4958 */ 4959 static void 4960 em_add_hw_stats(struct e1000_softc *sc) 4961 { 4962 device_t dev = iflib_get_dev(sc->ctx); 4963 struct em_tx_queue *tx_que = sc->tx_queues; 4964 struct em_rx_queue *rx_que = sc->rx_queues; 4965 4966 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 4967 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 4968 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 4969 struct e1000_hw_stats *stats; 4970 4971 struct sysctl_oid *stat_node, *queue_node, *int_node; 4972 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 4973 4974 #define QUEUE_NAME_LEN 32 4975 char namebuf[QUEUE_NAME_LEN]; 4976 4977 /* Driver Statistics */ 4978 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 4979 CTLFLAG_RD, &sc->dropped_pkts, 4980 "Driver dropped packets"); 4981 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 4982 CTLFLAG_RD, &sc->link_irq, 4983 "Link MSI-X IRQ Handled"); 4984 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 4985 CTLFLAG_RD, &sc->rx_overruns, 4986 "RX overruns"); 4987 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 4988 CTLFLAG_RD, &sc->watchdog_events, 4989 "Watchdog timeouts"); 4990 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 4991 CTLTYPE_UINT | CTLFLAG_RD, 4992 sc, E1000_CTRL, em_sysctl_reg_handler, "IU", 4993 "Device Control Register"); 4994 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 4995 CTLTYPE_UINT | CTLFLAG_RD, 4996 sc, E1000_RCTL, em_sysctl_reg_handler, "IU", 4997 "Receiver Control Register"); 4998 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 4999 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 5000 "Flow Control High Watermark"); 5001 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 5002 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 5003 "Flow Control Low Watermark"); 5004 5005 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 5006 struct tx_ring *txr = &tx_que->txr; 5007 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 5008 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 5009 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 5010 queue_list = SYSCTL_CHILDREN(queue_node); 5011 5012 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 5013 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 5014 true, em_sysctl_interrupt_rate_handler, 5015 "IU", "Interrupt Rate"); 5016 5017 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 5018 CTLTYPE_UINT | CTLFLAG_RD, sc, 5019 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU", 5020 "Transmit Descriptor Head"); 5021 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 5022 CTLTYPE_UINT | CTLFLAG_RD, sc, 5023 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU", 5024 "Transmit Descriptor Tail"); 5025 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 5026 CTLFLAG_RD, &txr->tx_irq, 5027 "Queue MSI-X Transmit Interrupts"); 5028 } 5029 5030 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 5031 struct rx_ring *rxr = &rx_que->rxr; 5032 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 5033 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 5034 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 5035 queue_list = SYSCTL_CHILDREN(queue_node); 5036 5037 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 5038 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 5039 false, em_sysctl_interrupt_rate_handler, 5040 "IU", "Interrupt Rate"); 5041 5042 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 5043 CTLTYPE_UINT | CTLFLAG_RD, sc, 5044 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU", 5045 "Receive Descriptor Head"); 5046 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 5047 CTLTYPE_UINT | CTLFLAG_RD, sc, 5048 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU", 5049 "Receive Descriptor Tail"); 5050 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 5051 CTLFLAG_RD, &rxr->rx_irq, 5052 "Queue MSI-X Receive Interrupts"); 5053 } 5054 5055 /* MAC stats get their own sub node */ 5056 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 5057 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 5058 stat_list = SYSCTL_CHILDREN(stat_node); 5059 5060 /* 5061 ** VF adapter has a very limited set of stats 5062 ** since its not managing the metal, so to speak. 5063 */ 5064 if (sc->vf_ifp) { 5065 struct e1000_vf_stats *vfstats = &sc->ustats.vf_stats; 5066 5067 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5068 CTLFLAG_RD, &vfstats->gprc, 5069 "Good Packets Received"); 5070 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5071 CTLFLAG_RD, &vfstats->gptc, 5072 "Good Packets Transmitted"); 5073 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5074 CTLFLAG_RD, &vfstats->gorc, 5075 "Good Octets Received"); 5076 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5077 CTLFLAG_RD, &vfstats->gotc, 5078 "Good Octets Transmitted"); 5079 SYSCTL_ADD_QUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5080 CTLFLAG_RD, &vfstats->mprc, 5081 "Multicast Packets Received"); 5082 return; 5083 } 5084 5085 stats = &sc->ustats.stats; 5086 5087 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 5088 CTLFLAG_RD, &stats->ecol, 5089 "Excessive collisions"); 5090 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 5091 CTLFLAG_RD, &stats->scc, 5092 "Single collisions"); 5093 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 5094 CTLFLAG_RD, &stats->mcc, 5095 "Multiple collisions"); 5096 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 5097 CTLFLAG_RD, &stats->latecol, 5098 "Late collisions"); 5099 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 5100 CTLFLAG_RD, &stats->colc, 5101 "Collision Count"); 5102 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 5103 CTLFLAG_RD, &stats->symerrs, 5104 "Symbol Errors"); 5105 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 5106 CTLFLAG_RD, &stats->sec, 5107 "Sequence Errors"); 5108 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 5109 CTLFLAG_RD, &stats->dc, 5110 "Defer Count"); 5111 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 5112 CTLFLAG_RD, &stats->mpc, 5113 "Missed Packets"); 5114 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 5115 CTLFLAG_RD, &stats->rlec, 5116 "Receive Length Errors"); 5117 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 5118 CTLFLAG_RD, &stats->rnbc, 5119 "Receive No Buffers"); 5120 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 5121 CTLFLAG_RD, &stats->ruc, 5122 "Receive Undersize"); 5123 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 5124 CTLFLAG_RD, &stats->rfc, 5125 "Fragmented Packets Received "); 5126 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 5127 CTLFLAG_RD, &stats->roc, 5128 "Oversized Packets Received"); 5129 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 5130 CTLFLAG_RD, &stats->rjc, 5131 "Recevied Jabber"); 5132 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 5133 CTLFLAG_RD, &stats->rxerrc, 5134 "Receive Errors"); 5135 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 5136 CTLFLAG_RD, &stats->crcerrs, 5137 "CRC errors"); 5138 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 5139 CTLFLAG_RD, &stats->algnerrc, 5140 "Alignment Errors"); 5141 /* On 82575 these are collision counts */ 5142 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs", 5143 CTLFLAG_RD, &stats->cexterr, 5144 "Collision/Carrier extension errors"); 5145 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 5146 CTLFLAG_RD, &stats->xonrxc, 5147 "XON Received"); 5148 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 5149 CTLFLAG_RD, &stats->xontxc, 5150 "XON Transmitted"); 5151 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 5152 CTLFLAG_RD, &stats->xoffrxc, 5153 "XOFF Received"); 5154 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 5155 CTLFLAG_RD, &stats->xofftxc, 5156 "XOFF Transmitted"); 5157 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 5158 CTLFLAG_RD, &stats->fcruc, 5159 "Unsupported Flow Control Received"); 5160 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 5161 CTLFLAG_RD, &stats->mgprc, 5162 "Management Packets Received"); 5163 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 5164 CTLFLAG_RD, &stats->mgpdc, 5165 "Management Packets Dropped"); 5166 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 5167 CTLFLAG_RD, &stats->mgptc, 5168 "Management Packets Transmitted"); 5169 5170 /* Packet Reception Stats */ 5171 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 5172 CTLFLAG_RD, &stats->tpr, 5173 "Total Packets Received "); 5174 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 5175 CTLFLAG_RD, &stats->gprc, 5176 "Good Packets Received"); 5177 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 5178 CTLFLAG_RD, &stats->bprc, 5179 "Broadcast Packets Received"); 5180 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 5181 CTLFLAG_RD, &stats->mprc, 5182 "Multicast Packets Received"); 5183 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 5184 CTLFLAG_RD, &stats->prc64, 5185 "64 byte frames received "); 5186 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 5187 CTLFLAG_RD, &stats->prc127, 5188 "65-127 byte frames received"); 5189 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 5190 CTLFLAG_RD, &stats->prc255, 5191 "128-255 byte frames received"); 5192 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 5193 CTLFLAG_RD, &stats->prc511, 5194 "256-511 byte frames received"); 5195 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 5196 CTLFLAG_RD, &stats->prc1023, 5197 "512-1023 byte frames received"); 5198 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 5199 CTLFLAG_RD, &stats->prc1522, 5200 "1023-1522 byte frames received"); 5201 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 5202 CTLFLAG_RD, &stats->gorc, 5203 "Good Octets Received"); 5204 5205 /* Packet Transmission Stats */ 5206 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 5207 CTLFLAG_RD, &stats->gotc, 5208 "Good Octets Transmitted"); 5209 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 5210 CTLFLAG_RD, &stats->tpt, 5211 "Total Packets Transmitted"); 5212 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 5213 CTLFLAG_RD, &stats->gptc, 5214 "Good Packets Transmitted"); 5215 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 5216 CTLFLAG_RD, &stats->bptc, 5217 "Broadcast Packets Transmitted"); 5218 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 5219 CTLFLAG_RD, &stats->mptc, 5220 "Multicast Packets Transmitted"); 5221 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 5222 CTLFLAG_RD, &stats->ptc64, 5223 "64 byte frames transmitted "); 5224 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 5225 CTLFLAG_RD, &stats->ptc127, 5226 "65-127 byte frames transmitted"); 5227 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 5228 CTLFLAG_RD, &stats->ptc255, 5229 "128-255 byte frames transmitted"); 5230 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 5231 CTLFLAG_RD, &stats->ptc511, 5232 "256-511 byte frames transmitted"); 5233 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 5234 CTLFLAG_RD, &stats->ptc1023, 5235 "512-1023 byte frames transmitted"); 5236 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 5237 CTLFLAG_RD, &stats->ptc1522, 5238 "1024-1522 byte frames transmitted"); 5239 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 5240 CTLFLAG_RD, &stats->tsctc, 5241 "TSO Contexts Transmitted"); 5242 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail", 5243 CTLFLAG_RD, &stats->tsctfc, 5244 "TSO Contexts Failed"); 5245 5246 /* Interrupt Stats */ 5247 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 5248 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 5249 int_list = SYSCTL_CHILDREN(int_node); 5250 5251 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 5252 CTLFLAG_RD, &stats->iac, 5253 "Interrupt Assertion Count"); 5254 5255 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer", 5256 CTLFLAG_RD, &stats->icrxptc, 5257 "Interrupt Cause Rx Pkt Timer Expire Count"); 5258 5259 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer", 5260 CTLFLAG_RD, &stats->icrxatc, 5261 "Interrupt Cause Rx Abs Timer Expire Count"); 5262 5263 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer", 5264 CTLFLAG_RD, &stats->ictxptc, 5265 "Interrupt Cause Tx Pkt Timer Expire Count"); 5266 5267 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer", 5268 CTLFLAG_RD, &stats->ictxatc, 5269 "Interrupt Cause Tx Abs Timer Expire Count"); 5270 5271 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty", 5272 CTLFLAG_RD, &stats->ictxqec, 5273 "Interrupt Cause Tx Queue Empty Count"); 5274 5275 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh", 5276 CTLFLAG_RD, &stats->ictxqmtc, 5277 "Interrupt Cause Tx Queue Min Thresh Count"); 5278 5279 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 5280 CTLFLAG_RD, &stats->icrxdmtc, 5281 "Interrupt Cause Rx Desc Min Thresh Count"); 5282 5283 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun", 5284 CTLFLAG_RD, &stats->icrxoc, 5285 "Interrupt Cause Receiver Overrun Count"); 5286 } 5287 5288 static void 5289 em_fw_version_locked(if_ctx_t ctx) 5290 { 5291 struct e1000_softc *sc = iflib_get_softc(ctx); 5292 struct e1000_hw *hw = &sc->hw; 5293 struct e1000_fw_version *fw_ver = &sc->fw_ver; 5294 uint16_t eep = 0; 5295 5296 /* 5297 * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet 5298 * the NVM locking model, so we do it in em_if_attach_pre() and store 5299 * the info in the softc 5300 */ 5301 ASSERT_CTX_LOCK_HELD(hw); 5302 5303 *fw_ver = (struct e1000_fw_version){0}; 5304 5305 if (hw->mac.type >= igb_mac_min) { 5306 /* 5307 * Use the Shared Code for igb(4) 5308 */ 5309 e1000_get_fw_version(hw, fw_ver); 5310 } else { 5311 /* 5312 * Otherwise, EEPROM version should be present on (almost?) 5313 * all devices here 5314 */ 5315 if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) { 5316 INIT_DEBUGOUT("can't get EEPROM version"); 5317 return; 5318 } 5319 5320 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 5321 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT; 5322 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK); 5323 } 5324 } 5325 5326 static void 5327 em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf) 5328 { 5329 const char *space = ""; 5330 5331 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 5332 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 5333 fw_ver->eep_minor, fw_ver->eep_build); 5334 space = " "; 5335 } 5336 5337 if (fw_ver->invm_major || fw_ver->invm_minor || 5338 fw_ver->invm_img_type) { 5339 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 5340 space, fw_ver->invm_major, fw_ver->invm_minor, 5341 fw_ver->invm_img_type); 5342 space = " "; 5343 } 5344 5345 if (fw_ver->or_valid) { 5346 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 5347 space, fw_ver->or_major, fw_ver->or_build, 5348 fw_ver->or_patch); 5349 space = " "; 5350 } 5351 5352 if (fw_ver->etrack_id) 5353 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 5354 } 5355 5356 static void 5357 em_print_fw_version(struct e1000_softc *sc ) 5358 { 5359 device_t dev = sc->dev; 5360 struct sbuf *buf; 5361 int error = 0; 5362 5363 buf = sbuf_new_auto(); 5364 if (!buf) { 5365 device_printf(dev, "Could not allocate sbuf for output.\n"); 5366 return; 5367 } 5368 5369 em_sbuf_fw_version(&sc->fw_ver, buf); 5370 5371 error = sbuf_finish(buf); 5372 if (error) 5373 device_printf(dev, "Error finishing sbuf: %d\n", error); 5374 else if (sbuf_len(buf)) 5375 device_printf(dev, "%s\n", sbuf_data(buf)); 5376 5377 sbuf_delete(buf); 5378 } 5379 5380 static int 5381 em_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 5382 { 5383 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5384 device_t dev = sc->dev; 5385 struct sbuf *buf; 5386 int error = 0; 5387 5388 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5389 if (!buf) { 5390 device_printf(dev, "Could not allocate sbuf for output.\n"); 5391 return (ENOMEM); 5392 } 5393 5394 em_sbuf_fw_version(&sc->fw_ver, buf); 5395 5396 error = sbuf_finish(buf); 5397 if (error) 5398 device_printf(dev, "Error finishing sbuf: %d\n", error); 5399 5400 sbuf_delete(buf); 5401 5402 return (0); 5403 } 5404 5405 /********************************************************************** 5406 * 5407 * This routine provides a way to dump out the adapter eeprom, 5408 * often a useful debug/service tool. This only dumps the first 5409 * 32 words, stuff that matters is in that extent. 5410 * 5411 **********************************************************************/ 5412 static int 5413 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 5414 { 5415 struct e1000_softc *sc = (struct e1000_softc *)arg1; 5416 int error; 5417 int result; 5418 5419 result = -1; 5420 error = sysctl_handle_int(oidp, &result, 0, req); 5421 5422 if (error || !req->newptr) 5423 return (error); 5424 5425 /* 5426 * This value will cause a hex dump of the 5427 * first 32 16-bit words of the EEPROM to 5428 * the screen. 5429 */ 5430 if (result == 1) 5431 em_print_nvm_info(sc); 5432 5433 return (error); 5434 } 5435 5436 static void 5437 em_print_nvm_info(struct e1000_softc *sc) 5438 { 5439 struct e1000_hw *hw = &sc->hw; 5440 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx); 5441 u16 eeprom_data; 5442 int i, j, row = 0; 5443 5444 /* Its a bit crude, but it gets the job done */ 5445 printf("\nInterface EEPROM Dump:\n"); 5446 printf("Offset\n0x0000 "); 5447 5448 /* We rely on the IFLIB_CTX_LOCK as part of NVM locking model */ 5449 sx_xlock(iflib_ctx_lock); 5450 ASSERT_CTX_LOCK_HELD(hw); 5451 for (i = 0, j = 0; i < 32; i++, j++) { 5452 if (j == 8) { /* Make the offset block */ 5453 j = 0; ++row; 5454 printf("\n0x00%x0 ",row); 5455 } 5456 e1000_read_nvm(hw, i, 1, &eeprom_data); 5457 printf("%04x ", eeprom_data); 5458 } 5459 sx_xunlock(iflib_ctx_lock); 5460 printf("\n"); 5461 } 5462 5463 static int 5464 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5465 { 5466 struct em_int_delay_info *info; 5467 struct e1000_softc *sc; 5468 u32 regval; 5469 int error, usecs, ticks; 5470 5471 info = (struct em_int_delay_info *) arg1; 5472 usecs = info->value; 5473 error = sysctl_handle_int(oidp, &usecs, 0, req); 5474 if (error != 0 || req->newptr == NULL) 5475 return (error); 5476 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5477 return (EINVAL); 5478 info->value = usecs; 5479 ticks = EM_USECS_TO_TICKS(usecs); 5480 5481 sc = info->sc; 5482 5483 regval = E1000_READ_OFFSET(&sc->hw, info->offset); 5484 regval = (regval & ~0xffff) | (ticks & 0xffff); 5485 /* Handle a few special cases. */ 5486 switch (info->offset) { 5487 case E1000_RDTR: 5488 break; 5489 case E1000_TIDV: 5490 if (ticks == 0) { 5491 sc->txd_cmd &= ~E1000_TXD_CMD_IDE; 5492 /* Don't write 0 into the TIDV register. */ 5493 regval++; 5494 } else 5495 sc->txd_cmd |= E1000_TXD_CMD_IDE; 5496 break; 5497 } 5498 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval); 5499 return (0); 5500 } 5501 5502 static int 5503 em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 5504 { 5505 struct e1000_softc *sc; 5506 u32 reg, val, shift; 5507 int error, mask; 5508 5509 sc = oidp->oid_arg1; 5510 switch (oidp->oid_arg2) { 5511 case 0: 5512 reg = E1000_DTXTCPFLGL; 5513 shift = 0; 5514 break; 5515 case 1: 5516 reg = E1000_DTXTCPFLGL; 5517 shift = 16; 5518 break; 5519 case 2: 5520 reg = E1000_DTXTCPFLGH; 5521 shift = 0; 5522 break; 5523 default: 5524 return (EINVAL); 5525 break; 5526 } 5527 val = E1000_READ_REG(&sc->hw, reg); 5528 mask = (val >> shift) & 0xfff; 5529 error = sysctl_handle_int(oidp, &mask, 0, req); 5530 if (error != 0 || req->newptr == NULL) 5531 return (error); 5532 if (mask < 0 || mask > 0xfff) 5533 return (EINVAL); 5534 val = (val & ~(0xfff << shift)) | (mask << shift); 5535 E1000_WRITE_REG(&sc->hw, reg, val); 5536 return (0); 5537 } 5538 5539 static void 5540 em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name, 5541 const char *description, struct em_int_delay_info *info, int offset, 5542 int value) 5543 { 5544 info->sc = sc; 5545 info->offset = offset; 5546 info->value = value; 5547 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 5548 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), 5549 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 5550 info, 0, em_sysctl_int_delay, "I", description); 5551 } 5552 5553 /* 5554 * Set flow control using sysctl: 5555 * Flow control values: 5556 * 0 - off 5557 * 1 - rx pause 5558 * 2 - tx pause 5559 * 3 - full 5560 */ 5561 static int 5562 em_set_flowcntl(SYSCTL_HANDLER_ARGS) 5563 { 5564 int error; 5565 static int input = 3; /* default is full */ 5566 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5567 5568 error = sysctl_handle_int(oidp, &input, 0, req); 5569 5570 if ((error) || (req->newptr == NULL)) 5571 return (error); 5572 5573 if (input == sc->fc) /* no change? */ 5574 return (error); 5575 5576 switch (input) { 5577 case e1000_fc_rx_pause: 5578 case e1000_fc_tx_pause: 5579 case e1000_fc_full: 5580 case e1000_fc_none: 5581 sc->hw.fc.requested_mode = input; 5582 sc->fc = input; 5583 break; 5584 default: 5585 /* Do nothing */ 5586 return (error); 5587 } 5588 5589 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 5590 e1000_force_mac_fc(&sc->hw); 5591 return (error); 5592 } 5593 5594 /* 5595 * Manage DMA Coalesce: 5596 * Control values: 5597 * 0/1 - off/on 5598 * Legal timer values are: 5599 * 250,500,1000-10000 in thousands 5600 */ 5601 static int 5602 igb_sysctl_dmac(SYSCTL_HANDLER_ARGS) 5603 { 5604 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5605 int error; 5606 5607 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 5608 5609 if ((error) || (req->newptr == NULL)) 5610 return (error); 5611 5612 switch (sc->dmac) { 5613 case 0: 5614 /* Disabling */ 5615 break; 5616 case 1: /* Just enable and use default */ 5617 sc->dmac = 1000; 5618 break; 5619 case 250: 5620 case 500: 5621 case 1000: 5622 case 2000: 5623 case 3000: 5624 case 4000: 5625 case 5000: 5626 case 6000: 5627 case 7000: 5628 case 8000: 5629 case 9000: 5630 case 10000: 5631 /* Legal values - allow */ 5632 break; 5633 default: 5634 /* Do nothing, illegal value */ 5635 sc->dmac = 0; 5636 return (EINVAL); 5637 } 5638 /* Reinit the interface */ 5639 em_if_init(sc->ctx); 5640 return (error); 5641 } 5642 5643 /* 5644 * Manage Energy Efficient Ethernet: 5645 * Control values: 5646 * 0/1 - enabled/disabled 5647 */ 5648 static int 5649 em_sysctl_eee(SYSCTL_HANDLER_ARGS) 5650 { 5651 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5652 int error, value; 5653 5654 if (sc->hw.mac.type < igb_mac_min) 5655 value = sc->hw.dev_spec.ich8lan.eee_disable; 5656 else 5657 value = sc->hw.dev_spec._82575.eee_disable; 5658 error = sysctl_handle_int(oidp, &value, 0, req); 5659 if (error || req->newptr == NULL) 5660 return (error); 5661 if (sc->hw.mac.type < igb_mac_min) 5662 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0); 5663 else 5664 sc->hw.dev_spec._82575.eee_disable = (value != 0); 5665 em_if_init(sc->ctx); 5666 5667 return (0); 5668 } 5669 5670 static int 5671 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5672 { 5673 struct e1000_softc *sc; 5674 int error; 5675 int result; 5676 5677 result = -1; 5678 error = sysctl_handle_int(oidp, &result, 0, req); 5679 5680 if (error || !req->newptr) 5681 return (error); 5682 5683 if (result == 1) { 5684 sc = (struct e1000_softc *) arg1; 5685 em_print_debug_info(sc); 5686 } 5687 5688 return (error); 5689 } 5690 5691 static int 5692 em_get_rs(SYSCTL_HANDLER_ARGS) 5693 { 5694 struct e1000_softc *sc = (struct e1000_softc *) arg1; 5695 int error; 5696 int result; 5697 5698 result = 0; 5699 error = sysctl_handle_int(oidp, &result, 0, req); 5700 5701 if (error || !req->newptr || result != 1) 5702 return (error); 5703 em_dump_rs(sc); 5704 5705 return (error); 5706 } 5707 5708 static void 5709 em_if_debug(if_ctx_t ctx) 5710 { 5711 em_dump_rs(iflib_get_softc(ctx)); 5712 } 5713 5714 /* 5715 * This routine is meant to be fluid, add whatever is 5716 * needed for debugging a problem. -jfv 5717 */ 5718 static void 5719 em_print_debug_info(struct e1000_softc *sc) 5720 { 5721 device_t dev = iflib_get_dev(sc->ctx); 5722 if_t ifp = iflib_get_ifp(sc->ctx); 5723 struct tx_ring *txr = &sc->tx_queues->txr; 5724 struct rx_ring *rxr = &sc->rx_queues->rxr; 5725 5726 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 5727 printf("Interface is RUNNING "); 5728 else 5729 printf("Interface is NOT RUNNING\n"); 5730 5731 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 5732 printf("and INACTIVE\n"); 5733 else 5734 printf("and ACTIVE\n"); 5735 5736 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 5737 device_printf(dev, "TX Queue %d ------\n", i); 5738 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5739 E1000_READ_REG(&sc->hw, E1000_TDH(i)), 5740 E1000_READ_REG(&sc->hw, E1000_TDT(i))); 5741 5742 } 5743 for (int j=0; j < sc->rx_num_queues; j++, rxr++) { 5744 device_printf(dev, "RX Queue %d ------\n", j); 5745 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5746 E1000_READ_REG(&sc->hw, E1000_RDH(j)), 5747 E1000_READ_REG(&sc->hw, E1000_RDT(j))); 5748 } 5749 } 5750 5751 /* 5752 * 82574 only: 5753 * Write a new value to the EEPROM increasing the number of MSI-X 5754 * vectors from 3 to 5, for proper multiqueue support. 5755 */ 5756 static void 5757 em_enable_vectors_82574(if_ctx_t ctx) 5758 { 5759 struct e1000_softc *sc = iflib_get_softc(ctx); 5760 struct e1000_hw *hw = &sc->hw; 5761 device_t dev = iflib_get_dev(ctx); 5762 u16 edata; 5763 5764 e1000_read_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5765 if (bootverbose) 5766 device_printf(dev, "EM_NVM_PCIE_CTRL = %#06x\n", edata); 5767 if (((edata & EM_NVM_MSIX_N_MASK) >> EM_NVM_MSIX_N_SHIFT) != 4) { 5768 device_printf(dev, "Writing to eeprom: increasing " 5769 "reported MSI-X vectors from 3 to 5...\n"); 5770 edata &= ~(EM_NVM_MSIX_N_MASK); 5771 edata |= 4 << EM_NVM_MSIX_N_SHIFT; 5772 e1000_write_nvm(hw, EM_NVM_PCIE_CTRL, 1, &edata); 5773 e1000_update_nvm_checksum(hw); 5774 device_printf(dev, "Writing to eeprom: done\n"); 5775 } 5776 } 5777